Semiconductor device and method of manufacturing the same, electronic device

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic device, relate to the technical field of semiconductors; the manufacturing method of the semiconductor device comprises: sequentially forming a stack structure of a first electrode, an insulating layer and a second electrode on a substrate; forming a hole extending along a direction perpendicular to the substrate on the stack structure, the hole exposing at least part of the first electrode and the second electrode; growing a semiconductor layer on the inner wall of the hole by an oxidizing agent through an atomic layer deposition process, the semiconductor layer being a metal oxide semiconductor layer; the semiconductor layer being in contact with the exposed first electrode and second electrode respectively; growing a semiconductor layer on the inner wall of the hole by an oxidizing agent through an atomic layer deposition process, comprising: introducing an oxidizing agent and a precursor into a cavity, wherein the oxidizing agent is a gas or a plasma; wherein the oxidizing property of the gas or the plasma is enhanced in the process of increasing the thickness of the semiconductor layer; reducing the oxidation of the first electrode and the second electrode in the process of oxidizing the semiconductor layer.

Description

TECHNICAL FIELD

[0001] The embodiments of the present disclosure relate to, but are not limited to, the semiconductor technology, in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. BACKGROUND

[0002] Metal-oxide transistors are increasingly important in emerging fields such as flexible displays, Internet of Things, wearable electronics, memory, etc. However, during the growth of metal-oxide as the channel layer of the transistor, the interface layer will be oxidized to different degrees, which still exists between the interface of the metal source-drain electrode and the metal-oxide channel material in the vertical channel device, especially for the metal-oxide semiconductor channel material, the excessive oxidation of the interface will limit the performance improvement of the device. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of protection of the present application.

[0004] The embodiments of the present disclosure provide a manufacturing method of a semiconductor device, comprising:

[0005] forming a stack structure of a first electrode, an insulating layer and a second electrode on a substrate in sequence;

[0006] forming a hole extending along a direction perpendicular to the substrate on the stack structure, the hole exposing at least part of the first electrode and the second electrode;

[0007] growing a semiconductor layer on the inner wall of the hole by an oxidation agent through an atomic layer deposition process, the semiconductor layer being a metal-oxide semiconductor layer; the semiconductor layer being in contact with the exposed first electrode and the second electrode respectively;

[0008] growing a semiconductor layer on the inner wall of the hole by an oxidation agent through an atomic layer deposition process, comprising: introducing an oxidation agent and a precursor into a cavity, wherein the oxidation agent is a gas or a plasma;

[0009] wherein the oxidizability of the gas or the plasma is enhanced in the process of increasing the thickness of the semiconductor layer.

[0010] In an exemplary embodiment, growing a semiconductor layer on the inner wall of the hole by an oxidation agent through an atomic layer deposition process comprises:

[0011] growing the semiconductor layer on the sidewall of the hole by a weak oxidizing gas or plasma first, and then by a strong oxidizing gas or plasma through an atomic layer deposition process.

[0012] In an example embodiment, the weakly oxidizing gas or plasma is a weak oxidizer; and the strongly oxidizing gas or plasma is a strong oxidizer.

[0013] In an example embodiment, the weak oxidizer includes water, hydrogen peroxide, or alcohol; and the strong oxidizer includes ozone or fluorine gas.

[0014] In an example embodiment, the weakly oxidizing gas or plasma is ozone with a concentration ranging from 2% to 10%, or active oxygen plasma with a power ranging from 10W to 30W; and the strongly oxidizing gas or plasma is ozone with a concentration ranging from 10% to 20%, or active oxygen plasma with a power ranging from 30W to 60W.

[0015] In an example embodiment, the weakly oxidizing gas or plasma is used to grow a semiconductor layer with a thickness greater than or equal to 0.5nm and less than or equal to 2nm.

[0016] In an example embodiment, after the weakly oxidizing gas or plasma is used to grow a semiconductor layer, the strongly oxidizing gas or plasma is used to grow the semiconductor layer, and further comprising:

[0017] Performing oxygen atmosphere annealing on the grown semiconductor layer.

[0018] In an example embodiment, the same gas or plasma is used as the weakly oxidizing gas and the strongly oxidizing gas to continuously grow the semiconductor layer, and after the semiconductor layer is obtained, an annealing process is performed.

[0019] In an example embodiment, as the thickness of the semiconductor layer increases, the oxygen concentration in the semiconductor layer gradually increases.

[0020] The disclosure also provides a semiconductor device manufactured by the method of manufacturing a semiconductor device described above.

[0021] In an example embodiment, the material of the semiconductor layer includes at least one of indium gallium zinc oxide, indium gallium oxide, indium zinc oxide, indium tin oxide, indium tungsten oxide, and indium oxide.

[0022] The disclosure also provides an electronic device including the semiconductor device described above.

[0023] The manufacturing process of the semiconductor device of the disclosure reduces the oxidation of the first electrode and the second electrode during the oxidation of the semiconductor layer by increasing the oxidizing property of the gas or plasma during the increase of the thickness of the semiconductor layer, thereby improving the contact resistance of the first electrode and the second electrode.

[0024] The manufacturing process of the semiconductor device of the present disclosure grows the semiconductor layer on the sidewall of the hole by first using a weakly oxidizing gas or plasma and then using a strongly oxidizing gas or plasma, thereby reducing the oxidation of the exposed first electrode and second electrode during the growth of the semiconductor layer; the semiconductor layer formed by the weakly oxidizing gas or plasma serves as a barrier layer, thereby reducing the oxidation of the first electrode and second electrode by the strongly oxidizing gas or plasma, and thus improving the contact resistance of the first electrode and second electrode.

[0025] The manufacturing process of the semiconductor device of the present disclosure uses a strongly oxidizing gas or plasma to form the semiconductor layer, thereby improving the quality of the semiconductor layer.

[0026] The manufacturing process of the semiconductor device of the present disclosure gradually increases the oxidizing property of the gas or plasma, thereby reducing the oxidation of the exposed first electrode and second electrode during the oxidation of the semiconductor layer, and thus improving the contact resistance of the first electrode and second electrode.

[0027] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art upon examination of the following or can be learned by practice of the present application. The objects and advantages of the present application can be realized and attained by means of the instrumentalities and combinations particularly pointed out in the description and appended claims.

[0028] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0029] The accompanying drawings are included to provide a further understanding of the present technology and are incorporated in and constitute a part of this specification, illustrate embodiments of the present technology and serve to explain the principles of the present technology, and do not limit the technology.

[0030] Figure 1 A cross-sectional view of a semiconductor device according to an exemplary embodiment is provided;

[0031] Figure 2 A cross-sectional view of a semiconductor device according to an exemplary embodiment after forming a first electrode is provided;

[0032] Figure 3 A cross-sectional view of a semiconductor device according to an exemplary embodiment after forming a second electrode is provided;

[0033] Figure 4 A cross-sectional view of a semiconductor device according to an exemplary embodiment after forming a hole is provided;

[0034] Figure 5 A cross-sectional view of a semiconductor device according to an exemplary embodiment after forming a semiconductor layer, a gate dielectric film, and a gate electrode film is provided;

[0035] Figure 6a FIG. 3 is a partial schematic view of a semiconductor device manufacturing process according to an exemplary embodiment after forming a first growth film;

[0036] Figure 6b FIG. 4 is a partial schematic view of a semiconductor device manufacturing process according to an exemplary embodiment after forming a second growth film;

[0037] Figure 7 FIG. 5 is a cross-sectional view of a semiconductor device according to another exemplary embodiment. DETAILED DESCRIPTION

[0038] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The features of the embodiments of the present disclosure and the embodiments can be combined with each other unless they conflict.

[0039] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as those understood by a person of ordinary skill in the art to which the present disclosure belongs.

[0040] The embodiments of the present disclosure are not necessarily limited to the shapes and sizes of the components shown in the drawings, and the shapes and sizes of the components shown in the drawings can be changed as needed.

[0041] The ordinal numbers "first", "second", "third", and so on in the present disclosure are used to avoid confusion between components, and do not mean any order, number, or importance.

[0042] In the present disclosure, for convenience of explanation, words indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the disclosure, and can be appropriately replaced according to the situation.

[0043] In the present disclosure, unless otherwise explicitly defined and limited, the terms "mount", "connected", and "connection" should be interpreted broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or the communication inside two elements. The specific meaning of the above terms in the present disclosure can be understood by a person of ordinary skill in the art according to the specific circumstances.

[0044] In the present disclosure, a transistor refers to an element including at least three terminals of a gate, a drain, and a source. The transistor has a first channel region between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode), and a current can flow through the drain, the first channel region, and the source. In the present disclosure, the first channel region refers to a region through which a current mainly flows.

[0045] In the present disclosure, it can be that the first electrode is the drain and the second electrode is the source, or it can be that the first electrode is the source and the second electrode is the drain. In the case of using a transistor having opposite polarity, or in the case of a change in the direction of current in circuit operation, the functions of the "source" and the "drain" are sometimes exchanged with each other. Therefore, in the present disclosure, the "source" and the "drain" can be exchanged with each other.

[0046] In the present disclosure, "electrically connected" includes a case where constituent elements are connected together through an element having some electrical action. The element having some electrical action is not particularly limited as long as it can perform transmission and reception of an electrical signal between the connected constituent elements. Examples of the element having some electrical action include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0047] In the present disclosure, "parallel" means approximately parallel or almost parallel, such as a state where two straight lines form an angle of -10° or more and 10° or less, and thus also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular, such as a state where two straight lines form an angle of 80° or more and 100° or less, and thus also includes a state where the angle is 85° or more and 95° or less.

[0048] In the present disclosure, "film" and "layer" can be exchanged with each other. For example, "a conductive layer" can be sometimes replaced with "a conductive film". Similarly, "an insulating film" can be sometimes replaced with "an insulating layer".

[0049] In the present disclosure, "A and B are provided in the same layer" means that A and B are formed at the same time by one patterning process. "A orthographic projection is within the range of B orthographic projection" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0050] In the present disclosure, "A and B are of an integral structure" can mean that there is no clear boundary or gap, or a clear boundary surface, in the microscopic structure. Generally, a film layer formed by patterning on another film layer is of an integral structure. For example, A and B are of an integral structure formed by using the same material and by one patterning process.

[0051] In a vertical channel oxide transistor, especially in a structure where the source electrode and the drain electrode surround the ring-shaped channel, the source electrode and the drain electrode are formed first, and then the metal oxide semiconductor layer is formed to contact the source electrode and the drain electrode. In some embodiments, after the metal oxide semiconductor is formed, the gate insulating layer and / or the gate can be further formed in an oxygen atmosphere. Especially when the semiconductor layer, the gate insulating layer, the gate, etc. are formed by chemical vapor deposition, the film layer needs to be deposited in an oxygen atmosphere, for example, the semiconductor, the insulating layer or the conductive film layer containing O is prepared by atomic layer deposition method.

[0052] In the process of growing the metal oxide channel material by atomic layer deposition process, a strong oxidizing agent is needed to grow the metal oxide film. Too much or too strong oxidizing agent can oxidize the surface of the source electrode and the drain electrode of the transistor, significantly increase the contact resistance of the source electrode and the drain electrode, and reduce the on-state current of the transistor, thereby limiting the improvement of the performance of the memory.

[0053] Embodiments of the present disclosure provide a semiconductor device and a manufacturing method, and an electronic device, the semiconductor device manufactured by the method can effectively improve the performance of the device.

[0054] The manufacturing method of the semiconductor device of the embodiments of the present disclosure comprises:

[0055] forming a stack structure of a first electrode, an insulating layer and a second electrode on a substrate in sequence;

[0056] forming a hole extending along a direction perpendicular to the substrate on the stack structure, the hole exposing at least part of the first electrode and the second electrode;

[0057] growing a semiconductor layer on the inner wall of the hole by an oxidizing agent by an atomic layer deposition process, the semiconductor layer being a metal oxide semiconductor layer; the semiconductor layer being in contact with the exposed first electrode and the second electrode respectively;

[0058] growing a semiconductor layer on the inner wall of the hole by an oxidizing agent by an atomic layer deposition process, comprising: introducing an oxidizing agent and a precursor into a cavity, wherein the oxidizing agent is a gas or a plasma;

[0059] wherein the oxidizing property of the gas or the plasma is enhanced in the process of increasing the thickness of the semiconductor layer.

[0060] The semiconductor device of the present disclosure is illustrated by some exemplary embodiments.

[0061] Figure 1 A cross-sectional schematic diagram of a semiconductor device provided for an exemplary embodiment. In an exemplary embodiment, as shown in FIG. 1, a stack structure of a first electrode 101, an insulating layer 102 and a second electrode 103 is formed on a substrate 100 in sequence. Figure 1As shown, the semiconductor device comprises: a substrate (not shown in the figure), a first insulating medium layer 11 disposed on the substrate, a first electrode 21 disposed on the far side of the first insulating medium layer 11 away from the substrate, a second insulating medium layer 12 disposed on the far side of the first electrode 21 away from the substrate, a second electrode 22 disposed on the far side of the second insulating medium layer 12 away from the substrate, and a third insulating medium layer 13 disposed on the far side of the second electrode 22 away from the substrate. The first electrode 21 and the second electrode 22 are both conductive film layers, such as metal layers, extending along a direction parallel to the substrate, and the orthographic projections of the first electrode 21 and the second electrode 22 on the substrate overlap. The first electrode 21 and the second electrode 22 are patterned conductive film layers.

[0062] In an exemplary embodiment, the semiconductor device further comprises: a hole 31, a semiconductor layer 14, a gate medium layer 15, and a gate electrode 16. The hole 31 extends along a direction perpendicular to the substrate, and the hole 31 penetrates the third insulating medium layer 13, the second electrode 22, and the second insulating medium layer 12 in sequence from the surface of the third insulating medium layer 13 away from the substrate, and extends to the surface of the first electrode 21, thereby exposing the surface of the corresponding hole on the first electrode 21. The bottom wall of the hole 31 is the exposed surface of the first electrode 21, and the sidewall of the hole 31 exposes the sidewall of the corresponding hole on the second electrode 22.

[0063] In some embodiments, the hole extends into the first electrode, thereby forming a groove on the first electrode and exposing the sidewall and the bottom wall of the groove; or the hole penetrates the first electrode from the upper surface of the first electrode, thereby exposing the sidewall of the first electrode.

[0064] In some embodiments, the semiconductor device can not be provided with the third insulating medium layer on the far side of the second electrode away from the substrate, and the disclosure will not be described here.

[0065] In an exemplary embodiment, the semiconductor layer 14 is a film layer structure. The semiconductor layer 14 can be prepared by an atomic layer deposition process. At least part of the semiconductor layer 14 covers the sidewall and the bottom wall of the hole 31, and the semiconductor layer 14 is in contact with the exposed surface of the first electrode 21 and the sidewall of the second electrode 22, respectively.

[0066] In an exemplary embodiment, the semiconductor layer 14 at least covers the sidewall and the bottom wall of the hole 31. For example, the semiconductor layer 14 covers the sidewall and the bottom wall of the hole 31 and extends to the surface located at the opening periphery of the hole 31, i.e., the surface of the third insulating medium layer 13 located at the opening periphery of the hole 31.

[0067] In an exemplary embodiment, the gate dielectric layer 15 is a film layer structure. The gate dielectric layer 15 can be prepared by an atomic layer deposition process. The gate dielectric layer 15 is disposed on the side of the semiconductor layer 14 away from the inner wall of the hole 31.

[0068] In an exemplary embodiment, the gate electrode 16 is disposed on the side of the gate dielectric layer 15 away from the semiconductor layer 14 and fills the hole 31. The gate dielectric layer 15 is between the gate electrode 16 and the semiconductor layer 14, and the gate electrode 16 is connected to the semiconductor layer 14 through the gate dielectric layer 15.

[0069] In an exemplary embodiment, the semiconductor layer 14, the gate dielectric layer 15, and the gate electrode 16 all cover the bottom wall of the hole 31 and extend along a direction perpendicular to the substrate from the bottom wall of the hole 31 to cover the side wall of the hole 31 and extend to the surface at the opening periphery of the hole 31, thereby facilitating the preparation of the semiconductor layer, the gate dielectric layer, and the gate electrode.

[0070] In an exemplary embodiment, in the thickness direction of the semiconductor layer 14, the oxygen concentration on the side of the semiconductor layer 14 close to the exposed first electrode 21 and the second electrode 22 is less than the oxygen concentration on the side of the semiconductor layer 14 away from the exposed first electrode 21 and the second electrode 22.

[0071] In an exemplary embodiment, in the thickness direction of the semiconductor layer 14, the side of the semiconductor layer 14 close to the exposed first electrode 21 and the second electrode 22 isolates the side of the semiconductor layer 14 away from the exposed first electrode 21 and the second electrode 22 from the exposed first electrode 21 and the second electrode 22.

[0072] The semiconductor device of the present disclosure reduces the oxidation of the exposed first electrode and the second electrode during the oxidation of the semiconductor layer by the oxygen concentration on the side of the semiconductor layer 14 close to the exposed first electrode 21 and the second electrode 22 being less than the oxygen concentration on the side of the semiconductor layer 14 away from the exposed first electrode 21 and the second electrode 22, thereby improving the contact resistance of the first electrode and the second electrode.

[0073] In an exemplary embodiment, in the thickness direction of the semiconductor layer 14, the carrier concentration on the side of the semiconductor layer 14 close to the exposed first electrode 21 and the second electrode 22 is greater than the carrier concentration on the side of the semiconductor layer away from the exposed first electrode 21 and the second electrode 22.

[0074] In an exemplary embodiment, the hole 31 penetrates the second insulating dielectric layer 12, the hole 31 exposes the sidewall of the second insulating dielectric layer 12, the semiconductor layer 14 contacts the exposed second insulating dielectric layer 12, and in the thickness direction of the semiconductor layer 14, the oxygen concentration on the side of the semiconductor layer 14 closer to the exposed second insulating dielectric layer 12 is less than the oxygen concentration on the side of the semiconductor layer 14 farther from the exposed second insulating dielectric layer 12.

[0075] The semiconductor device disclosed herein reduces the influence of the second insulating dielectric layer on the semiconductor layer by having a lower oxygen concentration on the side of the semiconductor layer closer to the second insulating dielectric layer than on the side of the semiconductor layer farther from the second insulating dielectric layer.

[0076] In one exemplary embodiment, the material of the semiconductor layer includes at least one of indium gallium zinc oxide, indium gallium oxide, indium zinc oxide, indium tin oxide, indium tungsten oxide, and indium oxide.

[0077] In one exemplary embodiment, the material of the gate dielectric layer includes at least one selected from silicon oxide, aluminum oxide, hafnium oxide, hafnium aluminum oxide, and hafnium lanthanum oxide.

[0078] In one exemplary embodiment, the material of the gate electrode includes at least one selected from indium zinc oxide, indium tin oxide, titanium nitride, tungsten, molybdenum, and nickel.

[0079] Figure 7 This is a schematic cross-sectional view of a semiconductor device provided for yet another exemplary embodiment. In one exemplary embodiment, as... Figure 7 As shown, the semiconductor device further includes a first lead 51, a second lead 52, and a third lead 53. All three leads extend parallel to the substrate and are located on the side of the gate electrode 16 away from the substrate. The first lead 51 is connected to the first electrode 21 via a first via, and is used to connect the first electrode 21 to an external circuit. The second lead 52 is connected to the gate electrode 16 via a second via, and is used to connect the gate electrode 16 to an external circuit. The third lead 53 is connected to the second electrode 22 via a third via, and is used to connect the second electrode 22 to an external circuit.

[0080] The technical solution of the present embodiment is further illustrated by the manufacturing process of the semiconductor device in the present embodiment. The "patterning process" in the present embodiment includes deposition of a film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist, etc., which are mature manufacturing processes in the related art. The "lithography process" in the present embodiment includes coating of a film layer, mask exposure and development, which are mature manufacturing processes in the related art. Deposition can use known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can use known coating processes, and etching can use known methods, which are not specifically limited herein. In the description of the present embodiment, it should be understood that "film" refers to a film made of a certain material on a substrate by deposition or coating process. If the "film" does not need patterning process or lithography process during the entire manufacturing process, the "film" can also be referred to as "layer". If the "film" still needs patterning process or lithography process during the entire manufacturing process, it is referred to as "film" before the patterning process and "layer" after the patterning process. The "layer" after the patterning process or lithography process contains at least one "pattern".

[0081] In an exemplary embodiment, the manufacturing process of the semiconductor device can include:

[0082] Step 101, forming a first electrode.

[0083] Forming the first electrode includes: providing a substrate; then, forming a first insulating medium layer 11 on the substrate; then, depositing a first conductive film on the side of the first insulating medium layer 11 away from the substrate, and forming the first conductive film into a first electrode 21 by a patterning etching process, as shown in Figure 2 . The first electrode can serve as a source electrode or a drain electrode of the semiconductor device.

[0084] In an exemplary embodiment, the first electrode 21 can be in a strip shape or a block shape in a direction parallel to the substrate.

[0085] In an exemplary embodiment, the substrate can be a semiconductor substrate, such as a silicon substrate, or a supporting base containing an insulating layer or a functional layer. The first insulating medium layer 11 in the Figure 1 can be understood as the substrate.

[0086] In an exemplary embodiment, the first insulating medium layer 11 can be a low-K medium layer, i.e., a medium layer with a dielectric constant K≤3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc.

[0087] In some embodiments, the first insulating layer is optional, and the first electrode 21 can be directly formed on the substrate, such as a silicon substrate.

[0088] In an exemplary embodiment, the first electrode 21 can employ a conductive material such as a metal, an alloy, or a metal compound. For example, the first electrode 21 can employ at least one of titanium nitride (TiN), tungsten (W), molybdenum (Mo), nickel (Ni), titanium aluminum alloy (TiAl), and indium tin oxide (ITO).

[0089] In an exemplary embodiment, the first insulating medium layer 11 and the first conductive thin film can be formed by an atomic layer deposition process, a chemical vapor deposition process, physical vapor deposition, sputtering, or the like.

[0090] Step 102, forming a second electrode.

[0091] The forming of the second electrode includes: on the basis of the aforementioned patterned substrate, forming a second insulating medium layer 12 on the side of the first electrode 21 away from the substrate; then, depositing a second conductive thin film on the side of the second insulating medium layer 12 away from the substrate, and forming a second electrode 22 by a patterning etching process, the second electrode 22 and the first electrode 21 have an overlap in orthographic projection on the substrate; then, optionally, forming a third insulating medium layer 13 on the side of the second electrode 22 away from the substrate; as shown in Figure 3 The second electrode 22 can serve as a source electrode or a drain electrode of a semiconductor device. The first electrode 21, the second insulating medium layer 12, the second electrode 22, and the third insulating medium layer 13 form a stacked structure.

[0092] In an exemplary embodiment, the second insulating medium layer 12 and the third insulating medium layer 13 serve to isolate the conductive layer, and at the same time, the second insulating layer is in contact with the semiconductor layer, and needs to have a larger blocking isolation effect, for example, can be a low-K medium layer, i.e., a medium layer with a dielectric constant K≤3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2) or silicon dioxide doped materials, etc.

[0093] In an exemplary embodiment, the first insulating medium layer 11, the second insulating medium layer 12, and the third insulating medium layer 13 can be the same or different in material.

[0094] In an exemplary embodiment, the second electrode 22 can employ a conductive material such as a metal, an alloy, or a metal compound. For example, the second electrode 22 can employ at least one of titanium nitride (TiN), tungsten (W), molybdenum (Mo), nickel (Ni), titanium aluminum alloy (TiAl), and indium tin oxide (ITO).

[0095] In an exemplary embodiment, the second electrode 22 can be the same or different in material from the first electrode 21.

[0096] In an exemplary embodiment, the second insulating medium layer 12 and the second conductive thin film can be formed by a single-atom deposition process, a chemical vapor deposition process or a sputtering method.

[0097] In step 103, a hole is formed.

[0098] The forming of the hole includes: on the basis of the substrate with the aforementioned pattern, a patterned etching process is used to form a hole 31 extending along a direction perpendicular to the substrate on the aforementioned stack structure, the hole 31 is formed by the surface of the third insulating medium layer 13 away from the substrate, and sequentially penetrates the third insulating medium layer 13, the upper and lower surfaces of the second electrode 22 and the second insulating medium layer 12, and extends to the upper surface of the first electrode 21, exposing the upper surface of the first electrode 21, the bottom wall of the hole 31 is the upper surface of the first electrode 21 exposed, and the sidewall of the hole 31 exposes the sidewall of the second electrode 22 corresponding to the hole, as shown in FIG. 3. Figure 4 The upper surface of the first electrode 21 is the surface of the first electrode 21 close to the second electrode 22.

[0099] In another exemplary embodiment, the hole extends into the first electrode, forms a groove on the first electrode, and exposes the sidewall and the bottom wall of the groove.

[0100] In another exemplary embodiment, the hole penetrates the first electrode from the upper surface of the first electrode, and exposes the sidewall of the first electrode corresponding to the hole.

[0101] In step 103, a semiconductor layer, a gate medium thin film and a gate electrode thin film are formed.

[0102] The forming of the semiconductor layer, the gate medium thin film and the gate electrode thin film includes: on the basis of the substrate with the aforementioned pattern, an atomic layer deposition process is used to grow a semiconductor layer on the inner wall of the hole by an oxidizing agent, and the semiconductor layer is a metal oxide semiconductor layer; the semiconductor layer is in contact with the exposed first electrode and the second electrode, respectively.

[0103] The atomic layer deposition process is used to grow a semiconductor layer on the inner wall of the hole by an oxidizing agent, which includes: the oxidizing agent and the precursor are introduced into the cavity, and a plurality of layers of metal oxide atomic layers are grown on the inner wall surface of the hole 31 in sequence, and the plurality of layers of metal oxide atomic layers serve as the semiconductor layer 14. The oxidizing agent is a gas or a plasma, and the oxidizing property of the gas or the plasma is enhanced in the process of increasing the thickness of the semiconductor layer.

[0104] It should be noted that the oxidizability of the gas or plasma is oxidation ability, which is related to the type of the gas or plasma and the concentration of the gas or plasma. The same gas or plasma can change the oxidation ability by changing the gas concentration or the power of the plasma.

[0105] In an exemplary embodiment, the semiconductor layer 14 covers at least the sidewall and the bottom wall of the hole 31, and contacts the surface of the exposed first electrode 21 and the sidewall of the second electrode 22.

[0106] In an exemplary embodiment, the semiconductor layer can be formed by a continuous deposition process or two processes. The continuous deposition process can be understood as using the same gas or plasma to form semiconductor layers with different film qualities by controlling the gas concentration or the power of the plasma, and then performing an annealing process. The two processes can be understood as forming semiconductor layers with different film qualities in two time periods. The materials of the gas or plasma in the two time periods can be the same or different, and an annealing process can be performed between the two time periods.

[0107] Subsequently, the gate dielectric film 42 and the gate electrode film 43 are sequentially deposited on the semiconductor layer 14 by an atomic layer deposition process, and the gate electrode film 43 fills the hole 31, as shown in FIG. 4C. Figure 5

[0108] In an exemplary embodiment, the semiconductor layer is grown on the inner wall of the hole by an atomic layer deposition process using an oxidizing agent, including:

[0109] First, a first growth film 411 is grown on at least the sidewall and the bottom wall of the hole 31 by a weakly oxidizing gas or plasma by an atomic layer deposition process, and the first growth film 411 contacts the exposed first electrode 21 and the second electrode 22, as shown in FIG. 4B. Figure 6a

[0110] Subsequently, the first growth film 411 is annealed in an oxygen atmosphere to densify the first growth film 411, remove residual impurities in the first growth film 411, improve the quality of the first growth film 411, and fill oxygen vacancies in the growth process of the first growth film 411. The annealed first growth film 411 has the same or similar oxygen concentration as a metal oxide film grown by a strongly oxidizing gas or plasma, thereby obtaining the same or similar opening voltage, reducing the oxidation degree of the first electrode 21 and the second electrode 22, avoiding the formation of a higher contact resistance after the source and drain electrodes are severely oxidized, and ensuring a higher on-state current.

[0111] ​​Subsequently, a second growth thin film 412 is grown on the surface of the first growth thin film 411 by a strongly oxidizing gas or plasma, the second growth thin film 412 being connected to the exposed first electrode 21 and second electrode 22 through the first growth thin film 411, the first growth thin film 411 and the second growth thin film 412 forming the semiconductor layer 14, as shown in Figure 6b

[0112] Subsequently, the second growth thin film 412 is subjected to oxygen atmosphere annealing, densifying the second growth thin film 412, removing residual impurities of the second growth thin film 412, improving the quality of the second growth thin film 412, and filling oxygen vacancies in the second growth thin film 412.

[0113] In an exemplary embodiment, the weakly oxidizing gas or plasma is a weak oxidizer, and the strongly oxidizing gas or plasma is a strong oxidizer.

[0114] In an exemplary embodiment, the weak oxidizer includes water, hydrogen peroxide, or alcohol, and the strong oxidizer includes ozone or fluorine gas.

[0115] In an exemplary embodiment, the weakly oxidizing gas or plasma is ozone with a concentration ranging from 2% to 10%, or active oxygen plasma with a power ranging from 10W to 30W; for example, the weakly oxidizing gas or plasma is ozone with a concentration ranging from 5% to 8%, or active oxygen plasma with a power ranging from 20W to 25W.

[0116] In an exemplary embodiment, the strongly oxidizing gas or plasma is ozone with a concentration ranging from 10% to 20%, or active oxygen plasma with a power ranging from 30W to 60W; for example, the strongly oxidizing gas or plasma is ozone with a concentration ranging from 14% to 18%, or active oxygen plasma with a power ranging from 40W to 50W.

[0117] The manufacturing process of the semiconductor device of the present disclosure reduces the oxidation of the first electrode and the second electrode during the oxidation of the semiconductor layer by strengthening the oxidizing property of the gas or plasma during the increase in the thickness of the semiconductor layer, thereby improving the contact resistance of the first electrode and the second electrode.

[0118] ​The manufacturing process of the semiconductor device of the present disclosure grows the semiconductor layer on the sidewall of the hole by first using a weakly oxidizing gas or plasma and then using a strongly oxidizing gas or plasma, thereby reducing the oxidation of the exposed first electrode and second electrode during the growth of the semiconductor layer; the semiconductor layer formed by the weakly oxidizing gas or plasma serves as a barrier layer, thereby reducing the oxidation of the first electrode and second electrode by the strongly oxidizing gas or plasma, and thus improving the contact resistance of the first electrode and second electrode.

[0119] The manufacturing process of the semiconductor device of the present disclosure uses a strongly oxidizing gas or plasma to form the semiconductor layer, thereby improving the quality of the semiconductor layer.

[0120] The manufacturing process of the semiconductor device of the present disclosure gradually increases the oxidizing property of the gas or plasma, thereby reducing the oxidation of the exposed first electrode and second electrode during the oxidation of the semiconductor layer, and thus improving the contact resistance of the first electrode and second electrode.

[0121] In an exemplary embodiment, the material of the first growth film 411 and the second growth film 412 can be a metal oxide. The semiconductor layer 14 formed by the first growth film 411 and the second growth film 412 is of a monolithic structure.

[0122] In an exemplary embodiment, the oxygen content of the first growth film 411 is substantially the same as the oxygen content of the second growth film 412.

[0123] In an exemplary embodiment, the thickness of the first growth film 411 can be greater than or equal to 0.5 nm and less than or equal to 2 nm. For example, the thickness of the first growth film 411 can be greater than or equal to 1 nm and less than or equal to 1.5 nm.

[0124] In an exemplary embodiment, the semiconductor layer with a thickness greater than or equal to 0.5 nm and less than or equal to 2 nm is grown by using a weakly oxidizing gas or plasma.

[0125] In some embodiments, the same kind of gas or plasma can be used as the weakly oxidizing gas and the strongly oxidizing gas to successively form the semiconductor layer, and an annealing process can be performed after the semiconductor layer is obtained.

[0126] In another exemplary embodiment, the atomic layer deposition process is used to grow the semiconductor layer on the inner wall of the hole by using an oxidizing agent, which includes:

[0127] The atomic layer deposition process is used to grow the semiconductor layer on the inner wall of the hole by using an oxidizing agent, and the semiconductor layer is a metal oxide semiconductor layer; the semiconductor layer is in contact with the exposed first electrode and second electrode, respectively;

[0128] The semiconductor layer is grown on the inner wall of the hole by an oxidizing agent using an atomic layer deposition process, including: first, introducing an oxidizing agent and a precursor into a cavity, and growing a plurality of metal oxide atomic layers on the inner wall surface of the hole 31 in sequence, the plurality of metal oxide atomic layers serving as the semiconductor layer 14; then, performing oxygen atmosphere annealing on the grown semiconductor layer 14 to densify the semiconductor layer. The oxidizing agent is a gas or plasma, and the oxidizing property of the gas or plasma gradually increases in the process of increasing the thickness of the semiconductor layer. For example, the atomic layer deposition process uses a gas (e.g., ozone) as the oxidizing agent, and the concentration of the gas gradually increases as the thickness of the semiconductor layer increases.

[0129] In an example embodiment, the oxygen concentration in the semiconductor layer gradually increases as the thickness of the semiconductor layer increases.

[0130] In an example embodiment, there is no annealing process in the process of forming the semiconductor layer.

[0131] In an example embodiment, the atomic layer deposition device can be used to control the parameters of the gas (e.g., ozone) so that the concentration of the gas (e.g., ozone) gradually increases in the process of increasing the thickness of the semiconductor layer.

[0132] In another example embodiment, the semiconductor layer is grown on the inner wall of the hole by an oxidizing agent using an atomic layer deposition process, including:

[0133] The semiconductor layer is grown on the inner wall of the hole by an oxidizing agent using an atomic layer deposition process, and the semiconductor layer is a metal oxide semiconductor layer; the semiconductor layer is in contact with the exposed first electrode and the second electrode, respectively;

[0134] The semiconductor layer is grown on the inner wall of the hole by an oxidizing agent using an atomic layer deposition process, including: first, introducing an oxidizing agent and a precursor into a cavity, and growing a plurality of metal oxide atomic layers on the inner wall surface of the hole 31 in sequence, the plurality of metal oxide atomic layers serving as the semiconductor layer 14; then, performing oxygen atmosphere annealing on the grown semiconductor layer 14 to densify the semiconductor layer. The oxidizing agent is a gas or plasma, and the oxidizing property of the gas or plasma gradually increases in the process of increasing the thickness of the semiconductor layer. For example, the atomic layer deposition process uses a gas (e.g., ozone) as the oxidizing agent, and the concentration of the gas gradually increases as the thickness of the semiconductor layer increases.

[0135] In an example embodiment, there is no annealing process in the process of forming the semiconductor layer.

[0136] In an exemplary embodiment, the plasma (e.g., active oxygen plasma) related parameters can be controlled by an atomic layer deposition apparatus such that the power of the plasma (e.g., active oxygen plasma) gradually increases during the process of increasing the thickness of the semiconductor layer.

[0137] The manufacturing process of the semiconductor device of the present disclosure reduces the oxidation of the exposed first electrode and the second electrode during the oxidation of the semiconductor layer by gradually increasing the oxidizing property of the gas or the plasma to grow the semiconductor layer, thereby improving the contact resistance of the first electrode and the second electrode.

[0138] Step 104, forming a patterned semiconductor layer, a gate dielectric layer and a gate electrode.

[0139] Forming the semiconductor layer, the gate dielectric layer and the gate electrode includes: on the basis of forming the aforementioned patterned substrate, using a patterned etching process to etch the semiconductor layer, the gate dielectric film and the gate electrode film, leaving the semiconductor layer, the gate dielectric film and the gate electrode film in the hole 31, etching and removing part of the semiconductor layer, the gate dielectric film and the gate electrode film on the surface of the third insulating dielectric layer 13, leaving the semiconductor layer, the gate dielectric film and the gate electrode film on the surface of the third insulating dielectric layer 13 at the opening periphery of the hole 31, so that the gate dielectric film forms the gate dielectric layer 15, and the gate electrode film forms the gate electrode 16, the semiconductor layer 14 covers the bottom wall and the sidewall of the hole 31, and extends to the surface of the third insulating dielectric layer 13 at the opening periphery of the hole 31, the gate dielectric layer 15 and the gate electrode 16 both extend to the surface of the third insulating dielectric layer 13 at the opening periphery of the hole, and the semiconductor layer 14 on the surface of the third insulating dielectric layer 13 at the opening periphery of the hole 31 is located between the surface of the third insulating dielectric layer 13 and the gate dielectric layer 15, as shown in Figure 1 .

[0140] In an exemplary embodiment, the semiconductor layer can be a metal oxide, which can be at least one of indium gallium zinc oxide (IGZO), indium gallium oxide (InGaO), indium zinc oxide (IZO), indium tin oxide (ITO), indium tungsten oxide (IWO), indium oxide (InO). For example, when the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 1E-18A), where 1E-18A refers to 10 to the power of -18 amperes, thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the metal oxide material can also be IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiO x , InSnO x , Zn x O y N z , Mg x Zny O z In x Zn y O z In x Ga y Zn z Oa、Zr x In y Zn z O a Hf x In y Zn z O a Sn x In y Zn z O a Al x Sn y In z Zn a O d Si x In y Zn z O a Zn x Sn y O z Al x Zn y Sn z O a Ga x Zn y Sn z O a Zr x Zn y Sn z O a InG a For materials such as SiO, as long as the leakage current of the transistor meets the requirements, it is acceptable; adjustments can be made based on the actual situation.

[0141] In one exemplary embodiment, the gate dielectric layer may be a high-k dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. The high-k dielectric material may include, but is not limited to, at least one of the following: silicon oxide, aluminum oxide, hafnium oxide, hafnium aluminum oxide, and hafnium lanthanum oxide. The high-k dielectric material may also be a ferroelectric material layer.

[0142] In one exemplary embodiment, the material of the gate electrode may be at least one selected from indium zinc oxide (IZO), indium tin oxide (ITO), titanium nitride (TiN), tungsten (W), molybdenum (Mo), and nickel (Ni).

[0143] In some embodiments, the lead can be formed after the transistor is formed, and in some embodiments, the lead and the source or the drain are formed at one time, and the structure is integrated.

[0144] In step 105, the first lead, the second lead and the third lead are formed.

[0145] The formation of the first lead, the second lead and the third lead includes: on the basis of the substrate with the aforementioned pattern, a fourth insulating medium layer 17 covering the gate electrode 16 is formed on the side of the gate electrode 16 away from the substrate; then, a first via, a second via and a third via are formed by using a patterned etching process, the first via extends to the surface of the first electrode 21 by penetrating the fourth insulating medium layer 17, the third insulating medium layer 13 and the second insulating medium layer 12 in sequence, and exposes the surface of the first electrode 21; the second via extends to the surface of the gate electrode 16 by penetrating the fourth insulating medium layer 17, and exposes the surface of the gate electrode 16; the third via extends to the surface of the second electrode 22 by penetrating the fourth insulating medium layer 17 and the third insulating medium layer 13 in sequence, and exposes the surface of the second electrode 22; then, the first lead 51, the second lead 52 and the third lead 53 are formed on the side of the fourth insulating medium layer 17 away from the substrate, the first lead 51 is connected with the first electrode 21 through the first via, and the first lead 51 is used to connect the first electrode 21 with an external circuit; the second lead 52 is connected with the gate electrode 16 through the second via, and the second lead 52 is used to connect the gate electrode 16 with the external circuit; the third lead 53 is connected with the second electrode 22 through the third via, and the third lead 53 is used to connect the second electrode 22 with the external circuit, as shown in FIG. 1C. Figure 7

[0146] In an exemplary embodiment, the semiconductor device of the present application can be a transistor, and according to the material of the transistor semiconductor or channel layer, the transistor can be an n-type or p-type metal oxide semiconductor transistor.

[0147] According to the type of gate insulating layer, the transistor can be a transistor with a low-K gate medium layer or a high-K gate medium layer. According to the material of the transistor, the transistor can be a transistor with a ferroelectric material as a gate medium layer (FeFET).

[0148] According to the application of the transistor in the field of memory, the transistor can be used in a 1T memory cell, such as a memory cell containing only one FeFET; the transistor can be used in a 1T1C memory cell; the transistor can be used in a 2T memory cell containing a read transistor and a write transistor, at least one of which can apply the transistor described in the present application, and the present application does not limit whether the 2T memory cell has additional features such as a capacitor or a back gate; the transistor can be used in a SRAM memory cell, and any multi-transistor memory cell can use the transistor described in the present application according to the needs.​

[0149] The transistor described in the embodiments of the present application can be used in a two-dimensional memory cell array, or in a three-dimensional memory cell array.

[0150] The embodiments of the present disclosure also provide an electronic device comprising the semiconductor device described in any of the foregoing embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which are not limited herein.

[0151] Although the embodiments of the present application are disclosed as above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present application, and is not intended to limit the present application. Any person skilled in the art of the present application can make any modification and change in the form and details without departing from the spirit and scope of the present application. The patent protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A stacked structure consisting of a first electrode, an insulating layer, and a second electrode is sequentially formed on a substrate; Holes are formed in the stacked structure, extending in a direction perpendicular to the substrate, and the holes expose at least a portion of the first electrode and at least a portion of the second electrode; An atomic layer deposition process is used to grow a semiconductor layer on the inner wall of the hole using an oxidant. The semiconductor layer is a metal oxide semiconductor layer. The semiconductor layer is in contact with the exposed first electrode and the second electrode, respectively. A semiconductor layer is grown on the inner wall of the hole using an atomic layer deposition process with an oxidant, including: introducing an oxidant and a precursor into a cavity, wherein the oxidant is a gas or plasma; The oxidizing power of the gas or plasma is enhanced as the thickness of the semiconductor layer increases.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The process of growing a semiconductor layer on the inner wall of the hole using an atomic layer deposition process with an oxidant includes: The semiconductor layer is grown on the sidewalls of the hole using an atomic layer deposition process, first through a weak oxidizing gas or plasma, and then through a strong oxidizing gas or plasma.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The weakly oxidizing gas or plasma is a weak oxidizing agent; the strongly oxidizing gas or plasma is a strong oxidizing agent.

4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, The weak oxidizing agent includes water, hydrogen peroxide, or alcohols; the strong oxidizing agent includes ozone or fluorine gas.

5. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The weak oxidizing gas or plasma is ozone with a concentration range of 2% to 10%, or active oxygen plasma with a power range of 10W to 30W; the strong oxidizing gas or plasma is ozone with a concentration range of 10% to 20%, or active oxygen plasma with a power range of 30W to 60W.

6. The method for manufacturing a semiconductor device according to claim 2, characterized in that, First, a semiconductor layer with a thickness of 0.5 nanometers or less than 2 nanometers is grown using a weakly oxidizing gas or plasma.

7. The method for manufacturing a semiconductor device according to claim 2, characterized in that, After growing the semiconductor layer with a weakly oxidizing gas or plasma, and before growing the semiconductor layer with a strongly oxidizing gas or plasma, the process further includes: The grown semiconductor layer is annealed in an oxygen atmosphere.

8. The method for manufacturing a semiconductor device according to claim 5, characterized in that, Semiconductor layers are continuously fabricated using the same gas or plasma as both weak and strong oxidizing gases, and then subjected to an annealing process after the semiconductor layers are obtained.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, As the thickness of the semiconductor layer increases, the oxygen concentration in the semiconductor layer gradually increases.

10. A semiconductor device, characterized in that, It is manufactured using the manufacturing method of any one of claims 1-9.

11. The semiconductor device according to claim 10, characterized in that, The semiconductor layer is made of at least one of indium gallium zinc oxide, indium gallium oxide, indium zinc oxide, indium tin oxide, indium tungsten oxide, and indium oxide.

12. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 10 or 11.

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