Silicon-on-insulator tri-gate LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor with P buried layer

Abstract

The invention discloses a silicon-on-insulator tri-gate LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor with a P buried layer. The transistor comprises a substrate layer, a buried oxide layer, a silicon film layer and a device top layer which are stacked in sequence. The columnar P buried layer wrapped by the drift region is arranged in the silicon film layer to form a folded super junction structure and modulate the electric field of the drift region, so that the electric field of the drift region is distributed more uniformly, the RESURF effect is improved, and the breakdown voltage of the device is improved; in addition, the drift region of the U-shaped structure is additionally provided with a plurality of surfaces as current paths, so that the on-resistance is effectively reduced. In addition, the gate electrode adopts a three-surface U-shaped gate structure, so that the channel width is expanded, the channel width is matched with an expanded current path of a drift region, the on resistance of the device is further reduced, meanwhile, electric field crowding near the gate electrode is relieved, and the breakdown voltage of the device is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of high-voltage semiconductor power integrated circuit dedicated devices, and in particular relates to a silicon-on-insulation-layer three-gate LDMOS transistor with a P buried layer. Background Art

[0002] With the rapid development of power electronics technology, the demand for high voltage resistance and high efficiency of integrated circuits has gradually increased. Lateral double diffused metal oxide semiconductor (LDMOS) plays an important role as an integrated power device. The two major performances pursued by power devices are high voltage resistance and low power consumption. The commonly used quality factor (FOM = BV2 / R on,sp ) is used to measure the performance of the device. LDMOS has the advantages of high breakdown characteristics and compatibility with standard low-voltage CMOS processes, and is widely used in various power ICs.

[0003] In order to achieve high performance of the device, researchers often continuously introduce new materials and advanced processes. LDMOS devices will play a greater role in high-voltage, high-frequency and high-efficiency applications. The three-gate structure introduces a multi-segment gate electrode to adjust the potential distribution in the drift region, reduce the electric field peak, improve the voltage resistance, and expand the channel width to effectively reduce the on-resistance of the device. P-type buried layer technology refers to the introduction of a P-type doped region in the drift region of LDMOS to optimize the electric field distribution under the drift region and improve the voltage resistance of the device. In addition, the P-type buried layer can effectively isolate the parasitic channel between the drift region and the substrate and reduce leakage current. However, the surface unevenness caused by the injection of the P buried layer will enhance the impurity scattering of electrons in the channel, thereby reducing the channel electron mobility and causing the on-state resistance to degrade. Summary of the invention

[0004] The object of the present invention is to provide a lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor based on a silicon-on-insulator (SOI) substrate and having a P buried layer and a triple-gate structure.

[0005] In a first aspect, the present invention provides a silicon-on-insulator tri-gate LDMOS transistor with a P buried layer, comprising a substrate layer, a buried oxide layer, a silicon film layer and a device top layer stacked in sequence; the silicon film layer comprises a source region, a silicon body, a drain region, a drift region and a P buried layer. The source region is arranged on a side of the top of the silicon body away from the drift region. The P buried layer is embedded in the bottom of the drift region, so that the drift region is in a U-shaped structure with an opening toward the buried oxide layer, forming a folded super junction structure.

[0006] Preferably, the gate electrode in the top layer of the device is in a U-shaped structure, covering the top surface and both side surfaces of the silicon body.

[0007] Preferably, the bottom of the gate electrode covers the connection between the silicon body and the buried oxide layer.

[0008] Preferably, the gate electrode is separated from each side of the silicon body by a gate oxide layer. The material of the gate oxide layer is silicon dioxide.

[0009] Preferably, the gate oxide layer has a thickness of 0.1 μm.

[0010] Preferably, the doping type of the P buried layer is P type, and the doping concentration is 4×10 14 cm -3 ~5×10 17 cm -3 .

[0011] Preferably, the source electrode in the top layer of the device is arranged on the source region. The drain electrode in the top layer of the device is located above the drain region.

[0012] Preferably, the drift region having a U-shaped structure has equal thickness in different directions, and the thickness value is 0.3 μm to 0.49 μm.

[0013] Preferably, the source region includes a source region P+ part and a source region N+ part arranged in parallel.

[0014] Preferably, the drift region is doped with N-type doping and the doping concentration is 1×10 16 cm -3 ~5×10 16 cm -3 .

[0015] The present invention has the following beneficial effects: 1. The present invention inserts a columnar P buried layer in the middle of the drift region of the LDMOS to form a super junction structure, modulate the electric field in the drift region, make the electric field distribution in the drift region more uniform, improve the RESURF effect, and help to increase the breakdown voltage of the device.

[0016] 2. The P buried layer in the present invention enables the drift region to form a U-shaped structure, adding multiple surfaces as current paths, and effectively reducing the on-resistance.

[0017] 3. The gate electrode in the present invention adopts a three-sided U-shaped gate structure, which expands the channel width and matches the current path expanded by the drift region, further reducing the on-resistance of the device, while alleviating the electric field crowding near the gate electrode, which helps to increase the breakdown voltage of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1This is a device structure diagram provided for Example 1 of the present invention.

[0019] Figure 2 This is a cross-sectional view of the device at x=3 of Example 1 of the present invention.

[0020] Figure 3 This is a cross-sectional view of the device at z=0.5 of Example 1 of the present invention.

[0021] Figure 4 This is a device structure diagram provided for comparative example 1 of the present invention.

[0022] Figure 5 This is a cross-sectional view of the device at x=3 of Comparative Example 1 of the present invention.

[0023] Figure 6 This is a comparison diagram of the change of the surface electric field of the silicon film layer with the lateral position in Example 1 of the present invention and Comparative Example 1.

[0024] Figure 7 A comparison diagram of the electron concentration in a circle of the gate electrode of Example 1 of the present invention and Comparative Example 1 as a function of position.

[0025] Figure 8 A comparison diagram of the current density of a circle of gate electrodes of Example 1 of the present invention and Comparative Example 1 as a function of position.

[0026] Fig. 9 This is a comparison diagram of the effect of the concentration of the drift region 5 on the breakdown voltage of the device under different thicknesses of the drift region 5 in Example 1 of the present invention.

[0027] Fig.10 This is a comparison diagram of the effect of the concentration of the drift region 5 on the on-resistance of the device under different drift region 5 thicknesses in Example 1 of the present invention.

[0028] Fig.11 This is a comparison diagram of the effect of the concentration of the drift region 5 on the FOM value of the device under different thicknesses of the drift region 5 in Example 1 of the present invention.

[0029] Fig.12 This is a comparison chart of the effect of drift region thickness on device breakdown voltage, on-resistance and FOM value in Example 1 of the present invention.

[0030] Fig.13 It is a comparison diagram of the output characteristic curves of Example 1 of the present invention and Comparative Example 1.

[0031] Fig.14 It is a comparison diagram of the breakdown characteristic curves of Example 1 of the present invention and Comparative Example 1. DETAILED DESCRIPTION

[0032] The present invention is further described below with reference to the accompanying drawings and examples.

[0033] Example 1 A silicon-on-insulator tri-gate LDMOS transistor with a P buried layer comprises a substrate layer 8, a buried oxide layer 7, a silicon film layer and a device top layer stacked in sequence. In this embodiment, the substrate layer 8, the buried oxide layer 7, the silicon film layer and the device top layer are arranged in a bottom-to-top direction. A spatial rectangular coordinate system is established with the top-to-bottom direction as the y-axis direction, the device length direction as the x-axis direction, and the device width direction as the z-axis direction.

[0034] In this embodiment, the overall length of the LDMOS transistor is 10 μm, the overall thickness is 4 μm, the overall width is 1 μm; the thickness of the silicon film layer is 1 μm; the thickness of the buried oxide layer is 1 μm; and the thickness of the substrate layer is 2 μm.

[0035] The substrate layer 8 is arranged at the bottom, and the doping type is P type, and the doping concentration is 4×10 14 cm -3 The substrate layer 8 is made of silicon material, and the thickness of the substrate layer 8 is 2 μm; the substrate layer 8 is provided with a buried oxide layer 7, and the buried oxide layer 7 is made of silicon dioxide material with a thickness of 1 μm.

[0036] The buried oxide layer 7 is provided with a silicon film layer, which includes a source region, a silicon body 3, a drain region 4, a drift region 5 and a P buried layer 6. The silicon body 3 and the drift region 5 are arranged on the buried oxide layer 7 along the length direction of the device.

[0037] The source region is embedded on a side of the top surface of the silicon body 3 away from the drift region 5 .

[0038] The P buried layer 6 is embedded in the bottom surface of the drift region 5. The P buried layer 6 runs through both end surfaces of the drift region 5 along the length direction, that is, extends from the side of the silicon body 3 to the edge of the device. The bottom surface of the P buried layer 6 is in contact with the buried oxide layer 7. The P buried layer 6 makes the longitudinal section of the drift region 5 form a U-shaped structure, so that the drift region 5 tightly wraps the columnar P buried layer 6 to form a folded super junction structure.

[0039] The drain region 4 is embedded on a side of the top surface of the drift region 5 away from the silicon body 3 .

[0040] The source region includes a source region P+ part 1 and a source region N+ part 2 arranged side by side along the length direction of the device. The source region N+ part 2 is made of silicon material, with an N-type doping type and a doping concentration of 1×10 20 cm -3 , with a width of 1 μm and a thickness of 0.25 μm; the source region P+ part 1 is made of silicon material, with a doping type of P type and a doping concentration of 1×10 20 cm -3 , with a width of 1 μm and a thickness of 0.25 μm.

[0041] The silicon body 3 separates the source region from the buried oxide layer 7 and the drift region 5; the silicon body 3 is made of silicon material with a length of 1 μm and a thickness of 1 μm, and the doping type is P type with a doping concentration of 1×10 17 cm -3 .

[0042] The drain region 4 is made of silicon material with a length of 0.8 μm and a thickness of 0.4 μm, and the doping type is N-type with a doping concentration of 1×10 20 cm -3 ; The doping type of drift region 5 is N-type, and the doping concentration is 1.4×10 16 cm -3 .

[0043] The top layer of the device includes a source electrode 9 , a drain electrode 10 and a gate electrode 11 .

[0044] The gate electrode 11 is disposed on the silicon body 3 and presents an inverted U-shaped structure, covering the entire top surface and partial areas of the left and right side surfaces of the silicon body 3. The left and right side surfaces specifically refer to the two side surfaces perpendicular to the z-axis.

[0045] The two side edges of the gate electrode 11 cover the source region and the drift region 5 respectively; a gate oxide layer is passed between the gate electrode 11 and the source region, the silicon body 3 and the drift region 5; and the thickness of the gate oxide layer is 0.1 μm.

[0046] The source electrode 9 is located above the source region P+ portion 1 and the source region N+ portion 2 .

[0047] The drain electrode 10 is located above the drain region 4 .

[0048] The thickness of the drift region 5 in the U-shaped structure is equal in different directions; the drift region 5 has a total of three thicknesses in different directions; the distance between the side of the P buried layer 6 facing the positive direction of the z-axis and the side of the drift region 5 facing the positive direction of the z-axis is the thickness of the drift region 5 in the first direction. The distance between the side of the P buried layer 6 facing the negative direction of the z-axis and the side of the drift region 5 facing the negative direction of the z-axis is the thickness of the drift region 5 in the second direction. The distance between the side of the P buried layer 6 facing the negative direction of the y-axis and the side of the drift region 5 facing the negative direction of the y-axis is the thickness of the drift region 5 in the second direction.

[0049] The surface of the gate electrode 11 facing the silicon body 3 includes a top directly opposite and two side directly opposite. The top directly opposite of the gate electrode 11 directly faces the top surface of the silicon body 3. The side directly opposite of the gate electrode 11 directly faces the two side surfaces of the silicon body 3 respectively. In this embodiment, the bottom of the gate electrode 11 covers the connection between the silicon body 3 and the buried oxide layer 7; thereby greatly increasing the current flow area between the gate electrode 11 and the silicon body.

[0050] In this embodiment, the thickness tn of the drift region 5 (ie, the dimension along the thickness direction of the silicon film layer) is 0.47 μm.

[0051] Comparative Example 1 like Figure 3 , Figure 4 and Figure 5 As shown, a silicon-on-insulator super junction LDMOS transistor (Con. SJ LDMOS), the difference between this comparative example and Example 1 is that: the gate electrode 11 does not adopt a U-shaped structure, but a planar structure. In this embodiment, the gate electrode 11 is arranged on the top surface of the silicon body 3;

[0052] In this embodiment, the P buried layer 6 is not embedded in the drift region 5; instead, two P buried layers 6 and one drift region 5 are arranged along the width direction of the device; the drift region 5 is arranged between two independent P buried layers 6. The thickness of a single P buried layer 6 is 1 μm and the width is 0.25 μm;

[0053] The remaining parameters are the same as those in Example 1. According to the test, the optimal doping concentration of the drift region 5 in the structure of this embodiment is 1.3×10 16 cm -3 .

[0054] The device length direction is set as the X-axis direction, the device thickness direction is set as the Y-axis direction, and the device width direction is set as the Z-axis direction. Based on the three-dimensional TCAD software simulation, the following experiments are carried out to obtain the super junction LDMOS transistor performance of Example 1 and Comparative Example 1. In the simulation study, the substrate layer 8 is grounded.

[0055] The following is a description of the significant superiority of Example 1 over Comparative Example 1: According to the above parameters, simulations are performed to obtain curves showing the change of the surface electric field of the silicon film layer of the LDMOS transistor provided in Example 1 (TG P-Buried LDMOS) and Comparative Example 1 (Con.SJ LDMOS) with the lateral position. Figure 6 As shown. Figure 6 It can be seen that the electric field distribution on the surface of the silicon film of Example 1 is more uniform. Since Example 1 has a three-sided "U"-shaped gate electrode 11, the electric field crowding phenomenon near the gate electrode is alleviated, the electric field peak on the surface of the gate electrode is reduced, and the lateral withstand voltage capability of the device is improved.

[0056] The curve comparison of the electron concentration and current density of the ring below the gate electrode of the LDMOS transistor provided in Example 1 (TG P-Buried LDMOS) and Comparative Example 1 (Con. SJ LDMOS) as a function of position is shown in FIG. Figure 7 and Figure 8 As shown. Figure 7 and Figure 8 It can be seen that the "U"-shaped drift region 5 and the U-shaped wrapped gate electrode 11 increase the current path, expand the channel width, and greatly increase the electron concentration under the gate electrode, thereby effectively reducing the device on-resistance.

[0057] Determination process of the optimal values ​​of each key parameter in Example 1: The doping concentration of the drift region 5 , the thickness tn of the drift region 5 , and the doping concentration of the P buried layer 6 of the LDMOS transistor provided in Example 1 are changed to study the influence of key parameters on the performance of the device, such as breakdown voltage, on-resistance, and FOM value.

[0058] Fig. 9 The effect of the concentration of the drift region 5 on the breakdown voltage of the device under different drift region 5 thicknesses of the silicon film layer is described. At this time, the concentration of the P buried layer 6 is the optimal doping concentration corresponding to the drift region 5 concentration. As the concentration of the drift region 5 increases, the optimal doping concentration of the P buried layer 6 also increases. It can be seen from the figure that under a certain drift region 5 thickness, as the concentration of the drift region 5 increases, the breakdown voltage of the device first increases and then decreases; as the thickness of the drift region 5 increases, the optimized doping concentration of the drift region 5 also becomes smaller and smaller.

[0059] Fig.10 Describe the effect of the concentration of the drift region 5 on the on-resistance of the device under different drift region 5 thicknesses of the silicon film layer. At this time, the concentration of the P buried layer 6 is the optimal doping concentration corresponding to the concentration of the drift region 5. As the concentration of the drift region 5 increases, the optimal doping concentration of the P buried layer 6 also increases. As can be seen from the figure, under a certain thickness of the drift region 5, the concentration of the drift region 5 increases, and the on-resistance of the device first decreases, then increases, and then decreases, which is mainly due to the effect of the concentration of the P buried layer 6 on the thickness of the depletion layer of the drift region 5. The on-resistance is mainly related to the concentration of the drift region 5 and the thickness of the depletion layer. When the concentration of the drift region 5 is very small or very large, the on-resistance depends on the influence of the concentration of the drift region 5; when the concentration of the drift region 5 reaches a certain value, the on-resistance at this time mainly depends on the influence of the thickness of the depletion layer of the drift region 5.

[0060] Fig.11 Describes the effect of the concentration of the drift region 5 on the FOM value of the device under different drift region 5 thicknesses of the silicon film layer. It can be seen from the figure that under a certain drift region 5 thickness, as the concentration of the drift region 5 increases, the FOM value of the device changes in the same trend as the on-resistance, and the optimal value appears at the drift region 5 concentration corresponding to the highest breakdown voltage.

[0061] Fig.12Describe the effect of the thickness of the drift region 5 of the silicon film layer on the breakdown voltage, on-resistance and FOM value of the device. At this time, the concentration of the drift region 5 is the optimal doping concentration corresponding to the thickness of the drift region 5. It can be seen from the figure that as the thickness of the drift region 5 increases, the breakdown voltage of the device first increases and then decreases, and the on-resistance first decreases and then increases. When the thickness of the drift region 5 is 0.47μm, the device reaches the highest breakdown voltage of 122V and the lowest on-resistance of 3.41mΩ•cm 2 , at this time the highest FOM value (i.e. the best overall performance) is achieved.

[0062] Based on the above four figures, it can be concluded that when the thickness of drift region 5 is 0.47 μm and the concentration of drift region 5 is 1.4×10 16 cm -3 When the concentration of P buried layer 6 is 4.2×10 15 cm -3 The device achieves the highest breakdown voltage of 122V and the lowest on-resistance of 3.41mΩ•cm 2 At this time, the highest FOM value of 4.36MW / cm 2 , showing the best overall performance.

[0063] Fig.13 and Fig.14 The output characteristic curve and breakdown characteristic curve of Example 1 of the present invention and Comparative Example 1 are compared. It can be seen from the figure that the breakdown voltage of the present invention is 122V, and the breakdown voltage of the traditional super junction device is 117V, which is improved by 4%; the on-resistance of the present invention is 3.41mΩ•cm 2 , the on-resistance of the conventional superjunction device is 5.08mΩ•cm 2 , reduced by 32.8%; the FOM value of the present invention is 4.36MW / cm 2 The FOM value of traditional superjunction devices is 2.69MW / cm 2 , an increase of 62.1%. The performance of the present invention surpasses the traditional super junction LDMOS, has a higher breakdown voltage and lower on-resistance, and has more superior performance.

Claims

1. A silicon-on-insulator tri-gate LDMOS transistor with a P buried layer, comprising a substrate layer (8), a buried oxide layer (7), a silicon film layer and a device top layer stacked in sequence; the silicon film layer comprises a source region, a silicon body (3), a drain region (4), a drift region (5) and a P buried layer (6); characterized in that: The source region is arranged on a side of the top of the silicon body (3) away from the drift region (5); the P buried layer (6) is embedded in the bottom of the drift region (5), so that the drift region (5) presents a U-shaped structure with an opening facing the buried oxide layer (7).

2. The silicon-on-insulator tri-gate LDMOS transistor with a P buried layer according to claim 1, characterized in that: The gate electrode (11) in the top layer of the device is in a U-shaped structure, covering the top surface and both side surfaces of the silicon body (3).

3. The silicon-on-insulator tri-gate LDMOS transistor with a P buried layer according to claim 2, characterized in that: The bottom of the gate electrode (11) covers the connection between the silicon body (3) and the buried oxide layer (7).

4. The silicon-on-insulator tri-gate LDMOS transistor with a P buried layer according to claim 2, characterized in that: The gate electrode (11) is separated from each side surface of the silicon body (3) by a gate oxide layer.

5. The silicon-on-insulator tri-gate LDMOS transistor with a P buried layer according to claim 4, characterized in that: The thickness of the gate oxide layer is 0.1 μm.

6. The silicon-on-insulator tri-gate LDMOS transistor with a P buried layer according to claim 1, characterized in that: The doping type of the P buried layer (6) is P type, and the doping concentration is 4×10 14 cm -3 ~5×10 17 cm -3 .

7. The silicon-on-insulator tri-gate LDMOS transistor with a P buried layer according to claim 1, characterized in that: The source electrode (9) in the top layer of the device is arranged on the source region; and the drain electrode (10) in the top layer of the device is located above the drain region (4).

8. The silicon-on-insulator tri-gate LDMOS transistor with a P buried layer according to claim 1, characterized in that: The drift region (5) with a U-shaped structure has the same thickness in different directions, with a thickness value of 0.3 μm to 0.49 μm.

9. The silicon-on-insulator tri-gate LDMOS transistor with a P buried layer according to claim 1, characterized in that: The source region comprises a source region P+ part (1) and a source region N+ part (2) arranged in parallel.

10. The silicon-on-insulator tri-gate LDMOS transistor with a P buried layer according to claim 1, characterized in that: The doping type of the drift region (5) is N-type, and the doping concentration is 1×10 16 cm -3 ~5×10 16 cm -3 .

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