Source-gate oxide thin film transistor and preparation method thereof

Abstract

The invention provides a source-gate oxide thin film transistor and a preparation method thereof, and relates to the technical field of semiconductors. A graphical gate layer, a gate dielectric layer, a graphical semiconductor layer and a graphical source layer are sequentially prepared on a substrate, the source layer comprises a first source electrode layer and a second source electrode layer which are in contact with each other, and projection areas of the first source electrode layer and the second source electrode layer on the substrate are at least partially overlapped. The second source electrode layer is made of a P-type conductor or semiconductor material with the work function higher than that of the N-type oxide semiconductor material, so that the second source electrode layer is in contact with the semiconductor layer to form a high potential barrier, and a wide depletion region is formed in a local region, in direct contact with the second source electrode layer, of the semiconductor layer. And in combination with ohmic contact or quasi ohmic contact formed by the first source electrode layer and the semiconductor layer, the electrical characteristics of the device with high saturation output current and low barrier change sensitivity are realized.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a source-gate oxide thin film transistor and a method for preparing the same. Background Art

[0002] With the continuous advancement of technology, the related technical requirements of many high-tech technologies such as high-resolution active matrix display technology, dynamic random access memory (DRAM) technology and flexible integrated circuit technology are driving the development of thin film transistors (TFT) towards short channel, high mobility, high stability and low power consumption. Among them, compared with traditional thin film transistors, source-gate thin film transistors (SGT) have the advantages of shorter channel, better device stability and lower power consumption due to the introduction of Schottky barriers in the source of traditional thin film transistors (TFT). Therefore, source-gate thin film transistors are actually suitable for application in current-driven display devices or low-power integrated circuits such as AMOLED (active matrix organic light-emitting diode display), Mini-LED (mini light-emitting diode) display devices, Micro-LED (micro light-emitting diode) display devices with high pixel density, and are also suitable for use in the construction of dynamic random access memory.

[0003] However, since the source-gate thin-film transistor introduces a Schottky barrier at the source, the device contact resistance will be greatly increased compared to the traditional thin-film transistor, which often greatly reduces the device output current and makes it difficult to meet the high saturation output current requirements of many applications. For this reason, the industry currently mainly increases the device saturation output current by reducing the Schottky barrier height of the corresponding source-gate thin-film transistor. However, because the device electrical characteristics are extremely sensitive to changes in the Schottky barrier height, when the source-gate thin-film transistor is mass-produced using the Schottky barrier height reduction scheme, there will be obvious differences in electrical characteristics between the large number of transistor products produced. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a source-gate oxide thin film transistor and a preparation method thereof, by introducing a first source electrode layer and a second source electrode layer in contact with each other at the source of the transistor, so that the first source electrode layer forms an ohmic contact or a quasi-ohmic contact with the semiconductor layer, and because the second source electrode layer adopts a P-type conductor or semiconductor material with a higher work function than the N-type oxide semiconductor material, the second source electrode layer contacts the semiconductor layer to form a higher potential barrier, and a local area of ​​the semiconductor layer that is in direct contact with the second source electrode layer forms a wider depletion region, so as to achieve device electrical characteristics of high saturation output current and low sensitivity to potential barrier changes, improve the uniformity of electrical characteristics of the corresponding device during large-scale preparation, and at the same time, there is no need to use high-cost high-work function precious metals (such as platinum, palladium, gold, etc.) to prepare the source, thereby achieving lower device preparation costs.

[0005] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0006] In a first aspect, the present application provides a method for preparing a source-gate oxide thin film transistor, the method comprising:

[0007] providing a substrate;

[0008] A gate layer, a gate dielectric layer and a semiconductor layer are sequentially stacked on one side of the substrate to obtain an intermediate stage device, wherein the gate layer and the semiconductor layer are both patterned, and the semiconductor layer is prepared from an N-type oxide semiconductor material;

[0009] A source layer and a drain layer spaced apart from each other are prepared on a side of the intermediate stage device away from the substrate; or a source layer is prepared on a side of the intermediate stage device away from the substrate, and the film layer portion of the semiconductor layer not covered by the source layer is conductorized to form a conductorized film layer portion for serving as a drain region; wherein the source layer comprises a first source electrode layer and a second source electrode layer in contact with each other, the first source electrode layer forms an ohmic contact or a quasi-ohmic contact with the semiconductor layer, the second source electrode layer contacts the semiconductor layer to form a potential barrier, and a local area of ​​the semiconductor layer directly in contact with the second source electrode layer forms a depletion region, the projection areas of the first source electrode layer and the second source electrode layer on the substrate at least partially overlap, and the second source electrode layer is prepared from a P-type conductor material or a P-type semiconductor material.

[0010] In an optional embodiment, the step of sequentially stacking a gate layer, a gate dielectric layer and a semiconductor layer on one side of the substrate to obtain an intermediate stage device comprises:

[0011] sputtering and depositing a gate layer on a surface of one side of the substrate, and performing photolithography patterning on the deposited gate layer;

[0012] On the side of the substrate where the gate layer is prepared, a gate dielectric layer is grown based on a plasma enhanced chemical vapor deposition method or an atomic layer deposition method, so that the grown gate dielectric layer covers the gate layer and the side area of ​​the substrate that is not blocked by the gate layer;

[0013] On the outer surface of the gate dielectric layer away from the substrate, an N-type oxide semiconductor material is deposited to form a semiconductor layer based on magnetron sputtering or atomic layer deposition, and the deposited semiconductor layer is patterned by photolithography to obtain the intermediate stage device.

[0014] In an optional embodiment, the step of forming a source layer and a drain layer spaced apart from each other on a side of the device at the intermediate stage away from the substrate comprises:

[0015] On the outer surface of the intermediate stage device away from the substrate, a first electrode film layer is deposited by using a P-type conductor material or a P-type semiconductor material based on a magnetron sputtering method or an atomic layer deposition method, and the deposited first electrode film layer is patterned by photolithography to obtain the second source electrode layer; wherein the projection area corresponding to the second source electrode layer is within the projection area corresponding to the semiconductor layer;

[0016] On the outer surface of the second source electrode layer prepared in the intermediate stage device, depositing a second electrode film layer based on a magnetron sputtering method or an atomic layer deposition method, so that the second electrode film layer covers the second source electrode layer and the side area of ​​the semiconductor layer that is not blocked by the second source electrode layer;

[0017] The deposited second electrode film layer is patterned by photolithography to obtain the first source electrode layer and the drain electrode layer spaced apart from each other, so that the drain electrode layer and the second source electrode layer are spaced apart from each other, and the first source electrode layer is in direct contact with the semiconductor layer and at least partially covers the second source electrode layer.

[0018] In an optional embodiment, the step of forming a source layer and a drain layer spaced apart from each other on a side of the device at the intermediate stage away from the substrate comprises:

[0019] On the outer surface of the intermediate stage device away from the substrate, a third electrode film layer is deposited based on a magnetron sputtering method or an atomic layer deposition method, and the deposited third electrode film layer is patterned by photolithography to obtain a first source electrode layer and a drain electrode layer spaced from each other;

[0020] On the outer surface of the first source electrode layer and the drain layer prepared in the intermediate stage device, a fourth electrode film layer is formed by depositing a P-type conductor material or a P-type semiconductor material based on a magnetron sputtering method or an atomic layer deposition method, and the deposited fourth electrode film layer is photolithographically patterned so that the patterned second source electrode layer and the drain layer are spaced apart from each other and at least partially cover the first source electrode layer.

[0021] In an optional embodiment, the step of preparing a source layer on a side of the device at the intermediate stage away from the substrate comprises:

[0022] On the outer surface of the intermediate stage device away from the substrate, a fifth electrode film layer is formed by depositing a P-type conductor material or a P-type semiconductor material based on a magnetron sputtering method or an atomic layer deposition method, and the deposited fifth electrode film layer is patterned by photolithography to obtain the second source electrode layer; wherein the projection area corresponding to the second source electrode layer is within the projection area corresponding to the semiconductor layer;

[0023] On the outer surface of the second source electrode layer prepared in the intermediate stage device, a sixth electrode film layer is deposited based on magnetron sputtering or atomic layer deposition, and the deposited sixth electrode film layer is photolithographically patterned so that the patterned first source electrode layer at least partially covers the second source electrode layer and partially covers the local film layer area of ​​the semiconductor layer not blocked by the second source electrode layer.

[0024] In an optional embodiment, the step of preparing a source layer on a side of the device at the intermediate stage away from the substrate comprises:

[0025] On the outer surface of the intermediate stage device away from the substrate, a seventh electrode film layer is deposited based on a magnetron sputtering method or an atomic layer deposition method, and the deposited seventh electrode film layer is patterned by photolithography so that a projection area corresponding to the patterned first source electrode layer partially covers a projection area corresponding to the semiconductor layer;

[0026] On the outer surface of the first source electrode layer prepared in the intermediate stage device, an eighth electrode film layer is formed by depositing a P-type conductor material or a P-type semiconductor material based on a magnetron sputtering method or an atomic layer deposition method, and the deposited eighth electrode film layer is photolithographically patterned so that the patterned second source electrode layer at least partially covers the first source electrode layer, and partially covers the local film layer area of ​​the semiconductor layer not blocked by the first source electrode layer.

[0027] In an optional embodiment, the gate layer, the first source electrode layer and the drain electrode layer are each made of any one of copper, molybdenum, cobalt, titanium, tungsten, nickel, chromium, indium tin oxide material, and aluminum-doped zinc oxide material;

[0028] The gate dielectric layer is made of a stack of any one or more materials selected from silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, and zirconium oxide;

[0029] The N-type oxide semiconductor material is any one of indium gallium zinc oxide, indium zinc oxide, indium zinc tin oxide, rare earth doped indium zinc oxide, indium gallium oxide, zinc oxide, gallium oxide, indium oxide and tin oxide;

[0030] The second source electrode layer is made of any one of tellurium, telluride, P-type doped silicon material, and P-type doped germanium material.

[0031] In an optional embodiment, the gate layer has a thickness ranging from 10 to 1000 nm;

[0032] The thickness of the gate dielectric layer is in the range of 5-500 nm;

[0033] The thickness of the semiconductor layer is in the range of 5-200 nm;

[0034] The thickness of the first source electrode layer and the drain electrode layer is in the range of 5-1000 nm;

[0035] The thickness of the second source electrode layer is in the range of 1-1000 nm, and the width of a non-projected overlapping region of the second source electrode layer relative to the first source electrode layer is less than or equal to 10 μm.

[0036] In a second aspect, the present application provides a source-gate oxide thin film transistor, the thin film transistor comprising:

[0037] substrate;

[0038] A gate layer, a gate dielectric layer and a semiconductor layer are sequentially stacked on one side of the substrate, wherein the gate dielectric layer covers the gate layer, and a material for preparing the semiconductor layer is an N-type oxide semiconductor material;

[0039] A source layer and a drain layer are spaced apart from each other on the semiconductor layer, wherein the source layer comprises a first source electrode layer and a second source electrode layer in contact with each other, the first source electrode layer forms an ohmic contact or a quasi-ohmic contact with the semiconductor layer, the second source electrode layer contacts the semiconductor layer to form a potential barrier, and a local area of ​​the semiconductor layer that is in direct contact with the second source electrode layer forms a depletion area, the projection areas of the first source electrode layer and the second source electrode layer on the substrate at least partially overlap, and the second source electrode layer is made of a P-type conductor material or a P-type semiconductor material.

[0040] In a third aspect, the present application provides a source-gate oxide thin film transistor, the thin film transistor comprising:

[0041] substrate;

[0042] A gate layer, a gate dielectric layer and a semiconductor layer are sequentially stacked on one side of the substrate, wherein the gate dielectric layer covers the gate layer, and a material for preparing the semiconductor layer is an N-type oxide semiconductor material;

[0043] A source layer is arranged on a side of the semiconductor layer away from the substrate, wherein the semiconductor layer includes a semiconductor film layer portion and a conductive film layer portion, the source layer includes a first source electrode layer and a second source electrode layer in contact with each other, the first source electrode layer and the second source electrode layer jointly cover the semiconductor film layer portion, the first source electrode layer and the semiconductor film layer portion form an ohmic contact or a quasi-ohmic contact, the projection areas of the first source electrode layer and the second source electrode layer on the substrate at least partially overlap, the second source electrode layer contacts the semiconductor film layer portion to form a potential barrier, a local area of ​​the semiconductor film layer portion that is in direct contact with the second source electrode layer forms a depletion region, the second source electrode layer is prepared from a P-type conductor material or a P-type semiconductor material, and the conductive film layer portion is used as a drain region of a corresponding thin film transistor.

[0044] In this case, the beneficial effects of the embodiments of the present application may include the following:

[0045] The present application sequentially prepares a patterned gate layer, a gate dielectric layer, a patterned semiconductor layer and a patterned source layer on a substrate, wherein the source layer includes a first source electrode layer and a second source electrode layer which are in contact with each other and whose projection areas on the substrate at least partially overlap, the first source electrode layer forms an ohmic contact or a quasi-ohmic contact with the semiconductor layer, and the second source electrode layer uses a P-type conductor or semiconductor material with a higher work function than an N-type oxide semiconductor material, so that the second source electrode layer contacts the semiconductor layer to form a higher potential barrier, and a local area of ​​the semiconductor layer that is in direct contact with the second source electrode layer forms a wider depletion region, so as to achieve device electrical characteristics of high saturation output current and low sensitivity to potential barrier changes, improve the uniformity of device electrical characteristics of transistor devices during large-scale preparation, and at the same time, there is no need to use high-cost high-work function precious metals (such as platinum, palladium, gold, etc.) to prepare the source, so as to achieve lower device preparation costs.

[0046] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 One of the schematic diagrams of the composition of the source-gate oxide thin film transistor provided in the embodiment of the present application;

[0049] Figure 2 The second schematic diagram of the composition of the source-gate oxide thin film transistor provided in the embodiment of the present application;

[0050] Figure 3 The third schematic diagram of the composition of the source-gate oxide thin film transistor provided in the embodiment of the present application;

[0051] Figure 4 A fourth schematic diagram of the composition of a source-gate oxide thin film transistor provided in an embodiment of the present application;

[0052] Figure 5 One of the flow diagrams of the method for preparing a source-gate oxide thin film transistor provided in an embodiment of the present application;

[0053] Figure 6 for Figure 5 A schematic flow chart of the sub-steps included in step S220;

[0054] Figure 7 A schematic diagram of manufacturing an intermediate stage device provided in an embodiment of the present application;

[0055] Figure 8 for Figure 5 One of the flowchart diagrams of the sub-steps included in step S230;

[0056] Fig. 9 For Figure 8 The corresponding transistor fabrication schematic diagram;

[0057] Fig.10 for Figure 5 The second flowchart diagram of the sub-steps included in step S230;

[0058] Fig.11 For Fig.10 The corresponding transistor fabrication schematic diagram;

[0059] Fig.12 A second schematic flow chart of a method for preparing a source gate oxide thin film transistor provided in an embodiment of the present application;

[0060] Fig.13 for Fig.12 One of the flowchart diagrams of the sub-steps included in step S330;

[0061] Fig.14 For Fig.13 The corresponding transistor fabrication schematic diagram;

[0062] Fig.15 for Fig.12 The second flowchart diagram of the sub-steps included in step S330;

[0063] Fig.16 For Fig.15 The corresponding transistor fabrication schematic.

[0064] Icon: 10-source-gate oxide thin film transistor; 11-substrate; 12-gate layer; 13-gate dielectric layer; 14-semiconductor layer; 15-source layer; 151-first source electrode layer; 152-second source electrode layer; 16-drain layer; 141-conductive film layer portion; 142-semiconductor film layer portion; 17-depletion region. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0066] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0067] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0068] In the description of the present application, it should be understood that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is conventionally placed when in use, or are the orientations or positional relationships conventionally understood by those skilled in the art. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0069] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0070] In addition, in the description of the present application, it is understood that the relational terms such as the term "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood by specific circumstances.

[0071] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0072] Please refer to Figure 1 and Figure 2 ,in Figure 1 is one of the schematic diagrams of the composition of the source-gate oxide thin film transistor 10 provided in the embodiment of the present application, Figure 2This is the second schematic diagram of the composition of the source-gate oxide thin film transistor 10 provided in the embodiment of the present application. In the embodiment of the present application, the source-gate oxide thin film transistor 10 provided in the present application can utilize the characteristic that P-type conductors or semiconductor materials generally have a higher work function than N-type oxide semiconductor materials to achieve a higher contact barrier (for example, the barrier height under thermal equilibrium is greater than or equal to 0.4 eV) and a larger depletion region width, so as to significantly reduce the electron injection from the source electrode to the semiconductor layer at the depletion region contact interface, thereby reducing the capture of electrons by defects in the depletion region contact interface, improving the electrical hysteresis of the device, ensuring that the source-gate oxide thin film transistor 10 can easily achieve the channel pinch-off effect, and has the electrical characteristics of a high saturation output current, and at the same time can have better uniformity of device electrical characteristics during large-scale preparation, and reduce the preparation cost of the device.

[0073] In the embodiments of the present application, Figure 1 or Figure 2 The source-gate oxide thin film transistor 10 shown may include a substrate 11 , a gate layer 12 , a gate dielectric layer 13 , a semiconductor layer 14 , a source electrode layer 15 , and a drain electrode layer 16 .

[0074] In this embodiment, the gate layer 12, the gate dielectric layer 13 and the semiconductor layer 14 are sequentially stacked on one side of the substrate 11. The gate dielectric layer 13 covers the outer surface of the gate layer 12 away from the substrate 11, and the side area of ​​the substrate 11 on which the gate layer 12 is prepared that is not blocked by the gate layer 12; the projection area of ​​the gate layer 12 on the substrate 11 is less than or equal to the side area of ​​the substrate 11 for preparing the gate layer 12. The semiconductor layer 14 is prepared by using an N-type oxide semiconductor material, and the N-type oxide semiconductor material is any one of indium gallium zinc oxide, indium zinc oxide, indium zinc tin oxide, rare earth doped indium zinc oxide, indium gallium oxide, zinc oxide, gallium oxide, indium oxide and tin oxide.

[0075] In the embodiment of the present application, the source electrode layer 15 and the drain electrode layer 16 are spaced apart from each other, and the source electrode layer 15 and the drain electrode layer 16 are both disposed on the side of the semiconductor layer 14 away from the substrate 11. The source electrode layer 15 includes a first source electrode layer 151 and a second source electrode layer 152 that are in contact with and electrically connected to each other, and the projection areas of the first source electrode layer 151 and the second source electrode layer 152 on the substrate 11 at least partially overlap (for example, Figure 1 The first source electrode layer 151 at least partially covers the second source electrode layer 152, or Figure 2The second source electrode layer 152 at least partially covers the first source electrode layer 151, the first source electrode layer 151 is in direct contact with the semiconductor layer 14 to form an ohmic contact or a quasi-ohmic contact, the second source electrode layer 152 is in direct contact with the semiconductor layer 14 to form a potential barrier, and a local area of ​​the semiconductor layer 14 that is in direct contact with the second source electrode layer 152 forms a depletion region 17; the second source electrode layer 152 and the drain layer 16 are spaced apart from each other.

[0076] When Figure 1 or Figure 2 When the source-gate oxide thin film transistor 10 shown in the figure works in a saturated state, the depletion region 17 in the source-gate oxide thin film transistor 10 corresponding to the source layer 15 is a local semiconductor region in the semiconductor layer 14 that is directly contacted (covered) by the second source electrode layer 152. The depletion region 17 will extend from the side where the source layer 15 realizes ohmic (quasi-ohmic) contact to the side where the drain layer 16 is located, and will reach the interlayer interface between the semiconductor layer 14 and the gate dielectric layer 13 on the drain layer 16 side (refer to Figure 1 or Figure 2 The expansion distribution of the depletion region 17 in the channel is determined to achieve a pinch-off effect of the channel.

[0077] In the embodiment of the present application, the first source electrode layer 151 and the drain layer 16 belong to the same electrode film layer, and the second source electrode layer 152 can be prepared by using a P-type conductor material or a P-type semiconductor material (for example, the preparation material of the second source electrode layer 152 is any one of tellurium, telluride, P-type doped silicon material, and P-type doped germanium material), so as to utilize the characteristic that P-type conductor or semiconductor material generally has a higher work function than N-type oxide semiconductor material to achieve a higher potential barrier and a larger depletion region width, without using a high-cost high-work function noble metal to prepare the source layer 15 and the drain layer 16, thereby reducing the source The preparation cost of the drain electrode is reduced, and the electron injection of the source layer 15 in the direct contact area between the second source electrode layer 152 and the semiconductor layer 14 is greatly reduced, so as to effectively reduce the capture of electrons by the interface defects of the corresponding depletion region 17, and avoid the thermal electron effect and electron traps of the semiconductor layer 14 under the strong longitudinal electric field, thereby greatly improving the electrical hysteresis of the device, improving the stability and reliability of the device, and easily achieving the channel pinch-off effect, which can provide a high saturation output current, improve the uniformity of the electrical characteristics of the corresponding source-gate oxide thin film transistor 10 during large-scale preparation, and effectively reduce the preparation cost of the device. Figure 1 or Figure 2During the actual use of the source-gate oxide thin film transistor 10 shown, the bias voltage of the gate layer 12 can be adjusted to adjust the degree of "pinch-off" of the depletion region 17 at the interlayer interface between the semiconductor layer 14 and the gate dielectric layer 13, thereby effectively regulating the conductivity of the semiconductor layer 14 where the depletion region 17 is located, so as to adjust the transport capacity of the electrons injected from the first source electrode layer 151 into the semiconductor layer 14 to the drain layer 16 (i.e., adjust the size of the drain current).

[0078] In the embodiment of the present application, the first source electrode layer 151 and the drain electrode layer 16 are formed by using the same electrode material, and the work function of the electrode material used by the first source electrode layer 151 and the drain electrode layer 16 may be greater than the work function of the semiconductor layer 14. The electrode material of each of the first source electrode layer 151 and the drain electrode layer 16 is any one of copper, molybdenum, cobalt, titanium, tungsten, nickel, chromium, indium tin oxide material, and aluminum-doped zinc oxide material, and the thickness of the first source electrode layer 151 and the drain electrode layer 16 is in the range of 5-1000 nm.

[0079] In the embodiment of the present application, the substrate 11 can be a rigid substrate such as glass, silicon, etc., or a polymer flexible substrate such as polyimide, polyethylene naphthalate, etc. It is understood that the actual type of the substrate 11 includes but is not limited to the above examples, and any material that can be used as a substrate of a metal oxide thin film transistor device falls within the protection scope of the present application.

[0080] In an embodiment of the present application, the gate layer 12 is made of any one of copper, molybdenum, cobalt, titanium, tungsten, nickel, chromium, indium tin oxide, and aluminum-doped zinc oxide, and the thickness of the gate layer 12 is in the range of 10-1000 nm; the gate dielectric layer 13 is made of any one or more of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, and zirconium oxide, and the thickness of the gate dielectric layer 13 is in the range of 5-500 nm; the semiconductor layer 14 is in the range of 5-200 nm.

[0081] In the embodiment of the present application, the thickness of the second source electrode layer 152 is in the range of 1-1000 nm, and the width of the non-projected overlapping area of ​​the second source electrode layer 152 relative to the first source electrode layer 151 is less than or equal to 10 μm.

[0082] It is understandable that Figure 1 or Figure 2A passivation layer is deposited on the outer surface of the source-gate oxide thin film transistor 10 away from the substrate 11 based on a plasma enhanced chemical vapor deposition method or an atomic layer deposition method to cover and encapsulate the source-gate oxide thin film transistor 10 through the passivation layer, and then a first via hole and a second via hole are opened on the passivation layer, so that the first via hole partially exposes the first source electrode layer 151, and the second via hole partially exposes the drain layer 16, so that the source wiring layer is arranged to be electrically connected to the first source electrode layer 151 through the first via hole, and the drain wiring layer is arranged to be electrically connected to the drain layer 16 through the second via hole, thereby completing the Figure 1 or Figure 2 The device packaging effect of the source-gate oxide thin film transistor 10 is shown.

[0083] Among them, for Figure 1 or Figure 2 The passivation layer deposited on the source-gate oxide thin film transistor 10 shown in the figure, the material used for the passivation layer at least includes silicon nitride material and silicon dioxide material. When the corresponding passivation layer is prepared by using silicon nitride material and silicon dioxide material, the passivation layer can be formed by stacking an oxide layer formed by using silicon dioxide material and a silicon nitride layer formed by using silicon nitride material, wherein the silicon nitride layer is arranged on the side of the oxide layer away from the source-gate oxide thin film transistor 10.

[0084] Optionally, see Figure 3 and Figure 4 ,in Figure 3 This is the third schematic diagram of the composition of the source-gate oxide thin film transistor 10 provided in the embodiment of the present application. Figure 4 FIG. 4 is a schematic diagram of the composition of the source-gate oxide thin film transistor 10 provided in the embodiment of the present application. Figure 1 or Figure 2 Compared with the source gate oxide thin film transistor 10 shown, Figure 3 or Figure 4 The source gate oxide thin film transistor 10 shown is relative to Figure 1 or Figure 2 The differences of the source gate oxide thin film transistor 10 shown are mainly as follows: Figure 3 and Figure 4 The source-gate oxide thin film transistor 10 shown does not have a separate drain electrode layer 16. Figure 3 and Figure 4 The film layer portion of the semiconductor layer 14 not covered by the source layer 15 (including the first source electrode layer 151 and the second source electrode layer 152) is used as a drain region after being conductively converted.

[0085] Specifically, in the embodiments of the present application, Figure 3 or Figure 4The semiconductor layer 14 in the source-gate oxide thin film transistor 10 shown includes a semiconductor film layer portion 142 and a conductive film layer portion 141, wherein the semiconductor film layer portion 142 is jointly covered by the first source electrode layer 151 and the second source electrode layer 152 that are in contact with each other and electrically connected, the first source electrode layer 151 is in direct contact with the semiconductor film layer portion 142 to form an ohmic contact or a quasi-ohmic contact, and the projection areas of the first source electrode layer 151 and the second source electrode layer 152 on the substrate 11 at least partially overlap (for example, Figure 3 The first source electrode layer 151 at least partially covers the second source electrode layer 152, or Figure 4 The second source electrode layer 152 at least partially covers the first source electrode layer 151, the second source electrode layer 152 contacts the semiconductor film layer portion 142 to form a potential barrier, and the local area of ​​the semiconductor film layer portion 142 that is directly in contact with the second source electrode layer 152 forms a depletion region; and the conductive film layer portion 141 is a film layer portion of the semiconductor layer 14 that is not covered by the source layer 15, and the conductive film layer portion 141 is used as Figure 3 or Figure 4 The drain region of the source gate oxide thin film transistor 10 is shown.

[0086] When Figure 3 or Figure 4 When the source-gate oxide thin film transistor 10 shown in the figure works in a saturated state, the depletion region 17 in the source-gate oxide thin film transistor 10 corresponding to the source layer 15 is a local semiconductor region in the semiconductor layer 14 that is directly contacted (covered) by the second source electrode layer 152. The depletion region 17 will extend from the side where the source layer 15 realizes ohmic (quasi-ohmic) contact to the side where the drain layer 16 is located, and will reach the interlayer interface between the semiconductor layer 14 and the gate dielectric layer 13 on the drain layer 16 side (refer to Figure 3 or Figure 4 The expansion distribution of the depletion region 17 in the channel is determined to achieve a pinch-off effect of the channel.

[0087] In the embodiment of the present application, for Figure 3 or Figure 4 For the conductive film layer portion 141 shown in FIG. 1 , the film layer portion of the semiconductor layer 14 not covered by the source layer 15 can be bombarded with argon plasma to convert the bombarded film layer portion with semiconductor characteristics into the conductive film layer portion 141; Figure 3 or Figure 4On the outer surface of the source-gate oxide thin-film transistor 10 shown, which is away from the substrate 11, at least silicon nitride material and silicon dioxide material are used to deposit a passivation layer, and the deposited passivation layer is annealed, so that the film layer portion of the semiconductor layer 14 that is in direct contact with the passivation layer (i.e., the film layer portion not covered by the source electrode layer 15) is conductively conductive under the action of hydrogen diffusion doping of the passivation layer, so as to convert the film layer portion of the semiconductor layer 14 that is in direct contact with the passivation layer and has semiconductor properties into the conductive film layer portion 141.

[0088] Therefore, the application provides Figure 3 or Figure 4 The source-gate oxide thin-film transistor 10 shown can form an ohmic (quasi-ohmic) contact between the first source electrode layer 151 and the semiconductor layer 14, and utilize the characteristic that P-type conductors or semiconductor materials generally have a higher work function than N-type oxide semiconductor materials to achieve a higher contact barrier (for example, the barrier height in the thermal equilibrium state is greater than or equal to 0.4 eV) and a larger depletion region width between the second source electrode layer 152 and the semiconductor layer 14, so as to significantly reduce the injection of electrons from the source into the semiconductor layer 14 at the depletion region contact interface, thereby reducing the capture of electrons by defects in the depletion region contact interface, improving the electrical hysteresis of the device, ensuring that the source-gate oxide thin-film transistor 10 can easily achieve a channel pinch-off effect, and has the device electrical characteristics of a high saturation output current, and at the same time, there is no need to use high-cost precious metals (such as platinum, palladium, gold, etc.) to prepare a transistor source with a high work function, so as to effectively reduce the preparation cost of the device.

[0089] It is understandable that when Figure 3 or Figure 4 After the conductive film layer 141 in the embodiment is conductively formed by argon plasma bombardment, Figure 3 or Figure 4 A passivation layer is deposited on the outer surface of the source-gate oxide thin film transistor 10 away from the substrate 11, so as to cover and encapsulate the source-gate oxide thin film transistor 10 through the passivation layer, and then a first via hole and a second via hole are opened on the passivation layer, so that the first via hole partially exposes the first source electrode layer 151, and the second via hole partially exposes the conductive film layer portion 141, so that the source wiring layer is arranged to be electrically connected to the first source electrode layer 151 through the first via hole, and the drain wiring layer is arranged to be electrically connected to the conductive film layer portion 141 through the second via hole, thereby completing the Figure 3 or Figure 4The device packaging effect of the source-gate oxide thin film transistor 10 shown in the figure. The passivation layer is formed by deposition based on plasma enhanced chemical vapor deposition or atomic layer deposition, and the material used in the passivation layer includes at least silicon nitride material and silicon dioxide material; when the corresponding passivation layer is prepared by silicon nitride material and silicon dioxide material, the passivation layer can be formed by stacking an oxide layer formed by silicon dioxide material and a silicon nitride layer formed by silicon nitride material, wherein the silicon nitride layer is arranged on the side of the oxide layer away from the source-gate oxide thin film transistor 10.

[0090] It is also understandable that when Figure 3 or Figure 4 When the conductive film layer portion 141 in the conductive film layer is conductively made by utilizing the hydrogen diffusion doping effect of the passivation layer, Figure 3 or Figure 4 The passivation layer deposited on the source-gate oxide thin film transistor 10 is opened to expose the first source electrode layer 151 in the first via hole portion, and expose the conductive film layer portion 141 in the second via hole portion, so that the source wiring layer is arranged to be electrically connected to the first source electrode layer 151 through the first via hole, and the drain wiring layer is arranged to be electrically connected to the conductive film layer portion 141 through the second via hole, thereby completing the Figure 3 or Figure 4 The device packaging effect of the source-gate oxide thin film transistor 10 shown in the figure. The passivation layer is formed by deposition based on plasma enhanced chemical vapor deposition or atomic layer deposition, and the material used in the passivation layer includes at least silicon nitride material and silicon dioxide material; when the corresponding passivation layer is prepared by silicon nitride material and silicon dioxide material, the passivation layer can be formed by stacking an oxide layer formed by silicon dioxide material and a silicon nitride layer formed by silicon nitride material, wherein the silicon nitride layer is arranged on the side of the oxide layer away from the source-gate oxide thin film transistor 10.

[0091] In this application, to ensure Figure 1 or Figure 2 The source gate oxide thin film transistor 10 shown can be prepared and formed quickly and orderly to reduce the device preparation cost and effectively improve the device's electrical hysteresis phenomenon on the basis of ensuring the device's electrical characteristics of high saturation output current, thereby improving the uniformity of the device's electrical characteristics during large-scale preparation of transistor devices. The embodiment of the present application achieves the above functions by providing a method for preparing a source gate oxide thin film transistor.

[0092] Please refer to Figure 5 , Figure 5 It is one of the flow diagrams of the method for preparing a source gate oxide thin film transistor provided in the embodiment of the present application. In the embodiment of the present application, Figure 5 The preparation method shown may include steps S210 to S230 to prepare Figure 1 or Figure 2 The source gate oxide thin film transistor 10 is shown.

[0093] Step S210, providing a substrate.

[0094] Step S220, a gate layer, a gate dielectric layer and a semiconductor layer are sequentially stacked on one side of the substrate to obtain an intermediate stage device, wherein the gate layer and the semiconductor layer are both patterned, and the semiconductor layer is prepared using an N-type oxide semiconductor material.

[0095] In this embodiment, the gate dielectric layer 13 in the intermediate stage device covers the gate layer 12 .

[0096] Optionally, please refer to Figure 6 and Figure 7 ,in Figure 6 yes Figure 5 The flowchart of the sub-steps included in step S220 in FIG. Figure 7 Schematic diagram of manufacturing an intermediate stage device provided in an embodiment of the present application. In the embodiment of the present application, step S220 may include sub-steps S221 to S223 to prepare an intermediate stage device in which both the gate layer 12 and the semiconductor layer 14 are patterned.

[0097] Sub-step S221 , forming a gate layer by sputtering deposition on one side surface of the substrate, and performing photolithography patterning on the deposited gate layer.

[0098] In this embodiment, Figure 7 (a) is a schematic diagram of a device in which a patterned gate layer 12 is prepared on one side surface of the substrate 11. In one implementation of this embodiment, a photoresist layer can be spin-coated on the outer surface of the substrate 11 where the gate layer 12 has just been deposited, and the photoresist layer can be patterned, and then under the shielding effect of the patterned photoresist layer, the local area of ​​the gate layer 12 not covered by the photoresist layer is etched to achieve the patterning effect of the gate layer 12, wherein acetone can be used to remove the patterned photoresist layer.

[0099] Sub-step S222, on the side of the substrate with the gate layer, grow a gate dielectric layer based on plasma enhanced chemical vapor deposition or atomic layer deposition, so that the grown gate dielectric layer covers the gate layer and the side area of ​​the substrate not blocked by the gate layer.

[0100] In this embodiment, Figure 7 (b) is a schematic diagram of a device in which the gate dielectric layer 13 is grown on the outer surface of the substrate 11 on which the gate layer 12 is prepared.

[0101] Sub-step S223, on the outer surface of the gate dielectric layer away from the substrate, a semiconductor layer is formed by depositing an N-type oxide semiconductor material based on a magnetron sputtering method or an atomic layer deposition method, and the deposited semiconductor layer is patterned by photolithography to obtain an intermediate stage device.

[0102] In this embodiment, Figure 7 (c) is a schematic diagram of a device in which a patterned semiconductor layer 14 is prepared on the outer surface of the gate dielectric layer 13 away from the substrate 11. Figure 7 The device structure shown in (c) is the intermediate stage device. In one implementation of this embodiment, a photoresist layer can be spin-coated on the outer surface of the gate dielectric layer 13 where the semiconductor layer 14 is just deposited, and the photoresist layer can be patterned, and then under the shielding effect of the patterned photoresist layer, the local area of ​​the semiconductor layer 14 not covered by the photoresist layer is etched to achieve the patterning effect of the semiconductor layer 14, wherein acetone can be used to remove the patterned photoresist layer.

[0103] Step S230, preparing a source layer and a drain layer spaced apart from each other on a side of the device away from the substrate in the intermediate stage, wherein the source layer includes a first source electrode layer and a second source electrode layer in contact with each other, the projection areas of the first source electrode layer and the second source electrode layer on the substrate at least partially overlap, and the second source electrode layer is prepared from a P-type conductor material or a P-type semiconductor material.

[0104] In this embodiment, the first source electrode layer 151 forms an ohmic contact or a quasi-ohmic contact with the semiconductor layer 14, the second source electrode layer 152 contacts the semiconductor layer 14 to form a potential barrier, and a local area of ​​the semiconductor layer 14 that is in direct contact with the second source electrode layer 152 forms a depletion region 17, and the second source electrode layer 152 and the drain layer 16 are spaced apart from each other; the first source electrode layer 151 may at least partially cover the second source electrode layer 152, or the second source electrode layer 152 may at least partially cover the first source electrode layer 151.

[0105] Optionally, please refer to Figure 8 and Fig. 9 ,in Figure 8 yes Figure 5 One of the flowchart diagrams of the sub-steps included in step S230 in the embodiment, Fig. 9 is with Figure 8 In the embodiment of the present application, the step S230 may include sub-steps S231 to S233 to prepare a transistor. Figure 1 Source gate oxide thin film transistor shown.

[0106] Sub-step S231, on the outer surface of the intermediate stage device away from the substrate, a first electrode film layer is formed by depositing a P-type conductor material or a P-type semiconductor material based on a magnetron sputtering method or an atomic layer deposition method, and the deposited first electrode film layer is photolithographically patterned to obtain a second source electrode layer.

[0107] In this embodiment, Fig. 9 (a) is a schematic diagram of a device in which a first electrode film layer is prepared on the device at the intermediate stage; Fig. 9 (b) is a schematic diagram of a device in which the first electrode film layer is patterned into the second source electrode layer 152 using the Lift-Off process, wherein the projection area of ​​the second source electrode layer 152 on the substrate 11 is within the projection area of ​​the semiconductor layer 14 on the substrate 11.

[0108] Sub-step S232, on the outer surface of the second source electrode layer prepared in the intermediate stage device, a second electrode film layer is deposited based on magnetron sputtering or atomic layer deposition, so that the second electrode film layer covers the second source electrode layer and the side areas of the semiconductor layer that are not blocked by the second source electrode layer.

[0109] In this embodiment, Fig. 9 (c) is a schematic diagram of a device in which a second electrode film layer is further prepared on the intermediate stage device after the second source electrode layer 152 is prepared.

[0110] Sub-step S233, photolithography and patterning the deposited second electrode film layer to obtain a first source electrode layer and a drain electrode layer spaced apart from each other, so that the drain electrode layer and the second source electrode layer are spaced apart from each other, and the first source electrode layer is in direct contact with the semiconductor layer and at least partially covers the second source electrode layer.

[0111] In this embodiment, Fig. 9 (d) is a schematic diagram of a device in which the second electrode film layer is patterned into a first source electrode layer 151 and a drain electrode layer 16 spaced apart from each other by using a Lift-Off process. Fig. 9 The device structure shown in (d) is Figure 1 Source gate oxide thin film transistor shown.

[0112] Optionally, please refer to Fig.10 and Fig.11 ,in Fig.10 yes Figure 5 The second flowchart diagram of the sub-steps included in step S230 in FIG. Fig.11 is with Fig.10 In the embodiment of the present application, the step S230 may include sub-steps S235 to S236 to prepare the transistor. Figure 2 Source gate oxide thin film transistor shown.

[0113] Sub-step S235, on the outer surface of the intermediate stage device away from the substrate, a third electrode film layer is deposited based on magnetron sputtering or atomic layer deposition, and the deposited third electrode film layer is photolithographically patterned to obtain a first source electrode layer and a drain layer spaced apart from each other.

[0114] In this embodiment, Fig.11 (a) is a schematic diagram of a device in which a third electrode film layer is prepared on the device at the intermediate stage; Fig.11 (b) is a schematic diagram of a device in which the third electrode film layer is patterned into a first source electrode layer 151 and a drain electrode layer 16 spaced apart from each other by using a Lift-Off process.

[0115] Sub-step S236, on the outer surface of the first source electrode layer and the drain layer prepared in the intermediate stage device, a fourth electrode film layer is formed by depositing a P-type conductor material or a P-type semiconductor material based on a magnetron sputtering method or an atomic layer deposition method, and the deposited fourth electrode film layer is photolithographically patterned so that the patterned second source electrode layer and the drain layer are spaced apart from each other and at least partially cover the first source electrode layer.

[0116] In this embodiment, Fig.11 (c) is a schematic diagram of a device in which a fourth electrode film layer is further prepared on the intermediate stage device after the first source electrode layer 151 and the drain electrode layer 16 are prepared. Fig.11 (d) is a schematic diagram of a device in which the fourth electrode film layer is patterned into the second source electrode layer 152 by using the Lift-Off process. Fig.11 The device structure shown in (d) is Figure 2 Source gate oxide thin film transistor shown.

[0117] Therefore, the present application can quickly and orderly prepare the Figure 1 or Figure 2 The source-gate oxide thin-film transistor 10 shown can reduce the device preparation cost and effectively improve the device's electrical hysteresis phenomenon on the basis of ensuring the device's electrical characteristics of high saturation output current, thereby improving the uniformity of the device's electrical characteristics during large-scale preparation of transistor devices.

[0118] In addition, it can be understood that the above steps S220 and S230 are performed in a flip-chip manner based on step S210 (for example, the source electrode layer 15 and the drain electrode layer 16 are first prepared on the substrate 11, and then the semiconductor layer 14, the gate dielectric layer 13 and the gate layer 12 are prepared in sequence), so that the corresponding source-gate oxide thin film transistor is Figure 1 or Figure 2The source-gate oxide thin film transistor 10 is a flip-chip device structure, to which the present application does not impose any limitation.

[0119] In this application, to ensure Figure 3 or Figure 4 The source gate oxide thin film transistor 10 shown can be prepared and formed quickly and orderly to reduce the device preparation cost and effectively improve the device's electrical hysteresis phenomenon on the basis of ensuring the device's electrical characteristics of high saturation output current, thereby improving the uniformity of the device's electrical characteristics during large-scale preparation of transistor devices. The embodiment of the present application achieves the above functions by providing a method for preparing a source gate oxide thin film transistor.

[0120] Please refer to Fig.12 , Fig.12 This is the second flow chart of the method for preparing a source gate oxide thin film transistor provided in the embodiment of the present application. In the embodiment of the present application, Fig.12 The preparation method shown may include steps S310 to S330 to prepare Figure 3 or Figure 4 The source gate oxide thin film transistor 10 is shown.

[0121] Step S310, providing a substrate.

[0122] Step S320, a gate layer, a gate dielectric layer and a semiconductor layer are sequentially stacked on one side of the substrate to obtain an intermediate stage device, wherein the gate layer and the semiconductor layer are both patterned, and the semiconductor layer is prepared using an N-type oxide semiconductor material.

[0123] In this embodiment, the specific execution process of step S320 is consistent with the specific execution process of step S220, and will not be described in detail here.

[0124] Step S330, in the intermediate stage, a source layer is prepared on a side of the device away from the substrate, and the film layer portion of the semiconductor layer not covered by the source layer is conductorized to form a conductorized film layer portion for serving as a drain region, wherein the source layer includes a first source electrode layer and a second source electrode layer in contact with each other, the projection areas of the first source electrode layer and the second source electrode layer on the substrate at least partially overlap, and the second source electrode layer is prepared from a P-type conductor material or a P-type semiconductor material.

[0125] In this embodiment, the film layer portion of the semiconductor layer 14 covered by the source layer 15 is the semiconductor film layer portion 142 mentioned above, the first source electrode layer 151 forms an ohmic contact or a quasi-ohmic contact with the semiconductor film layer portion 142, the second source electrode layer 152 contacts the semiconductor film layer portion 142 to form a potential barrier, and a local area of ​​the semiconductor layer 14 that is in direct contact with the second source electrode layer 152 forms a depletion region 17; the first source electrode layer 151 may at least partially cover the second source electrode layer 152, or the second source electrode layer 152 may at least partially cover the first source electrode layer 151.

[0126] Optionally, please refer to Fig.13 and Fig.14 ,in Fig.13 yes Fig.12 One of the flowchart diagrams of the sub-steps included in step S330 in the embodiment of the present invention, Fig.14 is with Fig.13 In the embodiment of the present application, the step of "preparing and forming a source layer 15 on the side of the device away from the substrate 11 in the intermediate stage" in step S330 may include sub-steps S331 and S332 to prepare and form the source layer 15. Figure 3 The source-gate oxide thin film transistor 10 shown corresponds to a transistor device to be conductively connected.

[0127] Sub-step S331, on the outer surface of the intermediate stage device away from the substrate, a fifth electrode film layer is formed by depositing a P-type conductor material or a P-type semiconductor material based on a magnetron sputtering method or an atomic layer deposition method, and the deposited fifth electrode film layer is patterned by photolithography to obtain a second source electrode layer.

[0128] In this embodiment, Fig.14 (a) is a schematic diagram of a device in which a fifth electrode film layer is prepared on the device at the intermediate stage; Fig.14 (b) is a schematic diagram of a device in which the fifth electrode film layer is patterned into the second source electrode layer 152 using the Lift-Off process, wherein the projection area of ​​the second source electrode layer 152 on the substrate 11 is within the projection area of ​​the semiconductor layer 14 on the substrate 11.

[0129] Sub-step S332, on the outer surface of the second source electrode layer prepared in the intermediate stage device, a sixth electrode film layer is deposited based on a magnetron sputtering method or an atomic layer deposition method, and the deposited sixth electrode film layer is photolithographically patterned so that the patterned first source electrode layer at least partially covers the second source electrode layer, and partially covers the local film layer area of ​​the semiconductor layer not blocked by the second source electrode layer.

[0130] In this embodiment, Fig.14(c) is a schematic diagram of a device in which a sixth electrode film layer is further prepared on the device at the intermediate stage of preparing the second source electrode layer 152; Fig.14 (d) is a schematic diagram of a device in which the sixth electrode film layer is patterned into the first source electrode layer 151 by using the Lift-Off process. Fig.14 The device structure shown in (d) can expose the local film layer area to be conductive (corresponding to the conductive film layer part 141 mentioned above) under the joint coverage of the first source electrode layer 151 and the second source electrode layer 152. Fig.14 The device structure shown in (d) is similar to Figure 3 The source-gate oxide thin film transistor 10 shown corresponds to a transistor device to be conductively connected.

[0131] Optionally, please refer to Fig.15 and Fig.16 ,in Fig.15 yes Fig.12 The second flowchart diagram of the sub-steps included in step S330 in FIG. Fig.16 is with Fig.15 In the embodiment of the present application, the step of "preparing and forming a source layer 15 on the side of the device away from the substrate 11 in the intermediate stage" in step S330 may include sub-steps S333 to S334 to prepare and form a source layer 15 on the side of the device away from the substrate 11 in the intermediate stage. Figure 4 The source-gate oxide thin film transistor 10 shown corresponds to a transistor device to be conductively connected.

[0132] In sub-step S333, a seventh electrode film layer is deposited on the outer surface of the intermediate stage device away from the substrate based on a magnetron sputtering method or an atomic layer deposition method, and the deposited seventh electrode film layer is photolithographically patterned so that the projection area corresponding to the patterned first source electrode layer partially covers the projection area corresponding to the semiconductor layer.

[0133] In this embodiment, Fig.16 (a) is a schematic diagram of a device in which a seventh electrode film layer is prepared on the device at the intermediate stage; Fig.16 (b) is a schematic diagram of a device in which the seventh electrode film layer is patterned into a first source electrode layer 151 by using a Lift-Off process, wherein the projection area of ​​the first source electrode layer 151 on the substrate 11 partially covers the projection area of ​​the semiconductor layer 14 on the substrate 11. Sub-step S334, on the outer surface of the first source electrode layer prepared in the intermediate stage device, an eighth electrode film layer is formed by depositing a P-type conductor material or a P-type semiconductor material based on a magnetron sputtering method or an atomic layer deposition method, and the deposited eighth electrode film layer is patterned by photolithography, so that the patterned second source electrode layer at least partially covers the first source electrode layer, and partially covers the local film area of ​​the semiconductor layer that is not blocked by the first source electrode layer.

[0134] In this embodiment, Fig.16 (c) is a schematic diagram of a device in which an eighth electrode film layer is further prepared on the intermediate stage device after the first source electrode layer 151 is prepared; Fig.16 (d) is a schematic diagram of a device in which the eighth electrode film layer is patterned into the second source electrode layer 152 by using the Lift-Off process. Fig.16 The device structure shown in (d) can expose the local film layer area to be conductive (corresponding to the conductive film layer part 141 mentioned above) under the joint coverage of the first source electrode layer 151 and the second source electrode layer 152. Fig.16 The device structure shown in (d) is similar to Figure 4 The source-gate oxide thin film transistor 10 shown corresponds to a transistor device to be conductively connected.

[0135] And targeting Figure 3 or Figure 4 For the transistor device to be conductorized corresponding to the source-gate oxide thin film transistor 10 shown, the step of "conducting the film layer portion of the semiconductor layer 14 not covered by the source electrode layer 15" may include:

[0136] Using argon plasma to bombard the film layer portion of the semiconductor layer 14 that is not covered by the source electrode layer 15, so as to convert the bombarded film layer portion with semiconductor characteristics into the conductive film layer portion 141;

[0137] Alternatively, on the outer surface of the source layer 15 prepared in the intermediate stage device, at least silicon nitride material among silicon nitride material and silicon dioxide material is deposited to form a passivation layer, and the passivation layer is annealed, so that the film layer portion of the semiconductor layer 14 that is in direct contact with the passivation layer is conductively conductive under the action of hydrogen diffusion doping of the passivation layer, so as to convert the film layer portion of the semiconductor layer 14 that is in direct contact with the passivation layer and has semiconductor properties into the conductive film layer portion 141.

[0138] Therefore, the present application can quickly and orderly prepare the Figure 3 or Figure 4 The source-gate oxide thin-film transistor 10 shown can reduce the device preparation cost and effectively improve the device's electrical hysteresis phenomenon on the basis of ensuring the device's electrical characteristics of high saturation output current, thereby improving the uniformity of the device's electrical characteristics during large-scale preparation of transistor devices.

[0139] The above are only various implementations of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for preparing a source-gate oxide thin film transistor, characterized in that: The preparation method comprises: providing a substrate; A gate layer, a gate dielectric layer and a semiconductor layer are sequentially stacked on one side of the substrate to obtain an intermediate stage device, wherein the gate layer and the semiconductor layer are both patterned, and the semiconductor layer is prepared from an N-type oxide semiconductor material; A source layer and a drain layer spaced apart from each other are prepared on a side of the intermediate stage device away from the substrate; or a source layer is prepared on a side of the intermediate stage device away from the substrate, and the film layer portion of the semiconductor layer not covered by the source layer is conductorized to form a conductorized film layer portion for serving as a drain region; wherein the source layer comprises a first source electrode layer and a second source electrode layer in contact with each other, the first source electrode layer forms an ohmic contact or a quasi-ohmic contact with the semiconductor layer, the second source electrode layer contacts the semiconductor layer to form a potential barrier, and a local area of ​​the semiconductor layer directly in contact with the second source electrode layer forms a depletion region, the projection areas of the first source electrode layer and the second source electrode layer on the substrate at least partially overlap, and the second source electrode layer is prepared from a P-type conductor material or a P-type semiconductor material.

2. The preparation method according to claim 1, characterized in that: The step of sequentially stacking a gate layer, a gate dielectric layer and a semiconductor layer on one side of the substrate to obtain an intermediate stage device comprises: sputtering and depositing a gate layer on a surface of one side of the substrate, and performing photolithography patterning on the deposited gate layer; On the side of the substrate where the gate layer is prepared, a gate dielectric layer is grown based on a plasma enhanced chemical vapor deposition method or an atomic layer deposition method, so that the grown gate dielectric layer covers the gate layer and the side area of ​​the substrate that is not blocked by the gate layer; On the outer surface of the gate dielectric layer away from the substrate, an N-type oxide semiconductor material is deposited to form a semiconductor layer based on magnetron sputtering or atomic layer deposition, and the deposited semiconductor layer is patterned by photolithography to obtain the intermediate stage device.

3. The preparation method according to claim 1, characterized in that: The step of preparing a source layer and a drain layer spaced apart from each other on a side of the device at the intermediate stage away from the substrate comprises: On the outer surface of the intermediate stage device away from the substrate, a first electrode film layer is deposited by using a P-type conductor material or a P-type semiconductor material based on a magnetron sputtering method or an atomic layer deposition method, and the deposited first electrode film layer is patterned by photolithography to obtain the second source electrode layer; wherein the projection area corresponding to the second source electrode layer is within the projection area corresponding to the semiconductor layer; On the outer surface of the second source electrode layer prepared in the intermediate stage device, depositing a second electrode film layer based on a magnetron sputtering method or an atomic layer deposition method, so that the second electrode film layer covers the second source electrode layer and the side area of ​​the semiconductor layer that is not blocked by the second source electrode layer; The deposited second electrode film layer is patterned by photolithography to obtain the first source electrode layer and the drain electrode layer spaced apart from each other, so that the drain electrode layer and the second source electrode layer are spaced apart from each other, and the first source electrode layer is in direct contact with the semiconductor layer and at least partially covers the second source electrode layer.

4. The preparation method according to claim 1, characterized in that: The step of preparing a source layer and a drain layer spaced apart from each other on a side of the device at the intermediate stage away from the substrate comprises: On the outer surface of the intermediate stage device away from the substrate, a third electrode film layer is deposited based on a magnetron sputtering method or an atomic layer deposition method, and the deposited third electrode film layer is patterned by photolithography to obtain a first source electrode layer and a drain electrode layer spaced from each other; On the outer surface of the first source electrode layer and the drain layer prepared in the intermediate stage device, a fourth electrode film layer is formed by depositing a P-type conductor material or a P-type semiconductor material based on a magnetron sputtering method or an atomic layer deposition method, and the deposited fourth electrode film layer is photolithographically patterned so that the patterned second source electrode layer and the drain layer are spaced apart from each other and at least partially cover the first source electrode layer.

5. The preparation method according to claim 1, characterized in that: The step of preparing a source layer on a side of the device at the intermediate stage away from the substrate comprises: On the outer surface of the intermediate stage device away from the substrate, a fifth electrode film layer is formed by depositing a P-type conductor material or a P-type semiconductor material based on a magnetron sputtering method or an atomic layer deposition method, and the deposited fifth electrode film layer is patterned by photolithography to obtain the second source electrode layer; wherein the projection area corresponding to the second source electrode layer is within the projection area corresponding to the semiconductor layer; On the outer surface of the second source electrode layer prepared in the intermediate stage device, a sixth electrode film layer is deposited based on magnetron sputtering or atomic layer deposition, and the deposited sixth electrode film layer is photolithographically patterned so that the patterned first source electrode layer at least partially covers the second source electrode layer and partially covers the local film layer area of ​​the semiconductor layer not blocked by the second source electrode layer.

6. The preparation method according to claim 1, characterized in that: The step of preparing a source layer on a side of the device at the intermediate stage away from the substrate comprises: On the outer surface of the intermediate stage device away from the substrate, a seventh electrode film layer is deposited based on a magnetron sputtering method or an atomic layer deposition method, and the deposited seventh electrode film layer is patterned by photolithography so that a projection area corresponding to the patterned first source electrode layer partially covers a projection area corresponding to the semiconductor layer; On the outer surface of the first source electrode layer prepared in the intermediate stage device, an eighth electrode film layer is formed by depositing a P-type conductor material or a P-type semiconductor material based on a magnetron sputtering method or an atomic layer deposition method, and the deposited eighth electrode film layer is photolithographically patterned so that the patterned second source electrode layer at least partially covers the first source electrode layer, and partially covers the local film layer area of ​​the semiconductor layer not blocked by the first source electrode layer.

7. The preparation method according to any one of claims 1 to 6, characterized in that: The gate layer, the first source electrode layer and the drain electrode layer are each made of any one of copper, molybdenum, cobalt, titanium, tungsten, nickel, chromium, indium tin oxide material and aluminum-doped zinc oxide material; The gate dielectric layer is made of a stack of any one or more materials selected from silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, and zirconium oxide; The N-type oxide semiconductor material is any one of indium gallium zinc oxide, indium zinc oxide, indium zinc tin oxide, rare earth doped indium zinc oxide, indium gallium oxide, zinc oxide, gallium oxide, indium oxide and tin oxide; The second source electrode layer is made of any one of tellurium, telluride, P-type doped silicon material, and P-type doped germanium material.

8. The preparation method according to any one of claims 1 to 6, characterized in that: The thickness of the gate layer is in the range of 10-1000 nm; The thickness of the gate dielectric layer is in the range of 5-500 nm; The thickness of the semiconductor layer is in the range of 5-200 nm; The thickness of the first source electrode layer and the drain electrode layer is in the range of 5-1000 nm; The thickness of the second source electrode layer is in the range of 1-1000 nm, and the width of a non-projected overlapping region of the second source electrode layer relative to the first source electrode layer is less than or equal to 10 μm.

9. A source-gate oxide thin film transistor, characterized in that: The thin film transistor comprises: substrate; A gate layer, a gate dielectric layer and a semiconductor layer are sequentially stacked on one side of the substrate, wherein the gate dielectric layer covers the gate layer, and a material for preparing the semiconductor layer is an N-type oxide semiconductor material; A source layer and a drain layer are spaced apart from each other on the semiconductor layer, wherein the source layer comprises a first source electrode layer and a second source electrode layer in contact with each other, the first source electrode layer forms an ohmic contact or a quasi-ohmic contact with the semiconductor layer, the second source electrode layer contacts the semiconductor layer to form a potential barrier, and a local area of ​​the semiconductor layer that is in direct contact with the second source electrode layer forms a depletion area, the projection areas of the first source electrode layer and the second source electrode layer on the substrate at least partially overlap, and the second source electrode layer is made of a P-type conductor material or a P-type semiconductor material.

10. A source-gate oxide thin film transistor, characterized in that: The thin film transistor comprises: substrate; A gate layer, a gate dielectric layer and a semiconductor layer are sequentially stacked on one side of the substrate, wherein the gate dielectric layer covers the gate layer, and a material for preparing the semiconductor layer is an N-type oxide semiconductor material; A source layer is arranged on a side of the semiconductor layer away from the substrate, wherein the semiconductor layer includes a semiconductor film layer portion and a conductive film layer portion, the source layer includes a first source electrode layer and a second source electrode layer in contact with each other, the first source electrode layer and the second source electrode layer jointly cover the semiconductor film layer portion, the first source electrode layer and the semiconductor film layer portion form an ohmic contact or a quasi-ohmic contact, the projection areas of the first source electrode layer and the second source electrode layer on the substrate at least partially overlap, the second source electrode layer contacts the semiconductor film layer portion to form a potential barrier, and a local area of ​​the semiconductor film layer portion that is in direct contact with the second source electrode layer forms a depletion region, the second source electrode layer is prepared from a P-type conductor material or a P-type semiconductor material, and the conductive film layer portion is used as a drain region of a corresponding thin film transistor.

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