Image sensor including ground region

Abstract

An image sensor is provided. The image sensor includes: a substrate including a plurality of pixels, each of the plurality of pixels including a left sub-pixel and a right sub-pixel; a well region in the substrate on each of the plurality of pixels, the well region connecting the left and right sub-pixels to each other; a pixel separation portion separating the plurality of pixels from each other and extending in the substrate between the left sub-pixel and the right sub-pixel; a left transfer transistor and a first logic transistor on the left sub-pixel; a right transfer transistor and a second logic transistor on the right sub-pixel; and a ground region in the substrate on one of the left and right sub-pixels, and in contact with the well region. A ground region is adjacent to a corner of each of the plurality of pixels.

Description

Technical Field

[0001] The present disclosure relates to an image sensor, and more particularly, to an image sensor including a grounding area. Background Art

[0002] Image sensor is a semiconductor device that converts optical image into electrical signal. Image sensor can be divided into charge coupled device (CCD) type and complementary metal oxide semiconductor (CMOS) type. CMOS type image sensor can be called CMOS image sensor (CIS). CIS can include multiple pixels arranged in two dimensions. Each pixel includes a photodiode (PD). Photodiode is used to convert incident light into electrical signal. Summary of the invention

[0003] One or more embodiments provide an image sensor capable of achieving clear image quality.

[0004] According to one aspect of the embodiment, an image sensor includes: a substrate including a plurality of pixels, each of the plurality of pixels including a left sub-pixel and a right sub-pixel; a well region in the substrate on each of the plurality of pixels, the well region connecting the left sub-pixel and the right sub-pixel to each other; a pixel separator separating the plurality of pixels from each other and extending in the substrate between the left sub-pixel and the right sub-pixel; a left transfer transistor and a first logic transistor on the left sub-pixel; a right transfer transistor and a second logic transistor on the right sub-pixel; and a grounding region in the substrate on one of the left sub-pixel and the right sub-pixel and in contact with the well region. The grounding region is adjacent to a corner of each of the plurality of pixels.

[0005] According to one aspect of the embodiment, an image sensor includes: a substrate including a plurality of pixel groups, each of the plurality of pixel groups including a plurality of pixels arranged in 2×2, each of the plurality of pixels including a left sub-pixel and a right sub-pixel; a well region in the substrate on each of the plurality of pixels, the well region connecting the left sub-pixel and the right sub-pixel to each other; a pixel separator separating the plurality of pixels from each other and extending in the substrate between the left sub-pixel and the right sub-pixel; a left transfer transistor and a left active region on the left sub-pixel; a right transfer transistor and a right active region on the right sub-pixel; a grounding region in the substrate on one of the left sub-pixel and the right sub-pixel and in contact with the well region; and a grounding line extending over the substrate between the plurality of pixel groups. On each of the plurality of pixels, the grounding region is adjacent to the grounding line.

[0006] According to one aspect of the embodiment, an image sensor includes: a substrate having a first surface and a second surface opposite to each other, the substrate including a plurality of pixel groups, each of the plurality of pixel groups including a plurality of pixels arranged in a 2×2 matrix, and each of the plurality of pixels including a left sub-pixel and a right sub-pixel; a first color filter covering one of the plurality of pixel groups on the first surface; a second color filter covering another of the plurality of pixel groups on the first surface; a third color filter covering yet another of the plurality of pixel groups on the first surface; a plurality of microlenses provided on the first color filter, the second color filter, and the third color filter, respectively, and covering each of the plurality of pixels; a well region, in the substrate on each of the plurality of pixels, the well region A left sub-pixel and a right sub-pixel are connected to each other; a pixel separation portion separating the plurality of pixels from each other and extending between the left sub-pixel and the right sub-pixel; a device isolation portion adjacent to the second surface in the substrate, the device isolation portion separating the left active region on the left sub-pixel from the right active region on the right sub-pixel; a left photoelectric conversion region in the substrate on the left sub-pixel of each of the plurality of pixels; a right photoelectric conversion region in the substrate on the right sub-pixel of each of the plurality of pixels; a left transfer transistor on the second surface on the left sub-pixel of each of the plurality of pixels; a right transfer transistor on the second surface on the right sub-pixel of each of the plurality of pixels; and a grounding region in the substrate on one of the left sub-pixel and the right sub-pixel and in contact with the well region. The grounding region is provided in plurality, and the plurality of grounding regions are adjacent to the corners of each of the plurality of pixel groups. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects and features will become more apparent from the following description of embodiments in conjunction with the accompanying drawings.

[0008] Figure 1 A top view showing an image sensor according to some embodiments is shown.

[0009] Figure 2A and Figure 2B Shown along Figure 1 A cross-sectional view taken along line AA'.

[0010] Figure 3 Shown along Figure 1 A cross-sectional view taken along line BB'.

[0011] Figure 4 A top view showing groups of pixels in an image sensor according to some embodiments is shown.

[0012] Figure 5 A top view showing a pixel group in an image sensor according to some embodiments is shown.

[0013] Figure 6 Shows the display Figure 5 A top view of the arrangement of pixel groups and the connection relationship between transistors.

[0014] Figure 7 Shows Figure 6 An enlarged view of portion P1.

[0015] Figure 8 Shows Figure 6 The circuit diagram of the image sensor shown in .

[0016] Fig. 9 Shows Figure 6 An enlarged view of part P2.

[0017] Fig.10 Shown along Fig. 9 A cross-sectional view taken along line CC'.

[0018] Fig.11 Shows Figure 6 An enlarged view of part P2.

[0019] Fig.12 Shown along Fig.11 A cross-sectional view taken along line CC'.

[0020] Fig.13 Shows Figure 6 An enlarged view of part P2.

[0021] Fig.14 Shown along Fig.13 A cross-sectional view taken along line D-D'.

[0022] Fig.15 A top view showing a pixel group in an image sensor according to some embodiments is shown.

[0023] Fig.16 Shows the display Fig.15 A top view of the arrangement of pixel groups and the connection relationship between transistors.

[0024] Fig.17 A top view showing a pixel group in an image sensor according to some embodiments is shown.

[0025] Fig.18 Shows the display Fig.17 A top view of the arrangement of pixel groups and the connection relationship between transistors.

[0026] Fig.19 Shown along Fig.18 A cross-sectional view taken along line EE'.

[0027] Fig. 20 Shows Fig.18The circuit diagram of the image sensor shown in .

[0028] Fig.21 A top view showing a pixel group in an image sensor according to some embodiments is shown.

[0029] Fig. 22 Shows the display Fig.21 A top view of the arrangement of pixel groups and the connection relationship between transistors.

[0030] Fig.23 A top view showing a pixel group in an image sensor according to some embodiments is shown.

[0031] Fig.24 Shows the display Fig.23 A top view of the arrangement of pixel groups and the connection relationship between transistors.

[0032] Fig.25 Shows Fig.24 The circuit diagram of the image sensor shown in .

[0033] Fig.26 A top view showing a pixel group in an image sensor according to some embodiments is shown.

[0034] Fig. 27 Shows the display Fig.26 A top view of the arrangement of pixel groups and the connection relationship between transistors.

[0035] Fig.28 Shows Fig. 27 The circuit diagram of the image sensor shown in .

[0036] Fig.29 A top view showing a pixel group in an image sensor according to some embodiments is shown.

[0037] Fig.30 Shows the display Fig.29 A top view of the arrangement of pixel groups and the connection relationship between transistors.

[0038] Fig.31 A top view showing a pixel group in an image sensor according to some embodiments is shown.

[0039] Fig.32 Shows the display Fig.31 A top view of the arrangement of pixel groups and the connection relationship between transistors.

[0040] Fig.33 A top view showing a pixel group in an image sensor according to some embodiments is shown.

[0041] Fig.34 Shows the display Fig.33 A top view of the arrangement of pixel groups and the connection relationship between transistors.

[0042] Fig.35 A cross-sectional view showing an image sensor according to some embodiments is shown. DETAILED DESCRIPTION

[0043] Some embodiments will now be described in detail with reference to the accompanying drawings to help clearly explain the inventive concept. In this specification, terms such as "first" and "second" can be used to simply distinguish the same or similar parts from each other, and the order of these terms can be changed according to the order of mentioning. Throughout the specification, the same parts are represented by the same reference numerals, and their repeated descriptions are omitted. It will be understood that when an element or layer is referred to as "on" another element or layer, "connected to" or "coupled to" another element or layer, it can be directly on another element or layer, connected or coupled to another element or layer, or there can be an intermediate element or layer. On the contrary, when an element is referred to as "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intermediate element or layer. The embodiments described herein are example embodiments, and therefore, the present disclosure is not limited thereto, and can be implemented in various other forms. Each embodiment provided in the following description does not exclude the association of one or more features of another example or another embodiment that is also provided herein or not provided herein but consistent with the present disclosure.

[0044] Figure 1 A top view showing an image sensor according to some embodiments is shown. Figure 2A and Figure 2B Shown along Figure 1 A cross-sectional view taken along line AA'. Figure 3 Shown along Figure 1 A cross-sectional view taken along line BB'.

[0045] Reference Figure 1 , Figure 2A , Figure 2B and Figure 3 , the substrate 1 may be provided in an image sensor. The image sensor may have both an autofocus function and an image sensor function. The substrate 1 may include a plurality of pixels PX two-dimensionally arranged along a first direction D1 and a second direction D2. Figure 1A pixel PX is depicted as an example. The substrate 1 may have a first surface 1a and a second surface 1b opposite to each other. The substrate 1 may receive light through the second surface 1b. For example, the substrate 1 may receive light incident on the second surface 1b. The substrate 1 may be a single crystal wafer including silicon and / or germanium or a silicon-on-insulator (SOI) substrate. A well region PW may be formed throughout the substrate 1. The well region PW may be doped with an impurity having a first conductivity type. The first conductivity type may be a p-type. The impurity having the first conductivity type may be, for example, boron.

[0046] The substrate 1 may be provided with a pixel separation portion DTI (ie, a pixel separation part) therein that separates and limits the pixels PX. The pixel separation portion DTI may have a grid shape when viewed in a top view. The pixel separation portion DTI may penetrate the substrate 1 to isolate the pixels PX from each other.

[0047] The pixel separation portion DTI may include a separation conductive pattern 10, a separation dielectric pattern 12, and a cover dielectric pattern 14. The separation conductive pattern 10 may be spaced apart from the substrate 1. The separation conductive pattern 10 may include a conductive material having a refractive index different from that of the substrate 1. The separation conductive pattern 10 may include, for example, polysilicon or metal doped with impurities. The separation dielectric pattern 12 may include a dielectric material having a refractive index different from that of the substrate 1. The separation dielectric pattern 12 may be interposed between the separation conductive pattern 10 and the substrate 1. For example, the separation dielectric pattern 12 may include silicon oxide. The cover dielectric pattern 14 may be disposed below the separation conductive pattern 10. The cover dielectric pattern 14 may include, for example, at least one selected from silicon oxide, silicon nitride, and silicon oxynitride.

[0048] A negative bias voltage may be applied to the separation conductive pattern 10. The separation conductive pattern 10 may be used as a common bias line. Therefore, holes that may exist on the surface of the substrate 1 in contact with the pixel separation portion DTI may be captured to improve dark current characteristics.

[0049] One pixel PX may be divided into a left sub-pixel SP (L) and a right sub-pixel SP (R). The left sub-pixel SP (L) and the right sub-pixel SP (R) may be arranged side by side in the second direction D2. The second direction D2 may be parallel to the first surface 1a of the substrate 1. A portion of the pixel separation portion DTI may extend between the left sub-pixel SP (L) and the right sub-pixel SP (R). A cutting area CR may be provided between the left sub-pixel SP (L) and the right sub-pixel SP (R). On the cutting area CR, the pixel separation portion DTI may be cut and disappear.

[0050] The pixel separation portion DTI may isolate one pixel PX from an adjacent pixel PX. At one pixel PX, a left sub-pixel SP(L) and a right sub-pixel SP(R) may be connected to each other through a well region PW.

[0051] The substrate 1 may be provided with a device isolation portion STI adjacent to the first surface 1a. The device isolation portion STI may be formed by a shallow trench isolation method. The device isolation portion STI may be formed as a single layer and a multilayer structure having at least one selected from a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Alternatively, the device isolation portion STI may be an impurity doped region. In this case, the device isolation portion STI may be doped with impurities of the same first conductivity type as the impurities doped in the well region PW.

[0052] The device isolation portion STI may separate active areas ACT1 to ACT4 on the first surface 1a. The device isolation portion STI may be in the substrate 1 at the center of the pixel PX. The left sub-pixel SP(L) may be provided with first to third active areas ACT1 to ACT3 arranged side by side along the first direction D1. The right sub-pixel SP(R) may be provided with first and fourth active areas ACT1 and ACT4 arranged side by side along the first direction D1. The first direction D1 may intersect with the second direction D2. For example, the first direction D1 may be orthogonal to the second direction D2 and may be parallel to the first surface 1a of the substrate 1.

[0053] The first active area ACT1 disposed on the left sub-pixel SP(L) may occupy Figure 1 The first active area ACT1 disposed on the right sub-pixel SP(R) may occupy approximately half of the area of ​​the left sub-pixel SP(L) depicted in FIG. Figure 1 . The first active area ACT1 may be provided on the first side of the left sub-pixel SP(L) and the right sub-pixel SP(R). The first active area ACT1 may be provided with transfer transistors TXL and TXR. The left transfer transistor TXL may be provided on the first active area ACT1 of the left sub-pixel SP(L). The left transfer transistor TXL may include a left transfer gate electrode TGL and a left floating diffusion area FDL adjacent to the left transfer gate electrode TGL. The right transfer transistor TXR may be provided on the first active area ACT1 of the right sub-pixel SP(R). The right transfer transistor TXR may include a right transfer gate electrode TGR and a right floating diffusion area FDR adjacent to the right transfer gate electrode TGR. Each of the left floating diffusion area FDL and the right floating diffusion area FDR may be doped with an impurity having a second conductivity type opposite to the first conductivity type. For example, the second conductivity type may be an n-type, and the impurity having the second conductivity type may be phosphorus or arsenic.

[0054] Each of the left transfer gate electrode TGL and the right transfer gate electrode TGR may include a main portion PP1 disposed on the first surface 1a of the substrate 1 and a protrusion PP2 extending into the substrate 1. Each of the left transfer gate electrode TGL and the right transfer gate electrode TGR may include two protrusions PP2, but the embodiment is not limited thereto. The number of protrusions PP2 may be one, or three or more. In some embodiments, each of the left transfer gate electrode TGL and the right transfer gate electrode TGR may be a planar type without the protrusion PP2. The gate dielectric layer Gox may be interposed between the left transfer gate electrode TGL and the substrate 1 and between the right transfer gate electrode TGR and the substrate 1. The gate dielectric layer Gox may include a single layer or multiple layers of at least one selected from silicon oxide, metal oxide, silicon nitride, and silicon oxynitride.

[0055] The second active area ACT2 may have a shape that is elongated in the third direction D3. The third direction D3 may intersect the first direction D1 and the second direction D2, and may be parallel to the first surface 1a of the substrate 1. The first logic transistor AX1 may be disposed on the second active area ACT2. The second active area ACT2 may be referred to as a left active area. The first logic gate electrode AT1 may extend across the second active area ACT2 in a fourth direction D4. The fourth direction D4 may intersect the first direction D1, the second direction D2, and the third direction D3, and may be parallel to the first surface 1a of the substrate 1. The fourth direction D4 may intersect the third direction D3. On the second active area ACT2, the first source / drain area SD1 and the second source / drain area SD2 may be disposed on the opposite side of the first logic gate electrode AT1. The first logic transistor AX1 may be composed of the first logic gate electrode AT1 and the first source / drain area SD1 and the second source / drain area SD2 on the opposite side of the first logic gate electrode AT1.

[0056] The grounding region GN may be disposed on the third active region ACT3. The grounding region GN may be doped with impurities of the first conductivity type that are the same as those of the well region PW, and may have an impurity concentration greater than that of the well region PW. The grounding region GND may be in direct contact with the well region PW. The grounding region GN may be adjacent to one of the four corners of one pixel PX. Figure 1 As shown, the grounding area GN may be adjacent to a corner at an upper left end of the pixel PX.

[0057] The fourth active area ACT4 may have a shape elongated in the first direction D1. The second logic transistor AX2 may be disposed on the fourth active area ACT4. The fourth active area ACT4 may be referred to as a right active area. The second logic gate electrode AT2 may extend across the fourth active area ACT4 in the second direction D2. On the fourth active area ACT4, the first source / drain area SD1 and the second source / drain area SD2 may be disposed on the opposite side of the second logic gate electrode AT2. The first source / drain area SD1 and the second source / drain area SD2 may be doped with impurities having a second conductivity type. The second logic transistor AX2 may be composed of the second logic gate electrode AT2 and the first source / drain area SD1 and the second source / drain area SD2 on the opposite side of the second logic gate electrode AT2.

[0058] The gate dielectric layer Gox may be interposed between the first logic gate electrode AT1 and the substrate 1. The gate dielectric layer Gox may be interposed between the second logic gate electrode AT2 and the substrate 1. The first logic gate electrode AT1 may have a Figure 2A Alternatively, Figure 2B As shown, a portion of the first logic gate electrode AT1 may extend into the device isolation portion STI to cover the side surface of the substrate 1. The second logic gate electrode AT2 may have a Figure 2A or Figure 2B The shape of the first logic gate electrode AT1 is the same shape. Each of the first logic transistor AX1 and the second logic transistor AX2 may independently be a reset transistor, a selection transistor, a source follower transistor, or a dummy transistor. The reset transistor may be referred to as a double conversion transistor.

[0059] On the left sub-pixel SP (L), the left photoelectric conversion region PD (L) may be disposed in the substrate 1. On the right sub-pixel SP (R), the right photoelectric conversion region PD (R) may be disposed in the substrate 1. The well region PW may be disposed between the left photoelectric conversion region PD (L) and the right photoelectric conversion region PD (R). On the cutting region CR, the device isolation portion STI may be disposed on the first surface 1a of the substrate 1. The left photoelectric conversion region PD (L) and the right photoelectric conversion region PD (R) may be doped with impurities having a second conductivity type opposite to the first conductivity type. For example, the left photoelectric conversion region PD (L) and the right photoelectric conversion region PD (R) may be doped with n-type impurities such as phosphorus or arsenic. The n-type impurity region of each of the left photoelectric conversion region PD (L) and the right photoelectric conversion region PD (R) and the p-type impurity region of the well region PW surrounding it may form a PN junction, thereby constituting a photodiode. When light is incident thereon, the PN junction may generate an electron-hole pair.

[0060] The first surface 1a may be provided with a first interlayer dielectric layer IL1, a second interlayer dielectric layer IL2, a third interlayer dielectric layer IL3, and a fourth interlayer dielectric layer IL4 stacked in sequence. Each of the first interlayer dielectric layer IL1, the second interlayer dielectric layer IL2, the third interlayer dielectric layer IL3, and the fourth interlayer dielectric layer IL4 may have a single-layer or multi-layer structure of at least one selected from silicon oxide, silicon nitride, silicon oxynitride, and porous silicon.

[0061] The first interlayer dielectric layer IL1 may cover the gate electrodes TGL, TGR, AT1, and AT2. The first interlayer dielectric layer IL1, the second interlayer dielectric layer IL2, and the third interlayer dielectric layer IL3 may have contacts CT therein. The first interlayer dielectric layer IL1, the second interlayer dielectric layer IL2, the third interlayer dielectric layer IL3, and the fourth interlayer dielectric layer IL4 may have wirings IT therebetween.

[0062] The fixed charge layer 40 may be disposed on the second surface 1b and in contact with the second surface 1b. The fixed charge layer 40 may be formed by a metal oxide layer containing oxygen in an amount less than its stoichiometric ratio or a metal fluoride layer containing fluorine in an amount less than its stoichiometric ratio. Therefore, the fixed charge layer 40 may have a negative fixed charge. The fixed charge layer 40 may be formed by one of a metal oxide and a metal fluoride (which includes at least one metal selected from hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y) and lanthanide elements). Hole accumulation may occur around the fixed charge layer 40. Therefore, dark current and white spots can be effectively reduced. For example, the fixed charge layer 40 may be one or both of an aluminum oxide layer and a hafnium oxide layer.

[0063] The anti-reflection layer 42 may be disposed on the fixed charge layer 40. The anti-reflection layer 42 may include, for example, silicon nitride. The light shielding grid pattern 44 and the low refractive index pattern 46 may be sequentially stacked on the anti-reflection layer 42. When viewed in a top view, the light shielding grid pattern 44 and the low refractive index pattern 46 may have a grid shape and may overlap the pixel separation portion DTI. The light shielding grid pattern 44 and the low refractive index pattern 46 may expose the anti-reflection layer 42. The first color filter CF1 may be disposed on the anti-reflection layer 42. The microlens ML may be disposed on the first color filter CF1. One microlens ML may cover one pixel PX.

[0064] The light shielding grid pattern 44 may include a light-impermeable material such as titanium. The sidewalls of the low refractive index pattern 46 may be aligned with the sidewalls of the light shielding grid pattern 44. The light shielding grid pattern 44 and the low refractive index pattern 46 may prevent crosstalk between adjacent pixels PX. The low refractive index pattern 46 may include an organic material. The low refractive index pattern 46 may have a refractive index smaller than that of the first color filter CF1. For example, the low refractive index pattern 46 may have a refractive index equal to or less than about 1.3.

[0065] The first color filter CF1 may include a photoresist material to which a dye or pigment is added. The first color filter CF1 may have one of blue, red, and green. Alternatively, the first color filter CF1 may have one of cyan, yellow, and magenta.

[0066] The grounding region GN may be disposed at a corner portion of the pixel PX. Since the left sub-pixel SP(L) and the right sub-pixel SP(R) are connected to each other through the well region PW, even when the grounding region GN is disposed only on one of the left sub-pixel SP(L) and the right sub-pixel SP(R), the left sub-pixel SP(L) and the right sub-pixel SP(R) may all be electrically grounded.

[0067] The grounding region GN is not disposed on the cutting region CR, so that the gate width of the second logic transistor AX2 can be prevented from being reduced. The output of the second logic transistor AX2 can be increased and the random telegram signal (RTS) can be improved, so that the image sensor can achieve clear image quality. In addition, since the grounding region GN is not disposed on the cutting region CR, the auto focus (AF) segregation ratio can be increased to perform an excellent auto focus function.

[0068] Figure 4 A top view showing groups of pixels in an image sensor according to some embodiments is shown.

[0069] Reference Figure 4 , the substrate 1 may include a plurality of pixel groups GP. The pixel groups GP may be arranged two-dimensionally along a first direction D1 and a second direction D2. Each pixel group GP may include pixels PX arranged in a 2×2 matrix. Each pixel PX may include a left sub-pixel SP (L) and a right sub-pixel SP (R). Each pixel PX may have Figures 1 to 3The structure depicted in FIG. The pixel separator DTI may isolate the pixels PX from each other. The pixel separator DTI may separate the pixel groups GP from each other. One of the pixel groups GP may be covered by the first color filter CF1. Another of the pixel groups GP may be covered by the second color filter CF2. Yet another of the pixel groups GP may be covered by the third color filter CF3. The first color filter CF1 to the third color filter CF3 may have different colors from each other. The color filters CF1 to CF3 may be arranged in a 2×2 tetra pattern. The corner of each pixel group GP may correspond to or be adjacent to the corner of each of the color filters CF1 to CF3.

[0070] Figure 5 A top view showing a pixel group in an image sensor according to some embodiments is shown. Figure 6 Shows the display Figure 5 A top view of the arrangement of pixel groups and the connection relationship between transistors. Figure 7 Shows Figure 6 An enlarged view of part P1. Figure 8 Shows Figure 6 The circuit diagram of the image sensor shown in .

[0071] Reference Figures 5 to 8 , one pixel group GP may include pixels PX1 to PX4 arranged in a 2×2 matrix. One pixel group GP may include a first pixel PX1, a second pixel PX2, a third pixel PX3, and a fourth pixel PX4. The first pixel PX1 and the second pixel PX2 may be arranged side by side in the second direction D2 to form a first row. The third pixel PX3 and the fourth pixel PX4 may be arranged side by side in the second direction D2 to form a second row.

[0072] The arrangement of the active areas ACT1 to ACT4 disposed on the first pixel PX1 and the third pixel PX3 may be mirror-symmetrical to the arrangement of the active areas ACT1 to ACT4 disposed on the second pixel PX2 and the fourth pixel PX4. For example, on the first pixel PX1 and the third pixel PX3, the first active area ACT1 to the third active area ACT3 may be disposed on the left sub-pixel SP(L), but on the second pixel PX2 and the fourth pixel PX4, the first active area ACT1 to the third active area ACT3 may be disposed on the right sub-pixel SP(R).

[0073] The arrangement of the active areas ACT1 to ACT4 disposed on the first pixel PX1 and the second pixel PX2 may be symmetrical with the arrangement of the active areas ACT1 to ACT4 disposed on the third pixel PX3 and the fourth pixel PX4. For example, on the left sub-pixel SP(L) of the first pixel PX1 and the right sub-pixel SP(R) of the second pixel PX2, the first active area ACT1 to the third active area ACT3 may be disposed along the first direction D1. On the left sub-pixel SP(L) of the third pixel PX3 and the right sub-pixel SP(R) of the fourth pixel PX4, the first active area ACT1 to the third active area ACT3 may be disposed in a direction opposite to the first direction D1. On the first pixel PX1 to the fourth pixel PX4, the grounding area GN may be disposed in the third active area ACT3. When observed in a top view, on one pixel group GP, the grounding area GN may be correspondingly disposed adjacent to the four corners of one pixel group GP. As shown in FIG. Figure 4 As shown, when one pixel group GP is covered by one of the color filters CF1, CF2, and CF3, the grounding region GN of one pixel group GP may be disposed adjacent to a corner of one color filter when viewed in a top plan view.

[0074] Reference Figure 5 , on the left sub-pixel SP(L) of the first pixel PX1, the first left floating diffusion region FDL1 and the first left transfer gate electrode TGL1 may be disposed on the first active region ACT1. The first left floating diffusion region FDL1 and the first left transfer gate electrode TGL1 may constitute Figure 8 The first left transfer transistor TXL1 of the embodiment of the present invention may be provided. The first reset gate electrode RG1 may extend across the second active region ACT2 in the fourth direction D4. The first reset gate electrode RG1 and the first source / drain region SD1 and the second source / drain region SD2 disposed on opposite sides thereof may constitute Figure 8 The first reset transistor RX1.

[0075] In the right sub-pixel SP(R) of the first pixel PX1, the first right floating diffusion region FDR1 and the first right transfer gate electrode TGR1 may be disposed on the first active region ACT1. The first right floating diffusion region FDR1 and the first right transfer gate electrode TGR1 may constitute Figure 8 The first right transfer transistor TXR1 of the embodiment of the present invention. The second reset gate electrode RG2 may extend across the fourth active area ACT4 in the second direction D2. The second reset gate electrode RG2 and the first source / drain area SD1 and the second source / drain area SD2 disposed on opposite sides thereof may constitute Figure 8 The second reset transistor RX2.

[0076] In the left sub-pixel SP(L) of the second pixel PX2, the second left floating diffusion area FDL2 and the second left transfer gate electrode TGL2 may be disposed on the first active area ACT1. The second left floating diffusion area FDL2 and the second left transfer gate electrode TGL2 may constitute Figure 8 The third reset gate electrode RG3 may extend across the fourth active area ACT4 in the second direction D2. The third reset gate electrode RG3 and the first source / drain area SD1 and the second source / drain area SD2 disposed on opposite sides thereof may constitute Figure 8 The third reset transistor RX3.

[0077] In the right sub-pixel SP(R) of the second pixel PX2, the second right floating diffusion region FDR2 and the second right transfer gate electrode TGR2 may be disposed on the first active region ACT1. The second right floating diffusion region FDR2 and the second right transfer gate electrode TGR2 may constitute Figure 8 The second right transfer transistor TXR2 of the first dummy gate electrode DM1 may be provided. The first dummy gate electrode DM1 may extend across the second active area ACT2 in the third direction D3. The first dummy gate electrode DM1 and the first source / drain area SD1 and the second source / drain area SD2 disposed on the opposite side thereof may constitute a first dummy transistor. The pixel voltage Vpix or the ground voltage may be applied to the first dummy gate electrode DM1 and the first source / drain area SD1 and the second source / drain area SD2 disposed on the opposite side of the first dummy gate electrode DM1 through the pixel contact VPC.

[0078] In the left sub-pixel SP(L) of the third pixel PX3, the third left floating diffusion region FDL3 and the third left transfer gate electrode TGL3 may be disposed on the first active region ACT1. The third left floating diffusion region FDL3 and the third left transfer gate electrode TGL3 may constitute Figure 8 The selection gate electrode SEL may extend across the second active region ACT2 in the third direction D3. The selection gate electrode SEL and the first source / drain region SD1 and the second source / drain region SD2 disposed on opposite sides thereof may constitute Figure 8 of the selection transistor SLX.

[0079] In the right sub-pixel SP(R) of the third pixel PX3, the third right floating diffusion region FDR3 and the third right transfer gate electrode TGR3 may be disposed on the first active region ACT1. The third right floating diffusion region FDR3 and the third right transfer gate electrode TGR3 may constitute Figure 8 The third right transfer transistor TXR3.

[0080] In the left sub-pixel SP(L) of the fourth pixel PX4, the fourth left floating diffusion region FDL4 and the fourth left transfer gate electrode TGL4 may be disposed on the first active region ACT1. The fourth left floating diffusion region FDL4 and the fourth left transfer gate electrode TGL4 may constitute Figure 8 The fourth left transfer transistor TXL4.

[0081] The source follower gate electrode SF may extend in the second direction D2 to extend across the fourth active area ACT4 of the right sub-pixel SP(R) of the third pixel PX3 and the fourth active area ACT4 of the left sub-pixel SP(L) of the fourth pixel PX4. The source follower gate electrode SF may extend in the second direction D2 across the pixel separation portion DTI between the third pixel PX3 and the fourth pixel PX4. The width of the source follower gate electrode SF in the second direction D2 may be greater than the width of the second reset gate electrode RG2 or the third reset gate electrode RG3 in the second direction D2. The source follower gate electrode SF and the first source / drain area SD1 and the second source / drain area SD2 disposed on opposite sides thereof may constitute Figure 8 Since the source follower transistor SFX extends across two fourth active regions ACT4 adjacent to each other, there may be a circuit structure that is the same as a circuit structure in which two source follower transistors SFX are connected in parallel. This structure may constitute a fingered type source follower transistor SFX, which may reduce signal noise.

[0082] Among other transfer transistors, reset transistors, and selection transistors, the source follower transistor may be most sensitive to the influence of the intrinsic noise of the transistor (such as thermal noise and flicker noise). The noise at the source follower transistor may be transmitted to the internal circuit, so the image quality may deteriorate. Since the source follower transistor SFX is formed as a finger type, the influence of the intrinsic noise of the transistor (such as thermal noise and flicker noise) can be reduced to reduce signal noise and satisfactorily read the potential of the floating diffusion (FD) connection line FDC.

[0083] In the right sub-pixel SP(R) of the fourth pixel PX4, the fourth right floating diffusion region FDR4 and the fourth right transfer gate electrode TGR4 may be disposed on the first active region ACT1. The fourth right floating diffusion region FDR4 and the fourth right transfer gate electrode TGR4 may constitute Figure 8The fourth right transfer transistor TXR4 of the second dummy gate electrode DM2 may be provided. The second dummy gate electrode DM2 may extend across the second active area ACT2 in the fourth direction D4. The second dummy gate electrode DM2 and the first source / drain area SD1 and the second source / drain area SD2 disposed on the opposite side thereof may constitute a second dummy transistor. The pixel voltage Vpix or the ground voltage may be applied to the second dummy gate electrode DM2 and the first source / drain area SD1 and the second source / drain area SD2 disposed on the opposite side of the second dummy gate electrode DM2 through the pixel contact VPC.

[0084] The dummy gate electrodes DM1 and DM2 may be formed to prevent load effect failure during gate electrode formation. In addition, when the pixel voltage Vpix or the ground voltage is applied to all the dummy gate electrodes DM1 and DM2 and the first source / drain region SD1 and the second source / drain region SD2 on the opposite sides thereof, signal noise of the wiring IT adjacent thereto may be prevented or minimized.

[0085] Reference Figures 6 to 8 , Figure 5 The pixel groups GP may be arranged two-dimensionally along the first direction D1 and the second direction D2. In some embodiments, Figure 5 The pixel groups GP may be arranged to achieve mirror symmetry along the first direction D1 and the second direction D2.

[0086] The pixel group GP may be provided with a ground line GNL therebetween. The ground line GNL may extend along the first direction D1. The ground line GNL may be connected to the ground region GN through a contact CT and a wiring IT.

[0087] The pixel group GP may include a first pixel group GP(1) and a second pixel group GP(2) adjacent to each other in the first direction D1. Figure 4 , Figure 6 and Figure 7 , the first pixel group GP(1) may be covered by the first color filter CF1. The second pixel group GP(2) may be covered by the second color filter CF2. The first pixel group GP(1) may detect the first color light. The second pixel group GP(2) may detect the second color light.

[0088] The floating diffusion regions FDL1 to FDL4 and FDR1 to FDR4 disposed on the first pixel group GP(1) may all be connected to the FD connection line FDC, and the FD connection line FDC may be connected to the source follower gate electrode SF disposed on the first pixel group GP(1). Since the floating diffusion regions FDL1 to FDL4 and FDR1 to FDR4 are disposed adjacent to each other, the FD connection line FDC may have a relatively short length, and thus the noise of the image sensor may be reduced.

[0089] The FD connection line FDC can be connected to the source / drain region on one side of the third reset gate electrode RG3 of the second pixel group GP(2) that detects light whose color is different from the color of the light detected by the first pixel group GP(1). This connection structure can make the FD connection line FDC have a relatively short length. The parasitic capacitance between the FD connection line FDC and its adjacent wiring IT can be reduced, so that the signal noise can be reduced.

[0090] According to an operation mode of the image sensor, the first to fourth left transfer transistors TXL1 to TXL4 and the first to fourth right transfer transistors TXR1 to TXR4 may be turned on sequentially, or some of the transfer transistors TXL1 to TXL4 and TXR1 to TXR4 may be turned on selectively or simultaneously.

[0091] The first reset transistor RX1 to the third reset transistor RX3 can be connected in series through the wiring IT. The first reset transistor RX1 to the third reset transistor RX3 can be arranged interchangeably. The number of the first reset transistor RX1 to the third reset transistor RX3 that is turned on can be changed depending on the illumination of the image sensor operation. When the image sensor operates under high illumination, the first reset transistor RX1 to the third reset transistor RX3 can all be turned on. Therefore, the image sensor can have an increased full well capacity (FWC). When the image sensor operates under low illumination, only one of the first reset transistor RX1 to the third reset transistor RX3 can be turned on. At least one of the first reset transistor RX1 to the third reset transistor RX3 can be referred to as a dual conversion transistor.

[0092] On the first pixel group GP(1), one terminal (or source / drain region) of a source follower transistor SFX including a source follower gate electrode SF can be connected to one terminal (or source / drain region) of a selection transistor SLX including a selection gate electrode SEL. The other terminal (or source / drain region) of the selection transistor SLX can be connected to an output line Vout through an output contact VOC. The output contact VOC can be set adjacent to the ground line GNL, and thus the ground line GNL can be used as an electrical shield. Therefore, the output value through the output contact VOC can be unaffected by the adjacent pixel group GP. Therefore, the image sensor can achieve clear image quality.

[0093] Fig. 9 Shows the display Figure 6 An enlarged view of part P2. Fig.10 Shown along Fig. 9 A cross-sectional view taken along line CC'.

[0094] Reference Fig. 9 and Fig.10, the pixel group GP may include a first pixel group GP(1), a third pixel group GP(3), a fourth pixel group GP(4), and a fifth pixel group GP(5) which are adjacent to each other in a clockwise direction. Figure 4 , Figure 6 and Fig. 9 , the first pixel group GP(1) and the fourth pixel group GP(4) may be covered by the first color filter CF1. The third pixel group GP(3) may be covered by the second color filter CF2. The fifth pixel group GP(5) may be covered by the third color filter CF3. The first pixel group GP(1) and the fourth pixel group GP(4) may detect the first color light. The third pixel group GP(3) may detect the second color light. The fifth pixel group GP(5) may detect the third color light.

[0095] The ground line GNL may be disposed between the third pixel group GP(3) and the fourth pixel group GP(4) and between the first pixel group GP(1) and the fifth pixel group GP(5). The ground area GN may be gathered toward the center between the first pixel group GP(1), the third pixel group GP(3), the fourth pixel group GP(4) and the fifth pixel group GP(5).

[0096] The grounding regions GN of the first pixel group GP(1), the third pixel group GP(3), the fourth pixel group GP(4) and the fifth pixel group GP(5) may be adjacent and spaced apart from the ground line GNL at the same distance. The grounding region GN may be connected to the ground line GNL through a contact CT and a wiring IT. A second dummy gate electrode DM2 adjacent to the grounding region GN may be disposed on the fourth pixel PX4 of the third pixel group GP(3). A first dummy gate electrode DM1 adjacent to the grounding region GN may be disposed on the second pixel PX2 of the first pixel group GP(1). A selection gate electrode SEL adjacent to the grounding region GN may be disposed on the third pixel PX3 of the fourth pixel group GP(4). A first reset gate electrode RG1 adjacent to the grounding region GN may be disposed on the first pixel PX1 of the fifth pixel group GP(5).

[0097] The wiring IT may include a first wiring IT(1) and a second wiring IT(2). The first wiring IT(1) may extend in the second direction D2 to connect the grounding region GN of the fourth pixel PX4 in the third pixel group GP(3) to the grounding region GN of the third pixel PX3 in the fourth pixel group GP(4). The second wiring IT(2) may extend in the second direction D2 to connect the grounding region GN of the second pixel PX2 in the first pixel group GP(1) to the grounding region GN of the first pixel PX1 in the fifth pixel group GP(5). The first wiring IT(1) and the second wiring IT(2) may be spaced apart from each other in the first direction D1. The first wiring IT(1) and the second wiring IT(2) may be disposed between the first interlayer dielectric layer IL1 and the second interlayer dielectric layer IL2. The grounding line GNL may be located between the second interlayer dielectric layer IL2 and the third interlayer dielectric layer IL3. The grounding line GNL may intersect with the first wiring IT(1) and the second wiring IT(2) and be connected to the first wiring IT(1) and the second wiring IT(2).

[0098] Fig.11 Shows the display Figure 6 An enlarged view of part P2. Fig.12 Shown along Fig.11 A cross-sectional view taken along line CC'.

[0099] Reference Fig.11 and Fig.12 , in the case of Fig. 9 In the image sensor with pixel arrangement shown in FIG. 1 , the ground pattern ITP may be in contact with four grounding regions GN adjacent to each other. For example, the ground pattern ITP may be in contact with the grounding regions GN of the first pixel group GP(1), the third pixel group GP(3), the fourth pixel group GP(4), and the fifth pixel group GP(5). When viewed in a top view, the ground pattern ITP may have an octagonal shape. However, the embodiment is not limited thereto, and the ground pattern ITP may have a square or circular shape. In addition, the ground line GNL extends across the ground pattern ITP. The ground pattern ITP may be formed by Figure 2A The first logic gate electrode AT1 depicted in FIG. 1 may be formed of the same material with the same thickness. The ground pattern ITP and the first logic gate electrode AT1 may be formed of impurity-doped polysilicon. The first logic gate electrode AT1 may have a first thickness T1, and the ground pattern ITP may have a second thickness T2. The second thickness T2 may be about 0.9 times to about 1.1 times the first thickness T1. The ground pattern ITP and the first logic gate electrode AT1 may be located at the same height and may be covered by the first interlayer dielectric layer IL1. Other configurations may be similar to those of reference 1. Figures 9 and 10 The configurations discussed are the same or similar.

[0100] Fig.13Shows the display Figure 6 An enlarged view of part P2. Fig.14 Shown along Fig.13 A cross-sectional view taken along line D-D'.

[0101] Reference Fig.13 and Fig.14 , in the case of Fig. 9 In the image sensor with the pixel arrangement shown, the ground pattern ITP may contact four grounding regions GN adjacent to each other. For example, the ground pattern ITP may contact the grounding regions GN of the first pixel group GP(1), the third pixel group GP(3), the fourth pixel group GP(4), and the fifth pixel group GP(5). When viewed in a top view, the ground pattern ITP may have an "X" shape. The ground pattern ITP may extend in a fourth direction D4 to extend across the second active region ACT2 of the fourth pixel PX4 in the third pixel group GP(3). The gate dielectric layer Gox may be interposed between the second active region ACT2 and the ground pattern ITP. The ground pattern ITP on the second active region ACT2 may correspond to Fig. 9 The ground pattern ITP may extend in a direction opposite to the third direction D3 to extend across the second active area ACT2 of the second pixel PX2 in the first pixel group GP(1). The gate dielectric layer Gox may be interposed between the second active area ACT2 and the ground pattern ITP. The ground pattern ITP on the second active area ACT2 may correspond to Fig. 9 The other configurations may be the same or similar to those discussed above.

[0102] Fig.15 A top view showing a pixel group in an image sensor according to some embodiments is shown. Fig.16 Shows the display Fig.15 A top view of the arrangement of pixel groups and the connection relationship between transistors. Fig.16 The circuit diagram of the image sensor shown in Figure 8 The circuit diagram is the same.

[0103] Reference Fig.15 , one pixel group GP may include first to fourth pixels PX1 to PX4 arranged in a 2×2 arrangement. On the left sub-pixel SP(L) of the first pixel PX1, the first dummy gate electrode DM1 may extend across the second active area ACT2 in the fourth direction D4. On the right sub-pixel SP(R) of the first pixel PX1, the selection gate electrode SEL may extend across the fourth active area ACT4 in the second direction D2.

[0104] On the left subpixel SP(L) of the second pixel PX2, the first reset gate electrode RG1 may extend across the fourth active area ACT4 in the second direction D2. On the right subpixel SP(R) of the second pixel PX2, the second reset gate electrode RG2 may extend across the second active area ACT2 in the third direction D3.

[0105] On the left sub-pixel SP(L) of the third pixel PX3, the second dummy gate electrode DM2 may extend across the second active area ACT2 in the third direction D3. On the right sub-pixel SP(R) of the fourth pixel PX4, the third reset gate electrode RG3 may extend across the second active area ACT2 in the fourth direction D4. Other configurations may be the same as those described above. Figure 4 and Figure 5 The configurations discussed are the same or similar.

[0106] Reference Fig.16 , Fig.15 The pixel groups GP may be arranged two-dimensionally along the first direction D1 and the second direction D2. In some embodiments, Fig.15 The pixel groups GP may be arranged to achieve mirror symmetry along the first direction D1 and the second direction D2.

[0107] Still refer to Fig.16 , the pixel group GP may include a first pixel group GP(1) and a second pixel group GP(2) adjacent to each other in the first direction D1. A single FD connection line FDC may establish a connection between floating diffusion regions FDL1 to FDL4 and FDR1 to FDR4 provided on the first pixel group GP(1), a source follower gate electrode SF, and a source / drain region on one side of the third reset gate electrode RG3. One or more wirings IT may establish a series connection between a third reset transistor RX3 provided on the first pixel group GP(1) and a first reset transistor RX1 and a second reset transistor RX2 provided on the second pixel group GP(2). Another of the wirings IT may connect a terminal of a source follower transistor SFX provided on the first pixel group GP(1) to a terminal of a selection transistor SLX provided on the second pixel group GP(2). Other connection structures may be the same as those described with reference to FIG. Figures 5 to 14 The same or similar to those discussed.

[0108] Fig.17 A top view showing a pixel group in an image sensor according to some embodiments is shown. Fig.18 Shows the display Fig.17 A top view of the arrangement of pixel groups and the connection relationship between transistors. Fig.19 Shown along Fig.18 A cross-sectional view taken along line EE'. Fig. 20 Show Fig.18The circuit diagram of the image sensor shown in .

[0109] Reference Figures 17 to 20 , one pixel group GP may include first to fourth pixels PX1 to PX4 arranged in a 2×2 arrangement. On the left sub-pixel SP(L) of the first pixel PX1, the first capacitor region CP1 may be disposed on the second active region ACT2. Fig.18 and Fig.19 , the first capacitor region CP1 may be doped with impurities having a second conductivity type opposite to the first conductivity type of the impurities doped in the well region PW. The first capacitor region CP1 may be a junction capacitor. On the right sub-pixel SP(R) of the first pixel PX1, the first reset gate electrode RG1 may extend across the fourth active region ACT4 in the second direction D2.

[0110] On the left subpixel SP(L) of the second pixel PX2, the second reset gate electrode RG2 may extend in the second direction D2 across the fourth active area ACT4. On the right subpixel SP(R) of the second pixel PX2, the first dummy gate electrode DM1 may extend in the third direction D3 across the second active area ACT2.

[0111] On the left sub-pixel SP (L) of the third pixel PX3, the selection gate electrode SEL may extend across the second active area ACT2 in the third direction D3. On the right sub-pixel SP (R) of the fourth pixel PX4, the second dummy gate electrode DM2 may extend across the second active area ACT2 in the fourth direction D4. One pixel group GP may include two reset transistors RX1 and RX2 and does not include a third reset transistor RX3. Other configurations may be the same as those described above with reference to Figure 4 and Figure 5 The configurations discussed are the same or similar.

[0112] Reference Fig.18 , Fig.17 The pixel groups GP may be arranged two-dimensionally along the first direction D1 and the second direction D2. In some embodiments, Fig.17 The pixel groups GP may be arranged to achieve mirror symmetry along the first direction D1 and the second direction D2.

[0113] Still refer to Fig.18, the pixel group GP may include a first pixel group GP(1) and a second pixel group GP(2) adjacent to each other in a first direction D1. A single PD connection line FDC may establish a connection between floating diffusion regions FDL1 to FDL4 and FDR1 to FDR4 provided on the first pixel group GP(1), a source follower gate electrode SF, and a source / drain region on one side of a second reset gate electrode RG2 provided on the second pixel group GP(2). One or more wirings IT may establish a series connection between a first reset transistor RX1 and a second reset transistor RX2 provided on the second pixel group GP(2) and a first capacitor region CP1. Another of the wirings IT may connect a terminal of a source follower transistor SFX provided on the first pixel group GP(1) to a terminal of a selection transistor SLX provided on the first pixel group GP(1). Other connection structures may be the same as those described with reference to FIG. Figures 5 to 14 The same or similar to those discussed.

[0114] Fig.21 A top view showing a pixel group in an image sensor according to some embodiments is shown. Fig. 22 Shows the display Fig.21 A top view of the arrangement of pixel groups and the connection relationship between transistors. Fig. 22 The circuit diagram of the image sensor shown in Fig. 20 The circuit diagram is the same.

[0115] Reference Fig.21 and Fig. 22 , one pixel group GP may include first to fourth pixels PX1 to PX4 arranged in a 2×2 arrangement. On the left sub-pixel SP(L) of the first pixel PX1, the first dummy gate electrode DM1 may extend across the second active area ACT2 in the fourth direction D4. On the right sub-pixel SP(R) of the first pixel PX1, the selection gate electrode SEL may extend across the fourth active area ACT4 in the second direction D2.

[0116] On the left sub-pixel SP(L) of the second pixel PX2, the first capacitor region CP1 may be disposed on the fourth active region ACT4. The first capacitor region CP1 may be a junction capacitor. On the right sub-pixel SP(R) of the second pixel PX2, the first reset gate electrode RG1 may extend across the second active region ACT2 in the third direction D3.

[0117] On the left sub-pixel SP(L) of the third pixel PX3, the second dummy gate electrode DM2 may extend across the second active area ACT2 in the third direction D3. On the right sub-pixel SP(R) of the fourth pixel PX4, the second reset gate electrode RG2 may extend across the second active area ACT2 in the fourth direction D4. Other configurations may be similar to those of reference 1. Fig.17The configurations discussed are the same or similar.

[0118] Reference Fig. 22 , Fig.21 The pixel groups GP may be arranged two-dimensionally along the first direction D1 and the second direction D2. In some embodiments, Fig.21 The pixel groups GP may be arranged to achieve mirror symmetry along the first direction D1 and the second direction D2.

[0119] Still refer to Fig. 22 , the pixel group GP may include a first pixel group GP(1) and a second pixel group GP(2) that are adjacent to each other in the first direction D1. A single FD connection line FDC may establish a connection between floating diffusion regions FDL1 to FDL4 and FDR1 to FDR4 provided on the first pixel group GP(1), a source follower gate electrode SF, and a source / drain region on one side of the second reset gate electrode RG2. One or more wirings IT may establish a series connection between a second reset transistor RX2 provided on the first pixel group GP(1), a first reset transistor RX1 provided on the second pixel group GP(2), and a first capacitor region CP1. Another of the wirings IT may connect a terminal of a source follower transistor SFX provided on the first pixel group GP(1) to a terminal of a selection transistor SLX provided on the second pixel group GP(2). Other connection structures may be the same as those described with reference to FIG. Figures 17 to 20 The same or similar to those discussed.

[0120] Fig.23 A top view showing a pixel group in an image sensor according to some embodiments is shown. Fig.24 Shows the display Fig.23 A top view of the arrangement of pixel groups and the connection relationship between transistors. Fig.25 Shows Fig.24 The circuit diagram of the image sensor shown in .

[0121] Reference Figure 23 to Figure 25 , one pixel group GP may include first to fourth pixels PX1 to PX4 arranged in a 2×2 arrangement. On the left sub-pixel SP(L) of the first pixel PX1, the first dummy gate electrode DM1 may extend across the second active area ACT2 in the fourth direction D4. On the right sub-pixel SP(R) of the first pixel PX1, the selection gate electrode SEL may extend across the fourth active area ACT4 in the second direction D2.

[0122] On the left subpixel SP(L) of the second pixel PX2, the first reset gate electrode RG1 may extend across the fourth active area ACT4 in the second direction D2. On the right subpixel SP(R) of the second pixel PX2, the third dummy gate electrode DM3 may extend across the second active area ACT2 in the third direction D3.

[0123] On the left sub-pixel SP(L) of the third pixel PX3, the second dummy gate electrode DM2 may extend across the second active area ACT2 in the third direction D3. On the right sub-pixel SP(R) of the fourth pixel PX4, the fourth dummy gate electrode DM4 may extend across the second active area ACT2 in the fourth direction D4. One pixel group GP may include one reset transistor RX1 and does not include the second reset transistor RX2 and the third reset transistor RX3. One pixel group GP may include four dummy transistors. Other configurations may be the same as those described above with reference to Fig.21 and Fig. 22 The configurations discussed are the same or similar.

[0124] Reference Fig.24 , Fig.23 The pixel groups GP may be arranged two-dimensionally along the first direction D1 and the second direction D2. In some embodiments, Fig.23 The pixel groups GP may be arranged to achieve mirror symmetry along the first direction D1 and the second direction D2.

[0125] Reference Fig.24 and Fig.25 , the pixel group GP may include a first pixel group GP(1) and a second pixel group GP(2) adjacent to each other in the first direction D1. A single FD connection line FDC may establish a connection between floating diffusion regions FDL1 to FDL4 and FDR1 to FDR4 disposed on the first pixel group GP(1), a source follower gate electrode SF, and a source / drain region on one side of a first reset gate electrode RG1 disposed on the second pixel group GP(2). One of the wirings IT may connect a terminal of a source follower transistor SFX disposed on the first pixel group GP(1) to a terminal of a selection transistor SLX disposed on the second pixel group GP(2). Other connection structures may be the same as those described above with reference to FIG. Fig. 22 The same or similar to those discussed.

[0126] Fig.26 A top view showing a pixel group in an image sensor according to some embodiments is shown. Fig. 27 Shows the display Fig.26 A top view of the arrangement of pixel groups and the connection relationship between transistors. Fig.28 Show Fig. 27 The circuit diagram of the image sensor shown in .

[0127] Reference Figure 26 to Figure 28 , one pixel group GP may include first to fourth pixels PX1 to PX4 arranged in a 2×2 arrangement. On the left sub-pixel SP(L) of the first pixel PX1, the first dummy gate electrode DM1 may extend across the second active area ACT2 in the fourth direction D4. On the right sub-pixel SP(R) of the first pixel PX1, the selection gate electrode SEL may extend across the fourth active area ACT4 in the second direction D2.

[0128] In the left sub-pixel SP(L) of the second pixel PX2, the second source follower gate electrode SF2 may extend across the fourth active area ACT4 in the second direction D2. The second source follower gate electrode SF2 and the first source / drain area SD1 and the second source / drain area SD2 on the opposite sides thereof may constitute Fig.28 On the right sub-pixel SP(R) of the second pixel PX2, the third dummy gate electrode DM3 may extend in the third direction D3 across the second active area ACT2.

[0129] On the left sub-pixel SP(L) of the third pixel PX3, the second dummy gate electrode DM2 may extend in the third direction D3 across the second active area ACT2. The first source follower gate electrode SF1 may extend in the second direction D2 to extend across the fourth active area ACT4 of the right sub-pixel SP(R) in the third pixel PX3 and the fourth active area ACT4 of the left sub-pixel SP(L) in the fourth pixel PX4. The first source follower gate electrode SF1 and the first source / drain area SD1 and the second source / drain area SD2 on the opposite sides thereof may constitute Fig.28 The first source follower gate electrode SF1 may have a width greater than that of the second source follower gate electrode SF2.

[0130] On the right sub-pixel SP(R) of the fourth pixel PX4, the first reset gate electrode RG1 may extend across the second active area ACT2 in the fourth direction D4. One pixel group GP may include a first source follower transistor SFX1 and a second source follower transistor SFX2. One pixel group GP may include three dummy transistors. Other configurations may be similar to those of reference 1. Figure 23 to Figure 25 The configurations discussed are the same or similar.

[0131] Reference Fig. 27 and Fig.28 , Fig.25 The plurality of pixel groups GP may be arranged two-dimensionally along the first direction D1 and the second direction D2. In some embodiments, Fig.25 The pixel groups GP may be arranged to achieve mirror symmetry along the first direction D1 and the second direction D2.

[0132] Still refer to Fig. 27 and Fig.28 , the pixel group GP may include a first pixel group GP(1) and a second pixel group GP(2) adjacent to each other in the first direction D1. A single FD connection line FDC may establish a connection between floating diffusion regions FDL1 to FDL4 and FDR1 to FDR4 disposed on the first pixel group GP(1), a source / drain region on one side of the first reset gate electrode RG1, a first source follower gate electrode SF1, and a second source follower gate electrode SF2 disposed on the second pixel group GP(2). One of the wirings IT may connect a terminal of a first source follower transistor SFX1 disposed on the first pixel group GP(1) to a terminal of a selection transistor SLX disposed on the second pixel group GP(2) and to a terminal of a second source follower transistor SFX2 disposed on the second pixel group GP(2). Other connection structures may be the same as those described above with reference to FIG. Fig.24 The first source follower transistor SFX1 and the second source follower transistor SFX2 may be connected in parallel.

[0133] Fig.29 A top view showing a pixel group in an image sensor according to some embodiments is shown. Fig.30 Shows the display Fig.29 A top view of the arrangement of pixel groups and the connection relationship between transistors. Fig.30 The circuit diagram of the image sensor shown in Figure 8 The circuit diagram is the same.

[0134] Reference Fig.29 and Fig.30 , the arrangement of transistors on a pixel group GP can be Figure 5 The arrangement of the transistors is the same. On the first pixel PX1 and the fourth pixel PX4, the position of the second active area ACT2 may be interchanged with the position of the third active area ACT3 on which the grounding area GN is disposed. On the first pixel PX1, the first active area ACT1, the third active area ACT3, and the second active area ACT2 may be sequentially disposed along the first direction D1. On the fourth pixel PX4, the first active area ACT1, the third active area ACT3, and the second active area ACT2 may be sequentially disposed along a direction opposite to the first direction D1. On the first pixel PX1 and the fourth pixel PX4, the second active area ACT2 may be elongated along the fourth direction D4.

[0135] Reference Fig.30 , Fig.29 The plurality of pixel groups GP may be arranged two-dimensionally along the first direction D1 and the second direction D2. In some embodiments, Fig.29The pixel groups GP may be arranged to achieve mirror symmetry along the first direction D1 and the second direction D2.

[0136] Reference Fig.29 and Fig.30 , the connection relationship between transistors can be compared with the reference Figure 7 The wiring IT connecting the ground region GN to the ground line GNL may be disposed alternately left and right in a zigzag manner along the first direction D1. Other structural features may be the same or similar to those discussed above.

[0137] Fig.31 A top view showing a pixel group in an image sensor according to some embodiments is shown. Fig.32 Shows the display Fig.31 A top view of the arrangement of pixel groups and the connection relationship between transistors. Fig.30 The circuit diagram of the image sensor shown in Figure 8 The circuit diagram is similar.

[0138] Reference Fig.31 and Fig.32 , one pixel group GP may include first to fourth pixels PX1 to PX4 arranged in a 2×2 arrangement. On the left sub-pixel SP(L) of the first pixel PX1, the first active area ACT1, the third active area ACT3, and the second active area ACT2 may be sequentially arranged along the first direction D1. On the first pixel PX1, the second active area ACT2 may be elongated along the fourth direction D4. On the first pixel PX1, the second capacitor area CP2 may be arranged on the second active area ACT2. On the first pixel PX1, the first capacitor area CP1 may be arranged on the fourth active area ACT4. The first capacitor area CP1 and the second capacitor area CP2 may be junction capacitors.

[0139] On the left subpixel SP(L) of the second pixel PX2, the first reset gate electrode RG1 may extend across the fourth active area ACT4 in the second direction D2. On the right subpixel SP(R) of the second pixel PX2, the second reset gate electrode RG2 may extend across the second active area ACT2 in the third direction D3.

[0140] On the left sub-pixel SP(L) of the third pixel PX3, the first active area ACT1, the third active area ACT3, and the second active area ACT2 may be sequentially arranged in a direction opposite to the first direction D1. The selection gate electrode SEL may extend across the second active area ACT2 in a fourth direction D4. On the right sub-pixel SP(R) of the fourth pixel PX4, the third reset gate electrode RG3 may extend across the second active area ACT2 in the fourth direction D4. One pixel group GP may include three reset transistors RX1, RX2, and RX3 and two junction capacitors, but does not include a dummy transistor. Other configurations may be the same or similar to the configurations discussed above.

[0141] Reference Fig.32 , Fig.31 The plurality of pixel groups GP may be arranged two-dimensionally along the first direction D1 and the second direction D2. In some embodiments, Fig.31 The pixel groups GP may be arranged to achieve mirror symmetry along the first direction D1 and the second direction D2.

[0142] Still refer to Fig.32 , the pixel group GP may include a first pixel group GP(1) and a second pixel group GP(2) adjacent to each other in a first direction D1. A single FD connection line FDC may establish connections between floating diffusion regions FDL1 to FDL4 and FDR1 to FDR4 disposed on the first pixel group GP(1), a source follower gate electrode SF, and a source / drain region on one side of a third reset gate electrode RG3. One or more wirings IT may connect the terminal of the third reset transistor RX3 disposed on the first pixel group GP(1) to the terminals of the first reset transistor RX1 and the second reset transistor RX2 disposed on the second pixel group GP(2) and to the first capacitor region CP1 and the second capacitor region CP2. Another one of the wirings IT may connect the terminal of the source follower transistor SFX disposed on the first pixel group GP(1) to the terminal of the selection transistor SLX disposed on the first pixel group GP(1).

[0143] The wiring IT connecting the grounding area GN to the ground line GNL may be arranged alternately left and right in a zigzag manner along the first direction D1. The interval between adjacent wiring IT on the left side of the ground line GNL may be smaller than the interval between adjacent wiring IT on the right side of the ground line GNL. Other configurations may be the same or similar to the configuration discussed above.

[0144] Fig.33 A top view showing a pixel group in an image sensor according to some embodiments is shown. Fig.34 Shows the display Fig.33 A top view of the arrangement of pixel groups and the connection relationship between transistors. Fig.34The circuit diagram of the image sensor shown in Figure 8 The circuit diagram is similar.

[0145] Reference Figure 2A , Fig.33 and Fig.34 , on one pixel group GP in the image sensor, the well regions PW of the first pixel PX1 and the third pixel PX3 may be connected to each other. The pixel separator DTI may be partially inserted between the first pixel PX1 and the third pixel PX3, but may not completely isolate the first pixel PX1 from the third pixel PX3. The common floating diffusion region FFC may connect the first left floating diffusion region FDL1 and the third left floating diffusion region FDL3 to the first right floating diffusion region FDR1 and the third right floating diffusion region FDR3. The grounding region GN may be disposed on only one of the first pixel PX1 and the third pixel PX3. The grounding region GN may be disposed on the first pixel PX1.

[0146] On the pixel group GP, the well regions PW of the second pixel PX2 and the fourth pixel PX4 may be connected to each other. The pixel separator DTI may be partially inserted between the second pixel PX2 and the fourth pixel PX4, but the second pixel PX2 may not be completely isolated from the fourth pixel PX4. The common floating diffusion region FFC may extend through the pixel separator DTI and connect the second left floating diffusion region FDL2 and the fourth left floating diffusion region FDL4 to the second right floating diffusion region FDR2 and the fourth right floating diffusion region FDR4. The grounding region GN may be disposed on only one of the second pixel PX2 and the fourth pixel PX4. The grounding region GN may be disposed on the fourth pixel PX4. The right sub-pixel SP(R) of the second pixel PX2 may include a fifth active region ACT5 instead of including any one of the second active region ACT2 and the third active region ACT3. When viewed in a top view, the fifth active region ACT5 may have the same shape as that of the fourth active region ACT4. On each of the first to fourth pixels PX1 to PX4 , the pixel separation portion DTI may extend across a central portion between the left sub-pixel SP(L) and the right sub-pixel SP(R).

[0147] Reference Fig.34 , Fig.33 The plurality of pixel groups GP may be arranged two-dimensionally along the first direction D1 and the second direction D2. In some embodiments, Fig.33 The pixel groups GP may be arranged to achieve mirror symmetry along the first direction D1 and the second direction D2.

[0148] Still refer to Fig.34, the pixel group GP may include a first pixel group GP(1) and a second pixel group GP(2) adjacent to each other in the first direction D1. A single FD connection line FDC may establish a connection between a common floating diffusion region FFC, a source follower gate electrode SF, and a source / drain region on one side of a third reset gate electrode RG3 provided on the first pixel group GP(1). One or more wirings IT may connect a terminal of a third reset transistor RX3 provided on the first pixel group GP(1) to a terminal of a first reset transistor RX1 and a second reset transistor RX2 provided on the second pixel group GP(2). Another one of the wirings IT may connect a terminal of a source follower transistor SFX provided on the first pixel group GP(1) to a terminal of a selection transistor SLX provided on the second pixel group GP(2).

[0149] The wirings IT connecting the ground area GN to the ground line GNL may be disposed alternately left and right in a zigzag manner along the first direction D1. Other configurations may be the same or similar to those discussed above.

[0150] Fig.35 A cross-sectional view showing an image sensor according to some embodiments is shown.

[0151] Reference Fig.35 According to some embodiments, an image sensor may include a substrate 100 including a pixel array area AR, an optical black area OB, and a pad area PAD, and may also include a wiring layer 200 on a first surface 100a of the substrate 100 and a base substrate 400 on the wiring layer 200. The wiring layer 200 may include an upper wiring layer 221 and a lower wiring layer 223. The pixel array area AR may include a plurality of pixels PX. The pixels PX disposed on the pixel array area AR may be the same as those described above with reference to Figures 1 to 34 The pixels PX in question are essentially the same.

[0152] On the optical black area OB, the substrate 100 may be provided thereon with the first connection structure 50, the first conductive pad 81, and the body color filter 90. The first connection structure 50 may include a first light shielding pattern 51, a dielectric pattern 53, and a first capping pattern 55.

[0153] The first light shielding pattern 51 may be disposed on the second surface 100b of the substrate 100. For example, the first light shielding pattern 51 may conformally cover the inner wall of the third trench TR3 and the inner wall of the fourth trench TR4 while covering the second dielectric layer 136 on the second surface 100b. The first light shielding pattern 51 may penetrate the photoelectric conversion layer 150 and the upper wiring layer 221 to connect the photoelectric conversion layer 150 to the wiring layer 200. For example, the first light shielding pattern 51 may contact the wiring in the upper wiring layer 221 and the lower wiring layer 223 and the separation conductive pattern 10 of the pixel separation portion DTI in the photoelectric conversion layer 150. Therefore, the first connection structure 50 may be electrically connected to the wiring in the wiring layer 200. The first light shielding pattern 51 may include a metal material such as tungsten. The first light shielding pattern 51 may block light from being incident into the optical black area OB.

[0154] The first conductive pad 81 may be provided in the third trench TR3 to fill an unoccupied portion of the third trench TR3. The first conductive pad 81 may include a metal material such as aluminum. The first conductive pad 81 may be connected to Figure 2A The separated conductive pattern 10. A negative bias voltage may be applied to the separated conductive pattern 10 through the first conductive pad 81. Therefore, white spots and / or dark current may be prevented or reduced.

[0155] The dielectric pattern 53 may fill the unoccupied portion of the fourth trench TR4. The dielectric pattern 53 may completely or partially penetrate the photoelectric conversion layer 150 and the wiring layer 200. The first capping pattern 55 may be provided on the top surface of the dielectric pattern 53. The first capping pattern 55 may be provided on the dielectric pattern 53.

[0156] A body color filter 90 may be provided on the first conductive pad 81, the first light shielding pattern 51, and the first cover pattern 55. The body color filter 90 may cover the first conductive pad 81, the first light shielding pattern 51, and the first cover pattern 55. A first protective layer 71 may be provided on the body color filter 90 and encapsulate the body color filter 90. The first protective layer 71 may be formed of a transparent dielectric material.

[0157] The photoelectric conversion region 110' and the dummy region 111 may be provided on the optical black area OB of the substrate 100. The photoelectric conversion region 110' may be doped with impurities (e.g., impurities having a second conductivity type different from the first conductivity type). The second conductivity type may be, for example, an n-type. The pixel array region AR may include a plurality of pixels PX. The photoelectric conversion region 110' may have a structure similar to that of the photoelectric conversion region 110 on the pixel array region AR, but may not perform the same operation as that of the photoelectric conversion region 110 (e.g., generating an electrical signal from incident light). The dummy region 111 may not be doped with impurities. The dummy region 111 may generate a signal used as information for removing subsequent process noise.

[0158] On the pad area PAD, the substrate 100 may be provided thereon with a second connection structure 60, a second conductive pad 83, and a second protection layer 73. The second connection structure 60 may include a second light shielding pattern 61, a dielectric pattern 63, and a second capping pattern 65.

[0159] The second light shielding pattern 61 may be disposed on the second surface 100b of the substrate 100. For example, the second light shielding pattern 61 may conformally cover the inner wall of the fifth trench TR5 and the inner wall of the sixth trench TR6 while covering the second dielectric layer 136 on the second surface 100b. The second light shielding pattern 61 may penetrate the photoelectric conversion layer 150 and the upper wiring layer 221 to connect the photoelectric conversion layer 150 to the wiring layer 200. For example, the second light shielding pattern 61 may contact the wiring in the lower wiring layer 223. Therefore, the second connection structure 60 may be electrically connected to the wiring in the wiring layer 200. The second light shielding pattern 61 may include a metal material such as tungsten.

[0160] A second conductive pad 83 may be provided in the fifth trench TR5 to fill the unoccupied portion of the fifth trench TR5. The second conductive pad 83 may include a metal material such as aluminum. The second conductive pad 83 may be used as an electrical connection path through which the image sensor is connected to an external device. The dielectric pattern 63 may fill the unoccupied portion of the sixth trench TR6. The dielectric pattern 63 may fully or partially penetrate the photoelectric conversion layer 150 and the wiring layer 200. A second cover pattern 65 may be provided on the dielectric pattern 63. The second protective layer 73 may cover a portion of the second light shielding pattern 61 and the second cover pattern 65.

[0161] The current applied through the second conductive pad 83 may flow through the second light shielding pattern 61, the wiring in the wiring layer 200, and the first light shielding pattern 51 to the separation conductive pattern 10 of the pixel separation portion DTI. The photoelectric conversion regions 110 and 110' and the dummy region 111 may generate electrical signals, and the electrical signals may be transmitted to the outside through the wiring in the wiring layer 200, the second light shielding pattern 61, and the second conductive pad 83.

[0162] An image sensor according to some embodiments may be configured such that, on a pixel including two sub-pixels, a grounding region may be provided on a corner portion of the pixel. Since a grounding region is not provided on a cutting region of a pixel separator, a gate width of a logic transistor adjacent thereto may be reduced. Therefore, a random telegraph signal (RTS) may be improved, and the image sensor may achieve clear image quality. In addition, since a grounding region is not provided on a cutting region, an autofocus (AF) segregation ratio may be increased to perform an excellent autofocus function.

[0163] While aspects of the embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

[0164] This application claims the priority benefit of Korean Patent Application No. 10-2023-0142621 filed on October 24, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An image sensor, comprising: a substrate comprising a plurality of pixels, each of the plurality of pixels comprising a left sub-pixel and a right sub-pixel; a well region in the substrate on each of the plurality of pixels, the well region connecting the left sub-pixel and the right sub-pixel to each other; a pixel separation portion that separates the plurality of pixels from each other and extends in the substrate between the left sub-pixel and the right sub-pixel; a left transfer transistor and a first logic transistor on the left sub-pixel; a right transfer transistor and a second logic transistor on the right sub-pixel; as well as a grounding region in the substrate on one of the left sub-pixel and the right sub-pixel and in contact with the well region, Wherein the grounding region is adjacent to a corner of each of the plurality of pixels. 2 . The image sensor of claim 1 , further comprising a microlens on the left sub-pixel and the right sub-pixel on each of the plurality of pixels. 3 . The image sensor according to claim 1 , further comprising a device isolation portion in the substrate at a center of each of the plurality of pixels.

4. The image sensor according to claim 1 , wherein the left transfer transistor is spaced apart from the first logic transistor in a first direction, wherein the right transfer transistor is spaced apart from the second logic transistor in the first direction, wherein the grounding region is adjacent to the first logic transistor in a second direction, the second direction intersecting the first direction, wherein the gate electrode of the first logic transistor is elongated in the second direction, and The gate electrode of the second logic transistor is elongated in a third direction intersecting the first direction and the second direction.

5. The image sensor according to claim 1, further comprising a device isolation portion in the substrate, wherein the device isolation portion separates the active regions of the left transfer transistor, the right transfer transistor, the first logic transistor, the second logic transistor, and the ground region, and A portion of a gate electrode of one of the first logic transistor and the second logic transistor extends into the device isolation portion and covers a side surface of the substrate. 6 . The image sensor of claim 1 , wherein each of the gate electrodes of the left and right transfer transistors includes at least one protrusion extending into the substrate.

7. An image sensor, comprising: a substrate including a plurality of pixel groups, each of the plurality of pixel groups including a plurality of pixels in a 2×2 arrangement, each of the plurality of pixels including a left sub-pixel and a right sub-pixel; a well region in the substrate on each of the plurality of pixels, the well region connecting the left sub-pixel and the right sub-pixel to each other; a pixel separation portion that separates the plurality of pixels from each other and extends in the substrate between the left sub-pixel and the right sub-pixel; a left transfer transistor and a left active area on the left sub-pixel; a right transfer transistor and a right active area on the right sub-pixel; a grounding region in the substrate on one of the left sub-pixel and the right sub-pixel and in contact with the well region; as well as a ground line extending above the substrate between the plurality of pixel groups, Wherein, on each of the plurality of pixels, the grounding region is adjacent to the grounding line.

8. The image sensor according to claim 7, further comprising: a microlens on the left sub-pixel and the right sub-pixel of each of the plurality of pixels; a first color filter on one of the plurality of pixel groups; a second color filter on another one of the plurality of pixel groups; as well as A third color filter is on another one of the plurality of pixel groups.

9. The image sensor according to claim 7, wherein the left transfer transistor is spaced apart from the left active region in a first direction, wherein the right transfer transistor is spaced apart from the right active region in the first direction, and The ground line extends in the first direction.

10. The image sensor according to claim 7, wherein each of the plurality of pixel groups comprises a first pixel, a second pixel, a third pixel, and a fourth pixel, wherein the first pixels and the second pixels are arranged side by side in a first direction to form a first row, wherein the third pixel and the fourth pixel are arranged side by side in the first direction to form a second row, and The left transfer transistor and the right transfer transistor on the first pixel and the second pixel are adjacent to the left transfer transistor and the right transfer transistor on the third pixel and the fourth pixel, respectively.

11. The image sensor according to claim 10, further comprising: a first reset gate electrode extending over the left active area of ​​the first pixel; a second reset gate electrode extending above the right active area of ​​the first pixel; a third reset gate electrode extending above the right active area of ​​the second pixel; a first dummy gate electrode extending above the left active area of ​​the second pixel; a select gate electrode extending over the left active area of ​​the third pixel; a source follower gate electrode extending over the right active area of ​​the third pixel and the right active area of ​​the fourth pixel; as well as A second dummy gate extends above the left active area of ​​the fourth pixel.

12. The image sensor according to claim 11, wherein one of the first reset gate electrode, the second reset gate electrode, and the third reset gate electrode has a first width in the first direction, wherein the source follower gate electrode has a second width in the first direction, and The second width is greater than the first width.

13. The image sensor according to claim 10, wherein the plurality of pixel groups include a first pixel group, a second pixel group, a third pixel group, and a fourth pixel group in a 2×2 arrangement, The ground line is between the first pixel group and the second pixel group and between the third pixel group and the fourth pixel group. wherein the grounding area includes a plurality of first grounding areas on the fourth pixel of the first pixel group, the third pixel of the second pixel group, the second pixel of the third pixel group, and the first pixel of the fourth pixel group, and The plurality of first grounding regions are adjacent to the grounding line. The image sensor according to claim 13 , wherein the plurality of first grounding regions are spaced apart from the grounding line by the same distance.

15. The image sensor according to claim 13, further comprising: a first interlayer dielectric layer on the substrate; a plurality of first ground contacts extending into the first interlayer dielectric layer to correspondingly contact the plurality of first ground regions; a first wiring on the first interlayer dielectric layer to connect the plurality of first ground contacts to each other; as well as a second interlayer dielectric layer on the first wiring, The ground line is on the second interlayer dielectric layer and connected to the first wiring.

16. The image sensor according to claim 13, further comprising a ground pattern on the substrate and in contact with the plurality of first ground regions, The ground line extends across the ground pattern.

17. The image sensor according to claim 16, wherein: The ground pattern has an octagonal shape or a cross shape when viewed in a plan view.

18. The image sensor according to claim 16, further comprising a first reset gate electrode on the left active region of one of the plurality of pixels, The ground pattern and the first reset gate electrode have the same thickness.

19. The image sensor according to claim 16, wherein a portion of the ground pattern extends over the left active region of the fourth pixel of the first pixel group and over the left active region of the second pixel of the third pixel group, and The image sensor further includes a gate dielectric layer between the ground pattern and the left active region.

20. An image sensor, comprising: a substrate having a first surface and a second surface opposite to each other, the substrate comprising a plurality of pixel groups, each of the plurality of pixel groups comprising a plurality of pixels arranged in a 2×2 matrix, and each of the plurality of pixels comprising a left sub-pixel and a right sub-pixel; a first color filter covering one of the plurality of pixel groups on the first surface; a second color filter covering another one of the plurality of pixel groups on the first surface; a third color filter covering another one of the plurality of pixel groups on the first surface; a plurality of micro lenses, respectively provided on the first color filter, the second color filter, and the third color filter and covering each of the plurality of pixels; a well region in the substrate on each of the plurality of pixels, the well region connecting the left sub-pixel and the right sub-pixel to each other; a pixel separation portion that separates the plurality of pixels from each other and extends between the left sub-pixel and the right sub-pixel; a device isolation portion, adjacent to the second surface in the substrate, the device isolation portion separating a left active region on the left sub-pixel from a right active region on the right sub-pixel; a left photoelectric conversion region in the substrate on the left sub-pixel of each of the plurality of pixels; a right photoelectric conversion region in the substrate on the right sub-pixel of each of the plurality of pixels; a left transfer transistor on the second surface at each of the plurality of pixels; a right transfer transistor on the second surface at each of the plurality of pixels; as well as a grounding region in the substrate on one of the left sub-pixel and the right sub-pixel and in contact with the well region, wherein the grounding area is provided in plurality, and The plurality of grounding regions are adjacent to a corner of each of the plurality of pixel groups.

Images