Silicon-based heterogeneous integrated framework and preparation method thereof

Abstract

The invention discloses a silicon-based heterogeneous integrated framework and a preparation method thereof. The preparation method comprises the following steps: preparing a first substrate wafer, a silicon layer integrated photoelectric device of the first substrate wafer, a germanium-on-silicon layer integrated photoelectric detector and a silicon-on-silicon layer integrated passive optical device; forming a first bonding interface on the upper surface of the first substrate wafer and overturning and bonding the first bonding interface to the second substrate wafer; removing the substrate from the first substrate wafer, and thinning the buried oxide layer to form a second bonding interface; bonding a lithium niobate chip on the second bonding interface, and removing the substrate and the oxide layer of the lithium niobate chip until the lithium niobate layer is exposed; and processing and preparing a lithium niobate waveguide layer, removing the lithium niobate layer at the position of the metal through hole, processing and preparing a metal wiring layer at the position of the metal through hole, electrically communicating with the optoelectronic device on the first substrate wafer, and manufacturing an electrical interface. And meanwhile, bonding in an etching cavity is replaced by flat wafer interface bonding, so that the process integration complexity is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of silicon-based optoelectronic heterogeneous integration, and the present invention relates to a silicon-based heterogeneous integration architecture and a preparation method thereof. Background Art

[0002] After years of development and accumulation in the industry, the traditional silicon photonics process platform has formed a complete set of process flows. Various types of passive optical waveguide devices with excellent performance have been prepared through heterogeneous integrated silicon nitride, and high-speed and high-loudness photodetectors exceeding 70GHz have been prepared through heterogeneous integrated germanium. In order to realize high-speed and high-performance modulators on the silicon photonics platform, people began to focus on the process realization of heterogeneous integrated thin-film lithium niobate.

[0003] Patent CN116841060A, an optical chip, optical module and communication equipment published in 2023, describes a silicon-based heterogeneous integrated thin-film lithium niobate architecture, characterized in that the silicon nitride layer is located on the side of the silicon layer away from the substrate, and the thin-film lithium niobate is located on the side of the silicon nitride layer away from the substrate, so the lithium niobate layer needs to be efficiently coupled with the silicon nitride layer. Since the refractive index of silicon nitride is lower than that of lithium niobate, the line width of the lithium niobate waveguide usually needs to be less than 1um to meet the demand. For this reason, the post-processing technology of lithium niobate needs to adopt DUV lithography or electron beam exposure technology, and the mass production manufacturing cost is relatively high.

[0004] U.S. Patent US20240142809A1 disclosed in 2024 provides a method for preparing silicon-based heterogeneous integrated thin film lithium niobate, characterized in that the lithium niobate layer and the silicon nitride layer are both located on the side of the silicon layer away from the substrate, and are adjacent to the silicon layer at the same time, so the lithium niobate layer needs to be efficiently coupled with the silicon layer. Since the refractive index of silicon is higher than that of lithium niobate, the line width of the lithium niobate waveguide does not need to be less than 1um to meet the demand, and its subsequent processing technology can adopt low-cost photolithography technology. However, since there is already a silicon nitride layer above the silicon layer, in order to make the lithium niobate layer adjacent to the silicon layer, it is necessary to selectively etch to above the silicon layer in the area where bonding is required, and complete the bonding process in the etching chamber, which makes process integration difficult.

[0005] Therefore, the existing silicon-based lithium niobate heterogeneous integration process is not yet mature, and there is still a need to explore better heterogeneous integration process architecture and methods. Summary of the invention

[0006] The purpose of the present invention is to provide a silicon-based heterogeneous integrated architecture and a preparation method thereof, which reduces the line width process requirements of lithium niobate and simultaneously adopts flat wafer interface bonding to replace the bonding in the etching chamber to reduce the complexity of process integration.

[0007] The technical solution to achieve the purpose of the present invention is: A method for preparing a silicon-based heterogeneous integrated architecture comprises the following steps: S01: preparing a first substrate wafer, wherein the silicon layer of the first substrate wafer integrates optoelectronic devices, the germanium layer on silicon integrates photodetectors, and the silicon nitride layer on silicon integrates passive optical devices; S02: forming a first bonding interface on the upper surface of the first substrate wafer, and flipping the first bonding interface to bond to the second substrate wafer; S03: removing the substrate from the first substrate wafer and thinning the buried oxide layer to form a second bonding interface; S04: bonding a high-efficiency electro-optical effect material chip or wafer at the second bonding interface, and removing a substrate and an oxide layer of the high-efficiency electro-optical effect material chip or wafer until the high-efficiency electro-optical effect material layer leaks out; S05: Processing the high-efficiency electro-optical effect material layer to prepare a high-efficiency electro-optical effect material waveguide layer, removing the high-efficiency electro-optical effect material layer at the metal through-hole position, processing and preparing a metal wiring layer at the metal through-hole position, electrically connecting with the optoelectronic device on the first substrate wafer, and making an electrical interface.

[0008] In the preferred technical solution, the first substrate wafer comprises, from bottom to top, a first substrate, a buried oxide layer and a silicon layer, the silicon layer is prepared with a photoelectric device, a germanium-on-silicon layer is arranged on the silicon layer, the germanium-on-silicon layer is in contact with the silicon layer, and a photodetector is prepared, a silicon nitride layer on silicon is also arranged on the silicon layer, the silicon layer and the silicon nitride layer on silicon have a certain gap, the silicon nitride layer on silicon is prepared with a passive optical device, a heating electrode layer and a subsequent multilayer metal and its through-hole layer are arranged above the silicon nitride layer on silicon, the heating electrode layer and the silicon nitride layer have a certain gap, the subsequent multilayer metal and its through-hole layer are electrically connected with the optoelectronic device, the photodetector and the heating electrode layer, the heating electrode layer and the subsequent multilayer metal and its through-hole layer are wrapped by the first cladding layer, the metal through-hole pre-buried in the buried oxide layer is connected to the subsequent multilayer metal and its through-hole layer, and overlaps with the buried oxide layer.

[0009] In a preferred technical solution, copper pillars are provided on the back-end multi-layer metal and the through-hole layer thereof, and the copper pillars extend outside the first cladding layer.

[0010] In a preferred technical solution, the first bonding interface is indirectly bonded to the second substrate of the second substrate wafer via a buffer layer.

[0011] In the preferred technical solution, step S05 is a method for processing a high-efficiency electro-optical effect material layer to prepare a high-efficiency electro-optical effect material waveguide layer, comprising first partially etching the high-efficiency electro-optical effect material layer to form a ridge waveguide, the etching depth being 100nm-500nm, and after completing the first step of etching, depositing an oxide layer, the oxide layer thickness being 10nm-2um.

[0012] In a preferred technical solution, the high-efficiency electro-optical effect material is InP, LiTaO3, BaTiO3 or LiNbO3.

[0013] In a preferred technical solution, the method for processing and preparing the metal wiring layer at the metal through hole position in step S05 includes: The metal wiring layer is manufactured by a metal deposition preparation process to ensure that the metal wiring layer completely covers the position of the embedded metal through-hole; at the same time, the metal wiring layer is used as the electrode layer of the electro-optic modulator, and the second cladding layer wraps the high-efficiency electro-optic effect material layer, the oxide and the metal wiring layer to form a third bonding interface.

[0014] In the preferred technical scheme, step S05 also includes selecting a third bonding interface as an electrical interface. If there is no copper pillar, the second cladding is etched to the metal wiring layer at the pad that needs to form an electrical connection with the outside, and the pad window is completed; if there is a copper pillar, the second cladding is etched to the metal wiring layer at the pad that needs to form an electrical connection with the outside, the pad window is completed and the copper pillar is prepared through a ball planting process.

[0015] In the preferred technical scheme, step S05 also includes selecting the first bonding interface as the electrical interface. If there is no copper pillar, the first substrate wafer selects a scheme without integrated copper pillars, and then flips the third bonding interface and bonds it to the third substrate, and debonds the first bonding interface, and then etches the first cladding to the metal wiring layer at the pad that needs to form an electrical connection with the outside to complete the pad windowing; if there is a copper pillar, the first substrate wafer selects a scheme with integrated copper pillars, and then flips the third bonding interface and bonds it to the third substrate, and debonds the first bonding interface; or the first substrate wafer selects a scheme without integrated copper pillars, and then flips the third bonding interface and bonds it to the third substrate, and debonds the first bonding interface, and then etches the first cladding to the metal wiring layer at the pad that needs to form an electrical connection with the outside to complete the pad windowing and prepare the copper pillar through a ball implantation process.

[0016] The present invention also discloses a silicon-based heterogeneous integrated architecture, which is prepared by adopting the above-mentioned method for preparing the silicon-based heterogeneous integrated architecture.

[0017] Compared with the prior art, the present invention has the following significant advantages: (1) In this scheme, silicon nitride and lithium niobate are located on both sides of the silicon layer, respectively. Lithium niobate is directly coupled to the silicon layer, which reduces the line width process requirements of lithium niobate.

[0018] (2) In this scheme, lithium niobate is bonded to the side of the silicon layer close to the substrate, and the bonding interface is the entire flat wafer plane, which reduces the complexity of process integration.

[0019] (3) The material of the flip substrate wafer used in this scheme can use quartz to replace the original silicon according to design requirements to achieve a lithium niobate modulator with better high-frequency performance, avoiding the modulation area substrate hollowing process used in conventional silicon-based heterogeneous integrated lithium niobate schemes, enhancing the reliability of the chip and reducing the complexity of the chip process. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a flow chart of a method for preparing a silicon-based heterogeneous integrated architecture of this embodiment; Figure 2a is a cross-sectional view of a first substrate wafer without integrated copper pillars in one embodiment; Figure 2b is a cross-sectional view of a first substrate wafer with integrated copper pillars in another embodiment; Figure 3a-3b is a cross-sectional view of the first substrate wafer after being flipped and bonded to the second substrate in this embodiment; Figure 4a-4b is a cross-sectional view of the lithium niobate layer after bonding etching in this embodiment; Figure 5a-5b is a cross-sectional view of the metal electrode after preparation and deposition of the cladding layer in this embodiment; Figure 6a-6d are cross-sectional views of several final silicon-based lithium niobate heterogeneous integrated wafers in this embodiment; wherein, Figure 6a The third bonding interface is used as an electrical interface without copper pillars; Figure 6b The third bonding interface serves as an electrical interface and has copper pillars; Figure 6c The first bonding interface is used as an electrical interface without copper pillars; Figure 6d The first bonding interface serves as an electrical interface and has copper pillars. DETAILED DESCRIPTION

[0021] The principle of the present invention is: a new silicon-based heterogeneous integrated thin film lithium niobate architecture and method is proposed, which reduces the line width process requirements of lithium niobate, and at the same time uses flat wafer interface bonding to replace the bonding in the etching chamber to reduce the complexity of process integration.

[0022] Embodiment 1:

[0023] like Figure 1 As shown, a method for preparing a silicon-based heterogeneous integrated architecture comprises the following steps: S01: preparing a first substrate wafer, wherein the silicon layer of the first substrate wafer integrates optoelectronic devices, the germanium layer on silicon integrates photodetectors, and the silicon nitride layer on silicon integrates passive optical devices; S02: forming a first bonding interface on the upper surface of the first substrate wafer, and flipping the first bonding interface to bond to the second substrate wafer; S03: removing the substrate from the first substrate wafer and thinning the buried oxide layer to form a second bonding interface; S04: bonding a high-efficiency electro-optical effect material chip or wafer at the second bonding interface, and removing a substrate and an oxide layer of the high-efficiency electro-optical effect material chip or wafer until the high-efficiency electro-optical effect material layer leaks out; S05: Processing the high-efficiency electro-optical effect material layer to prepare a high-efficiency electro-optical effect material waveguide layer, removing the high-efficiency electro-optical effect material layer at the metal through-hole position, processing and preparing a metal wiring layer at the metal through-hole position, electrically connecting with the optoelectronic device on the first substrate wafer, and making an electrical interface.

[0024] The following is a detailed description using lithium niobate chips or wafers as an example: In a preferred embodiment, a method for preparing a novel silicon-based lithium niobate heterogeneous integrated architecture comprises the following steps: S1, prepare traditional silicon photonic devices on the first substrate wafer, including using the silicon layer to integrate various optoelectronic devices, such as grating couplers, MMI, resistors, adjustable optical attenuators, polarization combiners and splitters, etc., using the germanium layer on silicon to integrate high-performance photodetectors, using the silicon nitride layer on silicon to integrate various high-performance passive optical devices, using mature CMOS technology to pre-embed metal through holes to the BOX layer, and using the ball planting process to prepare copper pillars for flip-chip soldering.

[0025] S2, pre-treating the upper surface of the first substrate wafer to form a first bonding interface; S3, flipping and bonding the first bonding interface to the second substrate wafer; S4, removing the substrate from the first substrate wafer, grinding and thinning the BOX layer to form a second bonding interface, and the metal through hole pre-embedded in the BOX layer is in contact with the second bonding interface; S5, bonding the lithium niobate chip or wafer at the second bonding interface; S6, lithium niobate chip or wafer to remove substrate and oxide layer; S7, processing and preparing a lithium niobate waveguide layer, and completely removing the lithium niobate layer at the location of the embedded metal through hole; S8, processing and preparing a metal wiring layer to completely cover the position of the embedded metal through hole; S9, depositing a cladding material, pre-treating the surface, and forming a third bonding interface; S10a, if the third bonding interface is selected as the electrical interface of the chip, then at the pads that need to form electrical connection with the outside, the cladding layer is etched to the metal wiring layer to complete the pad windowing, and copper pillars are selectively prepared according to the needs; S10b, if the first bonding interface is selected as the electrical interface of the chip, the third bonding interface is flipped and bonded to the third substrate wafer, and the second substrate wafer is debonded at the same time, so that the first bonding interface is exposed, and the pads or copper pillars prepared on the initial silicon photonic wafer can be used as the electrical interface of the chip.

[0026] Figure 2a-2b The figure shows a cross-sectional view of a monolithic integrated wafer on the first substrate wafer. The cross-sectional structure can be prepared based on the existing mature process of the silicon photonics Fab factory, specifically including the first substrate 1, BOX layer (buried oxide layer) 2, various optoelectronic devices prepared by silicon layer 3, photodetectors prepared by germanium layer 4 on silicon, passive devices prepared by silicon nitride layer 5 on silicon, heating electrode layer 6, multi-layer back-end metal layers and interlayer vias 7, first cladding layer 8, and metal vias 9 pre-buried in the BOX layer. The top surface of the wafer is ground and polished to form the first bonding interface 10, and copper pillars are selectively integrated to prepare for wafer flip bonding, and copper pillars 21 are integrated as needed. Figure 2a is a cross-sectional view of a first substrate wafer without integrated copper pillars in one embodiment; Figure 2b is a cross-sectional view of a first substrate wafer with integrated copper pillars in another embodiment.

[0027] Figure 2a-2b The first substrate 1 is usually made of silicon material with a thickness of 1um-1mm. The BOX layer (i.e., buried oxide layer) 2 is silicon oxide, located above the first substrate 1, and is usually 100nm-5um thick. The silicon layer 3 is located above the BOX layer 2, and is usually 100nm-500nm thick. The silicon layer 3 can be used to prepare various optoelectronic devices such as grating couplers, MMIs, resistors, adjustable optical attenuators, polarization beam combiners and splitters through mature processes such as etching and ion implantation. The germanium layer 4 on silicon is located above the silicon layer 3 and in contact with the silicon layer, with a thickness of 100nm-800nm, and can be prepared by selective epitaxial growth technology. In combination with the silicon layer 3 and ion implantation processes, high-performance photodetectors can be realized. The silicon nitride layer 5 on silicon is located above the silicon layer 3, and the gap between the silicon layer and the silicon layer is usually 10nm-1um, and the thickness is 100nm-800nm. The silicon nitride layer 5 on silicon can be used to prepare various high-performance passive optical devices through etching. The heating electrode layer 6 is located above the silicon nitride layer 5 on silicon, and the gap between the heating electrode layer and the silicon nitride layer is usually 500nm-2um. The heating electrode layer 6 can be made of appropriate materials such as TiN and TaN, and the thickness is usually 50nm-300nm. The back-end multi-layer metal and its through-hole layer 7 are used to realize the electrical connection between the silicon layer 3 optoelectronic devices, the silicon germanium layer 4 photodetector, and the heating electrode layer 6, and are wrapped by the first cladding layer 8. The back-end multi-layer metal and its through-hole layer 7 usually contain 2-5 layers of metal wiring layers, and the metal material can be CMOS-compatible metal materials such as Al and Cu, with a thickness of 500nm-3um. The metal through hole 9 pre-buried in the BOX layer is connected to the back-end multi-layer metal and its through-hole layer 7, and overlaps with the BOX layer, and is used for electrical connection between the metal wiring and all optoelectronic devices in the initial silicon-based monolithic integrated wafer in the back-end process after wafer flip bonding, such as Figure 2a shown.

[0028] It should be noted that the material of the flip substrate wafer (first substrate wafer) used in this solution can use quartz to replace the original silicon according to design requirements to achieve a lithium niobate modulator with better high-frequency performance, avoiding the modulation area substrate hollowing process used in conventional silicon-based heterogeneous integrated lithium niobate solutions, enhancing the reliability of the chip and reducing the complexity of the chip process.

[0029] like Figure 2b As shown, the copper pillar 21 is usually prepared on the topmost wiring metal, and the material includes Ni / Cr / Ti / Cu / Sn / Ag, etc., with a diameter of 10um-100um and a gap greater than 20um.

[0030] Figure 3a-Figure 3b FIG. 1 is a cross-sectional view of a wafer after the first substrate wafer is flipped and bonded to the second substrate. If the copper pillar 21 is not integrated in the initial wafer (the first substrate wafer), the first bonding interface 10 is directly bonded to the second substrate 11. Figure 3a .

[0031] If the copper pillar 21 is integrated in the initial wafer, the first bonding interface 10 is indirectly bonded to the second substrate 11 through the buffer layer 18, such as Figure 3b .

[0032] Then, the first substrate 1 is removed by mechanical grinding or other means, and the BOX layer 2 is thinned to near the silicon layer 3 to form a second bonding interface 12, and it is ensured that the metal through hole 9 pre-buried in the BOX layer is connected to the second bonding interface 12. The gap between the second bonding interface 12 and the silicon layer is usually 10nm-500nm. The second substrate 11 can be various materials suitable for substrates, such as silicon and quartz.

[0033] Figure 4a-4b The figure shows a cross-sectional view of a wafer after the lithium niobate layer is bonded and etched. The lithium niobate chip or wafer can be bonded to the second bonding interface 12 by die-to-wafer bonding (a single chip (die) is bonded to another wafer (wafer)) or wafer-to-wafer (two wafers are directly bonded) bonding, and the substrate and oxide layer of the lithium niobate chip or wafer are removed until the lithium niobate layer 13 is exposed. The lithium niobate layer 13 is usually 200nm-1000nm thick and can be prepared into a lithium niobate waveguide by dry etching or wet etching.

[0034] The etching of lithium niobate is usually divided into two steps. First, the lithium niobate layer 13 is partially etched to form a ridge waveguide, and the etching depth is 100nm-500nm. After the first step of etching, the loss of the subsequent metal layer to the lithium niobate waveguide can be reduced by depositing an oxide layer 14, and the thickness of the oxide layer 14 is 10nm-2um. Finally, the lithium niobate layer at the position where the embedded metal through hole 9 is completely removed until the metal through hole leaks out.

[0035] It should be noted that the material of the lithium niobate layer 13 can also be replaced by other materials with high-efficiency electro-optical effect, such as InP, LiTaO3, BaTiO3, etc.

[0036] The bonding method of the lithium niobate layer 13 can be direct bonding or glue bonding such as BCB. The bonding layer of direct bonding is silicon dioxide with a thickness of 10-200nm. In the glue bonding method such as BCB, the thickness of BCB ranges from 40-400nm.

[0037] Figure 5a-Figure 5b The figure shows a cross-sectional view after the metal electrode is prepared and the cladding is deposited. The metal wiring layer 15 is made by a metal deposition preparation process to ensure that the metal wiring layer 15 completely covers the position of the embedded metal through hole 9, so that the metal wiring layer 15 can be electrically connected to all optoelectronic devices prefabricated in the initial silicon-based monolithic integrated wafer, and can be rewired. At the same time, the metal wiring layer 15 can also be used as an electrode layer of a lithium niobate modulator to achieve a high-performance electro-optical modulator. The metal electrode layer 15 is usually made of gold, and other suitable metal materials such as copper and aluminum can also be used. The thickness is usually 100nm-3um. The second cladding 16 wraps the lithium niobate layer 13, the oxide 14, and the metal wiring layer 15. The material is usually silicon oxide with a thickness of 1um-10um, and it can be ground and polished as needed to form a third bonding interface 19.

[0038] Figure 6a-6d The following are the cross-sectional views of several final silicon-based lithium niobate heterogeneous integrated wafers. If the third bonding interface 19 is selected as the electrical interface and there is no copper pillar, the second cladding layer 16 is etched to the metal wiring layer 15 at the pad that needs to be electrically connected to the outside, and the pad window 17 is completed. Figure 6a If the third bonding interface 19 is selected as the electrical interface and there is a copper column, the second cladding layer 16 is etched to the metal wiring layer 15 at the pad that needs to be electrically connected to the outside, the pad window is completed and the copper column 21 is prepared by the ball planting process, such as Figure 6b If the first bonding interface is selected as the electrical interface and there is no copper pillar, the first substrate wafer needs to select a solution without integrated copper pillars, and then the third bonding interface 19 is flipped and bonded to the third substrate 20, and the first bonding interface 10 is debonded, and then the first cladding layer 8 is etched to the metal wiring layer 15 at the pad that needs to be electrically connected to the outside, and the pad window 17 is completed, such as Figure 6c; If the first bonding interface is selected as the electrical interface and there is a copper pillar, the first substrate wafer can choose a solution with integrated copper pillars, and then flip the third bonding interface 19 to bond it to the third substrate 20, and debond the first bonding interface; at the same time, the first substrate wafer can also choose a solution without integrated copper pillars, and then flip the third bonding interface 19 to bond it to the third substrate 20, and debond the first bonding interface, and then at the pad that needs to form an electrical connection with the outside, etch the first cladding 8 to the metal wiring layer 15, complete the pad window opening, and prepare the copper pillar 21 through the ball planting process, such as Figure 6d .

[0039] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principles of the present invention shall be equivalent replacement modes and shall be included in the protection scope of the present invention.

Claims

1. A method for preparing a silicon-based heterogeneous integrated architecture, characterized in that: The following steps are involved: S01: preparing a first substrate wafer, wherein the silicon layer of the first substrate wafer integrates optoelectronic devices, the germanium layer on silicon integrates photodetectors, and the silicon nitride layer on silicon integrates passive optical devices; S02: forming a first bonding interface on the upper surface of the first substrate wafer, and flipping the first bonding interface to bond to the second substrate wafer; S03: removing the substrate from the first substrate wafer and thinning the buried oxide layer to form a second bonding interface; S04: bonding a high-efficiency electro-optical effect material chip or wafer at the second bonding interface, and removing a substrate and an oxide layer of the high-efficiency electro-optical effect material chip or wafer until the high-efficiency electro-optical effect material layer leaks out; S05: Processing the high-efficiency electro-optical effect material layer to prepare a high-efficiency electro-optical effect material waveguide layer, removing the high-efficiency electro-optical effect material layer at the metal through-hole position, processing and preparing a metal wiring layer at the metal through-hole position, electrically connecting with the optoelectronic device on the first substrate wafer, and making an electrical interface.

2. The method for preparing a silicon-based heterogeneous integrated architecture according to claim 1, characterized in that: The first substrate wafer comprises a first substrate, a buried oxide layer and a silicon layer from bottom to top, the silicon layer is prepared with a photoelectric device, a germanium-on-silicon layer is arranged on the silicon layer, the germanium-on-silicon layer is in contact with the silicon layer, and a photodetector is prepared, a silicon nitride layer on silicon is also arranged on the silicon layer, a certain gap exists between the silicon layer and the silicon nitride layer on silicon, a passive optical device is prepared on the silicon nitride layer on silicon, a heating electrode layer and a subsequent multilayer metal and a through-hole layer are arranged above the silicon nitride layer on silicon, the heating electrode layer and the silicon nitride layer have a certain gap, the subsequent multilayer metal and its through-hole layer are electrically connected with the optoelectronic device, the photodetector and the heating electrode layer, the heating electrode layer and the subsequent multilayer metal and its through-hole layer are wrapped by the first cladding layer, the metal through-hole pre-buried in the buried oxide layer is connected with the subsequent multilayer metal and its through-hole layer, and overlaps with the buried oxide layer.

3. The method for preparing a silicon-based heterogeneous integrated architecture according to claim 2, characterized in that: Copper pillars are arranged on the back-end multi-layer metal and the through-hole layer thereof, and the copper pillars extend outside the first cladding layer.

4. The method for preparing a silicon-based heterogeneous integrated architecture according to claim 3, characterized in that: The first bonding interface is indirectly bonded to the second substrate of the second substrate wafer via a buffer layer.

5. The method for preparing a silicon-based heterogeneous integrated architecture according to claim 1, characterized in that: Step S05: The method for processing the high-efficiency electro-optical effect material layer to prepare the high-efficiency electro-optical effect material waveguide layer includes firstly partially etching the high-efficiency electro-optical effect material layer to form a ridge waveguide, the etching depth is 100nm-500nm, and after completing the first step of etching, depositing an oxide layer, the oxide layer thickness is 10nm-2um.

6. The method for preparing a silicon-based heterogeneous integrated architecture according to claim 1, characterized in that: The high-efficiency electro-optical effect material is InP, LiTaO3, BaTiO3 or LiNbO3.

7. The method for preparing a silicon-based heterogeneous integrated architecture according to claim 1, characterized in that: The method for processing and preparing the metal wiring layer at the metal through hole position in step S05 includes: The metal wiring layer is manufactured by a metal deposition preparation process to ensure that the metal wiring layer completely covers the position of the embedded metal through-hole; at the same time, the metal wiring layer is used as the electrode layer of the electro-optic modulator, and the second cladding layer wraps the high-efficiency electro-optic effect material layer, the oxide and the metal wiring layer to form a third bonding interface.

8. The method for preparing a silicon-based heterogeneous integrated architecture according to claim 7, characterized in that: Step S05 also includes selecting a third bonding interface as an electrical interface. If there is no copper pillar, the second cladding layer is etched to the metal wiring layer at the pad that needs to form an electrical connection with the outside, and the pad window is completed; if there is a copper pillar, the second cladding layer is etched to the metal wiring layer at the pad that needs to form an electrical connection with the outside, the pad window is completed and the copper pillar is prepared through a ball planting process.

9. The method for preparing a silicon-based heterogeneous integrated architecture according to claim 7, characterized in that: Step S05 also includes selecting the first bonding interface as the electrical interface. If there is no copper pillar, the first substrate wafer selects a solution without integrated copper pillars, and then flips the third bonding interface and bonds it to the third substrate, and debonds the first bonding interface, and then etches the first cladding layer to the metal wiring layer at the pad that needs to form an electrical connection with the outside to complete the pad windowing; if there is a copper pillar, the first substrate wafer selects a solution with integrated copper pillars, and then flips the third bonding interface and bonds it to the third substrate, and debonds the first bonding interface; or the first substrate wafer selects a solution without integrated copper pillars, and then flips the third bonding interface and bonds it to the third substrate, and debonds the first bonding interface, and then etches the first cladding layer to the metal wiring layer at the pad that needs to form an electrical connection with the outside to complete the pad windowing and prepare the copper pillars through the ball implantation process.

10. A silicon-based heterogeneous integrated architecture, characterized in that: The silicon-based heterogeneous integrated architecture is prepared by the method for preparing the silicon-based heterogeneous integrated architecture according to any one of claims 1 to 9.

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