Quantum well infrared photodetector with back barrier and method of manufacturing the same

Abstract

The application belongs to the technical field of infrared photoelectric detectors, and particularly relates to a quantum well infrared photoelectric detector with a back barrier and a manufacturing method thereof. The quantum well infrared photoelectric detector with the back barrier comprises a GaAs substrate, an active layer, a dielectric layer, a first metal electrode and a second metal electrode, and the active layer comprises an emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer and an infrared detection layer. The manufacturing method comprises the following steps: epitaxially growing the emitter conductive layer, the back barrier layer, the functional layer, the collector conductive layer and the infrared detection layer on a semi-insulating GaAs substrate in sequence; removing part of the material in a first designated area on a wafer; depositing the dielectric layer on the wafer surface; removing the dielectric layer in a second designated area; depositing the metal electrode in the second designated area where the dielectric layer is removed and performing heat treatment. The application can improve the specific detectivity of the infrared photoelectric detector.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of infrared photodetectors, and particularly relates to a quantum well infrared photodetector with a back barrier and a manufacturing method thereof. BACKGROUND

[0002] As a III-V semiconductor material, gallium arsenide (GaAs) is an ideal material for infrared photodetectors due to its high electron mobility, adjustable band gap, and mature material and device processing technology. GaAs-based quantum well infrared photodiodes (QWIPs) use electron inter-well transitions in quantum well structures to detect long-wavelength optical signals. This structure can effectively expand the spectral response range of photodetectors and improve their performance. QWIPs use electron inter-well transitions in quantum wells to improve the specific detectivity of infrared detectors, so they have been widely used in the field of infrared detection. GaAs QWIPs have a detection light wavelength range covering two atmospheric low-loss transmission windows of 3-5 and 8-12 microns. Because of their high sensitivity and mature material and device processing technology, they have been widely studied and applied in the fields of remote control and remote sensing, optical coupling, etc. With the growing demand for infrared information detection and intelligent sensing in the fields of artificial intelligence, big data, and smart cities, higher requirements are placed on the performance of infrared photodetectors, including size, weight, power consumption, and price reduction, as well as performance improvement.

[0003] Due to the influence of dark current, the specific detectivity of current commercial QWIPs is generally less than 10 8 cm·Hz 1 / 2 / W when tested at low temperature in a liquid nitrogen environment (79K), which is not ideal and affects the detection effect of the device. SUMMARY

[0004] Therefore, the application provides a quantum well infrared photodetector with a back barrier and a manufacturing method thereof to solve the technical problem of the specific detectivity of QWIP devices being affected by dark current in the prior art.

[0005] The technical scheme adopted by the application is as follows:

[0006] In a first aspect, the present invention provides a quantum well infrared photodetector with a back barrier. The quantum well infrared photodetector includes a GaAs substrate, an active layer, a dielectric layer, a first metal electrode, and a second metal electrode. The active layer includes an emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer, and an infrared detection layer. The emitter conductive layer, the back barrier layer, the functional layer, the collector conductive layer, and the infrared detection layer are sequentially stacked on the GaAs substrate. At least a portion of the surface of the emitter conductive layer facing away from the GaAs substrate is exposed outside the back barrier layer. The dielectric layer covers the surface of the active layer. The first metal electrode is connected to the emitter conductive layer exposed outside the back barrier layer, and the second metal electrode is connected to the collector conductive layer.

[0007] In a second aspect, the present invention provides a method for manufacturing a quantum well infrared photodetector with a back barrier, for manufacturing the quantum well infrared photodetector with a back barrier described in the first aspect, the method comprising:

[0008] S1: An emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer, and an infrared detection layer are sequentially epitaxially grown on a semi-insulating GaAs substrate.

[0009] S2: Remove a portion of the material in a first designated region on the wafer to expose the emitter conductive layer in that region, wherein the first designated region is the region in the infrared detection layer that needs to form an electrical connection with the metal electrode;

[0010] S3: Deposit a dielectric layer across the entire wafer surface;

[0011] S4: Remove the dielectric layer located in the second designated region, where the second designated region is the region in the emitter conductive layer that needs to form an electrical connection with the metal electrode;

[0012] S5: The beneficial effects of depositing a metal electrode in the second designated region after removing the dielectric layer and performing heat treatment: The quantum well infrared photodetector with a back barrier of the present invention and its manufacturing method form a quantum well infrared photodetector by sequentially growing an emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer and an infrared detection layer on a GaAs substrate. This quantum well infrared photodetector can generate a back barrier on one side electrode of the quantum well infrared photodetector. The back barrier confines the charge carriers to effectively reduce the dark current caused by charge carrier drift, thereby significantly improving the specific detectivity of the quantum well infrared photodetector. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, and these are all within the protection scope of the present invention.

[0014] Figure 1 This is a schematic diagram of the structure of the quantum well infrared photodetector with a back barrier according to the present invention.

[0015] Figure 2 This is a schematic flowchart of the manufacturing method of the quantum well infrared photodetector with back barrier of the present invention.

[0016] Figure 3 This is a schematic diagram of the first step in the manufacturing method of the quantum well infrared photodetector with back barrier of the present invention.

[0017] Figure 4 This is a schematic diagram of the second step in the manufacturing method of the quantum well infrared photodetector with back barrier of the present invention.

[0018] Figure 5 This is a schematic diagram of the third step in the manufacturing method of the quantum well infrared photodetector with back barrier of the present invention.

[0019] Figure 6 This is a schematic diagram of the fourth step in the manufacturing method of the quantum well infrared photodetector with back barrier of the present invention.

[0020] Figure 7 This is a schematic diagram of the fifth step in the manufacturing method of the quantum well infrared photodetector with back barrier of the present invention.

[0021] Figure 8 This is a graph comparing the dark current test results of the present invention and the prior art.

[0022] Figure 9 This is a graph showing the responsiveness test results of the present invention and the prior art.

[0023] Figure 10 This is a graph showing the detection rate of the present invention compared to existing technologies.

[0024] Figure numbers and descriptions:

[0025] GaAs substrate 100, emitter conductive layer 200, n-doped GaAs layer 301, first undoped GaAs layer 302, p + Doped GaAs layer 303, second undoped GaAs layer 304, functional GaAs layer 401, In x Ga 1-xAs layer 402, third undoped GaAs layer 501, second n + The structure consists of a doped GaAs layer 502, an infrared detection layer 503, a dielectric layer 600, and a metal electrode 700. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. It should be noted that, in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. In the description of the present invention, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements, but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Where there is no conflict, embodiments of the present invention and the various features thereof can be combined with each other, all of which are within the scope of protection of the present invention.

[0027] Example 1

[0028] like Figure 1 As shown, this embodiment provides a quantum well infrared photodetector with a back barrier, including a GaAs substrate 100, an active layer, a dielectric layer 600, and two metal electrodes 700, namely a first metal electrode and a second metal electrode.

[0029] The active layer includes an emitter conductive layer 200, a back barrier layer, a functional layer, a collector conductive layer, and an infrared detection layer. These layers are sequentially stacked on a GaAs substrate. Specifically, the emitter conductive layer 200 is located above the GaAs substrate 100, the back barrier layer is located above the emitter conductive layer, the functional layer is located above the back barrier layer, the collector conductive layer is located above the functional layer, and the infrared detection layer is located above the functional layer.

[0030] Semi-insulating GaAs possesses extremely high resistivity, enabling it to effectively isolate current and prevent parasitic and leakage currents in the device. This ensures that the photocurrent in the quantum well structure is not interfered with by the substrate material, thereby improving the signal quality and response sensitivity of the detector.

[0031] The emitter conductive layer is primarily responsible for providing the electron source to the device, ensuring efficient electron injection into the quantum well. A good ohmic contact is formed between the emitter conductive layer and the external electrodes, thereby optimizing the device's current transport efficiency.

[0032] The back barrier layer reduces dark current by forming a barrier structure. Dark current in the quantum well (QWIP) is caused by thermally excited charge carriers. In the absence of an optical signal, dark current reduces the detector's signal-to-noise ratio, affecting its detection performance. The back barrier layer used in this embodiment effectively prevents thermally excited electrons from entering the quantum well, thereby reducing dark current.

[0033] The quantum well structure formed in the functional layer traps infrared photons, exciting electrons to jump from the quantum well to the conduction band, generating photoelectric signals. The collector conductive layer is used to collect the photogenerated electrons generated in the functional layer and transmit them to the external circuit.

[0034] The infrared detection layer is specifically designed to absorb infrared light. This layer captures incident infrared photons, excites electrons to enter the quantum trap, and generates a photocurrent signal through the action of other layers.

[0035] At least a portion of the surface of the emitter conductive layer facing away from the GaAs substrate is exposed outside the back barrier layer. That is, a portion of the emitter conductive layer is not covered by the other layers in the active layer.

[0036] The dielectric layer covers the surface of the active layer. The first metal electrode is connected to the emitter conductive layer exposed outside the back barrier layer, and the second metal electrode is connected to the collector conductive layer. The two metal electrodes electrically connect the quantum well infrared photodetector to external circuitry.

[0037] This implementation utilizes a back barrier layer to generate a back barrier on one electrode of the QWIP device to effectively reduce the dark current caused by carrier drift, thereby further improving the specific detectivity of the QWIP device.

[0038] In this embodiment, the thickness of the GaAs substrate is 50 μm to 1000 μm, and the bulk resistivity of the GaAs substrate is greater than 10. 7 The GaAs substrate with the aforementioned thickness not only provides sufficient mechanical support for the device, but also effectively suppresses leakage current and parasitic current, preventing the current conduction in the device from being interfered with by the substrate.

[0039] In this embodiment, the emitter conductive layer is a single layer or multiple layers of n + Doped GaAs layer, where n + The doping concentration is greater than 10 18 cm -3 The thickness of the emitter conductive layer is 1 nm to 1000 nm; for easy distinction, n in the emitter conductive layer + The doped GaAs layer is also referred to as the first n layer in this embodiment. + Doped GaAs layer.

[0040] n + Doped GaAs layers through n + Doping can introduce a large number of electrons as the main charge carriers. Using greater than 10... 18 cm -3 The doping concentration of the emitter layer can achieve a sufficiently high carrier concentration, thereby significantly reducing the resistivity of the layer. Low resistivity helps reduce the series resistance of the emitter layer, ensuring that electrons can be injected into the quantum well quickly and efficiently, enhancing the device's response speed and efficiency.

[0041] Under high temperature or high current conditions, electrons in QWIP devices may be thermally excited, affecting performance. + The doped layer can improve the electron injection efficiency, and together with the aforementioned thickness setting, it can reduce the interference of hot electrons on the quantum well, reduce the dark current of the device, and improve the stability of the detector.

[0042] The back barrier layer includes at least an n-doped GaAs layer 301, a first undoped GaAs layer 302, and a p-doped GaAs layer sequentially stacked in the direction of the back emitter conductive layer. + The system consists of a doped GaAs layer 303 and a second undoped GaAs layer 304, wherein the thickness of the n-doped GaAs layer is 1 nm to 1000 nm, and the doping concentration of n is 10. 16 ~10 18 cm -3 p + The thickness of the doped GaAs layer is 1 nm to 100 nm, p + The doping concentration is greater than 10 17 cm -3 The thickness of the first undoped GaAs layer is 1 nm to 100 nm, and the thickness of the second undoped GaAs layer is 1 nm to 100 nm.

[0043] In this embodiment, the back barrier layer has at least two undoped layers, which are referred to as the first undoped GaAs layer 302 and the second undoped GaAs layer 303 for easy distinction.

[0044] The aforementioned structure in the back barrier layer optimizes electron transport and barrier formation. The thickness and doping concentration of these four layers ensure barrier formation and current control, enabling the back barrier layer to provide good electron transport characteristics while suppressing dark current. The back barrier formed using the above structure can effectively control electron flow and reduce dark current.

[0045] In this embodiment, the functional layer consists of multiple loops of In. x Ga 1-x The multi-quantum-well structure composed of As and GaAs has a cycle count of 3 to 15, and the In of each cycle is... x Ga 1-x The thickness of the As layer 402 is the same as that of the In composition, and the thickness is 1 nm to 10 nm. The x ranges from 0.1 to 0.7. The thickness of the GaAs layer in each cycle is the same, and the thickness is 1 nm to 100 nm. For ease of description, the GaAs layer in each cycle is also referred to as the functional layer GaAs layer 401 in this paper.

[0046] One of the loops consists of a layer of In x Ga 1-x It consists of As and a GaAs layer. The quantum well structure is constructed using a narrow bandgap material (such as In). x Ga 1-x This structure is formed by alternating growth of In and wide-bandgap materials (such as GaAs). When a photon excites an electron in the quantum well, the electron jumps from the quantum well to the conduction band, generating a photoelectric signal. In this embodiment, multiple cycles of the terminal quantum well structure increase the light absorption area, thereby improving the photodetector's response to infrared light in a specific wavelength band. This embodiment can also control the strength of the quantum confinement effect by adjusting the thickness of the quantum well. x Ga 1-x The In component in As controls the bandgap width of the material, thereby controlling the device's response to infrared light of different wavelengths. By varying x within the range of 0.1 to 0.7, the bandgap of the material adjusts the peak absorption wavelength of the quantum well for infrared light, thus covering different infrared detection requirements. For example, a higher In component (x close to 0.7) corresponds to longer wavelength infrared detection, while a lower In component (x close to 0.1) is suitable for shorter wavelength detection.

[0047] In this embodiment, the functional layer of QWIP is designed with multiple loops of In x Ga 1-x As and GaAs quantum well structures, combined with a multilayer design of the collector conductive layer, can provide flexible wavelength tuning capabilities while optimizing photodetector performance. Using the aforementioned structure, the thickness of the quantum well and barrier, and the In... x Ga 1-xThe composition of As, combined with the aforementioned multilayer collector conductive layer structure, enables efficient infrared light absorption, low dark current, high sensitivity, and good electron collection efficiency.

[0048] In this embodiment, the collector conductive layer includes at least a third undoped GaAs layer 501 and a second n layer sequentially stacked in the direction away from the functional layer. + The doped GaAs layer 502; the infrared detection layer 503 includes n + In doping x Ga 1-x As layer, wherein the thickness of the third undoped GaAs layer is 1nm to 1000nm, n + The thickness of the doped GaAs layer ranges from 1 nm to 1000 nm, n + Doping concentration greater than 10 18 cm -3 n + In doping x Ga 1-x The thickness of the As layer is 1nm to 100nm, n + Doping concentration greater than 10 18 cm -3 The range of x is 0.1 to 0.9.

[0049] The undoped GaAs layer (third undoped GaAs layer) in the collector conductive layer can act as a buffer layer, effectively isolating the functional layer (quantum well structure) from the n-type collector conductive layer. + The doped layer prevents it from having an excessive influence on the behavior of electrons in the quantum well. Furthermore, the undoped GaAs layer prevents electrons from tunneling directly into the collector conductive layer, ensuring efficient electron transitions within the quantum well and increasing photoelectric conversion efficiency.

[0050] Using the aforementioned thickness for undoped GaAs layers can effectively control the degree of electronic isolation and tunneling effect, maintain sensitivity, and reduce dark current. + The doped GaAs layer has a high carrier concentration, which ensures that electrons can be effectively collected from the quantum well, reduces the resistance in current transmission, maintains high conductivity, thereby improving the response speed of the device, reducing series resistance, and enhancing the current output capability of the detector.

[0051] n + In doping x Ga 1-x The As layer has a narrow band gap, which is similar to that of quantum well materials (In). x Ga 1-xMatching the In composition (x) with the In content (x) allows for more efficient electron collection, improving the overall response efficiency of the device. By adjusting the In content (x) to (0.1–0.9), the electron collection capability of the device can be further optimized, ensuring that electrons in the quantum well can be efficiently transferred to external circuits. Highly doped In... x Ga 1-x The As layer not only improves conductivity but also enhances the overall performance of the device by reducing energy loss of electrons through reducing bandgap differences.

[0052] Example 2

[0053] like Figure 2 As shown, this embodiment provides a method for manufacturing a quantum well infrared photodetector with a back barrier. This method is used to manufacture the quantum well infrared photodetector with a back barrier described in Embodiment 1. The method includes:

[0054] S1: An emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer, and an infrared detection layer are sequentially epitaxially grown on a semi-insulating GaAs substrate; the structure after this step is as follows. Figure 3 As shown.

[0055] As an example, the back barrier layer includes at least an n-doped GaAs layer, a first undoped GaAs layer, a p+ doped GaAs layer, and a second undoped GaAs layer stacked sequentially in the direction away from the emitter conductive layer.

[0056] As another example, the back barrier layer includes, in addition to the n-doped GaAs layer, a transition layer, and a p-type layer sequentially stacked in the direction of the back emitter conductive layer, + A doped GaAs layer and a second undoped GaAs layer;

[0057] The transition layer is doped with n and p. +

[0058] The doping concentration of n in the transition layer decreases gradually from the direction away from the emitter conductive layer, p + The doping concentration increases gradually from the direction towards the back of the emitter conductive layer. In the first transition layer, the n-doping concentration gradually decreases from the preset concentration of the n-doping source to 0, while in the second transition layer, the p+ doping concentration gradually increases from 0 to the preset concentration of the p+ doping source.

[0059] This embodiment employs the aforementioned structure to avoid direct contact between the n-type and p-type layers in the back barrier, thus preventing potentially high barrier mismatch and carrier scattering at the interface. By introducing a doping gradient between the n-layer and p-layer, this embodiment creates a smooth bandgap transition region, which helps reduce backscattering of electrons in the transition region, thereby improving the device's current transport characteristics and quantum efficiency.

[0060] As one example, p + The doping begins at a point where the n-type doping concentration drops to 0. In the transition layer, the n-type doping concentration decreases progressively towards the emitter conductive layer, while the p+ doping concentration increases progressively towards the emitter conductive layer. This structure allows the n-type concentration to gradually decrease before slowly introducing p-type doping, resulting in a smooth potential change in the band structure within this region.

[0061] During epitaxial growth, a real-time adjustable doping source supply system is used for dynamic control. This can be divided into several growth sub-stages: Regarding S142: the evaporated As source, Ga source, and p-type dopant are controlled in a vacuum environment according to the parameters of the back barrier layer. + The doping source and the n-doping source move toward the emitter conductive layer and deposit on the emitter conductive layer to form a back barrier layer. The parameters of the back barrier layer include the thickness and doping concentration of each layer in the back barrier layer.

[0062] S1421: Determine the initial flux of the n-doped source based on the preset concentration of the n-doped source in the n-doped GaAs layer;

[0063] The flux of the n-doped source is directly proportional to its concentration. The preset concentration of the n-doped source in the n-doped GaAs layer is the ideal concentration of the n-doped source in the GaAs layer that meets the requirements, and this concentration is set by the designer.

[0064] S1422: Determine the flow rate variation law of the n-doped source based on the preset concentration variation law of the n-doped source in the first transition layer and the initial flow rate of the n-doped source, wherein the preset concentration variation law of the n-doped source is to gradually decrease from the initial concentration to 0.

[0065] Since the flow rate of the n-doped source is directly proportional to its concentration, the flow rate of the n-doped source at each doping concentration during the deposition process can be obtained by using the preset concentration variation law of the n-doped source, thus forming the flow rate variation law of the n-doped source.

[0066] S1423: The flow rate of the n-doped source during the deposition of the first transition layer is controlled according to the initial flow rate of the n-doped source and the flow rate variation law of the n-doped source.

[0067] S1424: According to p + p-doped GaAs layers + Determining the preset doping concentration p of the doping source + The final flow rate of the doped source;

[0068] The flux of the p+ doped source is directly proportional to its concentration. The preset concentration of the p+ doped source in the p+ doped GaAs layer is the ideal concentration of the n-doped source in the GaAs layer that meets the requirements; this concentration is set by the designer.

[0069] S1425: According to the p of the transition layer + The variation law of the preset concentration of the dopant source and p + The final flux of the doped source is determined by p. + The flow rate variation law of the doping source, wherein the preset concentration variation law of the p+ doping source is to gradually increase from 0 to the final flow rate;

[0070] S1426: According to p + The final flux and p of the doped source + The flux variation of the doping source controls the p during the deposition of the second transition layer. + The flow rate of the dopant source.

[0071] In this embodiment, the flux of the dopant source is finely adjusted multiple times to achieve the desired high doping level of p-type doping at the end of the transition region. After the gradient doping transition region is grown using the aforementioned method, the back barrier layer will have a smoother band transition region. This region reduces carrier backscattering and interface recombination caused by abrupt doping changes, improving the carrier transport efficiency of the device. This provides better electron injection and blocking conditions for the quantum well structure of subsequent functional layers, indirectly improving photoelectric conversion efficiency and detection sensitivity.

[0072] S1: The process of sequentially epitaxially growing an emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer, and an infrared detection layer on a semi-insulating GaAs substrate includes:

[0073] S11: Clean the semi-insulating GaAs substrate to remove organic matter, particles and surface oxide layer from the surface of the semi-insulating GaAs substrate.

[0074] S12: Polishing the cleaned GaAs substrate;

[0075] This step can also involve treating the wafer surface with high-temperature (around 700℃) H2 gas to improve surface smoothness and provide a high-quality foundation for subsequent growth.

[0076] S131: Connect the Ga source and n + The doping source is loaded into the source furnace of the molecular beam epitaxy equipment;

[0077] In practice, silicon (Si) can be used as a doping source to control the high carrier concentration.

[0078] S132: For Ga source and n +The dopant source is heated to evaporate and deposit onto the surface of the GaAs substrate to form an emitter conductive layer;

[0079] S141: For As source, Ga source, p + The doped source and n-doped source materials are heated to evaporate them;

[0080] S142: Controlling the evaporation of As, Ga, and p sources in a vacuum environment based on the parameters of the back barrier layer. + The doped source and the n-doped source move toward the emitter conductive layer and deposit on the emitter conductive layer to form a back barrier layer. The parameters of the back barrier layer include the thickness and doping concentration of each layer in the back barrier layer. The thickness is positively correlated with the deposition time, and the doping concentration is positively correlated with the flux of each material source.

[0081] During the growth of the back barrier layer, the uniformity of the layer can be ensured by adjusting the growth rate and temperature.

[0082] S151: Heating the As source, Ga source and In source materials causes them to evaporate and form As source, Ga source and In source gas streams;

[0083] S152: Control the As source, Ga source and In source to flow toward the back barrier layer according to the functional layer parameters and deposit them on the back barrier layer to form a functional layer. The parameters of the functional layer include the thickness of each layer in the functional layer.

[0084] During the functional layer growth process, precise control of growth conditions can ensure the uniformity and defect-free nature of the entire multi-quantum-well structure, maximizing photoelectric conversion efficiency. Thickness is positively correlated with deposition time, and doping concentration is positively correlated with the flux of each material source.

[0085] S161: For As source, Ga source, In source and n + The dopant source material is heated to evaporate it;

[0086] S162: Control the As source, Ga source, In source, and n based on the collector layer parameters. + The doped source gas flows toward the functional layer and is deposited on the functional layer to form a collector conductive layer. The parameters of the collector conductive layer include the thickness and doping concentration of each layer of the collector conductive layer.

[0087] After the current collector layer is grown, crystal quality is checked. Testing techniques such as X-ray diffraction (XRD) and scanning electron microscopy (SEM) are used to ensure the quality of the layer and the absence of defects at the interface.

[0088] S171: For As source, Ga source, In source and n + The doped source material is heated to evaporate it, forming As source, Ga source, In source and n source. + Doping source gas flow;

[0089] S172: Control the As source, Ga source, In source, and n based on the infrared detection layer parameters. + The doped source gas flow is directed toward the back barrier layer and deposits an infrared detector layer on the back barrier layer. The parameters of the infrared detector layer include the thickness and doping concentration of each layer. The thickness is positively correlated with the deposition time, and the doping concentration is positively correlated with the flow rate of each material source.

[0090] S2: Remove a portion of the material in a first designated region on the wafer to expose the emitter conductive layer in that region;

[0091] In practice, the material above the emitter conductive layer in the first designated region, namely the back barrier layer, functional layer, collector conductive layer, and infrared detection layer, can be removed. This exposes the upper surface of the emitter conductive layer in the first designated region, preventing it from being obscured by other layers and facilitating subsequent manufacturing processes. The structure after this step is as follows: Figure 4 As shown.

[0092] S3: A dielectric layer is deposited across the entire wafer surface to form electrical insulation, ensuring isolation between different electrodes and conductive layers and preventing short circuits or parasitic currents. Furthermore, in this embodiment, the dielectric layer can also protect the underlying structure from contamination by subsequent processes, ensuring long-term stable device performance. The structure after this step is as follows... Figure 5 As shown.

[0093] S4: Remove the dielectric layer located in the second specified region on the surface of the dielectric layer;

[0094] The second designated region is the area in the emitter conductive layer that needs to form an electrical connection with the metal electrode. This step first removes the dielectric layer in this region, leaving space for the subsequent deposition of the metal electrode. The structure after this step is as follows. Figure 6 As shown.

[0095] S5: Deposit a metal electrode in the second designated region after the dielectric layer has been removed and perform heat treatment. The structure after this step is as follows. Figure 7 As shown.

[0096] This embodiment utilizes epitaxial growth on a semi-insulating GaAs substrate. Each layer is grown according to a designed thickness and doping concentration, including an emitter conductive layer (providing electron injection), a back barrier layer (suppressing dark current), a functional layer (quantum well structure for infrared light absorption), a collector conductive layer (electron collection), and an infrared detector layer (absorbing infrared light). By precisely controlling the thickness and doping concentration of each layer, the electrical performance and matching between the layers are ensured, providing a foundation for high-performance detection devices. This approach improves the device's photoelectric conversion efficiency and signal-to-noise ratio, particularly through the effective suppression of dark current via the back barrier layer design. In this embodiment, heat treatment after metal electrode deposition improves the contact performance between the metal electrode and the emitter conductive layer, reduces contact resistance, and forms a stable ohmic contact.

[0097] The deposition of the dielectric layer not only provides electrical insulation, but also protects the quantum well structure, back barrier layer and conductive layer, ensuring that the device is not affected by external environmental interference during long-term operation.

[0098] The first designated region can be a continuous region or a combination of multiple non-contiguous regions; there is no restriction on this.

[0099] The second designated region can be a continuous region or a combination of multiple non-contiguous regions, and there is no restriction here.

[0100] The method for removing a portion of the material in a first designated area on the wafer is plasma dry etching and / or wet etching.

[0101] In practice, plasma dry etching can be used alone, wet etching can be used alone, or a combination of plasma dry etching and wet etching can be used.

[0102] Plasma etching is used to remove the dielectric layer by bombarding the surface of the dielectric layer with high-energy ions, removing material atoms layer by layer. This achieves etching precision down to the submicron to nanometer level, enabling precise machining of complex structures in high-precision QWIP devices and effectively ensuring device quality. Furthermore, plasma etching has strong directionality, allowing for vertical etching without lateral expansion. For the material removal of layered structures in this embodiment, it allows for precise etching of the first designated area without affecting surrounding areas, minimizing damage to surrounding materials and ensuring the structural integrity of the detector. This embodiment also utilizes plasma etching to rapidly remove dielectric layers made of oxide materials such as silicon oxide and silicon nitride.

[0103] This embodiment employs wet etching, which utilizes a chemical solution to react with the material, dissolving and removing it. This method allows for rapid etching, increasing the processing speed and significantly shortening the processing time.

[0104] In addition, this embodiment can also use a combination of plasma dry etching and wet etching. For example, wet etching can be used to remove more material first, and then dry etching can be used to finely process specific areas. This can effectively reduce the processing time of dry etching, reduce costs, and at the same time ensure etching accuracy.

[0105] The method for removing the dielectric layer in the second designated region is plasma dry etching and / or wet etching. In specific implementation, plasma dry etching can be used alone, wet etching can be used alone, or a combination of plasma dry etching and wet etching can be used.

[0106] The dielectric layer material includes an oxide film with a thickness of 1 nm to 1000 nm, formed using vapor deposition. This embodiment utilizes vapor deposition to form a uniform and dense thin film. The dielectric layer generated by vapor deposition has a smooth surface and a uniform internal structure, thereby reducing defect introduction. The high-quality thin film provided by vapor deposition effectively isolates the layers, preventing leakage or short circuits and ensuring long-term stable operation of the detector.

[0107] In this embodiment, the metal electrode comprises a metal layer formed of Ni and / or Ge and / or Au, with each metal layer having a thickness of 1 nm to 1000 nm. The metal electrode is deposited using sputtering and / or vapor deposition methods. The metal electrode can be deposited using sputtering, vapor deposition, or a combination of both.

[0108] The heat treatment temperature is 350℃~550℃, the heat treatment time is 1~3600s, and the heat treatment method is rapid annealing. This embodiment achieves high-temperature treatment in a very short time and cools rapidly after heat treatment. Utilizing the characteristics of rapid heating and cooling reduces the thermal diffusion effect, minimizing the impact on other layers of the device (such as the quantum well layer and back barrier layer), and avoiding material diffusion or crystal structure damage caused by prolonged heating. Rapid annealing effectively avoids excessively long high-temperature exposure, reduces material migration and interface diffusion, maintains the structural integrity of each layer, and improves the stability of the device. The high temperature of rapid annealing in this embodiment promotes atomic diffusion between the metal electrode and the emitter conductive layer, thereby enhancing the bonding force between the electrode and the semiconductor, reducing contact resistance, and forming a good ohmic contact. During the deposition of the metal electrode, certain mechanical stresses are generated between the materials. Rapid annealing can release these stresses under short-term high-temperature treatment, thereby eliminating stress between the thin film and the substrate. Stress elimination effectively avoids thin film cracking, warping, and other phenomena caused by temperature changes during subsequent use, ensuring the mechanical stability and long-term reliability of the electrode, thus extending the service life of the QWIP device. Rapid annealing can improve the crystallinity of metal thin films, resulting in a more uniform atomic arrangement and reducing grain boundaries and defects. This lattice rearrangement enhances the conductivity of the metal electrodes, allowing current to flow more smoothly. A high-quality metal crystal structure reduces electrode resistance, decreases signal transmission loss, and improves the electrical performance and response speed of the detector. The high temperature of rapid annealing helps remove impurities or residual gases from the material, while also repairing defects that may occur during metal deposition, optimizing the overall quality of the electrode layer. Figure 8 , Figure 9 and Figure 10 The comparative experiments show that the QWIP device in this embodiment has significant advantages over the prior art in suppressing dark current, improving device responsivity, and improving device specific detectivity.

[0109] In this embodiment, step S2: removing a portion of the material in a first designated region on the wafer to expose the emitter conductive layer in that region includes:

[0110] S21: Place the cleaned wafer into the plasma etching equipment;

[0111] The wafer surface is cleaned to remove dust, oil, and organic contaminants. An etching mask layer (e.g., photoresist or silicon oxide layer) is formed on the wafer surface using photolithography. The mask material covers non-designated areas, exposing a first designated area. The mask pattern is formed through photolithographic exposure and development processes, and the resolution of the mask edges should meet process requirements. Ensure that the shape, size, and location of the first designated area conform to the design; the designated area can be a continuous region or a combination of multiple discontinuous regions. The cleaned wafer is placed in a plasma etching apparatus (such as RIE or ICP equipment).

[0112] S22: Adjust the type and flow rate of the etching gas;

[0113] For example, using chlorine (Cl2) or argon (Ar) ensures that the gas can react effectively and etch the target material.

[0114] Gas flow rate: Controlled within the range of 10–100 sccm. Chamber pressure: Maintained within the range of 10–200 mTorr.

[0115] S23: Activate the plasma source to generate high-energy ions;

[0116] S24: Using high-energy ions to physically bombard and chemically react a first designated region, wherein the first designated region is a continuous region or a combination of multiple discontinuous regions.

[0117] During the etching process, optical monitoring systems (such as end-point detection) are used to determine the etching depth and progress. This ensures the integrity of the target area is maintained during etching, while avoiding over-etching that could damage the underlying emitter conductive layer.

[0118] In this embodiment, step S4: removing the dielectric layer located in the second designated region includes:

[0119] S41: Prepare the wet etching solution;

[0120] This step involves selecting a suitable wet etching solution based on the target material.

[0121] S42: Adjust the temperature and concentration of the wet etching solution according to the etching rate;

[0122] S43: Place the wafer in a wet etching tank so that the second designated area is in full contact with the etching solution shown. The second designated area is a continuous area or a combination of multiple discontinuous areas.

[0123] S44: Monitor the etching progress in real time until the dielectric layer of the second designated area is completely removed;

[0124] S45: Clean the etched area with deionized water. After cleaning, treat the wafer with a blower or low-temperature dryer to ensure no liquid residue remains on the surface. Ensure a clean surface after etching.

[0125] 7. The method for manufacturing a quantum well infrared photodetector with a back barrier according to claim 4, characterized in that, step S5: depositing a metal electrode in a second designated region where the dielectric layer has been removed and performing heat treatment includes;

[0126] S51: Clean the wafer to be deposited;

[0127] Standard wet cleaning processes (e.g., acetone, isopropanol, deionized water) are used to remove surface dust, organic contaminants, and particles. A dilute HF solution is used to remove the oxide layer and residues from the surface, achieving a high level of cleanliness. Nitrogen (N2) gas is used for blowing and drying, or a low-temperature drying process is employed to ensure that no residual liquid remains on the wafer surface.

[0128] S52: Place the clean and dry wafer on the sample stage of the deposition equipment;

[0129] S53: Start the vacuum pump to evacuate the reaction chamber to the preset vacuum level;

[0130] S54: Introduce precursor gas and oxidizing gas at the set flow rate;

[0131] S55: Starts the radio frequency power supply, generates plasma, and excites the gas to carry out a chemical reaction;

[0132] S56: An oxide film with a thickness of 1 nm to 1000 nm is generated on the wafer surface through plasma-enhanced chemical reaction.

[0133] After deposition is complete, the precursor gas and plasma are stopped, and the radio frequency power supply is turned off. Nitrogen gas (N2) is gradually introduced for cleaning. After the reaction product chamber is purged and returned to atmospheric pressure, the deposited wafer is removed.

[0134] In this embodiment, S3: depositing a dielectric layer on the entire wafer surface includes;

[0135] S31: Clean the wafer surface to remove any possible oxide layer;

[0136] Before electrode deposition, the wafer surface is cleaned to remove dust, organic matter, or residual oxide layers. A dilute hydrofluoric acid (HF) solution is used to remove any existing oxide layers, ensuring good contact between the metal layer and the emitter conductive layer.

[0137] S32: After rinsing the wafer with deionized water, dry it with high-purity nitrogen gas;

[0138] S33: Fix the cleaned wafer onto the sample stage of the vapor deposition chamber;

[0139] S34: Evacuate to the target vacuum level;

[0140] High vacuum evaporation equipment was used, and evaporation sources were configured to load metal targets for Ni, Ge, and Au, respectively.

[0141] S35: Start the evaporation source heating device and heat it to the evaporation temperature of nickel. The evaporated nickel atoms diffuse in the vacuum chamber and deposit on the wafer surface to form the first thin film. Control the coating time to achieve the target thickness of 5nm and measure it in real time through the film thickness monitor.

[0142] S36: Replace the evaporation source with germanium, heat it to its evaporation temperature, and the evaporated germanium atoms cover the nickel layer to form a second thin film; the evaporated germanium atoms cover the nickel layer to form a second thin film with a thickness controlled at 15nm.

[0143] S37: Replace the evaporation source with nickel and heat it to its evaporation temperature. The evaporated nickel atoms cover the germanium layer, forming a third thin film. Control the deposition time to deposit a 50nm thick nickel layer.

[0144] S38: Replace the vapor deposition source with gold, heat it to its evaporation temperature, and the evaporated gold atoms cover the gold layer to form a fourth thin film.

[0145] S5: Depositing a metal electrode in the second designated region after removing the dielectric layer and performing heat treatment includes:

[0146] S501: Rapidly heat the sample to be processed to 420℃;

[0147] A rapid annealing (RTA) apparatus was used, with the heating temperature set to 420°C and the annealing time to 60 seconds. High-purity nitrogen (N2) or an inert gas (such as argon, Ar) was introduced into the annealing chamber to prevent oxidation of the metal layer at high temperatures.

[0148] S502: Maintain the temperature at 420℃ for 60 seconds; during this process, Ge and Ni react to form a nickel-germanium alloy (NiGe), further reducing the contact resistance between the electrode and the conductive layer.

[0149] S503: After annealing, stop heating and allow the sample to cool to room temperature.

[0150] After annealing, heating should be stopped immediately, and the sample should be rapidly cooled to room temperature. Rapid cooling can prevent excessive diffusion or wafer stress buildup caused by high temperatures.

[0151] S1: The process of sequentially epitaxially growing an emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer, and an infrared detection layer on a semi-insulating GaAs substrate includes:

[0152] S11: Obtain the spectral range of infrared light detected by the detector;

[0153] Depending on the specific detection requirements, the range of infrared light detected by the detector can vary.

[0154] This embodiment uses an optimized design strategy to manufacture an infrared detector that can meet the set detection spectral range.

[0155] The infrared spectral range includes, but is not limited to, mid-wave infrared, long-wave infrared, or specific narrow bands. This embodiment can meet the spectral range required for detection by using the design parameters of a multi-quantum-well structure. These parameters include at least the material selection, thickness, and composition ratio of the quantum wells and barrier layers.

[0156] S12: Based on the spectral range of the infrared light, perform theoretical simulation using semiconductor physics simulation software to analyze In... x Ga- x The parameter ranges of As and GaAs layer thickness, In composition (x), and number of cycles are defined once to obtain the parameter space of the functional layer;

[0157] In x Ga 1-x The thickness of As affects the quantum confinement effect. Too thin a layer leads to enhanced tunneling and increased dark current; too thick a layer reduces the quantum confinement effect and weakens sensitivity to the target wavelength.

[0158] The GaAs layer, acting as a barrier layer for quantum wells, determines the probability of electron tunneling between quantum wells based on its thickness. Too thin a layer enhances electron tunneling and increases dark current; too thick a layer may weaken the coupling between quantum wells, reducing light absorption efficiency.

[0159] The number of cycles (3–15) determines the optical absorption path length of the quantum well. Too few cycles reduce the number of interactions between photons and the quantum well, leading to a decrease in optical absorption efficiency; too many cycles increase the device thickness and fabrication complexity.

[0160] The content of In component x value determines In x Ga 1-x The bandgap of the As layer. The higher the x value, the smaller the bandgap, and the more sensitive the quantum well is to long-wave infrared (LIR); the lower the x value, the larger the bandgap, and the more suitable it is for mid-wave infrared (MIR) or short-wave infrared (SWIR).

[0161] Specifically, this includes constructing quantum well models using simulation software (such as Silvaco TCAD, Nextnano, COMSOL Multiphysics, or other semiconductor physics simulation tools).

[0162] The infrared spectral range is input into the model. The software simulates the band structure and electronic energy levels, comparing the degree of matching between the transition energies and the infrared spectral range (photon energy = hc / λ) to select the transition energies of the quantum wells that match the detected spectral range. The energy level distribution of electrons in the quantum well is selected based on the transition energies. Then, the In value is given based on the energy level distribution. x Ga- x The parameter ranges for As and GaAs layer thickness, In composition (x), and cycle number are defined. A parameter space is generated using these given parameter ranges.

[0163] S13: Randomly generate a set of initial sampling points in the parameter space;

[0164] S14: Obtain the performance data corresponding to each initial sampling point;

[0165] This step involves using the initial sampling points as design parameters to conduct preliminary experiments or simulations to obtain the detector's performance data, such as the detector's dark current, responsivity, noise, specific detectivity, and electron collection efficiency.

[0166] S15: Sort each initial sampling point according to the performance evaluation criteria of the infrared detector and the performance corresponding to each initial sampling point;

[0167] This step ranks each sampling point according to its performance using performance evaluation criteria, thereby determining the merits and demerits of each sampling point.

[0168] S16: Sampling Point Distribution Optimization Process: Based on the performance data and ranking results of the sampling points, the sampling distribution is adjusted using an adaptive algorithm to obtain the optimized sampling points. The adaptive algorithm can employ a Gaussian mixture model. This step, by adjusting the sampling distribution using an adaptive algorithm, can concentrate the sampling more in regions with better performance.

[0169] S17: Sampling point search optimization process: Based on the physical model or experimental experience, heuristic rules are used to guide the search direction to search for the optimized sampling points to obtain the optimized sampling points.

[0170] This step utilizes heuristic rules to guide the search, allowing for concentrated sampling within a certain known effective parameter range and local fine-tuning, thereby improving optimization efficiency.

[0171] S18: Determine whether the detector corresponding to the optimized sampling point meets the preset conditions. If it does, output the optimized sampling point. Otherwise, repeat the sampling point distribution optimization process and the sampling point search optimization process until the detector corresponding to the optimized sampling point meets the preset conditions.

[0172] This step gradually improves performance by repeatedly updating the sampling strategy and optimizing the search direction until the predetermined optimization goal or convergence condition is reached. When the performance improvement is less than a certain preset threshold (meeting the preset condition), the optimization process is considered converged, and the optimal parameter combination is output as the final solution. Using the aforementioned method, the optimal In can be quickly found in the early design stages. x Ga 1-x The thickness of As, the x-value, the thickness of the GaAs layer, and the number of cycles are determined to meet the requirements of the spectral range and detection effect.

[0173] The following is a specific example, in which a semi-insulating GaAs substrate with a thickness of 435 μm and a bulk resistivity of 3 × 10⁻⁶ is selected. 8 Ω·cm. The preparation process includes the following steps:

[0174] (1) Epitaxial growth with a thickness of 300 nm and a doping concentration of 2 × 10⁻⁶ was performed sequentially on a semi-insulating GaAs substrate 100. 8 cm -3 n + -GaAs emitter conductive layer 200, 500 nm thick, doped with 5 × 10⁻⁶ 17 cm -3 The back barrier layer is an n-GaAs layer 301 with a thickness of 50 nm, an undoped GaAs layer 302 with a thickness of 10 nm and a doping concentration of 5 × 10⁻⁶. 17 cm -3 back barrier layer p + -GaAs layer 303, 50nm thick undoped GaAs back barrier layer 304, 10 cycles of 4nm thick In 0.3 Ga 0.7 A multi-quantum-well structure consisting of an As layer 401 and a GaAs layer 402 with a thickness of 40 nm, a 100 nm thick undoped GaAs collector conductive layer 501, and a 500 nm thick doped layer with a doping concentration of 5 × 10⁻⁶. 17 cm -3 collector conductive layer n + -GaAs layer 502, 20nm thick, doped at a concentration of 2×10⁻⁶ 8 cm -3 collector conductive layer n + -In 0.2 Ga 0.8 As layer;

[0175] (2) Using plasma dry etching, the unetched area is a circle with a diameter of 300 μm, the etched area exposes the emitter conductive layer 200, and the remaining thickness of the emitter conductive layer is greater than 400 nm.

[0176] (3) A silicon oxide dielectric film with a thickness of 100 nm was deposited using chemical vapor deposition 600.

[0177] (4) In step (2), circles with a diameter of 50 μm are formed in the unetched area and the etched area respectively, and the dielectric material 600 in the circular area is removed by plasma dry etching.

[0178] (5) Ni / Ge / Ni / Au electrodes with thicknesses of 5 / 15 / 50 / 300 nm were deposited sequentially by vapor deposition, and then annealed at 420 °C for 60 s by rapid annealing.

[0179] In this embodiment, step S2: removing a portion of the material in a first designated region on the wafer to expose the emitter conductive layer in that region includes:

[0180] S21: Place the cleaned wafer into the plasma etching equipment;

[0181] This step begins by cleaning the wafer surface to remove dust, oil, and organic contaminants. An etching mask layer is then formed on the wafer surface using photolithography. The mask material covers non-designated areas, exposing the first designated area. The mask pattern is formed through photolithography exposure and development processes, and the resolution of the mask edges should meet process requirements. Ensure that the shape, size, and position of the first designated area conform to the design; the designated area can be a continuous region or a combination of multiple discontinuous regions.

[0182] S22: Adjust the type and flow rate of the etching gas; ensure that the gas can effectively react and etch the target material. The gas can be chlorine (Cl2), argon (Ar), etc.

[0183] S23: Activate the plasma source to generate high-energy ions;

[0184] Before starting this step, you can set the following operating parameters:

[0185] RF power: The energy used to control the plasma, typically ranging from 50W to 500W.

[0186] Gas flow rate: Controlled within the range of 10 to 100 sccm.

[0187] Chamber pressure: maintained within the range of 10–200 mTorr.

[0188] Etching time: Adjusted according to material thickness and etching rate, usually from tens of seconds to several minutes.

[0189] S24: Using high-energy ions to physically bombard and chemically react a first designated region, wherein the first designated region is a continuous region or a combination of multiple discontinuous regions.

[0190] This step removes the material from the first designated area through physical bombardment and chemical reaction. After etching is complete, the ion source is stopped, the chamber is cleaned, and the wafer is removed.

[0191] The above is a detailed description of the manufacturing method of the quantum well infrared photodetector with back barrier provided in the embodiments of the present invention.

[0192] It should be clarified that the present invention is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of the present invention. The functional blocks shown in the above-described structural block diagrams can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application-specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present invention are programs or code segments used to perform the desired tasks. The programs or code segments can be stored in a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. The code segment can be downloaded via computer networks such as the Internet or intranets. It should also be noted that the exemplary embodiments mentioned in this invention describe methods or systems based on a series of steps or apparatus. However, this invention is not limited to the order of the steps described above; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0193] The above description is merely a specific embodiment of the present invention. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the protection scope of the present invention.

Claims

1. A quantum well infrared photodetector with a back barrier, characterized in that, The device includes a GaAs substrate, an active layer, a dielectric layer, a first metal electrode, and a second metal electrode. The active layer includes an emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer, and an infrared detection layer. The emitter conductive layer, back barrier layer, functional layer, collector conductive layer, and infrared detection layer are sequentially stacked on the GaAs substrate. At least a portion of the surface of the emitter conductive layer facing away from the GaAs substrate is exposed outside the back barrier layer. The dielectric layer covers the surface of the active layer. The first metal electrode is connected to the emitter conductive layer exposed outside the back barrier layer, and the second metal electrode is connected to the collector conductive layer. The thickness of the GaAs substrate is 50 μm to 1000 μm, and the bulk resistivity of the GaAs substrate is greater than 10. 7 Ω·cm; The emitter conductive layer comprises a single layer or multiple layers of a first n layer. + Doped GaAs layer, where n + The doping concentration is greater than 10 18 cm -3 The thickness of the emitter conductive layer is 1 nm to 1000 nm; The back barrier layer includes at least an n-doped GaAs layer, a first undoped GaAs layer, and a p-doped GaAs layer stacked sequentially in the direction of the back emitter conductive layer. + A doped GaAs layer and a second undoped GaAs layer; wherein the thickness of the n-doped GaAs layer is 1 nm to 1000 nm, and the doping concentration of n is 10. 16 ~10 18 cm -3 ; p + The thickness of the doped GaAs layer is 1 nm to 100 nm, p + The doping concentration is greater than 10 17 cm -3 ; The thickness of the first undoped GaAs layer is 1 nm to 100 nm, and the thickness of the second undoped GaAs layer is 1 nm to 100 nm. The current collector conductive layer includes at least a third undoped GaAs layer and a second n-layer layer stacked sequentially in the direction away from the functional layer. + The doped GaAs layer; the infrared detection layer includes n + In doping x Ga 1-x As layer, wherein the thickness of the third undoped GaAs layer is 1nm to 1000nm, n + The thickness of the doped GaAs layer ranges from 1 nm to 1000 nm, n + Doping concentration greater than 10 18 cm -3 n + In doping x Ga 1-x The thickness of the As layer is 1nm to 100nm, n + Doping concentration greater than 10 18 cm -3 The range of x is 0.1 to 0.

9.

2. The quantum well infrared photodetector with a back barrier as described in claim 1, characterized in that, The functional layer is In x Ga 1-x A multi-quantum-well structure composed of As and GaAs undergoing 3 to 15 cycles, with In in each cycle... x Ga 1-x Thickness of As layer and In x Ga 1-x The In components in the As layer are all the same, and the In content in each cycle is... x Ga 1-x The thickness of the GaAs layer is 1 nm to 10 nm, where x ranges from 0.1 to 0.

7. The thickness of the GaAs layer is the same for each cycle and the thickness of the GaAs layer for each cycle is 1 nm to 100 nm.

3. A method for manufacturing a quantum well infrared photodetector with a back barrier, characterized in that, The method for manufacturing a quantum well infrared photodetector with a back barrier as described in any one of claims 1 to 2, the method comprising: S1: An emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer, and an infrared detection layer are sequentially epitaxially grown on a semi-insulating GaAs substrate. S2: Remove a portion of the material in a first designated region on the wafer to expose the emitter conductive layer in that region, wherein the first designated region is the region in the infrared detection layer that needs to form an electrical connection with the metal electrode; S3: Deposit a dielectric layer across the entire wafer surface; S4: Remove the dielectric layer located in the second designated region, where the second designated region is the region in the emitter conductive layer that needs to form an electrical connection with the metal electrode; S5: Deposit a metal electrode in the second designated area where the dielectric layer has been removed and perform heat treatment.

4. The method for manufacturing a quantum well infrared photodetector with a back barrier according to claim 3, characterized in that, S1: The process of sequentially epitaxially growing an emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer, and an infrared detection layer on a semi-insulating GaAs substrate includes: S11: Clean the semi-insulating GaAs substrate to remove organic matter, particles and surface oxide layer from the surface of the semi-insulating GaAs substrate. S12: Polishing the cleaned GaAs substrate; S131: Connect the Ga source and n + The doping source is loaded into the source furnace of the molecular beam epitaxy equipment; S132: For Ga source and n + The dopant source is heated to evaporate and deposit onto the surface of the GaAs substrate to form an emitter conductive layer; S141: For As source, Ga source, p + The doped source and n-doped source materials are heated to evaporate them; S142: Controlling the evaporation of As, Ga, and p sources in a vacuum environment based on the parameters of the back barrier layer. + The doping source and the n-doping source move toward the emitter conductive layer and deposit a back barrier layer on the emitter conductive layer. The parameters of the back barrier layer include the thickness and doping concentration of each layer in the back barrier layer. S151: Heating the As source, Ga source and In source materials causes them to evaporate and form As source, Ga source and In source gas streams; S152: Control the As source, Ga source and In source to flow toward the back barrier layer according to the functional layer parameters and deposit them on the back barrier layer to form a functional layer. The parameters of the functional layer include the thickness of each layer in the functional layer. S161: For As source, Ga source, In source and n + The dopant source material is heated to evaporate it; S162: Control the As source, Ga source, In source, and n based on the collector layer parameters. + The doped source gas flows toward the functional layer and is deposited on the functional layer to form a collector conductive layer. The parameters of the collector conductive layer include the thickness and doping concentration of each layer of the collector conductive layer. S171: For As source, Ga source, In source and n + The doped source material is heated to evaporate it, forming As source, Ga source, In source and n source. + Doping source gas flow; S172: Control the As source, Ga source, In source, and n based on the infrared detection layer parameters. + The doped source gas flows toward the collector conductive layer and deposits an infrared detection layer on the collector conductive layer. The parameters of the infrared detection layer include the thickness and doping concentration of each layer of the infrared detection layer.

5. The method for manufacturing a quantum well infrared photodetector with a back barrier according to claim 4, characterized in that, The back barrier layer includes an n-doped GaAs layer, a first transition layer, a second transition layer, and a p-doped GaAs layer, which are sequentially stacked in the direction of the back emitter conductive layer. + A doped GaAs layer and a second undoped GaAs layer; In the first transition layer, the n-doping concentration gradually decreases from the preset concentration of the n-doping source to 0, while in the second transition layer, the p-doping concentration gradually decreases from the preset concentration of the n-doping source to 0. + The doping concentration is gradually increased from 0 to p + Preset concentration of the dopant source; S142: Controlling the evaporation of the As source, Ga source, and p source in a vacuum environment according to the parameters of the back barrier layer. + The doping source and the n-doping source move toward the emitter conductive layer and deposit on the emitter conductive layer to form a back barrier layer. The parameters of the back barrier layer include the thickness and doping concentration of each layer in the back barrier layer. S1421: Determine the initial flux of the n-doped source based on the preset concentration of the n-doped source in the n-doped GaAs layer; S1422: Determine the flow rate variation law of the n-doped source based on the preset concentration variation law of the n-doped source in the first transition layer and the initial flow rate of the n-doped source, wherein the preset concentration variation law of the n-doped source is to gradually decrease from the initial concentration to 0. S1423: Control the flow rate of the n-doped source during the deposition of the first transition layer based on the initial flow rate and the flow rate variation law of the n-doped source; S1424: According to p + p-doped GaAs layers + Determining the preset doping concentration p of the doping source + The final flow rate of the doped source; S1425: According to the p of the transition layer + The variation law of the preset concentration of the dopant source and p + The final flux of the doped source is determined by p. + The flux variation law of the doping source, the p + The preset concentration of the dopant source changes gradually from 0 to the final flow rate; S1426: According to p + The final flux and p of the doped source + The flux variation of the doping source controls the p during the deposition of the second transition layer. + The flow rate of the dopant source.

6. The method for manufacturing a quantum well infrared photodetector with a back barrier according to claim 3, characterized in that, S2: Removing a portion of the material in a first designated region on the wafer to expose the emitter conductive layer in that region, wherein the first designated region is the area in the infrared detection layer that needs to form an electrical connection with the metal electrode, including: S21: Place the cleaned wafer into the plasma etching equipment; S22: Adjust the type and flow rate of the etching gas; S23: Activate the plasma source to generate high-energy ions; S24: Using high-energy ions to physically bombard a first designated region and cause it to produce a chemical reaction, wherein the first designated region is a continuous region or a combination of multiple discontinuous regions.

7. The method for manufacturing a quantum well infrared photodetector with a back barrier according to claim 3, characterized in that, S5: The deposition of a metal electrode in the second designated region after the dielectric layer has been removed and the subsequent heat treatment include; S51: Clean the wafer to be deposited; S52: Place the clean and dry wafer on the sample stage of the deposition equipment; S53: Start the vacuum pump to evacuate the reaction chamber to the preset vacuum level; S54: Introduce precursor gas and oxidizing gas at the set flow rate; S55: Start the radio frequency power supply to generate plasma and excite the oxidizing gas to carry out a chemical reaction; S56: An oxide film with a thickness of 1 nm to 1000 nm is generated on the wafer surface through plasma-enhanced chemical reaction.

8. The method for manufacturing a quantum well infrared photodetector with a back barrier according to claim 3, characterized in that, S3: Depositing a dielectric layer across the entire wafer surface includes; S31: Clean the wafer surface to remove the oxide layer; S32: After rinsing the wafer with deionized water, dry it with high-purity nitrogen gas; S33: Fix the dried wafer onto the sample stage of the vapor deposition chamber; S34: Evacuate to the target vacuum level; S35: Start the evaporation source heating device and heat it to the evaporation temperature of nickel. The evaporated nickel atoms diffuse in the vacuum chamber and deposit on the wafer surface to form the first thin film. S36: Replace the vapor deposition source with germanium, heat it to its evaporation temperature, and the evaporated germanium atoms cover the nickel layer to form a second thin film; S37: Replace the vapor deposition source with nickel, heat it to its evaporation temperature, and the evaporated nickel atoms cover the germanium layer to form a third thin film. S38: Replace the vapor deposition source with gold, heat it to its evaporation temperature, and the evaporated gold atoms cover the nickel layer to form a fourth thin film.

9. The method for manufacturing a quantum well infrared photodetector with a back barrier according to claim 3, characterized in that, S1: The process of sequentially epitaxially growing an emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer, and an infrared detection layer on a semi-insulating GaAs substrate includes: S11: Obtain the spectral range of infrared light detected by the detector; S12: Based on the spectral range of the infrared light, perform theoretical simulation using semiconductor physics simulation software to analyze In... x Ga 1-x The parameter ranges of the As layer thickness, GaAs layer thickness, In composition (x), and number of cycles are defined once to obtain the parameter space of the functional layer; S13: Randomly generate a set of initial sampling points in the parameter space; S14: Obtain the performance data corresponding to each initial sampling point; S15: Sort each initial sampling point according to the performance evaluation criteria of the infrared detector and the performance data corresponding to each initial sampling point; S16: Sampling point distribution optimization process: Based on the performance data and sorting results of the sampling points, the sampling distribution is adjusted by an adaptive algorithm to obtain the optimized sampling points; S17: Sampling point search optimization process: Based on the physical model or experimental experience, heuristic rules are used to guide the search direction to search for the optimized sampling points to obtain the optimized sampling points. S18: Determine whether the detector corresponding to the optimized sampling point meets the preset conditions. If yes, output the optimized sampling point. Otherwise, repeat the sampling point distribution optimization process and the sampling point search optimization process until the detector corresponding to the optimized sampling point meets the preset conditions.

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