Light-emitting chip, display device and manufacturing method

Abstract

The invention discloses a light-emitting chip, a display device and a manufacturing method. The light-emitting chip comprises a first light-emitting unit, a second light-emitting unit and a third light-emitting unit, and the first light-emitting unit is configured to emit first color light; the second light-emitting unit comprises a second light-emitting layer and a first transflective layer, and the first transflective layer is configured to filter out the first color light, so that the second light-emitting unit emits second color light; the third light-emitting unit comprises a third light-emitting layer and a second transflective layer, and the second transflective layer is configured to filter out the first color light and / or the second color light, so that the third light-emitting unit emits third color light. According to the embodiment of the invention, a mode of combining a plurality of light-emitting layers with different colors instead of a single-light LED mode is adopted, a transflective layer is arranged, required color light rays are obtained through filtering, a full-color scheme is realized, a better display effect is achieved, full color is realized without adding quantum dots, and the production cost is greatly reduced.

Description

Technical Field

[0001] The present disclosure relates to but is not limited to the field of display technology, and in particular to a light-emitting chip, a display device and a manufacturing method. Background Art

[0002] Micro light emitting diode (Micro-LED) refers to a high-density integrated light-emitting diode array, where the distance between the light-emitting diode pixels in the array is on the order of 10 microns, and each light-emitting diode pixel can emit light by itself. Micro-LED has the characteristics of high brightness, high light efficiency, and low power consumption, but the full-color display effect of the current display using Micro-LED is not ideal, and the production cost is also high. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The technical problem to be solved by the present disclosure is to provide a light-emitting chip, a display device and a manufacturing method, which adopt the form of a combination of light-emitting layers of multiple different colors of light, rather than a single light emitting diode (LED) form, and have a transflective layer to filter the required color light to achieve a full-color solution with better display effects, and do not need to add quantum dots (QD) to achieve full color, thereby greatly reducing production costs.

[0005] At least one embodiment of the present disclosure provides a light-emitting chip, including a substrate and a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit located on the same side of the substrate;

[0006] The first light-emitting unit includes a first light-emitting layer disposed on the substrate, and the first light-emitting unit is configured to emit a first color light;

[0007] The second light-emitting unit includes a second light-emitting layer and a first transflective layer, the second light-emitting layer is arranged on the substrate, the first transflective layer is arranged on a side of the second light-emitting layer away from the substrate, and the first transflective layer is configured to filter out the first color light so that the second light-emitting unit emits the second color light;

[0008] The third light-emitting unit includes a third light-emitting layer and a second reflective layer, the third light-emitting layer is arranged on the substrate, the second reflective layer is arranged on a side of the third light-emitting layer away from the substrate, and the second reflective layer is configured to filter out the first color light and / or the second color light so that the third light-emitting unit emits a third color light.

[0009] In some exemplary embodiments, the first light emitting layer includes a first electrode layer, a first semiconductor layer, and a second electrode layer sequentially disposed on the substrate;

[0010] The second light-emitting layer comprises a first electrode layer, a first semiconductor layer, a second electrode layer and a second semiconductor layer sequentially arranged on the substrate, and the first transflective layer is located on a side of the second semiconductor layer away from the substrate;

[0011] The third light-emitting layer includes a first electrode layer, a first semiconductor layer, and a second electrode layer sequentially arranged on the substrate; the third light-emitting layer is provided with the second semiconductor and third semiconductor layers stacked on a side of the second electrode layer away from the first semiconductor layer, or the third light-emitting layer is provided with a third semiconductor layer on a side of the second electrode layer away from the first semiconductor layer, and the second reflective layer is located on a side of the third semiconductor layer away from the second electrode layer.

[0012] In some exemplary embodiments, the second light-emitting layer further comprises a third electrode layer covering a surface of the second semiconductor layer away from the second electrode layer, and in the second light-emitting layer, the first transflective layer covers a surface of the third electrode layer away from the second semiconductor layer, and the third electrode layer is electrically connected to the first electrode layer;

[0013] The third light-emitting layer also includes a third electrode layer and a fourth electrode layer. In the third light-emitting layer, the first electrode layer, the first semiconductor layer, the second electrode layer, the second semiconductor, the third electrode layer, the third semiconductor layer and the fourth electrode layer are arranged in sequence in a direction away from the substrate, the first electrode layer and the third electrode layer are electrically connected, the second electrode layer and the fourth electrode layer are electrically connected, and the second reflective layer covers the surface of the fourth electrode layer away from the third semiconductor layer.

[0014] In some exemplary embodiments, further comprising a first metal trace, a second metal trace, and a third metal trace;

[0015] The first metal wiring is located at the side of the second light-emitting layer, one end of the first metal wiring is connected to the first electrode layer, and the other end of the first metal wiring is connected to the third electrode layer, and the first semiconductor layer, the second electrode layer and the second semiconductor layer are provided with a first insulating layer on a side facing the first metal wiring;

[0016] The second metal wiring and the third metal wiring are respectively located on two opposite sides of the third light-emitting layer;

[0017] In the third light-emitting layer, one end of the second metal routing is connected to the first electrode layer, the other end of the second metal routing is connected to the third electrode layer, and the first semiconductor layer, the second electrode layer, and the second semiconductor layer are provided with a second insulating layer on the side facing the second metal routing; one end of the third metal routing is connected to the second electrode layer, the other end of the third metal routing is connected to the fourth electrode layer, and the second semiconductor layer, the third electrode layer, and the third semiconductor layer are provided with a third insulating layer on the side facing the third metal routing.

[0018] In some exemplary embodiments, in the second light-emitting layer, the orthographic projections of the first electrode layer, the first semiconductor layer, the second electrode layer, the second semiconductor layer, and the third electrode layer on the substrate are all located within the orthographic projection of the first electrode layer on the substrate;

[0019] In the third light-emitting layer, the orthographic projections of the second semiconductor, the third electrode layer, the third semiconductor layer and the fourth electrode layer on the substrate are all located within the orthographic projection of the second electrode layer on the substrate, and the orthographic projections of the second electrode layer and the first semiconductor layer on the substrate are all located within the orthographic projection of the first electrode layer on the substrate.

[0020] In some exemplary embodiments, in the third light emitting unit, the second semiconductor layer is arranged to cover a surface of the second electrode layer away from the first semiconductor layer, and the third semiconductor layer is arranged to cover a surface of the second semiconductor layer away from the second electrode layer;

[0021] The second reflective layer covers the surface of the third semiconductor layer away from the second electrode layer, and the second reflective layer is configured as a red-transmitting, blue-blocking, and green-blocking film.

[0022] In some exemplary embodiments, in the third light emitting unit, the third semiconductor layer is arranged to cover a surface of the second electrode layer away from the first semiconductor layer;

[0023] The second reflective transmissive layer covers the surface of the third semiconductor layer away from the second electrode layer, and the second reflective transmissive layer is configured as a red-transmitting and blue-blocking film.

[0024] In some exemplary embodiments, a fourth metal trace and a fifth metal trace are further included;

[0025] The second light-emitting layer is arranged on the substrate at intervals from the first light-emitting layer and the third light-emitting layer, respectively; the fourth metal wiring is located between the first light-emitting layer and the third light-emitting layer; and the second electrode layer of the second light-emitting layer is arranged to be electrically connected to the second electrode layer of the first light-emitting layer through the fourth metal wiring;

[0026] The fifth metal wiring is located between the second light-emitting layer and the third light-emitting layer, and the second electrode layer of the second light-emitting layer is configured to be electrically connected to the second electrode layer of the third light-emitting layer through the fifth metal wiring.

[0027] In some exemplary embodiments, the first semiconductor layer includes a first N-type contact layer, a first quantum well, and a first P-type contact layer sequentially arranged in a direction away from the substrate;

[0028] The second semiconductor layer includes a second P-type contact layer, a second quantum well, and a second N-type contact layer which are sequentially arranged in a direction away from the substrate;

[0029] The third semiconductor layer includes a third P-type contact layer, a third quantum well, and a third N-type contact layer which are sequentially arranged in a direction away from the substrate.

[0030] In some exemplary embodiments, the first semiconductor layer includes a first N-type contact layer, a first quantum well, and a first P-type contact layer sequentially arranged in a direction away from the substrate;

[0031] The second semiconductor layer includes a second P-type contact layer, a second quantum well, and a second N-type contact layer which are sequentially arranged in a direction away from the substrate;

[0032] The third semiconductor layer includes a third N-type contact layer, a third quantum well, and a third P-type contact layer which are sequentially arranged in a direction away from the substrate.

[0033] In some exemplary embodiments, the first color light is set to blue light, the second color light is set to green light, and the third color light is set to red light;

[0034] The first reflective layer is configured as a conductive green light-transmitting film, and the second reflective layer is configured as a conductive red light-transmitting film.

[0035] In some exemplary embodiments, a reflective film is further included, and the reflective film is configured to wrap at least the sides of the first light emitting unit, the second light emitting unit, and the third light emitting unit.

[0036] In some exemplary embodiments, a packaging structure is further included, wherein the packaging structure is disposed on the substrate and covers the first light emitting unit, the second light emitting unit, and the third light emitting unit.

[0037] At least one embodiment of the present disclosure provides a display device including the above-mentioned light-emitting chip.

[0038] At least one embodiment of the present disclosure provides a manufacturing method, which is applied to the above-mentioned light-emitting chip, including:

[0039] Depositing to form a composite film layer, depositing a first conductive layer, a first epitaxial layer, a second conductive layer, a second epitaxial layer, a third conductive layer, a third epitaxial layer and a fourth conductive layer on the substrate in sequence to obtain a composite film layer;

[0040] Etching the composite film layer to etch a light-emitting layer pattern from the composite film layer; the light-emitting layer pattern includes the first light-emitting layer, the second light-emitting layer and the third light-emitting layer spaced apart from each other, the first light-emitting layer includes a stacked first electrode layer, a first semiconductor layer and a second electrode layer; the second light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer, a second semiconductor layer and a third electrode layer; the third light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer, a second semiconductor layer, a third electrode layer, a third semiconductor layer and a fourth electrode layer;

[0041] Depositing an insulating film and etching to obtain an insulating layer pattern, wherein the insulating layer pattern includes a first insulating layer, a second insulating layer and a third insulating layer; the first insulating layer covers the end faces of the first semiconductor layer, the second semiconductor layer and the second electrode layer facing the second light-emitting unit; the second insulating layer covers the end faces of the first semiconductor layer, the second semiconductor layer and the second electrode layer facing the second light-emitting layer; the third insulating layer covers the end faces of the second semiconductor layer, the third semiconductor layer and the third electrode layer facing away from the second light-emitting layer;

[0042] Depositing a metal layer and etching to obtain a metal routing pattern, the metal routing pattern comprising a first metal routing, a second metal routing and a third metal routing, the first metal routing corresponding to the first insulating layer and connecting the third electrode layer and the first electrode layer of the second light-emitting layer; the second metal routing corresponding to the second insulating layer and connecting the third electrode layer and the first electrode layer of the third light-emitting layer; the third metal routing corresponding to the third insulating layer and connecting the fourth electrode layer and the second electrode layer of the third light-emitting layer;

[0043] Depositing a first transflective film on the metal wiring pattern and etching to obtain a first transflective pattern, wherein the first transflective pattern includes a first transflective layer;

[0044] Depositing a first transflective film on the first transflective pattern and etching to obtain a second transflective pattern, wherein the second transflective pattern includes a second transflective layer to form the first light-emitting unit, the second light-emitting unit and the third light-emitting unit independently;

[0045] Performing packaging, rotating and filling the packaging structure on the substrate, so that the first light-emitting unit, the second light-emitting unit and the third light-emitting unit are all embedded in the packaging structure;

[0046] The substrate is peeled off and transferred to the base plate.

[0047] At least one embodiment of the present disclosure provides a manufacturing method, which is applied to the above-mentioned light-emitting chip, including:

[0048] Depositing to form a composite film layer, depositing a first conductive layer, a first epitaxial layer, a second conductive layer, a second epitaxial layer, and a third epitaxial layer on the substrate in sequence to obtain a composite film layer;

[0049] Etching the composite film layer to etch a light-emitting layer pattern from the composite film layer; the light-emitting layer pattern includes the first light-emitting layer, the second light-emitting layer and the third light-emitting layer spaced apart from each other, the first light-emitting layer includes a stacked first electrode layer, a first semiconductor layer and a second electrode layer; the second light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer and a second semiconductor layer; the third light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer, a second semiconductor layer and a third semiconductor layer;

[0050] An insulating film is deposited and etched to obtain an insulating layer pattern, wherein the insulating layer pattern includes a fourth insulating layer, a fifth insulating layer, a sixth insulating layer and a seventh insulating layer; the fourth insulating layer covers the first electrode layer and the first semiconductor layer of the first light-emitting layer facing the end surface of the second light-emitting layer, the fifth insulating layer covers the first electrode layer and the first semiconductor layer of the second light-emitting layer facing the end surface of the first light-emitting layer; the sixth insulating layer covers the first electrode layer and the first semiconductor layer of the second light-emitting layer facing the end surface of the third light-emitting layer, and the seventh insulating layer covers the first electrode layer and the first semiconductor layer of the third light-emitting layer facing the end surface of the second light-emitting layer;

[0051] Depositing a metal layer and etching to obtain a metal wiring pattern, wherein the metal wiring pattern includes a fourth metal wiring and a fifth metal wiring, wherein the fourth metal wiring connects the first light-emitting layer and the second electrode layer of the second light-emitting layer; and the fifth metal wiring connects the third light-emitting layer and the second electrode layer of the second light-emitting layer;

[0052] Depositing a first transflective film on the metal wiring pattern and etching to obtain a first transflective pattern, wherein the first transflective pattern includes a first transflective layer;

[0053] Depositing a first transflective film on the first transflective pattern and etching to obtain a second transflective pattern, wherein the second transflective pattern includes a second transflective layer to form the first light-emitting unit, the second light-emitting unit and the third light-emitting unit independently;

[0054] Performing packaging, rotating and filling the packaging structure on the substrate, so that the first light-emitting unit, the second light-emitting unit and the third light-emitting unit are all embedded in the packaging structure;

[0055] The substrate is peeled off and transferred to the base plate.

[0056] At least one embodiment of the present disclosure provides a manufacturing method, which is applied to the above-mentioned light-emitting chip, including:

[0057] Depositing to form a composite film layer, depositing a first conductive layer, a first epitaxial layer, a second conductive layer, and a second epitaxial layer on the substrate in sequence to obtain a composite film layer;

[0058] Etching the composite film layer to etch a first light-emitting layer pattern from the composite film layer; the first light-emitting layer pattern includes the first light-emitting layer, the second light-emitting layer and the third light-emitting blank layer which are spaced apart from each other, the first light-emitting layer includes a stacked first electrode layer, a first semiconductor layer and a second electrode layer; the second light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer and a second semiconductor layer; the third light-emitting blank layer includes a stacked first electrode layer, a first semiconductor layer and a second electrode layer;

[0059] Depositing a third epitaxial layer on the first light-emitting layer pattern and etching to obtain a second light-emitting layer pattern; the second light-emitting layer pattern comprises the first light-emitting layer, the second light-emitting layer and the third light-emitting layer which are spaced apart from each other, and the third light-emitting layer comprises a stacked first electrode layer, a first semiconductor layer, a second electrode layer and a third semiconductor layer;

[0060] An insulating film is deposited and etched to obtain an insulating layer pattern, wherein the insulating layer pattern includes a fourth insulating layer, a fifth insulating layer, a sixth insulating layer and a seventh insulating layer; the fourth insulating layer covers the first electrode layer and the first semiconductor layer of the first light-emitting layer facing the end surface of the second light-emitting layer, the fifth insulating layer covers the first electrode layer and the first semiconductor layer of the second light-emitting layer facing the end surface of the first light-emitting layer; the sixth insulating layer covers the first electrode layer and the first semiconductor layer of the second light-emitting layer facing the end surface of the third light-emitting layer, and the seventh insulating layer covers the first electrode layer and the first semiconductor layer of the third light-emitting layer facing the end surface of the second light-emitting layer;

[0061] Depositing a metal layer and etching to obtain a metal wiring pattern, wherein the metal wiring pattern includes a fourth metal wiring and a fifth metal wiring, wherein the fourth metal wiring connects the first light-emitting layer and the second electrode layer of the second light-emitting layer; and the fifth metal wiring connects the third light-emitting layer and the second electrode layer of the second light-emitting layer;

[0062] Depositing a first transflective film on the metal wiring pattern and etching to obtain a first transflective pattern, wherein the first transflective pattern includes a first transflective layer;

[0063] Depositing a first transflective film on the first transflective pattern and etching to obtain a second transflective pattern, wherein the second transflective pattern includes a second transflective layer to form the first light-emitting unit, the second light-emitting unit and the third light-emitting unit independently;

[0064] Performing packaging, rotating and filling the packaging structure on the substrate, so that the first light-emitting unit, the second light-emitting unit and the third light-emitting unit are all embedded in the packaging structure;

[0065] The substrate is peeled off and transferred to the base plate.

[0066] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0068] Figure 1 A schematic diagram of a light-emitting chip according to an exemplary embodiment of the present disclosure;

[0069] Figure 2 for Figure 1 Schematic diagram of the first light-emitting unit in;

[0070] Figure 3 for Figure 1 Schematic diagram of the second light emitting unit in;

[0071] Figure 4 for Figure 1 Schematic diagram of the third light-emitting unit in FIG.

[0072] Figure 5 is a schematic diagram of another light-emitting chip according to this exemplary embodiment;

[0073] Figure 6 is a schematic diagram of another light-emitting chip according to this exemplary embodiment;

[0074] Figure 7 A schematic diagram of another light-emitting chip according to an embodiment of the present disclosure;

[0075] Figure 8 for Figure 7 Schematic diagram of the first light-emitting unit in;

[0076] Fig. 9 for Figure 7 Schematic diagram of the second light emitting unit in;

[0077] Fig.10 for Figure 7 Schematic diagram of the third light-emitting unit in FIG.

[0078] Fig.11 It is a schematic diagram of another light-emitting chip according to an embodiment of the present disclosure;

[0079] Fig.12 for Fig.11Schematic diagram of the first light-emitting unit in;

[0080] Fig.13 for Fig.11 Schematic diagram of the second light emitting unit in;

[0081] Fig.14 for Fig.11 Schematic diagram of the third light-emitting unit in FIG.

[0082] Fig.15a A schematic diagram of a composite film layer of an exemplary embodiment of the present disclosure;

[0083] Fig.15b A schematic diagram of a light-emitting layer pattern of an exemplary embodiment of the present disclosure;

[0084] Fig.16a is a schematic diagram of another composite film layer according to an exemplary embodiment of the present disclosure;

[0085] Fig.16b is a schematic diagram of another light-emitting layer pattern of an exemplary embodiment of the present disclosure;

[0086] Fig.17a is a schematic diagram of another composite film layer according to an exemplary embodiment of the present disclosure;

[0087] Fig.17b is a schematic diagram of a first blank of an exemplary embodiment of the present disclosure;

[0088] Fig.17c is a schematic diagram of deposition of a third epitaxial layer according to an exemplary embodiment of the present disclosure;

[0089] Fig.17d It is a schematic diagram of another light-emitting layer pattern of an exemplary embodiment of the present disclosure.

[0090] Description of reference numerals:

[0091] 1-substrate; 2-first light-emitting unit; 3-second light-emitting unit;

[0092] 4-third light-emitting unit; 5-first light-emitting layer; 6-second light-emitting layer;

[0093] 7-third light-emitting layer; 8-first transflective layer; 9-second transflective layer;

[0094] 10-first semiconductor layer; 11-second semiconductor layer; 12-third semiconductor layer;

[0095] 13-first electrode layer; 14-second electrode layer; 15-third electrode layer;

[0096] 16- fourth electrode layer; 17- first metal wiring; 18- second metal wiring;

[0097] 19-third metal wiring; 20-first N-type contact layer; 21-first quantum well;

[0098] 22-first P-type contact layer; 23-second N-type contact layer; 24-second quantum well;

[0099] 25-a second P-type contact layer; 26-a first insulating layer; 27-a third N-type contact layer;

[0100] 28-third quantum well; 29-third P-type contact layer; 30-second insulating layer;

[0101] 31-third insulating layer; 32-fourth metal wiring; 33-fifth metal wiring;

[0102] 34-first covering section; 35-second covering section; 36-third covering section;

[0103] 37- fourth covering segment; 38- fifth covering segment; 39- sixth covering segment;

[0104] 40- fourth insulating layer; 41- fifth insulating layer; 42- sixth insulating layer;

[0105] 43-seventh insulating layer; 44-reflective film; 45-packaging structure;

[0106] 47-first conductive film; 48-first epitaxial layer; 49-second conductive film;

[0107] 50-second epitaxial layer; 51-third conductive film; 52-third epitaxial layer;

[0108] 53- fourth conductive film; 54- composite film layer; 55- light-emitting layer pattern;

[0109] 56 - first light-emitting layer pattern; 57 - second light-emitting layer pattern. DETAILED DESCRIPTION

[0110] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0111] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0112] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0113] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0114] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0115] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0116] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0117] The term "about" in the embodiments of the present disclosure means that the limits are not strictly defined and a numerical value within the range of process and measurement errors is allowed.

[0118] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0119] At present, Micro-LED is a light emitting diode (LED) that directly focuses on vertical display. In the production process of display devices, due to the huge amount of mass transfer and the direct wafer-to-panel bonding method, the light-emitting chip can only use monochrome LED to achieve full-color solutions. The applicant found that due to the use of single light, the full-color display effect using this structure is not ideal. In addition, current Micro-LED products usually use a combination of blue light LED and quantum dots (QD) to achieve full color, among which the production cost of quantum dots is also relatively high.

[0120] Figure 1 Schematic diagram of a light-emitting chip of an exemplary embodiment of the present disclosure. The present disclosure provides a light-emitting chip, such as Figure 1 As shown, the light-emitting chip may include a substrate 1 and a first light-emitting unit 2, a second light-emitting unit 3, and a third light-emitting unit 4 located on the same side of the substrate 1, wherein the first light-emitting unit 2 may include a first light-emitting layer 5 disposed on the substrate 1, and the first light-emitting unit 2 may be configured to emit a first color light. The second light-emitting unit 3 may include a second light-emitting layer 6 and a first transflective layer 8, the second light-emitting layer 6 is disposed on the substrate 1, the first transflective layer 8 is disposed on a side of the second light-emitting layer 6 away from the substrate 1, and the first transflective layer 8 may be configured to filter out the first color light, so that the second light-emitting unit 3 emits a second color light. The third light-emitting unit 4 may include a third light-emitting layer 7 and a second transflective layer 9, the third light-emitting layer 7 may be disposed on the substrate 1, the second transflective layer 9 may be disposed on a side of the third light-emitting layer 7 away from the substrate 1, and the second transflective layer 9 may be configured to filter out the first color light and / or the second color light, so that the third light-emitting unit 4 emits a third color light. Therefore, the light-emitting chip utilizes the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 to emit lights of different colors respectively, thereby realizing full-color display of non-monochromatic light, achieving better display effect and significantly reducing manufacturing costs.

[0121] In some exemplary embodiments, Figure 1As shown, the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 are all located on one side of the substrate 1 in a direction perpendicular to the substrate 1, and the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 are spaced apart from each other, and the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 are all arranged to emit light away from the substrate 1, the first light-emitting unit 2 can emit light of a first color, the second light-emitting unit 3 can emit light of a second color, and the third light-emitting unit 4 can emit light of a third color. Among them, the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 are arranged in sequence along a first direction, the first direction is parallel to the substrate 1, and the spacing between the first light-emitting unit 2 and the second light-emitting unit 3, and the spacing between the second light-emitting unit 3 and the third light-emitting unit 4 are matched with the pixel spacing.

[0122] Figure 2 for Figure 1 Schematic diagram of the first light-emitting unit in some exemplary embodiments, such as Figure 1 and Figure 2As shown, the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 are all stacked structures. The first light-emitting unit 2 may include a single-layer first light-emitting layer 5. The single-layer refers to a semiconductor structure having only one layer. The first light-emitting layer 5 may include a first electrode layer 13, a first semiconductor layer 10 and a second electrode layer 14. The first electrode layer 13, the first semiconductor layer 10 and the second electrode layer 14 are stacked in sequence in a direction away from the substrate 1. The projection of the first electrode layer 13 on the substrate 1, the projection of the first semiconductor layer 10 on the substrate 1 and the projection of the second electrode layer 14 on the substrate 1 all overlap. The first electrode layer 13 may be an N-type electrode, and the first electrode layer 1 may be an opaque electrode that is not transparent to light, but is not limited thereto and may also be a transparent electrode; the second electrode layer 14 may be a P-type electrode and may be a light-transmitting electrode. The light-transmitting electrode is a transparent electrode material that is transparent to light. The light-transmitting electrode may be indium tin oxide (ITO), which has good visible light transmittance and low resistivity. The first semiconductor layer 10 may be a blue LED epitaxial layer, so that the first color light emitted by the first light emitting unit 2 is blue light, but it is not limited thereto. For example, the first semiconductor layer 10 may be a red LED epitaxial structure or a green LED epitaxial structure, and the corresponding first color light will also change accordingly. The first semiconductor layer 10 includes a first N-type contact layer 20, a first quantum well 21, and a first P-type contact layer 22 arranged in sequence in a direction away from the substrate 1, wherein the first quantum well 21 may be indium gallium nitride InGaN / gallium nitride GaN grown alternately in multiple periods, or may be aluminum gallium nitride AlGaN / gallium nitride GaN grown alternately in multiple periods, and the number of layers of the quantum well 27 is 1 to 10 layers. The material of the first P-type contact layer 22 may be GaN gallium nitride doped with magnesium Mg, aluminum nitride AlN doped with magnesium Mg, or aluminum gallium nitride AlGaN doped with magnesium Mg, etc. The material of the first N-type contact layer 20 may be gallium nitride GaN doped with silicon Si, aluminum nitride AlN doped with silicon Si, or aluminum gallium nitride AlGaN doped with silicon Si, etc.

[0123] Figure 3 for Figure 1 Schematic diagram of the second light emitting unit in, in some exemplary embodiments, as Figure 1 and Figure 3As shown, the second light-emitting unit 3 may include a second light-emitting layer 6 and a first transflective layer 8, wherein the second light-emitting layer 6 may be a double-layer semiconductor structure, and the second light-emitting layer 6 may include a stacked first electrode layer 13, a first semiconductor layer 10, a second electrode layer 14, a second semiconductor layer 11, and a third electrode layer 15, wherein the first electrode layer 13, the first semiconductor layer 10, the second electrode layer 14, the second semiconductor layer 11, and the third electrode layer 15 are sequentially arranged in a direction away from the substrate 1. The first electrode layer 13 may be an N-type electrode, and the first electrode layer 1 may be an opaque electrode that is not transparent to light, but is not limited thereto, and may also be a transparent electrode; the second electrode layer 14 may be a P-type electrode and may be a light-transmitting electrode, and the light-transmitting electrode is a transparent electrode material that is transparent to light, and the light-transmitting electrode may be indium tin oxide (ITO), which has good visible light transmittance and low resistivity; the third electrode layer 15 may be an N-type electrode and may be a light-transmitting electrode, and the material of the third electrode layer 15 may be consistent with the material of the second electrode 14. The first semiconductor layer 10 may adopt a blue LED epitaxial structure, and the second semiconductor layer 11 may adopt a green LED epitaxial structure, but is not limited thereto. For example, the second semiconductor layer 11 may adopt a red LED epitaxial structure. The first semiconductor layer 10 of the second light-emitting layer 6 may be arranged in the same layer as the first semiconductor layer 10 of the first light-emitting layer 5. "Same-layer arrangement" means that the two are formed simultaneously through the same patterning process. The first semiconductor layer 10 of the second light-emitting layer 6 includes a first N-type contact layer 20, a first quantum well 21, and a first P-type contact layer 22 arranged in sequence in a direction away from the substrate 1, wherein the orthographic projection of the first N-type contact layer 20 on the substrate 1, the orthographic projection of the first quantum well 21 on the substrate 1, and the orthographic projection of the first P-type contact layer 22 on the substrate 1 overlap. The second semiconductor layer 11 of the second light-emitting layer 6 may include a second P-type contact layer 25, a second quantum well 24, and a second N-type contact layer 23 arranged in sequence in a direction away from the substrate 1, and the orthographic projection of the second P-type contact layer 25 on the substrate 1, the orthographic projection of the second quantum well 24 on the substrate 1, and the orthographic projection of the second N-type contact layer 23 on the substrate 1 overlap. The first quantum well 21 and the second quantum well 24 can be made of indium gallium nitride InGaN / gallium nitride GaN grown alternately in multiple cycles, or aluminum gallium nitride AlGaN / gallium nitride GaN grown alternately in multiple cycles, and the number of quantum well layers is 1 to 10. The materials of the first P-type contact layer 22 and the second P-type contact layer 25 can be made of GaN gallium nitride doped with magnesium Mg, aluminum nitride AlN doped with magnesium Mg, or aluminum gallium nitride AlGaN doped with magnesium Mg. The materials of the first N-type contact layer 20 and the second N-type contact layer 23 can be made of gallium nitride GaN doped with silicon Si, aluminum nitride AlN doped with silicon Si, or aluminum gallium nitride AlGaN doped with silicon Si.The first reflective layer 8 can filter light of different wavelengths. The first reflective layer 8 is a reflective film. The reflective film can be a conductive green-transmitting and blue-blocking film. The green-transmitting and blue-blocking film can be a green-transmitting and blue-reflecting light-combining film. The green-transmitting and blue-reflecting light-combining film can transmit green light with a larger wavelength and reflect blue light with a smaller wavelength. The green-transmitting and blue-reflecting light-combining film can be prepared by an evaporation process or can be manufactured by a deposition process.

[0124] In some exemplary embodiments, Figure 1 and Figure 3 As shown, in the second light-emitting unit 3, the orthographic projections of the first semiconductor layer 10, the second electrode layer 14, the second semiconductor layer 11, the third electrode layer 15 and the first transflective layer 8 on the substrate 1 are all located within the orthographic projection of the first electrode layer 13 on the substrate 1, and one end of the first electrode layer 13 close to the first light-emitting unit 2 protrudes from other structural layers of the second light-emitting unit 3, so that the end surface of the first electrode layer 13 away from the substrate 1 has a portion not covered by the first semiconductor layer 10. The lateral direction of the second light-emitting layer 6 is the side wall of the second light-emitting layer 6 in the first direction.

[0125] In some exemplary embodiments, Figure 1 and Figure 3 As shown, the second light-emitting unit 3 further includes a first metal trace 14 and a first insulating layer 26. The first metal trace 14 is located at the side of the second light-emitting layer 6. The first insulating layer 26 can prevent the first metal trace 14 from contacting the first semiconductor layer 10, the second semiconductor layer 11, and the second electrode layer 14. The first insulating layer 26 covers the end faces of the first semiconductor layer 10, the second semiconductor layer 11, and the second electrode layer 14 facing the first light-emitting unit 2. The first metal trace 14 is located at the side of the second light-emitting layer 6 facing the first light-emitting unit 2. One end of the first metal trace 14 is connected to the third electrode layer 15, and the other end of the first metal trace 14 extends toward the substrate 1 and extends to the end face of the first electrode layer 13 that is not covered by the first semiconductor layer 10. At the same time, the first metal trace 14 is separated from the first semiconductor layer 10, the second semiconductor layer 11, and the second electrode layer 14 by the first insulating layer 26.

[0126] Figure 4 for Figure 1 Schematic diagram of the third light emitting unit in some exemplary embodiments, such as Figure 1 and Figure 4As shown, the third light-emitting unit 4 may include a third light-emitting layer 7 and a second transflective layer 9, wherein the third light-emitting layer 7 may be a three-layer semiconductor structure, and the third light-emitting layer 7 may include a stacked first electrode layer 13, a first semiconductor layer 10, a second electrode layer 14, a second semiconductor layer 11, a third electrode layer 15, a third semiconductor layer 12 and a fourth electrode layer 16, and the first electrode layer 13, the first semiconductor layer 10, the second electrode layer 14, the second semiconductor layer 11, the third electrode layer 15, the third semiconductor layer 12 and the fourth electrode layer 16 are arranged in sequence in a direction away from the substrate 1. The first electrode layer 13 can be an N-type electrode. The first electrode layer 1 can be an opaque electrode that cannot transmit light, but is not limited to this and can also be a transparent electrode. The second electrode layer 14 can be a P-type electrode and can be a light-transmitting electrode. The light-transmitting electrode is a transparent electrode material that can transmit light. The light-transmitting electrode can be indium tin oxide (ITO), which has good visible light transmittance and low resistivity. The third electrode layer 15 can be an N-type electrode and can be a light-transmitting electrode. The material of the third electrode layer 15 can be consistent with the material of the second electrode 14. The fourth electrode layer 16 can be a P-type electrode and can be a light-transmitting electrode. The material of the fourth electrode layer 16 can be consistent with the material of the second electrode 14. The first semiconductor layer 10 can adopt a blue light LED epitaxial structure, the second semiconductor layer 11 can adopt a green light LED epitaxial structure, and the third semiconductor layer 12 can adopt a red light LED epitaxial structure, but is not limited to this. For example, the second semiconductor layer 11 can adopt a red light LED epitaxial structure, and the third semiconductor layer 12 can adopt a green light LED epitaxial structure. The first semiconductor layer 10 of the third light-emitting layer 7 may be arranged in the same layer as the first semiconductor layer 10 of the first light-emitting layer 5 and the second light-emitting layer 6, and the second semiconductor layer 11 of the third light-emitting layer 7 may be arranged in the same layer as the second semiconductor layer 11 of the second light-emitting layer 6. The first semiconductor layer 10 of the third light-emitting layer 7 includes a first N-type contact layer 20, a first quantum well 21, and a first P-type contact layer 22 arranged in sequence in a direction away from the substrate 1, wherein the orthographic projection of the first N-type contact layer 20 on the substrate 1, the orthographic projection of the first quantum well 21 on the substrate 1, and the orthographic projection of the first P-type contact layer 22 on the substrate 1 overlap. The second semiconductor layer 11 of the third light-emitting layer 7 may include a second P-type contact layer 25, a second quantum well 24, and a second N-type contact layer 23 arranged in sequence in a direction away from the substrate 1, wherein the orthographic projection of the second P-type contact layer 25 on the substrate 1, the orthographic projection of the second quantum well 24 on the substrate 1, and the orthographic projection of the second N-type contact layer 23 on the substrate 1 overlap. The third semiconductor layer 12 of the third light-emitting layer 7 includes a third N-type contact layer 27, a third quantum well 28 and a third P-type contact layer 29 which are sequentially arranged in a direction away from the substrate 1, wherein the orthographic projection of the third N-type contact layer 27 on the substrate 1, the orthographic projection of the third quantum well 28 on the substrate 1 and the orthographic projection of the third P-type contact layer 29 on the substrate 1 overlap.The first quantum well 21, the second quantum well 24 and the third quantum well 28 can be made of indium gallium nitride InGaN / gallium nitride GaN grown alternately in multiple cycles, or aluminum gallium nitride AlGaN / gallium nitride GaN grown alternately in multiple cycles, and the number of quantum well layers is 1 to 10. The materials of the first P-type contact layer 22, the second P-type contact layer 25 and the third P-type contact layer 29 can be made of GaN gallium nitride doped with magnesium Mg, aluminum nitride AlN doped with magnesium Mg, or aluminum gallium nitride AlGaN doped with magnesium Mg. The materials of the first N-type contact layer 20, the second N-type contact layer 23 and the third N-type contact layer 27 can be made of gallium nitride GaN doped with silicon Si, aluminum nitride AlN doped with silicon Si, or aluminum gallium nitride AlGaN doped with silicon Si. The second reflective layer 9 covers the end face of the fourth electrode layer 16 away from the substrate 1. The second reflective layer 9 can be a conductive red-transmitting blue-green blocking film. The red-transmitting blue-green blocking film can be a red-transmitting, blue-reflecting, and green-light-combining film. The red-transmitting, blue-reflecting, and green-light-combining film can transmit red light and reflect blue light and green light. The red-transmitting, blue-reflecting, and green-light-combining film can be prepared by an evaporation process or can be manufactured by a deposition process.

[0127] In some exemplary embodiments, Figure 1 and Figure 4 As shown, in the third light-emitting unit 4, the orthographic projections of the second semiconductor layer 11, the third electrode layer 15, the third semiconductor layer 12, the fourth electrode 16 and the second transflective layer 9 on the substrate 1 are all located within the orthographic projection of the second electrode layer 14 on the substrate 1, and the end of the second electrode layer 14 away from the second light-emitting unit 3 protrudes the second semiconductor layer 11, the third electrode layer 15, the third semiconductor layer 12, the fourth electrode 16 and the second transflective layer 9 of the third light-emitting unit 3, so that the end surface of the second electrode layer 14 away from the substrate 1 has a part not covered by the second semiconductor layer 11. The lateral direction of the third light-emitting layer 7 is the side wall of the third light-emitting layer 7 in the first direction. The orthographic projections of the first semiconductor layer 10 and the second electrode layer 14 on the substrate 1 are all located within the orthographic projection of the first electrode layer 13 on the substrate 1, and the end of the first electrode layer 13 close to the second light-emitting unit 3 protrudes other structures of the third light-emitting unit 3, so that the end surface of the first electrode layer 13 away from the substrate 1 has a part not covered by the first semiconductor layer 10.

[0128] In some exemplary embodiments, Figure 1 and Figure 3As shown, the second light-emitting unit 3 further includes a second metal trace 18 and a second insulating layer 30, as well as a third metal trace 19 and a third insulating layer 31. The second metal trace 18 and the third metal trace 19 are respectively located on two opposite sides of the second light-emitting layer 6, the second insulating layer 30 can prevent the second metal trace 18 from contacting the first semiconductor layer 10, the second semiconductor layer 11 and the second electrode layer 14, and the third insulating layer 31 can prevent the third metal trace 19 from contacting the second semiconductor layer 11, the third semiconductor layer 12 and the third electrode layer 15. The second insulating layer 30 covers the end faces of the first semiconductor layer 10, the second semiconductor layer 11 and the second electrode layer 14 facing the second light-emitting unit 3, and the third insulating layer 31 covers the end faces of the second semiconductor layer 11, the third semiconductor layer 12 and the third electrode layer 15 facing away from the second light-emitting unit 3. The second metal trace 18 is located on the side of the third light-emitting layer 7 facing the second light-emitting unit 3, one end of the second metal trace 18 is connected to the third electrode layer 15, the other end of the first metal trace 14 extends toward the substrate 1, and extends to the end surface of the first electrode layer 13 that is not covered by the first semiconductor layer 10, and at the same time, the second metal trace 18 is separated from the first semiconductor layer 10, the second semiconductor layer 11, and the second electrode layer 14 by the second insulating layer 30. The third metal trace 19 is located on the side of the third light-emitting layer 7 that is not facing the second light-emitting unit 3, one end of the third metal trace 19 is connected to the fourth electrode layer 16, and the other end of the third metal trace 19 extends toward the substrate 1, and extends to the end surface of the second electrode layer 14 that is not covered by the second semiconductor layer 11, and at the same time, the third metal trace 19 is separated from the second semiconductor layer 11, the third semiconductor layer 12, and the third electrode layer 15 by the third insulating layer 31.

[0129] In some exemplary embodiments, Figures 1 to 4As shown, when the light-emitting chip is powered on, the first electrode layer 13 and the second electrode layer 14 are powered on respectively, and the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 emit light respectively. The first semiconductor layer 10 of the first light-emitting unit 2 emits blue light, and the blue light is emitted from the second electrode layer 14 back to the first electrode layer 13, so that the first light-emitting unit 2 emits blue light. After the first semiconductor layer 10 and the second semiconductor layer 11 of the second light-emitting unit 3 are powered on, the first semiconductor layer 10 emits blue light, and the blue light is emitted from the second electrode layer 13, the second semiconductor layer 11 and the third electrode layer 15; the second semiconductor layer 11 emits green light, and the green light is emitted from the third electrode layer 15; after the two colors of light pass through the first transflective layer 8, the first transflective layer 8 reflects the blue light and allows the green light to pass through the first transflective layer 8, so that the second light-emitting unit 3 electroluminescently emits green light. At the same time, in the second light-emitting unit 3, the blue light can excite the second semiconductor layer 11 to emit green light, thereby increasing the brightness of the green light. After the first semiconductor layer 10, the second semiconductor layer 11 and the third semiconductor layer 12 of the second light-emitting unit 3 are powered on, the first semiconductor layer 10 emits blue light, which is transmitted through the second electrode layer 13, the second semiconductor layer 11, the third electrode layer 15, the third semiconductor layer 12 and the fourth electrode layer 16 to the second transflective layer 9; the second semiconductor layer 11 emits green light, which is transmitted through the third electrode layer 15, the third semiconductor layer 12 and the fourth electrode layer 16 to the second transflective layer 9; the third semiconductor layer 12 emits red light, which is transmitted through the fourth electrode layer 16 to the second transflective layer 9; after the three colors of light pass through the second transflective layer 9, the second transflective layer 9 reflects the blue light and the green light and allows the red light to pass through the second transflective layer 9, so that the third light-emitting unit 4 electroluminescently emits red light. At the same time, in the third light-emitting unit 4, the blue light can excite the second semiconductor layer 11 to emit green light and can excite the third semiconductor layer 12 to emit red light, thereby increasing the brightness of the red light.

[0130] Figure 5 is another schematic diagram of a light emitting chip according to this exemplary embodiment. In some exemplary embodiments, Figure 5 As shown, the first electrode layer 13 of the first light-emitting layer 5 , the first electrode layer 13 of the second light-emitting layer 6 and the first electrode layer 13 of the third light-emitting layer 7 are integrated into one piece, so that the first light-emitting layer 5 , the second light-emitting layer 6 and the third light-emitting layer 7 share one first electrode layer 13 .

[0131] Figure 6 is a schematic diagram of another light-emitting chip of this exemplary embodiment. In some exemplary embodiments, as Figure 6As shown, the light-emitting chip further includes a reflective film 44, wherein the reflective film 44 is arranged to at least wrap the lateral direction of the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4, that is, the outer surfaces of the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 except the end faces facing and facing away from the substrate 1 are all wrapped with the reflective film 44, so as to prevent the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 from emitting light laterally. The reflective film 44 can adopt a distributed Bragg reflector structure, and the distributed Bragg reflector (Distributed Bragg reflection, DBR) is a periodic structure composed of two materials with different refractive indices arranged alternately in an ABAB manner, and the thickness of each layer of material is 1 / 4 of the wavelength (central wavelength) of the reflected light, so it is a quarter-wave multilayer system, which is equivalent to a group of photonic crystals. In this embodiment, the two materials with different refractive indices can be aluminum gallium nitride AlGaN and gallium nitride GaN, aluminum gallium arsenide AlGaAs and gallium arsenide GaAs, hafnium dioxide HfO2 and silicon dioxide SiO2, or titanium dioxide TiO2 / silicon dioxide SiO2. The calculation formula of the distributed Bragg reflector is d=λ / 4η, where d is the layer thickness, λ is the center wavelength, and η is the refractive index of the layer. Taking the blue light with a reflection center wavelength of 450nm and the distributed Bragg reflector using TiO2 / SiO2 as an example, the refractive index η of SiO2 is 1.47, so the thickness d of the layer is 76.5nm, and the refractive index η of TiO2 is 2.52, so the thickness d of the layer is 44.64nm. Since electromagnetic waves with frequencies falling within the energy gap range cannot penetrate, the reflectivity of the Bragg reflector can reach more than 99%, without the absorption problem of metal reflectors, and the more repeated layers of the distributed Bragg reflector, the higher the reflection efficiency. In actual implementation, the energy gap position can be adjusted by adjusting the thickness of each layer, or the refractive index can be adjusted by adjusting the composition of each layer material to adjust the energy gap position, as long as the thickness, refractive index and center wavelength are matched.

[0132] In some exemplary embodiments, Figure 6 As shown, the light-emitting chip also includes a packaging structure 45, wherein the packaging structure 45 is arranged on the substrate 1 and covers the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4. The packaging structure 45 embeds the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 therein, so that the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 are combined into one. The packaging structure 45 adopts a transparent material, and the packaging structure 45 is a transparent non-conductive medium, such as transparent silicon dioxide, transparent silicon nitride or transparent aluminum nitride, etc., which can transmit light. The packaging structure 45 can be provided with a first opening on the side corresponding to the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 away from the substrate 1.

[0133] In some exemplary embodiments, a manufacturing method is applied to Figure 6 The preparation of the light-emitting chip shown in the figure mainly includes deposition, etching, and packaging. First, prepare a substrate, and sequentially deposit a first conductive layer 47, a first epitaxial layer 48, a second conductive layer 49, a second epitaxial layer 50, a third conductive layer 51, a third epitaxial layer 52, and a fourth conductive layer 53 on the prepared substrate, wherein the first epitaxial layer 48 can adopt a blue light LED epitaxial structure, the second epitaxial layer 50 can adopt a green light LED epitaxial structure, and the third epitaxial layer 52 can adopt a red light LED epitaxial structure, to obtain the following: Fig.15a The composite membrane layer 54 is shown.

[0134] Next, the composite film layer 54 is etched to obtain a light-emitting layer pattern 55, and the composite film layer 54 is etched to obtain an independent first light-emitting layer 5, a second light-emitting layer 6 and a third light-emitting layer 7. Fig.15b The light-emitting layer pattern 55 shown may include a first light-emitting layer 5, a second light-emitting layer 6 and a third light-emitting layer 7; the first light-emitting layer 5 includes a stacked first electrode layer 13, a first semiconductor layer 10 and a second electrode layer 14; the second light-emitting layer 6 includes a stacked first electrode layer 13, a first semiconductor layer 10, a second electrode layer 14, a second semiconductor layer 11 and a third electrode layer 15; the third light-emitting layer 7 includes a stacked first electrode layer 13, a first semiconductor layer 10, a second electrode layer 14, a second semiconductor layer 11, a third electrode layer 15, a third semiconductor layer 12 and a fourth electrode layer 16.

[0135] Next, an insulating film is deposited and etched to obtain an insulating layer pattern, wherein the insulating layer pattern includes: Figure 3 The first insulating layer 26 shown, and Figure 4 The second insulating layer 30 and the third insulating layer 31 are shown, the first insulating layer 26 covers the end faces of the first semiconductor layer 10, the second semiconductor layer 11 and the second electrode layer 14 facing the second light-emitting unit 6; the second insulating layer 30 covers the end faces of the first semiconductor layer 10, the second semiconductor layer 11 and the second electrode layer 14 facing the second light-emitting layer 6; the third insulating layer 31 covers the end faces of the second semiconductor layer 11, the third semiconductor layer 12 and the third electrode layer 15 facing away from the second light-emitting layer 6.

[0136] Continue to deposit the metal layer and etch to obtain a metal wiring pattern, the metal wiring pattern includes: Figure 1The first metal routing 17, the second metal routing 18 and the third metal routing 19 shown, the first metal routing 17 corresponds to the first insulating layer 26 and connects the third electrode layer 15 and the first electrode layer 13 of the second light-emitting layer 6; the second metal routing 18 corresponds to the second insulating layer 30 and connects the third electrode layer 15 and the first electrode layer 13 of the third light-emitting layer 7; the third metal routing 19 corresponds to the third insulating layer 31 and connects the fourth electrode layer 16 and the second electrode layer 14 of the third light-emitting layer 7.

[0137] Then, a first transflective film is deposited on the metal wiring pattern and etched to obtain a first transflective pattern. The first transflective pattern includes: Figure 1 The first transflective layer 8 is shown.

[0138] Next, a first transflective film is deposited on the first transflective pattern and etched to obtain a second transflective pattern. The second transflective pattern includes: Figure 1 The second transflective layer 9 shown forms an independent first light-emitting unit 2 , a second light-emitting unit 3 and a third light-emitting unit 4 .

[0139] Subsequently, packaging is performed, and after the reflective film is deposited, the packaging structure is filled by rotation on the substrate, so that the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 are all embedded in the packaging structure;

[0140] Finally, the substrate is peeled off, and the first light-emitting unit 2 without the backing plate and other structures are transferred to the substrate 1, thereby completing the entire preparation process of the light-emitting chip.

[0141] Figure 7 is a schematic diagram of another light-emitting chip according to an embodiment of the present disclosure, Figure 8 for Figure 7 Schematic diagram of the first light-emitting unit in some exemplary embodiments, such as Figure 7 and Figure 8As shown, the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 are sequentially arranged along the first direction, the first direction is parallel to the substrate 1, and the spacing between the first light-emitting unit 2 and the second light-emitting unit 3, and the spacing between the second light-emitting unit 3 and the third light-emitting unit 4 are matched with the pixel spacing. The first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 are all stacked structures, the first light-emitting unit 2 may include a single-layer first light-emitting layer 5, a single layer means having only one semiconductor structure, the first light-emitting layer 5 may include a first electrode layer 13, a first semiconductor layer 10 and a second electrode layer 14, wherein the first electrode layer 13, the first semiconductor layer 10 and the second electrode layer 14 are sequentially stacked in a direction away from the substrate 1, and the projection of the first electrode layer 13 on the substrate 1, the projection of the first semiconductor layer 10 on the substrate 1 and the projection of the second electrode layer 14 on the substrate 1 all overlap. The first electrode layer 13 can be an N-type electrode. The first electrode layer 1 can be an opaque electrode that cannot transmit light, but is not limited to this, and can also be a transparent electrode; the second electrode layer 14 can be a P-type electrode and can be a light-transmitting electrode. The light-transmitting electrode is a transparent electrode material that can transmit light. The light-transmitting electrode can be indium tin oxide (ITO), which has good visible light transmittance and low resistivity. The first semiconductor layer 10 can use a blue light LED epitaxial layer, so that the first color light emitted by the first light-emitting unit 2 is blue light, but is not limited to this. For example, the first semiconductor layer 10 can be a red light LED epitaxial structure or a green light LED epitaxial structure, and the corresponding first color light will also change accordingly. The first semiconductor layer 10 includes a first N-type contact layer 20, a first quantum well 21, and a first P-type contact layer 22 arranged in sequence in a direction away from the substrate 1, wherein the first quantum well 21 may be made of indium gallium nitride InGaN / gallium nitride GaN grown alternately in multiple periods, or may be made of aluminum gallium nitride AlGaN / gallium nitride GaN grown alternately in multiple periods, and the number of layers of the quantum well 27 is 1 to 10. The material of the first P-type contact layer 22 may be GaN gallium nitride doped with magnesium Mg, aluminum nitride AlN doped with magnesium Mg, or aluminum gallium nitride AlGaN doped with magnesium Mg, etc. The material of the first N-type contact layer 20 may be gallium nitride GaN doped with silicon Si, aluminum nitride AlN doped with silicon Si, or aluminum gallium nitride AlGaN doped with silicon Si, etc.

[0142] Fig. 9 for Figure 7 Schematic diagram of the second light emitting unit in, in some exemplary embodiments, as Figure 7 and Fig. 9As shown, the second light-emitting unit 3 may include a second light-emitting layer 6 and a first transflective layer 8, wherein the second light-emitting layer 6 may be a double-layer semiconductor structure, and the second light-emitting layer 6 may include a stacked first electrode layer 13, a first semiconductor layer 10, a second electrode layer 14, and a second semiconductor layer 11, and the first electrode layer 13, the first semiconductor layer 10, the second electrode layer 14, and the second semiconductor layer 11 are arranged in sequence in a direction away from the substrate 1. The first electrode layer 13 may be an N-type electrode, and the first electrode layer 1 may be an opaque electrode that is not transparent to light, but is not limited thereto, and may also be a transparent electrode; the second electrode layer 14 may be a P-type electrode and may be a light-transmitting electrode, and the light-transmitting electrode is a transparent electrode material that is transparent to light, and the light-transmitting electrode may be indium tin oxide (ITO), which has good visible light transmittance and low resistivity. The first semiconductor layer 10 may adopt a blue light LED epitaxial structure, and the second semiconductor layer 11 may adopt a green light LED epitaxial structure, but is not limited thereto, for example, the second semiconductor layer 11 may adopt a red light LED epitaxial structure. The first semiconductor layer 10 of the second light-emitting layer 6 may be arranged in the same layer as the first semiconductor layer 10 of the first light-emitting layer 5, and "arranged in the same layer" means that the two are formed simultaneously through the same patterning process. The first semiconductor layer 10 of the second light-emitting layer 6 includes a first N-type contact layer 20, a first quantum well 21, and a first P-type contact layer 22 arranged in sequence in a direction away from the substrate 1, wherein the orthographic projection of the first N-type contact layer 20 on the substrate 1, the orthographic projection of the first quantum well 21 on the substrate 1, and the orthographic projection of the first P-type contact layer 22 on the substrate 1 overlap. The second semiconductor layer 11 of the second light-emitting layer 6 may include a second P-type contact layer 25, a second quantum well 24, and a second N-type contact layer 23 arranged in sequence in a direction away from the substrate 1, and the orthographic projection of the second P-type contact layer 25 on the substrate 1, the orthographic projection of the second quantum well 24 on the substrate 1, and the orthographic projection of the second N-type contact layer 23 on the substrate 1 overlap. The first quantum well 21 and the second quantum well 24 can be made of indium gallium nitride InGaN / gallium nitride GaN grown alternately in multiple cycles, or aluminum gallium nitride AlGaN / gallium nitride GaN grown alternately in multiple cycles, and the number of quantum well layers is 1 to 10. The materials of the first P-type contact layer 22 and the second P-type contact layer 25 can be made of GaN gallium nitride doped with magnesium Mg, aluminum nitride AlN doped with magnesium Mg, or aluminum gallium nitride AlGaN doped with magnesium Mg. The materials of the first N-type contact layer 20 and the second N-type contact layer 23 can be made of gallium nitride GaN doped with silicon Si, aluminum nitride AlN doped with silicon Si, or aluminum gallium nitride AlGaN doped with silicon Si. The first reflective layer 8 can filter light of different wavelengths. The first reflective layer 8 is a reflective film. The reflective film can be a conductive green-transmitting and blue-blocking film. The green-transmitting and blue-blocking film can be a green-transmitting and blue-reflecting light-combining film. The green-transmitting and blue-reflecting light-combining film can transmit green light with a larger wavelength and reflect blue light with a smaller wavelength. The green-transmitting and blue-reflecting light-combining film can be prepared by an evaporation process or can be manufactured by a deposition process.

[0143] In some exemplary embodiments, Figure 7 and Fig. 9 As shown, in the second light-emitting unit 3, the orthographic projections of the first semiconductor layer 10, the second electrode layer 14, the second semiconductor layer 11, the third electrode layer 15 and the first transflective layer 8 on the substrate 1 are all located within the orthographic projection of the first electrode layer 13 on the substrate 1, and the lateral direction of the second light-emitting layer 6 is the side wall of the second light-emitting layer 6 in the first direction.

[0144] In some exemplary embodiments, Figure 7 , Figure 8 and Fig. 9 As shown, the light-emitting chip further includes a fourth metal wiring 32, a fourth insulating layer 40 and a fifth insulating layer 41. The fourth metal wiring 32 is located between the second light-emitting layer 6 and the first light-emitting layer 5. The fourth insulating layer 40 can prevent the fourth metal wiring 32 from contacting the first electrode layer 13 and the first semiconductor layer 10 of the first light-emitting layer 5. The fifth insulating layer 41 can prevent the fourth metal wiring 32 from contacting the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6. The fourth insulating layer 40 covers the end faces of the first electrode layer 13 and the first semiconductor layer 10 of the first light-emitting layer 5 facing the second light-emitting layer 6, and the fifth insulating layer 41 covers the end faces of the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6 facing the first light-emitting layer 5. The fourth metal trace 32 includes a first covering section 34, a second covering section 35 and a third covering section 36 connected in sequence, wherein the first covering section 34 is located on the side of the first light-emitting layer 5 facing the second light-emitting layer 6, one end of the first covering section 34 is connected to the end of the second electrode layer 14 of the first light-emitting layer 5 facing the second light-emitting layer 6, and the other end of the first covering section 34 extends to the substrate 1 and connects to the second covering section 35; the second covering section 35 covers the part of the substrate 1 between the second light-emitting layer 6 and the first light-emitting layer 5; the third covering section 36 is located on the side of the second light-emitting layer 6 facing the first light-emitting layer 5, one end of the third covering section 36 is connected to the end of the second electrode layer 14 of the second light-emitting layer 6 facing the first light-emitting layer 5, and the other end of the third covering section 36 extends to the substrate 1 and connects to the second covering section 35. At the same time, the first covering section 34 is separated from the first electrode layer 13 and the first semiconductor layer 10 of the first light-emitting layer 5 by the fourth insulating layer 40, and the third covering section 36 is separated from the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6 by the fifth insulating layer 41. Thus, the second electrode layer 14 of the second light-emitting layer 6 and the second electrode layer 14 of the first light-emitting layer 5 are electrically connected.

[0145] Fig.10 for Figure 7 Schematic diagram of the third light emitting unit in some exemplary embodiments, such as Figure 7 and Fig.10As shown, the third light-emitting unit 4 may include a third light-emitting layer 7 and a second transflective layer 9, wherein the third light-emitting layer 7 may be a three-layer semiconductor structure, and the third light-emitting layer 7 may include a stacked first electrode layer 13, a first semiconductor layer 10, a second electrode layer 14, a second semiconductor layer 11, and a third semiconductor layer 12, wherein the first electrode layer 13, the first semiconductor layer 10, the second electrode layer 14, the second semiconductor layer 11, and the third semiconductor layer 12 are sequentially arranged in a direction away from the substrate 1. The first electrode layer 13 may be an N-type electrode, and the first electrode layer 1 may be an opaque electrode that is not transparent to light, but is not limited thereto, and may also be a transparent electrode; the second electrode layer 14 may be a P-type electrode and may be a light-transmitting electrode, and the light-transmitting electrode is a transparent electrode material that is transparent to light, and the light-transmitting electrode may be indium tin oxide (ITO), which has good visible light transmittance and low resistivity. The first semiconductor layer 10 may adopt a blue LED epitaxial structure, the second semiconductor layer 11 may adopt a green LED epitaxial structure, and the third semiconductor layer 12 may adopt a red LED epitaxial structure, but is not limited thereto. For example, the second semiconductor layer 11 may adopt a red LED epitaxial structure, and the third semiconductor layer 12 may adopt a green LED epitaxial structure. The first semiconductor layer 10 of the third light-emitting layer 7 may be arranged in the same layer as the first semiconductor layer 10 of the first light-emitting layer 5 and the second light-emitting layer 6, and the second semiconductor layer 11 of the third light-emitting layer 7 may be arranged in the same layer as the second semiconductor layer 11 of the second light-emitting layer 6. The first semiconductor layer 10 of the third light-emitting layer 7 includes a first N-type contact layer 20, a first quantum well 21, and a first P-type contact layer 22 sequentially arranged in a direction away from the substrate 1, wherein the orthographic projection of the first N-type contact layer 20 on the substrate 1, the orthographic projection of the first quantum well 21 on the substrate 1, and the orthographic projection of the first P-type contact layer 22 on the substrate 1 overlap. The second semiconductor layer 11 of the third light emitting layer 7 may include a second P-type contact layer 25, a second quantum well 24, and a second N-type contact layer 23 arranged in sequence in a direction away from the substrate 1, and the orthographic projection of the second P-type contact layer 25 on the substrate 1, the orthographic projection of the second quantum well 24 on the substrate 1, and the orthographic projection of the second N-type contact layer 23 on the substrate 1 overlap. The third semiconductor layer 12 of the third light emitting layer 7 includes a third N-type contact layer 27, a third quantum well 28, and a third P-type contact layer 29 arranged in sequence in a direction away from the substrate 1, wherein the orthographic projection of the third N-type contact layer 27 on the substrate 1, the orthographic projection of the third quantum well 28 on the substrate 1, and the orthographic projection of the third P-type contact layer 29 on the substrate 1 overlap. The first quantum well 21, the second quantum well 24, and the third quantum well 28 may be indium gallium nitride InGaN / gallium nitride GaN grown alternately in multiple cycles, or aluminum gallium nitride AlGaN / gallium nitride GaN grown alternately in multiple cycles, and the number of quantum well layers is 1 to 10.The materials of the first P-type contact layer 22, the second P-type contact layer 25 and the third P-type contact layer 29 can be GaN gallium nitride doped with magnesium Mg, aluminum nitride AlN doped with magnesium Mg or aluminum gallium nitride AlGaN doped with magnesium Mg. The materials of the first N-type contact layer 20, the second N-type contact layer 23 and the third N-type contact layer 27 can be GaN gallium nitride doped with silicon Si, aluminum nitride AlN doped with silicon Si or aluminum gallium nitride AlGaN doped with silicon Si. The second reflective layer 9 covers the end face of the third semiconductor layer 12 away from the substrate 1. The second reflective layer 9 can be a conductive red-transmitting blue-green blocking film. The red-transmitting blue-green blocking film can be a red-transmitting blue-reflecting green-light-combining film. The red-transmitting blue-reflecting green-light-combining film can transmit red light and reflect blue light and green light. The red-transmitting blue-reflecting green-light-combining film can be prepared by an evaporation process or can be manufactured by a deposition process.

[0146] In some exemplary embodiments, Figure 7 and Fig.10 As shown, in the third light-emitting unit 4, the orthographic projections of the first semiconductor 10, the second electrode layer 14, the second semiconductor layer 11, the third semiconductor layer 12 and the second reflective layer 9 on the substrate 1 are all located within the orthographic projection of the first electrode layer 13 on the substrate 1, and the lateral direction of the third light-emitting layer 7 is the side wall of the third light-emitting layer 7 in the first direction.

[0147] In some exemplary embodiments, Figure 7 , Fig. 9 and Fig.10As shown, the light-emitting chip further includes a fifth metal wiring 33, a sixth insulating layer 42 and a seventh insulating layer 43. The fifth metal wiring 33 is located between the second light-emitting layer 6 and the third light-emitting layer 7. The sixth insulating layer 42 can prevent the fifth metal wiring 33 from contacting the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6. The seventh insulating layer 43 can prevent the fifth metal wiring 33 from contacting the first electrode layer 13 and the first semiconductor layer 10 of the third light-emitting layer 7. The sixth insulating layer 42 covers the end faces of the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 5 facing the third light-emitting layer 7, and the seventh insulating layer 43 covers the end faces of the first electrode layer 13 and the first semiconductor layer 10 of the third light-emitting layer 7 facing the second light-emitting layer 6. The fifth metal wiring 33 includes a fourth covering section 37, a fifth covering section 38 and a sixth covering section 39 connected in sequence, wherein the fourth covering section 37 is located on the side of the second light-emitting layer 6 facing the third light-emitting layer 7, one end of the fourth covering section 37 is connected to the end of the second electrode layer 14 of the second light-emitting layer 6 facing the third light-emitting layer 7, and the other end of the fourth covering section 37 extends to the substrate 1 and connects to the fifth covering section 38; the fifth covering section 38 covers the part of the substrate 1 between the second light-emitting layer 6 and the third light-emitting layer 7; the sixth covering section 39 is located on the side of the third light-emitting layer 7 facing the second light-emitting layer 6, one end of the sixth covering section 39 is connected to the end of the second electrode layer 14 of the third light-emitting layer 7 facing the second light-emitting layer 6, and the other end of the sixth covering section 39 extends to the substrate 1 and connects to the fifth covering section 38. At the same time, the fourth covering section 37 is separated from the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6 by the sixth insulating layer 42, and the sixth covering section 39 is separated from the first electrode layer 13 and the first semiconductor layer 10 of the third light-emitting layer 7 by the seventh insulating layer 43. Thus, the second electrode layer 14 of the second light-emitting layer 6 and the second electrode layer 14 of the third light-emitting layer 7 are electrically connected, so that the first light-emitting layer 5, the second light-emitting layer 6 and the second electrode layer 14 of the third light-emitting layer 7 are electrically connected, forming a common electrode for the three.

[0148] In some exemplary embodiments, Figure 7As shown, when the light-emitting chip is powered on, the first electrode layer 13 and the second electrode layer 14 are respectively powered, and the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 emit light respectively. The first semiconductor layer 10 of the first light-emitting unit 2 emits blue light, and the blue light passes through the second electrode layer 14 and is emitted back to the first electrode layer 13, so that the first light-emitting unit 2 emits blue light through electroluminescence. The first semiconductor layer 10 of the second light-emitting unit 3 emits blue light, and the blue light passes through the second electrode layer 14, irradiates the second semiconductor layer 11, and can pass through the second semiconductor layer 11 to irradiate the first transflective layer 8. At the same time, the blue light can excite the second semiconductor layer 11 to emit green light, and the green light can irradiate the first transflective layer 8. After the two colors of light pass through the first transflective layer 8, the first transflective layer 8 reflects the blue light and allows the green light to pass through the first transflective layer 8, so that the second light-emitting unit 3 emits green light through photoluminescence. The first semiconductor layer 10 of the third light emitting unit 4 emits blue light, which passes through the second electrode layer 14, irradiates the second semiconductor layer 11, and can pass through the second semiconductor layer 11 to irradiate the third semiconductor layer 12, and the blue light can excite the second semiconductor layer 11 to emit green light, which can pass through the third semiconductor layer 12 to irradiate the second transflective layer 9, and the blue light can also excite the third semiconductor layer 12 to emit red light, which irradiates the second transflective layer 9. When the three colors of light pass through the second transflective layer 9, the second transflective layer 9 reflects the blue light and the green light and can allow the red light to pass through the second transflective layer 9, so that the third light emitting unit 4 emits red light through photoluminescence.

[0149] In some exemplary embodiments, a manufacturing method is applied to Figure 7 The preparation of the light-emitting chip shown in the figure mainly includes deposition, etching, and packaging. First, a substrate is prepared, and a first conductive layer 47, a first epitaxial layer 48, a second conductive layer 49, a second epitaxial layer 50, and a third epitaxial layer 52 are sequentially deposited on the prepared substrate. The first epitaxial layer 48 can adopt a blue light LED epitaxial structure, the second epitaxial layer 50 can adopt a green light LED epitaxial structure, and the third epitaxial layer 52 can adopt a red light LED epitaxial structure, so as to obtain Fig.16a The composite membrane layer 54 is shown.

[0150] Next, a first etching is performed to etch the composite film layer 54 into independent first light-emitting layer 5, second light-emitting layer 6 and third light-emitting layer 7, so as to obtain Fig.16b The light-emitting layer pattern 55 shown may include a first light-emitting layer 5, a second light-emitting layer 6 and a third light-emitting layer 7; the first light-emitting layer 5 includes a stacked first electrode layer 13, a first semiconductor layer 10 and a second electrode layer 14; the second light-emitting layer 6 includes a stacked first electrode layer 13, a first semiconductor layer 10, a second electrode layer 14 and a second semiconductor layer 11; the third light-emitting layer 7 includes a stacked first electrode layer 13, a first semiconductor layer 10, a second electrode layer 14 and a third semiconductor layer 12.

[0151] Next, an insulating film is deposited and etched to obtain an insulating layer pattern, wherein the insulating layer pattern includes: Figure 8 The fourth insulating layer 40 shown, and Fig. 9 The fifth insulating layer 41 and the sixth insulating layer 42 shown in FIG. Fig.10 The seventh insulating layer 43 shown, the fourth insulating layer 40 covers the first electrode layer 13 of the first light-emitting layer 5 and the end face of the first semiconductor layer 10 facing the second light-emitting layer 6, the fifth insulating layer 41 covers the first electrode layer 13 of the second light-emitting layer 6 and the end face of the first semiconductor layer 10 facing the first light-emitting layer 5; the sixth insulating layer 42 covers the first electrode layer 13 of the second light-emitting layer 5 and the end face of the first semiconductor layer 10 facing the third light-emitting layer 7, and the seventh insulating layer 43 covers the first electrode layer 13 of the third light-emitting layer 7 and the end face of the first semiconductor layer 10 facing the second light-emitting layer 6.

[0152] Deposit a metal layer and etch to obtain a metal wiring pattern, the metal wiring pattern includes: Figure 7 The fourth metal routing 32 and the fifth metal routing 33 shown are used to obtain the first blank, the fourth metal routing 32 corresponds to the fourth insulating layer 40 and the fifth insulating layer 41 and connects the second light-emitting layer 6 and the second electrode layer 14 of the first light-emitting layer 5; the fifth metal routing 33 corresponds to the sixth insulating layer 42 and the seventh insulating layer 43 and connects the second light-emitting layer 6 and the second electrode layer 14 of the third light-emitting layer 7.

[0153] Then, a first transflective film is deposited on the metal wiring pattern and etched to obtain a first transflective pattern. The first transflective pattern includes: Figure 7 The first transflective layer 8 is shown.

[0154] Next, a first transflective film is deposited on the first transflective pattern and etched to obtain a second transflective pattern. The second transflective pattern includes: Figure 7 The second transflective layer 9 shown forms an independent first light-emitting unit 2 , a second light-emitting unit 3 and a third light-emitting unit 4 .

[0155] Subsequently, packaging is performed, and after the reflective film is deposited, the packaging structure is filled by rotation on the substrate, so that the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 are all embedded in the packaging structure;

[0156] Finally, the substrate is peeled off, and the first light-emitting unit 2 without the backing plate and other structures are transferred to the substrate 1, thereby completing the entire preparation process of the light-emitting chip.

[0157] Fig.11 is a schematic diagram of another light-emitting chip according to an embodiment of the present disclosure, Fig.12 for Fig.11 Schematic diagram of the first light-emitting unit in some exemplary embodiments, such as Fig.11 and Fig.12 As shown, the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 are sequentially arranged along the first direction, the first direction is parallel to the substrate 1, and the spacing between the first light-emitting unit 2 and the second light-emitting unit 3, and the spacing between the second light-emitting unit 3 and the third light-emitting unit 4 are matched with the pixel spacing. The first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 are all stacked structures, the first light-emitting unit 2 may include a single-layer first light-emitting layer 5, a single layer means having only one semiconductor structure, the first light-emitting layer 5 may include a first electrode layer 13, a first semiconductor layer 10 and a second electrode layer 14, wherein the first electrode layer 13, the first semiconductor layer 10 and the second electrode layer 14 are sequentially stacked in a direction away from the substrate 1, and the projection of the first electrode layer 13 on the substrate 1, the projection of the first semiconductor layer 10 on the substrate 1 and the projection of the second electrode layer 14 on the substrate 1 all overlap. The first electrode layer 13 can be an N-type electrode. The first electrode layer 1 can be an opaque electrode that cannot transmit light, but is not limited to this, and can also be a transparent electrode; the second electrode layer 14 can be a P-type electrode and can be a light-transmitting electrode. The light-transmitting electrode is a transparent electrode material that can transmit light. The light-transmitting electrode can be indium tin oxide (ITO), which has good visible light transmittance and low resistivity. The first semiconductor layer 10 can use a blue light LED epitaxial layer, so that the first color light emitted by the first light-emitting unit 2 is blue light, but is not limited to this. For example, the first semiconductor layer 10 can be a red light LED epitaxial structure or a green light LED epitaxial structure, and the corresponding first color light will also change accordingly. The first semiconductor layer 10 includes a first N-type contact layer 20, a first quantum well 21, and a first P-type contact layer 22 arranged in sequence in a direction away from the substrate 1, wherein the first quantum well 21 may be made of indium gallium nitride InGaN / gallium nitride GaN grown alternately in multiple periods, or may be made of aluminum gallium nitride AlGaN / gallium nitride GaN grown alternately in multiple periods, and the number of layers of the quantum well 27 is 1 to 10. The material of the first P-type contact layer 22 may be GaN gallium nitride doped with magnesium Mg, aluminum nitride AlN doped with magnesium Mg, or aluminum gallium nitride AlGaN doped with magnesium Mg, etc. The material of the first N-type contact layer 20 may be gallium nitride GaN doped with silicon Si, aluminum nitride AlN doped with silicon Si, or aluminum gallium nitride AlGaN doped with silicon Si, etc.

[0158] Fig.13 for Fig.11 Schematic diagram of the second light emitting unit in, in some exemplary embodiments, as Fig.11 and Fig.13As shown, the second light-emitting unit 3 may include a second light-emitting layer 6 and a first transflective layer 8, wherein the second light-emitting layer 6 may be a double-layer semiconductor structure, and the second light-emitting layer 6 may include a stacked first electrode layer 13, a first semiconductor layer 10, a second electrode layer 14, and a second semiconductor layer 11, and the first electrode layer 13, the first semiconductor layer 10, the second electrode layer 14, and the second semiconductor layer 11 are arranged in sequence in a direction away from the substrate 1. The first electrode layer 13 may be an N-type electrode, and the first electrode layer 1 may be an opaque electrode that is not transparent to light, but is not limited thereto, and may also be a transparent electrode; the second electrode layer 14 may be a P-type electrode and may be a light-transmitting electrode, and the light-transmitting electrode is a transparent electrode material that is transparent to light, and the light-transmitting electrode may be indium tin oxide (ITO), which has good visible light transmittance and low resistivity. The first semiconductor layer 10 may adopt a blue light LED epitaxial structure, and the second semiconductor layer 11 may adopt a green light LED epitaxial structure, but is not limited thereto, for example, the second semiconductor layer 11 may adopt a red light LED epitaxial structure. The first semiconductor layer 10 of the second light-emitting layer 6 may be arranged in the same layer as the first semiconductor layer 10 of the first light-emitting layer 5, and "arranged in the same layer" means that the two are formed simultaneously through the same patterning process. The first semiconductor layer 10 of the second light-emitting layer 6 includes a first N-type contact layer 20, a first quantum well 21, and a first P-type contact layer 22 arranged in sequence in a direction away from the substrate 1, wherein the orthographic projection of the first N-type contact layer 20 on the substrate 1, the orthographic projection of the first quantum well 21 on the substrate 1, and the orthographic projection of the first P-type contact layer 22 on the substrate 1 overlap. The second semiconductor layer 11 of the second light-emitting layer 6 may include a second P-type contact layer 25, a second quantum well 24, and a second N-type contact layer 23 arranged in sequence in a direction away from the substrate 1, and the orthographic projection of the second P-type contact layer 25 on the substrate 1, the orthographic projection of the second quantum well 24 on the substrate 1, and the orthographic projection of the second N-type contact layer 23 on the substrate 1 overlap. The first quantum well 21 and the second quantum well 24 can be made of indium gallium nitride InGaN / gallium nitride GaN grown alternately in multiple cycles, or aluminum gallium nitride AlGaN / gallium nitride GaN grown alternately in multiple cycles, and the number of quantum well layers is 1 to 10. The materials of the first P-type contact layer 22 and the second P-type contact layer 25 can be made of GaN gallium nitride doped with magnesium Mg, aluminum nitride AlN doped with magnesium Mg, or aluminum gallium nitride AlGaN doped with magnesium Mg. The materials of the first N-type contact layer 20 and the second N-type contact layer 23 can be made of gallium nitride GaN doped with silicon Si, aluminum nitride AlN doped with silicon Si, or aluminum gallium nitride AlGaN doped with silicon Si. The first reflective layer 8 can filter light of different wavelengths. The first reflective layer 8 is a reflective film. The reflective film can be a conductive green-transmitting and blue-blocking film. The green-transmitting and blue-blocking film can be a green-transmitting and blue-reflecting light-combining film. The green-transmitting and blue-reflecting light-combining film can transmit green light with a larger wavelength and reflect blue light with a smaller wavelength. The green-transmitting and blue-reflecting light-combining film can be prepared by an evaporation process or can be manufactured by a deposition process.

[0159] In some exemplary embodiments, Fig.11 and Fig.13 As shown, in the second light-emitting unit 3, the orthographic projections of the first semiconductor layer 10, the second electrode layer 14, the second semiconductor layer 11, the third electrode layer 15 and the first transflective layer 8 on the substrate 1 are all located within the orthographic projection of the first electrode layer 13 on the substrate 1, and the lateral direction of the second light-emitting layer 6 is the side wall of the second light-emitting layer 6 in the first direction.

[0160] In some exemplary embodiments, Fig.11 , Fig.12 and Fig.13 As shown, the light-emitting chip further includes a fourth metal wiring 32, a fourth insulating layer 40 and a fifth insulating layer 41. The fourth metal wiring 32 is located between the second light-emitting layer 6 and the first light-emitting layer 5. The fourth insulating layer 40 can prevent the fourth metal wiring 32 from contacting the first electrode layer 13 and the first semiconductor layer 10 of the first light-emitting layer 5. The fifth insulating layer 41 can prevent the fourth metal wiring 32 from contacting the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6. The fourth insulating layer 40 covers the end faces of the first electrode layer 13 and the first semiconductor layer 10 of the first light-emitting layer 5 facing the second light-emitting layer 6, and the fifth insulating layer 41 covers the end faces of the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6 facing the first light-emitting layer 5. The fourth metal trace 32 includes a first covering section 34, a second covering section 35 and a third covering section 36 connected in sequence, wherein the first covering section 34 is located on the side of the first light-emitting layer 5 facing the second light-emitting layer 6, one end of the first covering section 34 is connected to the end of the second electrode layer 14 of the first light-emitting layer 5 facing the second light-emitting layer 6, and the other end of the first covering section 34 extends to the substrate 1 and connects to the second covering section 35; the second covering section 35 covers the part of the substrate 1 between the second light-emitting layer 6 and the first light-emitting layer 5; the third covering section 36 is located on the side of the second light-emitting layer 6 facing the first light-emitting layer 5, one end of the third covering section 36 is connected to the end of the second electrode layer 14 of the second light-emitting layer 6 facing the first light-emitting layer 5, and the other end of the third covering section 36 extends to the substrate 1 and connects to the second covering section 35. At the same time, the first covering section 34 is separated from the first electrode layer 13 and the first semiconductor layer 10 of the first light-emitting layer 5 by the fourth insulating layer 40, and the third covering section 36 is separated from the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6 by the fifth insulating layer 41. Thus, the second electrode layer 14 of the second light-emitting layer 6 and the second electrode layer 14 of the first light-emitting layer 5 are electrically connected.

[0161] Fig.14 for Fig.11 Schematic diagram of the third light emitting unit in some exemplary embodiments, such as Fig.11 and Fig.14As shown, the third light-emitting unit 4 may include a third light-emitting layer 7 and a second transflective layer 9, wherein the third light-emitting layer 7 may be a two-layer semiconductor structure, and the third light-emitting layer 7 may include a stacked first electrode layer 13, a first semiconductor layer 10, a second electrode layer 14, and a third semiconductor layer 12, wherein the first electrode layer 13, the first semiconductor layer 10, the second electrode layer 14, and the third semiconductor layer 12 are sequentially arranged in a direction away from the substrate 1. The first electrode layer 13 may be an N-type electrode, and the first electrode layer 1 may be an opaque electrode that is not transparent to light, but is not limited thereto, and may also be a transparent electrode; the second electrode layer 14 may be a P-type electrode and may be a light-transmitting electrode, and the light-transmitting electrode is a transparent electrode material that is transparent to light, and the light-transmitting electrode may be indium tin oxide (ITO), which has good visible light transmittance and low resistivity. The first semiconductor layer 10 may adopt a blue light LED epitaxial structure, and the third semiconductor layer 12 may adopt a red light LED epitaxial structure, but is not limited thereto, for example, the third semiconductor layer 12 may adopt a green light LED epitaxial structure. The first semiconductor layer 10 of the third light-emitting layer 7 may be arranged in the same layer as the first semiconductor layer 10 of the first light-emitting layer 5 and the second light-emitting layer 6, and the third semiconductor layer 12 of the third light-emitting layer 7 may be arranged in the same layer as the second semiconductor layer 11 of the second light-emitting layer 6. The first semiconductor layer 10 of the third light-emitting layer 7 includes a first N-type contact layer 20, a first quantum well 21, and a first P-type contact layer 22 arranged in sequence in a direction away from the substrate 1, wherein the orthographic projection of the first N-type contact layer 20 on the substrate 1, the orthographic projection of the first quantum well 21 on the substrate 1, and the orthographic projection of the first P-type contact layer 22 on the substrate 1 overlap. The third semiconductor layer 12 of the third light-emitting layer 7 may include a third P-type contact layer 29, a third quantum well 28, and a third N-type contact layer 27 arranged in sequence in a direction away from the substrate 1, wherein the orthographic projection of the third N-type contact layer 27 on the substrate 1, the orthographic projection of the third quantum well 28 on the substrate 1, and the orthographic projection of the third P-type contact layer 29 on the substrate 1 overlap. The first quantum well 21 and the third quantum well 28 may be made of indium gallium nitride InGaN / gallium nitride GaN grown alternately in multiple cycles, or aluminum gallium nitride AlGaN / gallium nitride GaN grown alternately in multiple cycles, and the number of quantum well layers is 1 to 10. The materials of the first P-type contact layer 22 and the third P-type contact layer 29 may be GaN gallium nitride doped with magnesium Mg, aluminum nitride AlN doped with magnesium Mg, or aluminum gallium nitride AlGaN doped with magnesium Mg. The materials of the first N-type contact layer 20 and the third N-type contact layer 27 may be gallium nitride GaN doped with silicon Si, aluminum nitride AlN doped with silicon Si, or aluminum gallium nitride AlGaN doped with silicon Si. The second reflective layer 9 covers the end face of the third semiconductor layer 12 away from the substrate 1. The second reflective layer 9 can be a conductive red-transmitting and blue-blocking film. The red-transmitting and blue-blocking film can be a red-transmitting and blue-reflecting light-combining film. The red-transmitting and blue-reflecting light-combining film can transmit red light and reflect blue light. The red-transmitting and blue-reflecting light-combining film can be prepared by an evaporation process or can be manufactured by a deposition process.

[0162] In some exemplary embodiments, Fig.11 and Fig.14 As shown, in the third light-emitting unit 4, the orthographic projections of the first semiconductor 10, the second electrode layer 14, the third semiconductor layer 12 and the second reflective layer 9 on the substrate 1 are all located within the orthographic projection of the first electrode layer 13 on the substrate 1, and the lateral direction of the third light-emitting layer 7 is the side wall of the third light-emitting layer 7 in the first direction.

[0163] In some exemplary embodiments, Fig.11 , Fig.13 and Fig.14 As shown, the light-emitting chip further includes a fifth metal wiring 33, a sixth insulating layer 42 and a seventh insulating layer 43. The fifth metal wiring 33 is located between the second light-emitting layer 6 and the third light-emitting layer 7. The sixth insulating layer 42 can prevent the fifth metal wiring 33 from contacting the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6. The seventh insulating layer 43 can prevent the fifth metal wiring 33 from contacting the first electrode layer 13 and the first semiconductor layer 10 of the third light-emitting layer 7. The sixth insulating layer 42 covers the end faces of the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 5 facing the third light-emitting layer 7, and the seventh insulating layer 43 covers the end faces of the first electrode layer 13 and the first semiconductor layer 10 of the third light-emitting layer 7 facing the second light-emitting layer 6. The fifth metal wiring 33 includes a fourth covering section 37, a fifth covering section 38 and a sixth covering section 39 connected in sequence, wherein the fourth covering section 37 is located on the side of the second light-emitting layer 6 facing the third light-emitting layer 7, one end of the fourth covering section 37 is connected to the end of the second electrode layer 14 of the second light-emitting layer 6 facing the third light-emitting layer 7, and the other end of the fourth covering section 37 extends to the substrate 1 and connects to the fifth covering section 38; the fifth covering section 38 covers the part of the substrate 1 between the second light-emitting layer 6 and the third light-emitting layer 7; the sixth covering section 39 is located on the side of the third light-emitting layer 7 facing the second light-emitting layer 6, one end of the sixth covering section 39 is connected to the end of the second electrode layer 14 of the third light-emitting layer 7 facing the second light-emitting layer 6, and the other end of the sixth covering section 39 extends to the substrate 1 and connects to the fifth covering section 38. At the same time, the fourth covering section 37 is separated from the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6 by the sixth insulating layer 42, and the sixth covering section 39 is separated from the first electrode layer 13 and the first semiconductor layer 10 of the third light-emitting layer 7 by the seventh insulating layer 43. Thus, the second electrode layer 14 of the second light-emitting layer 6 and the second electrode layer 14 of the third light-emitting layer 7 are electrically connected, so that the first light-emitting layer 5, the second light-emitting layer 6 and the second electrode layer 14 of the third light-emitting layer 7 are electrically connected, forming a common electrode for the three.

[0164] In some exemplary embodiments, Fig.11As shown, when the light-emitting chip is powered on, the first electrode layer 13 and the second electrode layer 14 are respectively powered, and the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 emit light respectively. The first semiconductor layer 10 of the first light-emitting unit 2 emits blue light, and the blue light passes through the second electrode layer 14 and is emitted back to the first electrode layer 13, so that the first light-emitting unit 2 emits blue light through electroluminescence. The first semiconductor layer 10 of the second light-emitting unit 3 emits blue light, and the blue light passes through the second electrode layer 14, irradiates the second semiconductor layer 11, and can pass through the second semiconductor layer 11 to irradiate the first transflective layer 8. At the same time, the blue light can excite the second semiconductor layer 11 to emit green light, and the green light can irradiate the first transflective layer 8. After the two colors of light pass through the first transflective layer 8, the first transflective layer 8 reflects the blue light and allows the green light to pass through the first transflective layer 8, so that the second light-emitting unit 3 emits green light through photoluminescence. The first semiconductor layer 10 of the third light-emitting unit 4 emits blue light, which passes through the second electrode layer 14, irradiates the third semiconductor layer 12, and can pass through the third semiconductor layer 12 to irradiate the second transflective layer 9. The blue light can excite the third semiconductor layer 12 to emit red light, and the red light irradiates the second transflective layer 9. When the two colors of light pass through the second transflective layer 9, the second transflective layer 9 reflects the blue light and allows the red light to pass through the second transflective layer 9, so that the third light-emitting unit 4 emits red light through photoluminescence.

[0165] In some exemplary embodiments, a manufacturing method is applied to Fig.11 The preparation of the light-emitting chip shown in the figure mainly includes deposition, etching and packaging. First, a substrate is prepared, and a first conductive layer 47, a first epitaxial layer 48, a second conductive layer 49 and a second epitaxial layer 50 are sequentially deposited on the prepared substrate. The first epitaxial layer 48 can adopt a blue light LED epitaxial structure, and the second epitaxial layer 50 can adopt a green light LED epitaxial structure, so as to obtain Fig.17a The composite membrane layer 54 is shown.

[0166] Subsequently, the second epitaxial layer 50 is etched to form a first light emitting pattern 56. The second semiconductor layer 11 includes a second semiconductor layer 11. Fig.17b shown.

[0167] Next, a third epitaxial layer 52 is deposited on the first light emitting pattern 56. The third epitaxial layer 52 may adopt a red light LED epitaxial structure, as shown in FIG. Fig.17c shown.

[0168] Then, the third epitaxial layer 52 is etched to form an independent first light-emitting layer 5, a second light-emitting layer 6 and a third light-emitting layer 7, and the following is obtained: Fig.17d The second light emitting layer pattern 55 shown in the figure can form a third light emitting layer 7 with the third semiconductor layer 12 . The third light emitting layer 7 includes a stacked first electrode layer 13 , a first semiconductor layer 10 , a second electrode layer 14 , and a third semiconductor layer 12 .

[0169] Next, an insulating film is deposited and etched to obtain an insulating layer pattern, wherein the insulating layer pattern includes: Fig.12 The fourth insulating layer 40 shown, and Fig.13 The fifth insulating layer 41 and the sixth insulating layer 42 shown in FIG. Fig.14 The seventh insulating layer 43 shown, the fourth insulating layer 40 covers the first electrode layer 13 of the first light-emitting layer 5 and the end face of the first semiconductor layer 10 facing the second light-emitting layer 6, the fifth insulating layer 41 covers the first electrode layer 13 of the second light-emitting layer 6 and the end face of the first semiconductor layer 10 facing the first light-emitting layer 5; the sixth insulating layer 42 covers the first electrode layer 13 of the second light-emitting layer 5 and the end face of the first semiconductor layer 10 facing the third light-emitting layer 7, and the seventh insulating layer 43 covers the first electrode layer 13 of the third light-emitting layer 7 and the end face of the first semiconductor layer 10 facing the second light-emitting layer 6.

[0170] Deposit a metal layer and etch to obtain a metal wiring pattern, the metal wiring pattern includes: Fig.11 The fourth metal routing 32 and the fifth metal routing 33 shown are used to obtain the first blank, the fourth metal routing 32 corresponds to the fourth insulating layer 40 and the fifth insulating layer 41 and connects the second light-emitting layer 6 and the second electrode layer 14 of the first light-emitting layer 5; the fifth metal routing 33 corresponds to the sixth insulating layer 42 and the seventh insulating layer 43 and connects the second light-emitting layer 6 and the second electrode layer 14 of the third light-emitting layer 7.

[0171] Then, a first transflective film is deposited on the metal wiring pattern and etched to obtain a first transflective pattern. The first transflective pattern includes: Fig.11 The first transflective layer 8 is shown.

[0172] Next, a first transflective film is deposited on the first transflective pattern and etched to obtain a second transflective pattern. The second transflective pattern includes: Fig.11 The second transflective layer 9 shown forms an independent first light-emitting unit 2 , a second light-emitting unit 3 and a third light-emitting unit 4 .

[0173] Subsequently, packaging is performed, and after the reflective film is deposited, the packaging structure is filled by rotation on the substrate, so that the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 are all embedded in the packaging structure;

[0174] Finally, the substrate is peeled off, and the first light-emitting unit 2 without the backing plate and other structures are transferred to the substrate 1, thereby completing the entire preparation process of the light-emitting chip.

[0175] In some exemplary embodiments, a display device includes the above-mentioned light-emitting chip. The display device provided by the embodiments of the present disclosure can be applied to electronic devices, such as mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigators, car displays, and any products or components with display functions such as wearable devices, such as smart watches, smart bracelets, smart glasses, smart headphones, smart clothing, head-mounted displays, etc.

[0176] In combination with the light-emitting chip of the above embodiment, a combination of blue LED, red LED and green LED is used instead of a single LED, and a transflective layer is used to filter the required color light to achieve RGB display, thus forming a full-color solution with better display effect. In addition, the light-emitting chip does not need to add quantum dots (QD) to achieve full color, which greatly reduces the production cost.

[0177] The above-described embodiments only express several embodiments of the present disclosure, and the descriptions thereof are relatively specific and detailed, but the contents described are only embodiments adopted for facilitating the understanding of the present disclosure, and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present disclosure, but the scope of patent protection of the present disclosure shall still be defined by the attached claims.

Claims

1. A light-emitting chip, characterized in that: It includes a substrate and a first light emitting unit, a second light emitting unit and a third light emitting unit located on the same side of the substrate; The first light-emitting unit includes a first light-emitting layer disposed on the substrate, and the first light-emitting unit is configured to emit a first color light; The second light-emitting unit includes a second light-emitting layer and a first transflective layer, the second light-emitting layer is arranged on the substrate, the first transflective layer is arranged on a side of the second light-emitting layer away from the substrate, and the first transflective layer is configured to filter out the first color light so that the second light-emitting unit emits the second color light; The third light-emitting unit includes a third light-emitting layer and a second reflective layer, the third light-emitting layer is arranged on the substrate, the second reflective layer is arranged on a side of the third light-emitting layer away from the substrate, and the second reflective layer is configured to filter out the first color light and / or the second color light so that the third light-emitting unit emits a third color light.

2. The light-emitting chip according to claim 1, characterized in that: The first light-emitting layer includes a first electrode layer, a first semiconductor layer, and a second electrode layer sequentially disposed on the substrate; The second light-emitting layer comprises a first electrode layer, a first semiconductor layer, a second electrode layer and a second semiconductor layer sequentially arranged on the substrate, and the first transflective layer is located on a side of the second semiconductor layer away from the substrate; The third light-emitting layer includes a first electrode layer, a first semiconductor layer, and a second electrode layer sequentially arranged on the substrate; the third light-emitting layer is provided with the second semiconductor and third semiconductor layers stacked on a side of the second electrode layer away from the first semiconductor layer, or the third light-emitting layer is provided with a third semiconductor layer on a side of the second electrode layer away from the first semiconductor layer, and the second reflective layer is located on a side of the third semiconductor layer away from the second electrode layer.

3. The light-emitting chip according to claim 2, characterized in that: The second light-emitting layer further comprises a third electrode layer covering a surface of the second semiconductor layer away from the second electrode layer, in the second light-emitting layer, the first transflective layer covers a surface of the third electrode layer away from the second semiconductor layer, and the third electrode layer is electrically connected to the first electrode layer; The third light-emitting layer also includes a third electrode layer and a fourth electrode layer. In the third light-emitting layer, the first electrode layer, the first semiconductor layer, the second electrode layer, the second semiconductor, the third electrode layer, the third semiconductor layer and the fourth electrode layer are arranged in sequence in a direction away from the substrate, the first electrode layer and the third electrode layer are electrically connected, the second electrode layer and the fourth electrode layer are electrically connected, and the second reflective layer covers the surface of the fourth electrode layer away from the third semiconductor layer.

4. The light-emitting chip according to claim 3, characterized in that: Also included is a first metal routing, a second metal routing, and a third metal routing; The first metal wiring is located at the side of the second light-emitting layer, one end of the first metal wiring is connected to the first electrode layer, and the other end of the first metal wiring is connected to the third electrode layer, and the first semiconductor layer, the second electrode layer and the second semiconductor layer are provided with a first insulating layer on a side facing the first metal wiring; The second metal wiring and the third metal wiring are respectively located on two opposite sides of the third light-emitting layer; In the third light-emitting layer, one end of the second metal routing is connected to the first electrode layer, the other end of the second metal routing is connected to the third electrode layer, and the first semiconductor layer, the second electrode layer, and the second semiconductor layer are provided with a second insulating layer on the side facing the second metal routing; one end of the third metal routing is connected to the second electrode layer, the other end of the third metal routing is connected to the fourth electrode layer, and the second semiconductor layer, the third electrode layer, and the third semiconductor layer are provided with a third insulating layer on the side facing the third metal routing.

5. The light-emitting chip according to claim 3, characterized in that: In the second light-emitting layer, the orthographic projections of the first electrode layer, the first semiconductor layer, the second electrode layer, the second semiconductor layer and the third electrode layer on the substrate are all located within the orthographic projection of the first electrode layer on the substrate; In the third light-emitting layer, the orthographic projections of the second semiconductor, the third electrode layer, the third semiconductor layer and the fourth electrode layer on the substrate are all located within the orthographic projection of the second electrode layer on the substrate, and the orthographic projections of the second electrode layer and the first semiconductor layer on the substrate are all located within the orthographic projection of the first electrode layer on the substrate.

6. The light emitting chip according to claim 2, characterized in that: In the third light-emitting unit, the second semiconductor layer is arranged to cover a surface of the second electrode layer away from the first semiconductor layer, and the third semiconductor layer is arranged to cover a surface of the second semiconductor layer away from the second electrode layer; The second reflective layer covers the surface of the third semiconductor layer away from the second electrode layer, and the second reflective layer is configured as a red-transmitting, blue-blocking, and green-blocking film.

7. The light-emitting chip according to claim 2, characterized in that: In the third light-emitting unit, the third semiconductor layer is arranged to cover a surface of the second electrode layer away from the first semiconductor layer; The second reflective transmissive layer covers the surface of the third semiconductor layer away from the second electrode layer, and the second reflective transmissive layer is configured as a red-transmitting and blue-blocking film.

8. The light-emitting chip according to claim 6 or 7, characterized in that: Also including a fourth metal routing and a fifth metal routing; The second light-emitting layer is arranged on the substrate at intervals from the first light-emitting layer and the third light-emitting layer, respectively; the fourth metal wiring is located between the first light-emitting layer and the third light-emitting layer; and the second electrode layer of the second light-emitting layer is arranged to be electrically connected to the second electrode layer of the first light-emitting layer through the fourth metal wiring; The fifth metal wiring is located between the second light-emitting layer and the third light-emitting layer, and the second electrode layer of the second light-emitting layer is configured to be electrically connected to the second electrode layer of the third light-emitting layer through the fifth metal wiring.

9. The light emitting chip according to claim 7, characterized in that: The first semiconductor layer includes a first N-type contact layer, a first quantum well, and a first P-type contact layer which are sequentially arranged in a direction away from the substrate; The second semiconductor layer includes a second P-type contact layer, a second quantum well, and a second N-type contact layer which are sequentially arranged in a direction away from the substrate; The third semiconductor layer includes a third P-type contact layer, a third quantum well, and a third N-type contact layer which are sequentially arranged in a direction away from the substrate.

10. The light emitting chip according to any one of claims 2 to 6, characterized in that: The first semiconductor layer includes a first N-type contact layer, a first quantum well, and a first P-type contact layer which are sequentially arranged in a direction away from the substrate; The second semiconductor layer includes a second P-type contact layer, a second quantum well, and a second N-type contact layer which are sequentially arranged in a direction away from the substrate; The third semiconductor layer includes a third N-type contact layer, a third quantum well, and a third P-type contact layer which are sequentially arranged in a direction away from the substrate.

11. The light-emitting chip according to any one of claims 1 to 7, characterized in that: The first color light is set to blue light, the second color light is set to green light, and the third color light is set to red light; The first reflective layer is configured as a conductive green light-transmitting film, and the second reflective layer is configured as a conductive red light-transmitting film.

12. The light-emitting chip according to any one of claims 1 to 7, characterized in that: A reflective film is also included, and the reflective film is configured to at least wrap the sides of the first light emitting unit, the second light emitting unit, and the third light emitting unit.

13. The light-emitting chip according to any one of claims 1 to 7, characterized in that: It also includes a packaging structure, which is disposed on the substrate and covers the first light emitting unit, the second light emitting unit and the third light emitting unit.

14. A display device, characterized in that: The invention comprises a light-emitting chip as claimed in any one of claims 1 to 13.

15. A manufacturing method, applied to the light-emitting chip according to claim 1, characterized in that: include: Depositing to form a composite film layer, depositing a first conductive layer, a first epitaxial layer, a second conductive layer, a second epitaxial layer, a third conductive layer, a third epitaxial layer and a fourth conductive layer on the substrate in sequence to obtain a composite film layer; Etching the composite film layer to etch a light-emitting layer pattern from the composite film layer; the light-emitting layer pattern includes the first light-emitting layer, the second light-emitting layer and the third light-emitting layer spaced apart from each other, the first light-emitting layer includes a stacked first electrode layer, a first semiconductor layer and a second electrode layer; the second light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer, a second semiconductor layer and a third electrode layer; the third light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer, a second semiconductor layer, a third electrode layer, a third semiconductor layer and a fourth electrode layer; Depositing an insulating film and etching to obtain an insulating layer pattern, wherein the insulating layer pattern includes a first insulating layer, a second insulating layer and a third insulating layer; the first insulating layer covers the end faces of the first semiconductor layer, the second semiconductor layer and the second electrode layer facing the second light-emitting unit; the second insulating layer covers the end faces of the first semiconductor layer, the second semiconductor layer and the second electrode layer facing the second light-emitting layer; The third insulating layer covers the end surface of the second semiconductor layer, the third semiconductor layer and the third electrode layer facing away from the second light-emitting layer; Depositing a metal layer and etching to obtain a metal routing pattern, the metal routing pattern comprising a first metal routing, a second metal routing and a third metal routing, the first metal routing corresponding to the first insulating layer and connecting the third electrode layer and the first electrode layer of the second light-emitting layer; the second metal routing corresponding to the second insulating layer and connecting the third electrode layer and the first electrode layer of the third light-emitting layer; the third metal routing corresponding to the third insulating layer and connecting the fourth electrode layer and the second electrode layer of the third light-emitting layer; Depositing a first transflective film on the metal wiring pattern and etching to obtain a first transflective pattern, wherein the first transflective pattern includes a first transflective layer; Depositing a first transflective film on the first transflective pattern and etching to obtain a second transflective pattern, wherein the second transflective pattern includes a second transflective layer to form the first light-emitting unit, the second light-emitting unit and the third light-emitting unit independently; Performing packaging, rotating and filling the packaging structure on the substrate, so that the first light-emitting unit, the second light-emitting unit and the third light-emitting unit are all embedded in the packaging structure; The substrate is peeled off and transferred to the base plate.

16. A manufacturing method, applied to the light-emitting chip according to claim 1, characterized in that: include: Depositing to form a composite film layer, depositing a first conductive layer, a first epitaxial layer, a second conductive layer, a second epitaxial layer, and a third epitaxial layer on the substrate in sequence to obtain a composite film layer; Etching the composite film layer to etch a light-emitting layer pattern from the composite film layer; the light-emitting layer pattern includes the first light-emitting layer, the second light-emitting layer and the third light-emitting layer spaced apart from each other, the first light-emitting layer includes a stacked first electrode layer, a first semiconductor layer and a second electrode layer; the second light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer and a second semiconductor layer; the third light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer, a second semiconductor layer and a third semiconductor layer; Depositing an insulating film and etching to obtain an insulating layer pattern, wherein the insulating layer pattern includes a fourth insulating layer, a fifth insulating layer, a sixth insulating layer and a seventh insulating layer; The fourth insulating layer covers the end surface of the first electrode layer and the first semiconductor layer of the first light-emitting layer facing the second light-emitting layer, and the fifth insulating layer covers the end surface of the first electrode layer and the first semiconductor layer of the second light-emitting layer facing the first light-emitting layer; the sixth insulating layer covers the end surface of the first electrode layer and the first semiconductor layer of the second light-emitting layer facing the third light-emitting layer, and the seventh insulating layer covers the end surface of the first electrode layer and the first semiconductor layer of the third light-emitting layer facing the second light-emitting layer; Depositing a metal layer and etching to obtain a metal wiring pattern, wherein the metal wiring pattern includes a fourth metal wiring and a fifth metal wiring, wherein the fourth metal wiring connects the first light-emitting layer and the second electrode layer of the second light-emitting layer; and the fifth metal wiring connects the third light-emitting layer and the second electrode layer of the second light-emitting layer; Depositing a first transflective film on the metal wiring pattern and etching to obtain a first transflective pattern, wherein the first transflective pattern includes a first transflective layer; Depositing a first transflective film on the first transflective pattern and etching to obtain a second transflective pattern, wherein the second transflective pattern includes a second transflective layer to form the first light-emitting unit, the second light-emitting unit and the third light-emitting unit independently; Performing packaging, rotating and filling the packaging structure on the substrate, so that the first light-emitting unit, the second light-emitting unit and the third light-emitting unit are all embedded in the packaging structure; The substrate is peeled off and transferred to the base plate.

17. A manufacturing method, applied to the light-emitting chip according to claim 1, characterized in that: include: Depositing to form a composite film layer, depositing a first conductive layer, a first epitaxial layer, a second conductive layer, and a second epitaxial layer on the substrate in sequence to obtain a composite film layer; Etching the composite film layer to etch a first light-emitting layer pattern from the composite film layer; the first light-emitting layer pattern includes the first light-emitting layer, the second light-emitting layer and the third light-emitting blank layer which are spaced apart from each other, the first light-emitting layer includes a stacked first electrode layer, a first semiconductor layer and a second electrode layer; the second light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer and a second semiconductor layer; the third light-emitting blank layer includes a stacked first electrode layer, a first semiconductor layer and a second electrode layer; Depositing a third epitaxial layer on the first light-emitting layer pattern and etching to obtain a second light-emitting layer pattern; the second light-emitting layer pattern includes a third semiconductor layer, and the first electrode layer, the first semiconductor layer, the second electrode layer and the third semiconductor layer constitute the third light-emitting layer; Depositing an insulating film and etching to obtain an insulating layer pattern, wherein the insulating layer pattern includes a fourth insulating layer, a fifth insulating layer, a sixth insulating layer and a seventh insulating layer; The fourth insulating layer covers the end surface of the first electrode layer and the first semiconductor layer of the first light-emitting layer facing the second light-emitting layer, and the fifth insulating layer covers the end surface of the first electrode layer and the first semiconductor layer of the second light-emitting layer facing the first light-emitting layer; the sixth insulating layer covers the end surface of the first electrode layer and the first semiconductor layer of the second light-emitting layer facing the third light-emitting layer, and the seventh insulating layer covers the end surface of the first electrode layer and the first semiconductor layer of the third light-emitting layer facing the second light-emitting layer; Depositing a metal layer and etching to obtain a metal wiring pattern, wherein the metal wiring pattern includes a fourth metal wiring and a fifth metal wiring, wherein the fourth metal wiring connects the first light-emitting layer and the second electrode layer of the second light-emitting layer; and the fifth metal wiring connects the third light-emitting layer and the second electrode layer of the second light-emitting layer; Depositing a first transflective film on the metal wiring pattern and etching to obtain a first transflective pattern, wherein the first transflective pattern includes a first transflective layer; Depositing a first transflective film on the first transflective pattern and etching to obtain a second transflective pattern, wherein the second transflective pattern includes a second transflective layer to form the first light-emitting unit, the second light-emitting unit and the third light-emitting unit independently; Performing packaging, rotating and filling the packaging structure on the substrate, so that the first light-emitting unit, the second light-emitting unit and the third light-emitting unit are all embedded in the packaging structure; The substrate is peeled off and transferred to the base plate.

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