Display device

Abstract

A display device includes: a substrate; a first display layer on a first surface of the substrate; a second display layer on a second surface of the substrate; a first pixel of the first display layer; and a second pixel of the second display layer, in which the first pixel and the second pixel include different numbers of transistors.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0144929 filed in the Korean Intellectual Property Office on October 26, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] An aspect of some embodiments of the present disclosure relates to a display device. Background Art

[0004] A head mounted display (HMD) is an image display device that can be worn on a user's head in the form of glasses or a helmet to form a focus at a close distance in front of the user's eyes. The head mounted display can realize virtual reality (VR) or augmented reality (AR).

[0005] The head-mounted display can magnify the image displayed in the small display device by using multiple lenses, and display the magnified image. Therefore, the display device applied to the head-mounted display can ideally provide a high-resolution image, for example, an image with a resolution of 3000PPI (pixels per inch) or higher. To this end, an organic light-emitting diode on silicon (OLEDoS), which is a high-resolution small organic light-emitting display device, can be used as a display device applied to the head-mounted display. OLEDoS is an image display device in which an organic light-emitting diode (OLED) can be formed on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is positioned.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background technology, and therefore, the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0007] Aspects of some embodiments of the present disclosure relate to a display device, and, for example, to a display device having a relatively small thickness and a relatively reduced manufacturing cost.

[0008] Aspects of some embodiments of the present disclosure include a display device having a relatively small thickness and a relatively reduced manufacturing cost.

[0009] According to some embodiments of the present disclosure, a display device includes: a substrate; a first display layer on a first surface of the substrate; a second display layer on a second surface of the substrate; a first pixel of the first display layer; and a second pixel of the second display layer, wherein the first pixel and the second pixel include different numbers of transistors.

[0010] According to some embodiments, the second pixel circuit of the second pixel includes a greater number of transistors than the number of transistors of the first pixel circuit of the first pixel.

[0011] According to some embodiments, the first pixel circuit includes five transistors and the second pixel circuit includes eight transistors.

[0012] According to some embodiments, the first pixel circuit includes: a first transistor, including a gate electrode connected to a first node, and the first transistor is connected between a second node and a third node; a second transistor, including a gate electrode connected to a first gate line, and the second transistor is connected between a data line and the first node; a third transistor, including a gate electrode connected to a third gate line, and the third transistor is connected between a reference voltage line and the first node; a fourth transistor, including a gate electrode connected to a second gate line, and the fourth transistor is connected between the third node and an initialization voltage line; and a fifth transistor, including a gate electrode connected to an emission line, and the fifth transistor is connected between a driving voltage line and the second node.

[0013] According to some embodiments, the first to fifth transistors each include an oxide semiconductor material.

[0014] According to some embodiments, the first to fifth transistors are n-type transistors.

[0015] According to some embodiments, the second transistor further includes a counter gate electrode connected to the first gate line, the third transistor further includes a counter gate electrode connected to the third gate line, and the fourth transistor further includes a counter gate electrode connected to the second gate line.

[0016] According to some embodiments, the first pixel circuit further includes: a first capacitor connected between the first node and the third node; and a second capacitor connected between the driving voltage line and the third node.

[0017] According to some embodiments, the second pixel circuit includes: a first transistor, including a gate electrode connected to a third node, and the first transistor is connected between the first node and the second node; a second transistor, including a gate electrode connected to a first gate line, and the second transistor is connected between a data line and the first node; a third transistor, including a gate electrode connected to a second gate line, and the third transistor is connected between the third node and the second node; a fourth transistor, including a gate electrode connected to a third gate line, and the fourth transistor is connected between the third node and a first initialization voltage line; a fifth transistor, including a gate electrode connected to an emission line, and the fifth transistor is connected between a driving voltage line and the first node; a sixth transistor, including a gate electrode connected to the emission line, and the sixth transistor is connected between the second node and the fourth node; a seventh transistor, including a gate electrode connected to a fourth gate line, and the seventh transistor is connected between the fourth node and the second initialization voltage line; and an eighth transistor, including a gate electrode connected to the fourth gate line, and the eighth transistor is connected between a bias voltage line and the first node.

[0018] According to some embodiments, the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor each include a silicon-based semiconductor material, and the third transistor and the fourth transistor each include an oxide semiconductor material.

[0019] According to some embodiments, the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are p-type transistors, and the third transistor and the fourth transistor are p-type transistors.

[0020] According to some embodiments, the third transistor further includes a counter gate electrode connected to the second gate line, and the fourth transistor further includes a counter gate electrode connected to the third gate line.

[0021] According to some embodiments, the second pixel circuit further includes a capacitor connected between the driving voltage line and the third node.

[0022] According to some embodiments, the first display layer and the second display layer have different areas.

[0023] According to some embodiments, the first display layer has an area larger than an area of ​​the second display layer.

[0024] According to some embodiments, the display device further includes a driving circuit on the second surface and connected to the first display layer and the second display layer.

[0025] According to some embodiments, the drive circuit is connected to the first display layer through a first pad terminal of the drive circuit, and the drive circuit is connected to the second display layer through a second pad terminal of the drive circuit.

[0026] According to some embodiments, the first pad terminal is connected to the first display layer through a first pad on the second surface, and the second pad terminal is connected to the second display layer through a second pad on the second surface.

[0027] According to some embodiments, the driving circuit supplies a gate signal, a data signal, and an emission signal to the first display layer through the first pad terminal, and the driving circuit supplies a gate signal, a data signal, and an emission signal to the second display layer through the second pad terminal.

[0028] According to some embodiments, the first pixel further includes a first light emitting element connected to the first pixel circuitry, and the second pixel further includes a second light emitting element connected to the second pixel circuitry.

[0029] In the display device according to some embodiments of the present disclosure, the thickness and manufacturing cost of the display device can be relatively reduced.

[0030] Features of some embodiments of the present disclosure are not limited to the above-mentioned effects, and other features not described herein will become apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the present disclosure will become more apparent by describing aspects of some embodiments of the present disclosure in more detail with reference to the accompanying drawings, in which:

[0032] Figure 1 is a perspective view of a display device according to some embodiments;

[0033] Figure 2 According to some embodiments Figure 1 An exploded perspective view of a display device;

[0034] Figure 3 is a diagram showing a folded state at a specific angle according to some embodiments Figure 1 a diagram of a display device;

[0035] Figure 4 is a diagram showing a fully folded state according to some embodiments Figure 1 a diagram of a display device;

[0036] Figure 5 According to some embodiments, Figure 1 an equivalent circuit diagram of a first pixel in a first display layer;

[0037] Figure 6 According to some embodiments Figure 1 A cross-sectional view of a first display layer;

[0038] Figure 7 According to some embodiments, Figure 1 an equivalent circuit diagram of a second pixel in a second display layer;

[0039] Figure 8 According to some embodiments Figure 1 A cross-sectional view of a second display layer;

[0040] Fig. 9 is a cross-sectional view showing a structure of a display element according to some embodiments;

[0041] Figures 10 to 13 is a cross-sectional view showing the structure of a light emitting element according to some embodiments;

[0042] Fig.14 is a diagram showing some embodiments of the present invention. Fig.12 A cross-sectional view of an example of an organic light emitting diode;

[0043] Fig.15 is a diagram showing some embodiments of the present invention. Fig.13 A cross-sectional view of an example of an organic light emitting diode; and

[0044] Fig.16 is a cross-sectional view showing a structure of a pixel of a display device according to some embodiments. DETAILED DESCRIPTION

[0045] From the description of the disclosed embodiments below with reference to the accompanying drawings, aspects and features of some embodiments of the present disclosure and methods for implementing them will become more apparent. However, embodiments according to the present disclosure are not limited to the embodiments disclosed herein, but can be implemented in various different ways. The disclosed embodiments are provided to make the disclosure of the present disclosure thorough, and to more fully convey the scope of the embodiments according to the present disclosure to those skilled in the art. It will be noted that the scope of the embodiments according to the present disclosure is defined by the attached claims and their equivalents.

[0046] As used herein, the phrase "element A on element B" means that element A can be directly positioned on element B and / or element A can be indirectly positioned on element B via another element C. Throughout the description, the same reference numerals represent the same elements. The figures, sizes, proportions, angles, and numbers of elements given in the drawings are illustrative only and not limiting.

[0047] Although terms such as first, second, etc. are used to arbitrarily distinguish the elements described by these terms, and therefore, these terms are not necessarily intended to indicate the temporal priority or other priority of these elements. These terms are only used to distinguish one element from another element. Therefore, as used herein, within the technical scope of the present disclosure, a first element may be a second element.

[0048] The features of the various embodiments of the present disclosure may be combined in part or in whole. As will be clearly appreciated by those skilled in the art, various interactions and operations are technically possible. The various embodiments may be practiced independently or in combination.

[0049] Hereinafter, aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0050] Figure 1 is a perspective view of a display device 1000 according to some embodiments. Figure 2 According to some embodiments Figure 1 1 is an exploded perspective view of a display device 1000.

[0051] like Figure 1 and Figure 2 As shown in , a display device 1000 according to some embodiments may include a substrate SUB, a first display layer 101 , a second display layer 102 , and a driving circuit 200 .

[0052] The substrate SUB may be a rigid substrate or a flexible substrate, and the flexible substrate may be bent, folded or curled without damaging the substrate SUB. The substrate SUB may be formed of an insulating material such as glass, quartz or a polymer resin. Examples of polymer resins may include any suitable polymer material, such as polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), cellulose acetate propionate (CAP) or a combination thereof. Optionally, the substrate SUB may include a metal material.

[0053] The substrate SUB may be positioned between the first display layer 101 and the second display layer 102. The substrate SUB may have a rectangular shape in a plan view, but is not limited thereto according to embodiments of the present disclosure. The substrate SUB may include a first surface S1 and a second surface S2 facing each other in a third direction DR3.

[0054] The first display layer 101 may be positioned on the first surface S1 of the substrate SUB. For example, the first display layer 101 may be positioned on the first surface S1 of the substrate SUB so as to overlap the entire first surface S1. The area of ​​the first display layer 101 may be equal to or smaller than the area of ​​the first surface S1. Here, the aforementioned area (e.g., the area of ​​the first display layer 101 or the area of ​​the first surface S1) may be a size in the first direction DR1 and the second direction DR2 (e.g., a size in the first direction DR1×a size in the second direction DR2).

[0055] The first display layer 101 may display an image through the first display surface DS1. The first display surface DS1 of the first display layer 101 may be positioned at the opposite side of the interface between the first display layer 101 and the substrate SUB.

[0056] The first display layer 101 may include a plurality of first pixels PX1 for displaying an image through the aforementioned first display surface DS1. Three adjacent first pixels PX1 may constitute a first unit pixel. For example, the first unit pixel may include three first pixels PX1 positioned adjacent to each other in the first direction DR1 in the first display layer 101.

[0057] The three first pixels PX1 of the first unit pixel may be pixels that provide light of different colors (or wavelengths). For example, among the three first pixels PX1, one first pixel PX1 may provide light of a first color, another first pixel PX1 may provide light of a second color, and yet another first pixel PX1 may provide light of a third color. Here, the first color may be any one of red, green, and blue, the second color may be any one of the above red, green, and blue that is different from the first color, and the third color may be any one of the above red, green, and blue that is different from the first color and the second color.

[0058] In addition, the first display layer 101 may further include a plurality of gate lines, a plurality of data lines, and a plurality of emission lines connected to the first pixel PX1.

[0059] The second display layer 102 may be positioned on the second surface S2 of the substrate SUB. For example, the second display layer 102 may be positioned on the second surface S2 of the substrate SUB so as to partially overlap with the second surface S2. According to some embodiments, the second surface S2 may include a display area and a non-display area. The aforementioned second display layer 102 may be positioned in the display area of ​​the second surface S2. The area of ​​the second surface S2 may be the same as the area of ​​the aforementioned first surface S1. The area of ​​the second display layer 102 may be smaller than the area of ​​the second surface S2.

[0060] The second display layer 102 may provide an image through the second display surface DS2. The second display surface DS2 of the second display layer 102 may be positioned on the opposite side of the interface between the second display layer 102 and the substrate SUB.

[0061] The second display layer 102 may include a plurality of second pixels PX2 for displaying an image through the aforementioned second display surface DS2. Three adjacent second pixels PX2 may constitute a second unit pixel. For example, the second unit pixel may include three second pixels PX2 adjacent to each other in the first direction DR1 in the second display layer 102.

[0062] The three second pixels PX2 of the second unit pixel may be pixels that provide light of different colors (or wavelengths). For example, among the three second pixels PX2, one second pixel PX2 may provide light of the first color, another second pixel PX2 may provide light of the second color, and another second pixel PX2 may provide light of the third color.

[0063] In addition, the second display layer 102 may further include a plurality of gate lines, a plurality of data lines, and a plurality of emission lines connected to the second pixels PX2.

[0064] The driving circuit 200 may provide a plurality of gate signals, a plurality of data signals, and a plurality of emission signals for driving the first display layer 101 and the second display layer 102. The driving circuit 200 may be positioned on the second surface S2 of the substrate SUB. For example, the driving circuit 200 may be positioned in a non-display area of ​​the second surface S2. The driving circuit 200 and the second display layer 102 may be positioned on the second surface S2 to be spaced apart from each other by a distance (e.g., a set distance or a predetermined distance) in the first direction DR1.

[0065] The driving circuit 200 may include, for example, a gate driver, an emission driver, and a data driver. Meanwhile, the display device according to some embodiments may further include a circuit board on which a timing control circuit and a power supply circuit are mounted. The circuit board may be electrically connected to the second surface S2 of the substrate SUB through a conductive adhesive member such as an anisotropic conductive film. The timing control circuit and the power supply circuit of the circuit board may be electrically connected to the driving circuit 200 through the pads of the second surface S2.

[0066] The timing control circuit may receive digital video data and timing signals from the outside. The timing control circuit may generate a gate control signal, an emission control signal, and a data control signal for controlling the display panel of the display device 1000 according to the timing signal. The timing control circuit may output the gate control signal to the gate driver and the emission control signal to the emission driver. The timing control circuit may output the digital video data and the data control signal to the data driver.

[0067] The power supply circuit may generate a plurality of driving voltages in response to a power voltage from the outside.

[0068] Each of the timing control circuit and the power supply circuit may be formed as an integrated circuit (IC) and attached to one surface of the circuit board. The gate control signal, emission control signal, digital video data, and data control signal of the timing control circuit may be supplied to the driving circuit 200 through the circuit board. The driving voltage of the power supply circuit may be supplied to the first display layer 101 and the second display layer 102 through the circuit board.

[0069] The gate driver may receive a gate control signal from the timing control circuit, and may generate gate signals according to the gate control signal of the timing control circuit, and output them to the gate lines of the first display layer 101 and the gate lines of the second display layer 102, respectively.

[0070] The data driver may receive digital video data and a data control signal from the timing control circuit. The data driver may convert the digital video data signal into an analog data signal according to the data control signal, and output them to the data line of the first display layer 101 and the data line of the second display layer 102, respectively. In this case, the first pixel PX1 of the first display layer 101 and the second pixel PX2 of the second display layer 102 may be selected by the gate signal of the gate driver, and the data signal may be supplied to the selected first pixel PX1 and the second pixel PX2, respectively.

[0071] The emission driver may receive an emission control signal from the timing control circuit, and may generate emission signals according to the emission control signal, and output them to the emission lines of the first display layer 101 and the emission lines of the second display layer 102, respectively.

[0072] like Figure 2 As shown in , the driving circuit 200 may include a plurality of first pad terminals 211 and a plurality of second pad terminals 212. The first pad terminals 211 and the second pad terminals 212 of the driving circuit 200 may be positioned on a surface of the driving circuit 200 facing the second surface S2 of the substrate SUB. The first pad terminal 211 of the driving circuit 200 may be electrically connected to the first display layer 101 through the first pad of the second surface S2. Therefore, the gate signal, data signal and emission signal of the driving circuit 200 may be supplied to the first display layer 101. In addition, the second pad terminal 212 of the driving circuit 200 may be electrically connected to the second display layer 102 through the second pad of the second surface S2. Therefore, the gate signal, data signal and emission signal of the driving circuit 200 may be supplied to the second display layer 102.

[0073] According to some embodiments, the first display layer 101 and the second display layer 102 may be formed on one substrate SUB. In other words, since the first display layer 101 and the second display layer 102 are respectively arranged on two surfaces of the substrate SUB, the two display layers 101 and 102 may be positioned on one substrate SUB. Therefore, the display device 1000 including the two display layers 101 and 102 may have a small thickness. In addition, since one substrate SUB may be used when manufacturing the display device 1000 including the two display layers 101 and 102, the manufacturing cost of the display device 1000 may be relatively reduced.

[0074] Figure 3 is a diagram showing a folded state at a specific angle according to some embodiments Figure 1 FIG. 1 is a diagram of a display device 1000 .

[0075] like Figure 3 As shown in , the display device 1000 can be folded at a specific angle θ. For example, the central portion of the substrate SUB and the first display layer 101 are folded at a specific angle θ, so that the display device 1000 can be folded at the specific angle θ.

[0076] Figure 4 is a diagram showing a fully folded state according to some embodiments Figure 1 FIG. 1 is a diagram of a display device 1000 .

[0077] like Figure 4 As shown in , the display device 1000 can be folded at an angle of 180 degrees so that the second display surface DS2 of the second display layer 102 faces the third direction DR3. For example, the central portion of the substrate SUB and the first display layer 101 are folded at an angle of 180 degrees so that the display device 1000 can be folded at an angle of 180 degrees. In this case, because the first display surface DS1 of the first display layer 101 can be divided into a first sub-display surface overlapping the second display layer 102 and a second sub-display surface overlapping the driving circuit 200, the first sub-display surface and the second sub-display surface can be arranged to face each other, as shown in FIG. Figure 4 as shown in .

[0078] Figure 5 According to some embodiments, Figure 1 1 is an equivalent circuit diagram of a first pixel PX1 in the first display layer 101.

[0079] Reference Figure 5 The first pixel PX1 may include a light emitting element LEL (eg, an organic light emitting diode) as a display element and a pixel circuit PC connected to the light emitting element LEL. The pixel circuit PC may include first to fifth transistors T1 to T5 and first and second capacitors C1 and C2.

[0080] The first transistor T1 can be a driving transistor in which the size of the source-drain current is determined according to the gate-source voltage, and the second transistor T2 to the fifth transistor T5 can be a switching transistor that is turned on / off according to the gate-source voltage (basically the gate voltage). The first transistor T1 to the fifth transistor T5 can be implemented as a thin film transistor. According to the type (p-type or n-type) and / or operating conditions of the transistor, the first electrode of each of the first transistor T1 to the fifth transistor T5 can be a source electrode or a drain electrode, and the second electrode can be an electrode different from the first electrode. For example, when the first electrode is a source electrode, the second electrode can be a drain electrode.

[0081] The first pixel PX1 may be connected to a first gate line GWL transmitting a first gate signal GW, a second gate line GIL transmitting a second gate signal GI, a third gate line GRL transmitting a third gate signal GR, an emission line EML transmitting an emission signal EM, and a data line DL transmitting a data signal DATA. The driving voltage line VDL may transmit a driving voltage ELVDD to the fifth transistor T5. The initialization voltage line VIL may transmit an initialization voltage VINT to the fourth transistor T4. The reference voltage line VRL may transmit a reference voltage VREF to the third transistor T3. Meanwhile, according to the pixel structure, the initialization voltage line VIL may include a plurality of initialization voltage lines (e.g., a first initialization voltage line and a second initialization voltage line) transmitting initialization voltages of different magnitudes.

[0082] The first transistor T1 to the fifth transistor T5 may include an oxide semiconductor material. Since the oxide semiconductor has high carrier mobility and low leakage current, the voltage drop is not large despite the long driving time. That is, in the case of the oxide semiconductor, since the color change of the image due to the voltage drop is not large even during low-frequency driving, low-frequency driving is possible. Therefore, the display device 1000 (see FIG. 1 ) that prevents or reduces the generation of leakage current and has relatively reduced power consumption can be realized by the first transistor T1 to the fifth transistor T5 including the oxide semiconductor material. Figure 1 ). In addition, when an oxide semiconductor transistor is used, it is not necessary to form a low temperature polycrystalline silicon (LTPS) semiconductor transistor by a crystallization process of excimer laser annealing (ELA), and thus the manufacturing cost of the display device 1000 can be relatively reduced, so that a large-area display device can be realized.

[0083] The oxide semiconductor is sensitive to light, so that fluctuations in the amount of current, etc. may occur due to light from the outside. Therefore, it can be considered to absorb or reflect light from the outside by positioning a metal layer under the oxide semiconductor. The metal layer positioned below the oxide semiconductor of each of the first transistor T1 to the fifth transistor T5 can be used as a gate electrode. That is, the first transistor T1 to the fifth transistor T5 can be a double-gate transistor having two gate electrodes (for example, a gate electrode and a gate electrode). The gate electrode and the gate electrode can be arranged to face each other on different layers. For example, each of the first transistor T1 to the fifth transistor T5 can be an n-channel oxide semiconductor transistor, and the gate electrode and the gate electrode of each of the first transistor T1 to the fifth transistor T5 can be positioned to face each other, and the oxide semiconductor is between the first gate electrode GE1 and the second gate electrode GE2.

[0084] The first transistor T1 includes a gate electrode connected to a first node N1 (or a gate node), a gate pair electrode connected to a third node N3, a first electrode connected to a second node N2, and a second electrode connected to the third node N3. The gate pair electrode of the first transistor T1 may be connected to the second electrode of the first transistor T1 to be controlled by a voltage applied to the second electrode of the first transistor T1, and the output saturation characteristic of the first transistor T1 may be relatively improved. The first electrode of the first transistor T1 may be connected to a driving voltage line VDL via a fifth transistor T5, and the second electrode of the first transistor T1 may be connected to a pixel electrode PE of the light emitting element LEL (see Figure 6 The first transistor T1 may be used as a driving transistor, and may control the size (eg, current amount) of a driving current Isd flowing to the light emitting element LEL by receiving a data signal DATA according to a switching operation of the second transistor T2.

[0085] The second transistor T2 includes a gate electrode and a gate electrode connected to the first gate line GWL, a first electrode connected to the data line DL, and a second electrode connected to the first node N1 (or the first gate electrode of the first transistor T1). The second transistor T2 can be turned on according to the first gate signal GW transmitted to the first gate line GWL to electrically connect the data line DL to the first node N1, and can transmit the data signal DATA transmitted to the data line DL to the first node N1.

[0086] The third transistor T3 may include a gate electrode and a gate electrode connected to a third gate line GRL, a first electrode connected to a reference voltage line VRL, and a second electrode connected to a first node N1 (or a first gate electrode of the first transistor T1). The third transistor T3 may be turned on according to a third gate signal GR transmitted to the third gate line GRL, and transmit a reference voltage VREF transmitted to the reference voltage line VRL to the first node N1.

[0087] The fourth transistor T4 includes a gate electrode and a gate electrode connected to the second gate line GIL, a first electrode connected to the third node N3 (or the second electrode of the first transistor T1), and a second electrode connected to the initialization voltage line VIL. The fourth transistor T4 can be turned on according to the second gate signal GI transmitted to the second gate line GIL, and transmits the initialization voltage VINT transmitted to the initialization voltage line VIL to the third node N3.

[0088] The fifth transistor T5 may include a gate electrode and a gate electrode connected to the emission line EML, a first electrode connected to the driving voltage line VDL, and a second electrode connected to the second node (or the first electrode of the first transistor T1). The fifth transistor T5 may be turned on or off according to the emission signal EM transmitted to the emission line EML.

[0089] The first capacitor C1 may be connected between the first node N1 and the third node N3. The first electrode of the first capacitor C1 may be connected to the gate electrode of the first transistor T1, and the second electrode of the first capacitor C1 may be connected to the gate electrode and the second electrode of the first transistor T1, the first electrode of the fourth transistor T4, and the pixel electrode PE (e.g., the anode electrode) of the light emitting element LEL. The first capacitor C1 may be a storage capacitor and may store a voltage corresponding to the threshold voltage of the first transistor T1 and the data signal.

[0090] The second capacitor C2 may be connected between the third node N3 and the driving voltage line VDL. A first electrode of the second capacitor C2 may be connected to the driving voltage line VDL, and a second electrode of the second capacitor C2 may be connected to the gate electrode and the second electrode of the first transistor T1, the second electrode of the first capacitor C1, the first electrode of the fourth transistor T4, and the pixel electrode PE of the light emitting element LEL. The capacitance of the first capacitor C1 may be greater than the capacitance of the second capacitor C2.

[0091] The light emitting element LEL may include a pixel electrode PE (eg, an anode electrode) and a counter electrode (eg, a cathode electrode or Figure 6The counter electrode may be connected to a common voltage line VSL transmitting the common voltage ELVSS. The counter electrode may be a common electrode CM commonly shared by a plurality of first pixels PX1.

[0092] although Figure 5 Various components in the pixel circuit PC are shown, but embodiments according to the present disclosure are not limited thereto. For example, according to some embodiments, the pixel circuit PC may include additional components or fewer components without departing from the spirit and scope of embodiments according to the present disclosure.

[0093] Figure 6 According to some embodiments Figure 1 sectional view of the first display layer 101.

[0094] like Figure 6 As shown in , the first display layer 101 may include a barrier layer BR, a thin film transistor layer TFTL, a light emitting element layer EMTL, and an encapsulation layer ENC positioned on the first surface S1 of the substrate SUB along the third direction DR3. In other words, the barrier layer BR, the thin film transistor layer TFTL, the light emitting element layer EMTL, and the encapsulation layer ENC may be sequentially positioned on the first surface S1 of the substrate SUB along the third direction DR3.

[0095] Combination Figure 5 , the first gate line GWL, the second gate line GIL, the third gate line GRL, the first electrode of the first capacitor C1, the first pair of gate electrodes Gb1 of the first transistor T1, the emission line EML, the first lower driving voltage line of the driving voltage line VDL, the first lower initialization voltage line of the initialization voltage line VIL, and the second lower initialization voltage line of the initialization voltage line VIL can be positioned on the barrier layer BR. Figure 6 An example is shown in which the first pair of gate electrodes Gb1 of the first transistor T1 is positioned on the barrier layer BR.

[0096] The buffer layer BF may be positioned on the above-mentioned first gate line GWL, the second gate line GIL, the third gate line GRL, the first electrode of the first capacitor C1, the first pair of gate electrodes Gb1 of the first transistor T1, the emission line EML, the first lower driving voltage line of the driving voltage line VDL, the first lower initialization voltage line of the initialization voltage line VIL, and the second lower initialization voltage line of the initialization voltage line VIL. The buffer layer BF may be a layer for protecting the transistors of the thin film transistor layer TFTL and the light emitting layer EL of the light emitting element layer EMTL from the influence of moisture penetrating through the substrate SUB susceptible to moisture penetration. The buffer layer BF may be formed of a plurality of inorganic layers alternately stacked. For example, the buffer layer BF may be formed of a plurality of layers in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0097] The active layers ACT of the first to fifth transistors T1 to T5 may be positioned on the buffer layer BF. Figure 6 An example is shown in which the active layer ACT of the first transistor T1 is positioned on the barrier layer BR. The active layer ACT may include a first channel region CH1 of the first transistor T1, a first electrode E11, and a second electrode E12. The active layer ACT may include an oxide semiconductor material.

[0098] The gate insulating layer GTI may be positioned on the active layer ACT. The gate insulating layer GTI may include tetraethyl orthosilicate (TEOS), silicon nitride (SiN x ) and silicon oxide (SiO 2 For example, the gate insulating layer GTI may have a double-layer structure in which a silicon nitride layer having a thickness of 40 nm and a tetraethyl orthosilicate layer having a thickness of 80 nm are sequentially stacked.

[0099] A first gate electrode GE1 of the first transistor T1, a second gate electrode of the second transistor T2, a third gate electrode of the third transistor T3, a fourth gate electrode of the fourth transistor T4, a fifth gate electrode of the fifth transistor T5, and a lower reference voltage line VRL may be positioned on the gate insulating layer GTI. Figure 6 An example is shown in which the first gate electrode GE1 of the first transistor is positioned on the gate insulating layer GTI. The first gate electrode GE1 may be positioned on the gate insulating layer GTI to overlap with the active layer ACT and the first pair of gate electrodes Gb1. The first channel region CH1 may be positioned in a region of the active layer ACT overlapping with the first gate electrode GE1. Meanwhile, the above-mentioned gate insulating layer GTI may have the same shape as the first gate electrode GE1, but may have an area larger than that of the first gate electrode GE1.

[0100] The interlayer insulating layer ITL may be positioned on the first gate electrode GE1, the second gate electrode, the third gate electrode, the fourth gate electrode, the fifth gate electrode, and the lower reference voltage line of the reference voltage line VRL. The interlayer insulating layer ITL may have a thickness greater than that of the gate insulating layer GTI. Here, the thickness may mean a dimension in the third direction DR3. The interlayer insulating layer ITL may include an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. At the same time, the interlayer insulating layer ITL may include a plurality of inorganic layers.

[0101] The data line DL, an upper driving voltage line of the driving voltage line VDL, the pixel connection electrode PCE, and a gate connection electrode connected to each gate electrode may be positioned on the interlayer insulating layer ITL. Figure 6 An example is shown in which the data line DL, the pixel connection electrode PCE, and the first gate connection electrode GCE1 are positioned on the interlayer insulating layer ITL. The first gate connection electrode GCE1 can be connected to the first gate electrode GE1 of the first transistor T1 by a first contact hole CT1 penetrating the interlayer insulating layer ITL. One side of the pixel connection electrode PCE can be connected to the first electrode E11 of the first transistor T1 by a second contact hole CT2 penetrating the interlayer insulating layer ITL, and the other side of the pixel connection electrode PCE can be connected to the first pair of gate electrodes Gb1 of the first transistor T1 by a third contact hole CT3 penetrating the interlayer insulating layer ITL and the buffer layer BF.

[0102] The planarization layer VA may be positioned on the data line DL, the upper driving voltage line of the driving voltage line VDL, the pixel connection electrode PCE, and the gate connection electrode connected to each gate electrode. The planarization layer VA may include an organic layer such as an acrylic resin layer, an epoxy resin layer, a phenolic resin layer, a polyamide resin layer, and a polyimide resin layer.

[0103] The light emitting element layer EMTL may be positioned on the planarization layer VA. For example, the light emitting element layer EMTL may be positioned on the thin film transistor layer TFTL. The light emitting element layer EMTL may include a light emitting element LEL and a pixel defining layer PDL.

[0104] The light emitting element LEL may include a pixel electrode PE, a light emitting layer EL, and a common electrode CM. An emission region EA in which the pixel electrode PE, the light emitting layer EL, and the common electrode CM are sequentially stacked represents a region in which holes from the pixel electrode PE and electrons from the common electrode CM are recombined with each other in the light emitting layer to emit light. In this case, the pixel electrode PE may be an anode electrode of the light emitting element LEL, and the common electrode CM may be a cathode electrode of the light emitting element LEL.

[0105] The pixel electrode PE may be positioned on the planarization layer VA. The pixel electrode PE may be connected to the pixel connection electrode PCE through a fourth contact hole CT4 penetrating the planarization layer VA.

[0106] In a top emission structure that emits light toward the common electrode CM relative to the light emitting layer EL, the pixel electrode PE may be formed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may be formed to have a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO) (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO) to increase reflectivity. The APC alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0107] The pixel defining layer PDL is used to define the emission area EA of the first pixel PX1. To this end, the pixel defining layer PDL may be arranged to expose a partial area of ​​the pixel electrode PE on the planarization layer VA. The pixel defining layer PDL may cover the edge of the pixel electrode PE. The pixel defining layer PDL may be positioned in the fourth contact hole CT4 penetrating the planarization layer VA. Therefore, the fourth contact hole CT4 penetrating the planarization layer VA may be filled with the pixel defining layer PDL. The pixel defining layer PDL may be formed of an organic layer such as an acrylic resin layer, an epoxy resin layer, a phenolic resin layer, a polyamide resin layer, and a polyimide resin layer.

[0108] The spacer SPC may be positioned on the pixel defining layer PDL. The spacer SPC may be used to support a mask during a process of manufacturing the light emitting layer EL. The spacer SPC may be formed of an organic layer such as an acrylic resin layer, an epoxy resin layer, a phenolic resin layer, a polyamide resin layer, and a polyimide resin layer.

[0109] The light-emitting layer EL may be formed on the pixel electrode PE. The light-emitting layer EL may include an organic material that emits light in one color (e.g., a set color or a predetermined color). For example, the light-emitting layer EL may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host and a dopant. The organic material layer may include a material that emits light (e.g., a set light or a predetermined light), and may be formed using a phosphorescent material or a fluorescent material.

[0110] For example, the organic material layer of the first light-emitting layer of the first emission region emitting light of the first color may be a phosphorescent material, the phosphorescent material including a host material and a dopant, the host material including carbazole biphenyl (CBP) or 1,3-bis(carbazole-9-yl)benzene (mCP), the dopant including at least one selected from the group consisting of PIQIr(acac) (bis(1-phenylisoquinoline) iridium acetylacetonate), PQIr(acac) (bis(1-phenylquinoline) iridium acetylacetonate), PQIr(tris(1-phenylquinoline)iridium) and PtOEP (octaethylporphyrin platinum). Alternatively, the organic material layer of the first light-emitting layer of the first emission region may include PBD:Eu(DBM) 3 The fluorescent material may be (Phen)(tris(dibenzoylmethane)mono(phenanthroline)europium(III)) or perylene, but the present disclosure is not limited thereto.

[0111] The organic material layer of the second light-emitting layer of the second emission region emitting light of the second color may be a phosphorescent material including a host material including CBP or mCP and a phosphorescent material including Ir(ppy). 3 Alternatively, the organic material layer of the second light emitting layer of the second emission region emitting light of the second color may be a fluorescent material including Alq3 (tris(8-hydroxyquinoline)aluminum), but the present disclosure is not limited thereto.

[0112] The organic material layer of the light-emitting layer of the third emission region emitting light of the third color may be a phosphorescent material, the phosphorescent material including a host material including CBP or mCP and a 2 ppy) 2 The doping material may be Irpic or L2BD111, but the present disclosure is not limited thereto.

[0113] The common electrode CM may be disposed on the light emitting layer EL. The common electrode CM may be disposed to cover the light emitting layer EL. The common electrode CM may be commonly disposed in the first pixel PX1 (see Figure 5 ) is a common layer on the light emitting layer EL. According to some embodiments, a capping layer may be formed on the common electrode CM.

[0114] In the top emission structure, the common electrode CM may be formed of a transparent conductive material (TCO) capable of transmitting light, such as ITO or indium zinc oxide (IZO), or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the common electrode CM is formed of a semi-transmissive conductive material, light emission efficiency may be improved due to a microcavity effect.

[0115] The encapsulation layer ENC may be positioned on the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer to prevent or reduce the penetration of pollutants such as oxygen or moisture into the light emitting element layer EMTL. In addition, the encapsulation layer ENC may include at least one organic layer to protect the light emitting element layer EMTL from foreign matter such as dust. For example, the encapsulation layer ENC may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3.

[0116] The first encapsulation inorganic layer TFE1 may be positioned on the common electrode CM, the encapsulation organic layer TFE2 may be positioned on the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may be positioned on the encapsulation organic layer TFE2. The first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 may be formed of a multilayer in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The encapsulation organic layer TFE2 may be an organic layer such as an acrylic resin layer, an epoxy resin layer, a phenolic resin layer, a polyamide resin layer, or a polyimide layer resin.

[0117] Figure 7 According to some embodiments, Figure 1 1 is an equivalent circuit diagram of a second pixel PX2 in the second display layer 102.

[0118] Reference Figure 7 The second pixel PX2 can be connected to the first gate line GWL', the second gate line GCL', the third gate line GIL', the fourth gate line EBL', the emission line EML', the data line DL', the driving voltage line VDL', the common voltage line VSL', the first initialization voltage line VIL1', the second initialization voltage line VIL2' and the bias voltage line VBL'.

[0119] The second pixel PX2 may include a pixel circuit PC' and a light emitting element LEL'. The pixel circuit PC' may include a first transistor T1', a second transistor T2', a third transistor T3', a fourth transistor T4', a fifth transistor T5', a sixth transistor T6', a seventh transistor T7', an eighth transistor T8' and a capacitor Cst'.

[0120] The first transistor T1' may include a gate electrode, a source electrode, and a drain electrode. The first transistor T1' may control a source-drain current (hereinafter, a driving current) according to a data signal applied to the gate electrode of the first transistor T1'. A driving current (Isd) flowing through a channel region of the first transistor T1' may be proportional to the square of a difference between a threshold voltage (Vth) of the first transistor T1' and a voltage (Vsg) between a source electrode and a gate electrode of the first transistor T1' (Isd = k × (Vsg - Vth) 2 ). Here, k is a proportionality coefficient determined by the structure and physical characteristics of the first transistor T1', Vsg is the source-gate voltage of the first transistor T1', and Vth is the threshold voltage of the first transistor T1'.

[0121] The light emitting element LEL' may emit light by receiving a driving current (Isd). The emission amount or brightness of the light emitting element LEL' may be proportional to the magnitude of the driving current (Isd).

[0122] The light emitting element LEL' may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer positioned between the first electrode and the second electrode. For another example, the light emitting element LEL' may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor positioned between the first electrode and the second electrode. For another example, the light emitting element LEL' may be a quantum dot light emitting element including a first electrode, a second electrode, and a quantum dot light emitting layer positioned between the first electrode and the second electrode. For another example, the light emitting element LEL' may be a micro light emitting diode.

[0123] A first electrode of the light emitting element LEL' may be electrically connected to a fourth node N4'. The first electrode of the light emitting element LEL' may be connected to a drain electrode of the sixth transistor T6' and a source electrode of the seventh transistor T7' through the fourth node N4'. A second electrode of the light emitting element LEL' may be connected to a common voltage line VSL'. The second electrode of the light emitting element LEL' may receive a common voltage ELVSS' (e.g., a low potential voltage) from the common voltage line VSL'.

[0124] The second transistor T2' may be turned on by the first gate signal GW' of the first gate line GWL' to electrically connect the data line DL' to the first node N1' which is the source electrode of the first transistor T1'. The second transistor T2' may be turned on according to the first gate signal GW' to supply the data signal to the first node N1'. The gate electrode of the second transistor T2' may be electrically connected to the first gate line GWL', the source electrode of the second transistor T2' may be electrically connected to the data line DL', and the drain electrode of the second transistor T2' may be electrically connected to the first node N1'.

[0125] The third transistor T3' may be turned on by the second gate signal GC' of the second gate line GCL' to electrically connect the second node N2', which is the drain electrode of the first transistor T1', to the third node N3', which is the gate electrode of the first transistor T1'. The third transistor T3' may be connected between the third node N3' and the second node N2'. For example, the gate electrode of the third transistor T3' may be electrically connected to the second gate line GCL', the source electrode of the third transistor T3' may be electrically connected to the third node N3', and the drain electrode of the third transistor T3' may be electrically connected to the second node N2'. The third transistor T3' may be turned on by the second gate signal GC' of the second gate line GCL' to electrically connect the second node N2', which is the drain electrode of the first transistor T1', to the third node N3', which is the gate electrode of the first transistor T1'. The third transistor T3' may be a dual-gate transistor having two gate electrodes (e.g., a gate electrode and a gate electrode). The gate electrode and the gate electrode may be arranged to face each other on different layers.

[0126] The fourth transistor T4' may be turned on by the third gate signal GI' of the third gate line GIL' to electrically connect the third node N3', which is the gate electrode of the first transistor T1', to the first initialization voltage line VIL1'. The fourth transistor T4' may be connected in series between the third node N3' and the first initialization voltage line VIL1'. For example, the gate electrode of the fourth transistor T4' may be electrically connected to the third gate line GIL', the source electrode of the fourth transistor T4' may be electrically connected to the third node N3', and the drain electrode of the fourth transistor T4' may be electrically connected to the first initialization voltage line VIL1'. The fourth transistor T4' may be a dual-gate transistor. The first initialization voltage line VIL1' may transmit the first initialization voltage VI1'.

[0127] The fifth transistor T5' may be turned on by the emission signal EM' of the emission line EML' to electrically connect the driving voltage line VDL' to the first node N1' which is the source electrode of the first transistor T1'. The gate electrode of the fifth transistor T5' may be electrically connected to the emission line EML', the source electrode of the fifth transistor T5' may be electrically connected to the driving voltage line VDL', and the drain electrode of the fifth transistor T5' may be electrically connected to the first node N1'.

[0128] The sixth transistor T6' may be turned on by the emission signal EM' of the emission line EML' to electrically connect the second node N2', which is the drain electrode of the first transistor T1', to the fourth node N4', which is the first electrode of the light emitting element LEL'. The gate electrode of the sixth transistor T6' may be electrically connected to the emission line EML', the source electrode of the sixth transistor T6' may be electrically connected to the second node N2', and the drain electrode of the sixth transistor T6' may be electrically connected to the fourth node N4'.

[0129] When all of the fifth transistor T5 ′, the first transistor T1 ′, and the sixth transistor T6 ′ are turned on, a driving current may be supplied to the light emitting element LEL′.

[0130] The seventh transistor T7' may be turned on by the fourth gate signal EB' of the fourth gate line EBL' to electrically connect the fourth node N4', which is the first electrode of the light emitting element LEL', to the second initialization voltage line VIL2'. By turning on the seventh transistor T7' based on the fourth gate signal EB', the first electrode of the light emitting element LEL' may be discharged to the second initialization voltage VI2'. The gate electrode of the seventh transistor T7' may be electrically connected to the fourth gate line EBL', the source electrode of the seventh transistor T7' may be electrically connected to the fourth node N4', and the drain electrode of the seventh transistor T7' may be electrically connected to the second initialization voltage line VIL2'. The second initialization voltage line VIL2' may transmit the second initialization voltage VI2'.

[0131] The eighth transistor T8' may be turned on by the fourth gate signal EB' of the fourth gate line EBL' to electrically connect the bias voltage line VBL' to the first node N1' which is the source electrode of the first transistor T1'. The eighth transistor T8' may be turned on according to the fourth gate signal EB' to supply the bias voltage VB' to the first node N1'. The eighth transistor T8' may relatively improve the hysteresis of the first transistor T1' by supplying the bias voltage VB' to the source electrode of the first transistor T1'. The gate electrode of the eighth transistor T8' may be electrically connected to the fourth gate line EBL', the source electrode of the eighth transistor T8' may be electrically connected to the bias voltage line VBL', and the drain electrode of the eighth transistor T8' may be electrically connected to the first node N1'.

[0132] Each of the first transistor T1', the second transistor T2', the fifth transistor T5', the sixth transistor T6', the seventh transistor T7', and the eighth transistor T8' may include a silicon-based active layer (or a silicon-based semiconductor layer). For example, each of the first transistor T1', the second transistor T2', the fifth transistor T5', the sixth transistor T6', the seventh transistor T7', and the eighth transistor T8' may be a p-type transistor including an active layer made of low-temperature polycrystalline silicon (LTPS). The active layer made of low-temperature polycrystalline silicon may have high electron mobility and excellent conduction characteristics. Therefore, in the display device 1000 (see Figure 1 ), since a transistor having an excellent conduction characteristic is included, it is possible to stably and effectively drive a plurality of second pixels PX2. Each of the first transistor T1', the second transistor T2', the fifth transistor T5', the sixth transistor T6', the seventh transistor T7', and the eighth transistor T8' can output a current flowing into the source electrode to the drain electrode based on a gate low voltage applied to the gate electrode.

[0133] The third transistor T3' and the fourth transistor T4' may be n-type transistors including an oxide-based active layer (or semiconductor layer). The transistor including an oxide-based active layer may have a coplanar structure on which a gate electrode is positioned. The transistor including an oxide-based active layer may output a current flowing into the drain electrode to the source electrode based on a gate high voltage applied to the gate electrode.

[0134] The capacitor Cst' may be electrically connected between the third node N3' as the gate electrode of the first transistor T1' and the driving voltage line VDL'. For example, a first electrode of the capacitor Cst' may be electrically connected to the third node N3', and a second electrode of the capacitor Cst' may be electrically connected to the driving voltage line VDL', so that a potential difference between the driving voltage line VDL' and the gate electrode of the first transistor T1' may be maintained.

[0135] although Figure 8 Various components of the pixel circuit PC' according to some embodiments of the present disclosure are shown, but the embodiments are not limited thereto. For example, according to some embodiments, the pixel circuit PC' may include additional components or fewer components without departing from the spirit and scope of the embodiments of the present disclosure.

[0136] Figure 8 According to some embodiments Figure 1 FIG. 1 is a cross-sectional view of the second display layer 102 .

[0137] like Figure 8As shown in , the second display layer 102 may include a barrier layer BR', a thin film transistor layer TFTL', a light emitting element layer EMTL', and an encapsulation layer ENC' positioned on the second surface S2 of the substrate SUB along the opposite direction of the third direction DR3 (hereinafter, referred to as the third opposite direction). In other words, the barrier layer BR', the thin film transistor layer TFTL', the light emitting element layer EMTL', and the encapsulation layer ENC' may be sequentially positioned on the second surface S2 of the substrate SUB along the third opposite direction.

[0138] The barrier layer BR' may be positioned on the substrate SUB. The barrier layer BR' may be positioned on the entire surface of the substrate SUB. The barrier layer BR' may be used to protect the transistors T1' to T8' (see Figure 7 ) and the light emitting layer EL' of the light emitting element layer EMTL' are protected from moisture penetrating through the substrate SUB susceptible to moisture penetration. The barrier layer BR' may be formed as a plurality of inorganic layers alternately stacked. For example, the barrier layer BR' may be formed of a plurality of layers in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0139] The light blocking layer BML' may be positioned on the barrier layer BR'. The light blocking layer BML' may be positioned on the barrier layer BR' to cover the overlapping region (e.g., the first channel region CH1') between the first gate electrode GE1' of the first transistor T1' and the first active layer ACT1'. In other words, the light blocking layer BML' may be positioned on the barrier layer BR' to overlap the channel region CH1' of the first transistor T1' as a driving transistor.

[0140] The light blocking layer BML may be made of, for example, a metal material (such as chromium (Cr) or molybdenum (Mo)) or a black dye (such as black ink), etc. Meanwhile, when the light blocking layer BML' is made of a metal material, the light blocking layer BML' may be supplied with a constant power supply. In this way, the light blocking layer BML' is not electrically floating, and the transistor on the light blocking layer BML' (e.g., the first transistor T1') may have its electrical characteristics stabilized.

[0141] The buffer layer BF' may be positioned on the light blocking layer BML'. The buffer layer BF' may be positioned on the barrier layer BR' over the entire surface of the substrate SUB. The buffer layer BF' may be a layer for protecting the transistors T1' to T8' of the thin film transistor layer TFTL' and the light emitting layer EL' of the light emitting element layer EMTL' from moisture penetrating through the substrate SUB susceptible to moisture penetration. The buffer layer BF' may be formed of a plurality of inorganic layers alternately stacked. For example, the buffer layer BF' may be formed of a plurality of layers in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0142] The first active layer ACT1' may be positioned on the buffer layer BF'. The first active layer ACT1' may include a first channel region CH1' of the first transistor T1', a second electrode E12' of the first transistor T1', a first electrode E61' of the sixth transistor T6', a second electrode E62' of the sixth transistor T6', and a sixth channel region CH6' of the sixth transistor T6'. The first active layer ACT1' may be an active layer made of low temperature polysilicon (LTPS).

[0143] The first gate insulating layer GTI1 ′ may be positioned on the first active layer ACT1 ′. In this case, the first gate insulating layer GTI1 ′ may be positioned on the first active layer ACT1 ′ over the entire surface of the substrate SUB.

[0144] The first gate insulating layer GTI1' may include tetraethyl orthosilicate (TEOS), silicon nitride (SiN x ) and silicon oxide (SiO 2 For example, the first gate insulating layer GTI1′ may have a double-layer structure in which a silicon nitride layer having a thickness of 40 nm and a tetraethyl orthosilicate layer having a thickness of 80 nm are sequentially stacked.

[0145] Combination Figure 7 The second gate electrode of the second transistor T2', the first gate electrode GE1' of the first transistor T1', the eighth gate electrode of the eighth transistor T8', the emission line EML', the fifth gate electrode of the fifth transistor T5', and the sixth gate electrode GE6' of the sixth transistor T6' may be positioned on the first gate insulating layer GTI1'. Figure 8An example is shown in which the first gate electrode GE1', the sixth gate electrode GE6', and the emission line EML' are positioned on the first gate insulating layer GTI1'. The first gate electrode GE1' may be positioned on the first gate insulating layer GTI1' to overlap with the first channel region CH1' of the first active layer ACT1'. The sixth gate electrode GE6' of the emission line EML' may be positioned on the first gate insulating layer GTI1' to overlap with the sixth channel region CH6 of the first active layer ACT1'.

[0146] The second gate insulating layer GTI2' may be positioned on the second gate electrode of the second transistor T2', the first gate electrode GE1' of the first transistor T1', the eighth gate electrode of the eighth transistor T8', the emission line EML', the fifth gate electrode of the fifth transistor T5', and the sixth gate electrode GE6' of the sixth transistor T6'. Figure 8 As shown in , the second gate insulating layer GTI2' can be positioned on the first gate electrode GE1', the sixth gate electrode GE6' and the emission line EML'. In this case, the second gate insulating layer GTI2' can be positioned on the first gate electrode GE1', the sixth gate electrode GE6' and the emission line EML' over the entire surface of the substrate SUB. The second gate insulating layer GTI2' can include the same material and structure as the above-mentioned first gate insulating layer GTI1'.

[0147] The fourth pair of gate electrodes of the fourth transistor T4 ′, the third pair of gate electrodes GEb3 ′ of the third transistor T3 ′, and the capacitor electrode CPE′ of the capacitor Cst′ may be positioned on the second gate insulating layer GTI2 ′. Figure 8 An example is shown where the capacitor electrode CPE' and the third pair of gate electrodes GEb3' are positioned on the second gate insulating layer GTI2'. The capacitor electrode CPE' may be positioned on the second gate insulating layer GTI2' to overlap with the first gate electrode GE1'. A capacitor Cst' may be formed between the capacitor electrode CPE' and the first gate electrode GE1'.

[0148] The first interlayer insulating layer ITL1' may be positioned on the fourth pair of gate electrodes of the fourth transistor T4', the third pair of gate electrodes GEb3' of the third transistor T3', and the capacitor electrode CPE' of the capacitor Cst'. Figure 8As shown in , the first interlayer insulating layer ITL1' may be positioned on the capacitor electrode CPE' and the third pair of gate electrodes GEb3'. In this case, the first interlayer insulating layer ITL1' may be positioned on the capacitor electrode CPE' and the third pair of gate electrodes GEb3' over the entire surface of the substrate SUB. The first interlayer insulating layer ITL1' may include an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. Meanwhile, the first interlayer insulating layer ITL1' may include a plurality of inorganic layers.

[0149] The second active layer ACT2' may be positioned on the first interlayer insulating layer ITL1'. Figure 8 As shown in , the second active layer ACT2' may be positioned on the first interlayer insulating layer ITL1' to overlap with the third pair of gate electrodes GEb3'. The second active layer ACT2' may include a first electrode E31' of the third transistor T3', a second electrode E32' of the third transistor T3', and a third channel region CH3' of the third transistor T3'. The third channel region CH3' of the second active layer ACT2' may overlap with the third pair of gate electrodes GEb3'. The second active layer ACT2' may be an oxide-based active layer. For example, the second active layer ACT2' may be an oxide semiconductor including indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO).

[0150] The third gate insulating layer GTI3' may be positioned on the second active layer ACT2'. Figure 8 As shown in , the third gate insulating layer GTI3' may be positioned on the second active layer ACT2'. The third gate insulating layer GTI3' may be positioned over the entire surface of the substrate SUB including the second active layer ACT2'. The third gate insulating layer GTI3' may have the same material and structure as the first gate insulating layer GTI1' described above.

[0151] The fourth gate electrode of the fourth transistor T4 ′ and the third gate electrode GE3 ′ of the third transistor T3 ′ may be positioned on the third gate insulating layer GTI3 ′. Figure 8 An example is shown in which the third gate electrode GE3 ′ is positioned on the third gate insulating layer GTI3 ′. The third gate electrode GE3 ′ may be arranged to overlap the third channel region CH3 ′ of the second active layer ACT2 ′.

[0152] The second interlayer insulating layer ITL2' may be positioned on the fourth gate electrode and the third gate electrode GE3'. Figure 8As shown in , the second interlayer insulating layer ITL2' may be positioned on the third gate electrode GE3'. The second interlayer insulating layer ITL2' may be positioned on the third gate electrode GE3' over the entire surface of the substrate SUB. The second interlayer insulating layer ITL2' may have the same material and structure as the above-described first interlayer insulating layer ITL1'.

[0153] The first initialization voltage line VIL1', the third gate line GIL', the data connection electrode, the first gate line GWL', the second gate line GCL', the gate connection electrode GCE', the active connection electrode ACE', the bias voltage line VBL', the capacitor connection electrode CCE', the lower pixel connection electrode PCEa', the fourth gate line EBL' and the second initialization voltage line VIL2' can be positioned on the second interlayer insulating layer ITL2'. Figure 8 An example is shown in which the gate connection electrode GCE', the active connection electrode ACE', the bias voltage line VBL' and the lower pixel connection electrode PCEa' are positioned on the second interlayer insulating layer ITL2'. The lower pixel connection electrode PCEa' may be connected to the second electrode E62' of the sixth transistor T6' by a first contact hole CT1' penetrating the second interlayer insulating layer ITL2', the third gate insulating layer GTI3', the first interlayer insulating layer ITL1', the second gate insulating layer GTI2' and the first gate insulating layer GTI1'. The active connection electrode ACE' may be connected to the second electrode of the first transistor T1' and the first electrode E61' of the sixth transistor T6' by a second contact hole CT2' penetrating the second interlayer insulating layer ITL2', the third gate insulating layer GTI3', the first interlayer insulating layer ITL1', the second gate insulating layer GTI2' and the first gate insulating layer GTI1'. Furthermore, the active connection electrode ACE' may be connected to the second electrode E32' of the third transistor T3' by a fifth contact hole CT5' penetrating the second interlayer insulating layer ITL2' and the third gate insulating layer GTI3'. The gate connection electrode GCE' may be connected to the first gate electrode GE1' by a hole 40' penetrating the second interlayer insulating layer ITL2', the third gate insulating layer GTI3', the first interlayer insulating layer ITL1', the capacitor electrode CPE', and the third contact hole CT3' of the second gate insulating layer GTI2'. Furthermore, the gate connection electrode GCE' may be connected to the first electrode E31' of the third transistor T3' by a fourth contact hole CT4' penetrating the second interlayer insulating layer ITL2' and the third gate insulating layer GTI3'.

[0154] The data link electrode may be connected to the first electrode of the first active layer ACT1 ′ (eg, the first electrode of the second transistor T2 ′) through the contact hole of the insulating layer.

[0155] The first planarization layer VA1' may be positioned on the first initialization voltage line VIL1', the third gate line GIL', the data connection electrode, the first gate line GWL', the second gate line GCL', the gate connection electrode GCE', the active connection electrode ACE', the bias voltage line VBL', the capacitor connection electrode CCE' of the capacitor Cst, the lower pixel connection electrode PCEa', the fourth gate line EBL', and the second initialization voltage line VIL2'. For example, Figure 8 As shown in , the first planarization layer VA1' may be positioned on the gate connection electrode GCE', the active connection electrode ACE', the bias voltage line VBL', and the lower pixel connection electrode PCEa'. The first planarization layer VA1' may be positioned on the gate connection electrode GCE', the active connection electrode ACE', the bias voltage line VBL', and the lower pixel connection electrode PCEa' over the entire surface of the substrate SUB. The first planarization layer VA1' may include an organic layer such as an acrylic resin layer, an epoxy resin layer, a phenolic resin layer, a polyamide resin layer, and a polyimide resin layer.

[0156] The data line DL′, the driving voltage line VDL′, and the upper pixel connection electrode PCEb′ may be positioned on the first planarization layer VA1 ′. Figure 8 An example is shown where the driving voltage line VDL' and the upper pixel connection electrode PCEb' are positioned on the first planarization layer VA1'. The upper pixel connection electrode PCEb' may be connected to the lower pixel connection electrode PCEa' through a sixth contact hole CT6' penetrating the first planarization layer VA1'.

[0157] The second planarization layer VA2' may be positioned on the data line DL', the driving voltage line VDL' and the upper pixel connection electrode PCEb'. Figure 8 As shown in , the second planarization layer VA2' may be positioned on the driving voltage line VDL' and the upper pixel connection electrode PCEb'. The second planarization layer VA2' may be positioned on the driving voltage line VDL' and the upper pixel connection electrode PCEb' over the entire surface of the substrate SUB. The second planarization layer VA2' may have the same material and structure as the first planarization layer VA1' described above.

[0158] The light emitting element layer EMTL' may be positioned on the second planarization layer VA2'. Figure 8 As shown in FIG. 1 , the pixel electrode PE′ may be positioned on the second planarization layer VA2 ′. The pixel electrode PE′ may be connected to the upper pixel connection electrode PCEb′ through a seventh contact hole CT7 ′ penetrating the second planarization layer VA2 ′.

[0159] In addition to the aforementioned pixel electrode PE', the aforementioned light emitting element layer EMTL' may further include a light emitting element LEL' and a pixel defining layer PDL'.

[0160] The light emitting element LEL' may include a pixel electrode PE', a light emitting layer EL' and a common electrode CM'. An emission region EA' in which the pixel electrode PE', the light emitting layer EL' and the common electrode CM' are sequentially stacked represents a region in which holes from the pixel electrode PE' and electrons from the common electrode CM' are recombined with each other in the light emitting layer to emit light. In this case, the pixel electrode PE' may be an anode electrode of the light emitting element LEL', and the common electrode CM' may be a cathode electrode of the light emitting element LEL'.

[0161] In a top emission structure that emits light toward the common electrode CM' relative to the light emitting layer EL', the pixel electrode PE' may be formed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu) or aluminum (Al), or may be formed to have a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO) to increase reflectivity. The APC alloy is an alloy of silver (Ag), palladium (Pd) and copper (Cu).

[0162] The pixel defining layer PDL' may be used to define the second pixel PX2 (see Figure 7 ) of the emission area EA'. To this end, the pixel defining layer PDL' may be arranged to expose a partial area of ​​the pixel electrode PE' on the second planarization layer VA2'. The pixel defining layer PDL' may cover the edge of the pixel electrode PE'. At the same time, the pixel defining layer PDL' may be positioned in the seventh contact hole CT7' penetrating the second planarization layer VA2'. Therefore, the seventh contact hole CT7' penetrating the second planarization layer VA2' may be filled with the pixel defining layer PDL'. The pixel defining layer PDL may be formed of an organic layer such as an acrylic resin layer, an epoxy resin layer, a phenolic resin layer, a polyamide resin layer, and a polyimide resin layer.

[0163] like Figure 8 As shown in , the spacer SPC' can be positioned on the pixel defining layer PDL'. The spacer SPC' can be used to support the mask in the process of manufacturing the light emitting layer EL'. The spacer SPC' can be formed of an organic layer such as an acrylic resin layer, an epoxy resin layer, a phenolic resin layer, a polyamide resin layer, and a polyimide resin layer.

[0164] The light-emitting layer EL' may be formed on the pixel electrode PE'. The light-emitting layer EL' may include an organic material to emit light of a color (e.g., a set color or a predetermined color). For example, the light-emitting layer EL' may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host and a dopant. The organic material layer may include a material that emits light (e.g., a set light or a predetermined light), and may be formed using a phosphorescent material or a fluorescent material.

[0165] The common electrode CM' may be disposed on the light emitting layer EL'. The common electrode CM' may be disposed to cover the light emitting layer EL'.

[0166] The encapsulation layer ENC' may be formed on the light emitting element layer EMTL'. The encapsulation layer ENC' may include at least one inorganic layer to prevent or reduce the penetration of oxygen or moisture into the light emitting element layer EMTL'. In addition, the encapsulation layer ENC' may include at least one organic layer to protect the light emitting element layer EMTL' from foreign matter such as dust. For example, the encapsulation layer ENC' may include a first encapsulation inorganic layer TFE1', an encapsulation organic layer TFE2', and a second encapsulation inorganic layer TFE3'.

[0167] On the other hand, the above-mentioned light emitting element (at least one of the light emitting elements LEL and LEL′) may have a series structure, which will be referred to as Figures 9 to 16 Description is as follows.

[0168] Fig. 9 is a cross-sectional view showing a structure of a display element according to some embodiments, and Figures 10 to 13 is a cross-sectional view illustrating a structure of a light emitting element according to some embodiments.

[0169] Reference Fig. 9 According to some embodiments, a light emitting element (eg, an organic light emitting diode) may include the pixel electrode 201 , the common electrode 205 , and the intermediate layer 203 between the pixel electrode 201 and the common electrode 205 as described above.

[0170] The pixel electrode 201 may include a light-transmitting conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). The pixel electrode 201 may include a reflective layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. For example, the pixel electrode 201 may have a three-layer structure of ITO / Ag / ITO.

[0171] The common electrode 205 may be positioned on the intermediate layer 203. The common electrode 205 may include a low work function metal, an alloy, a conductive compound, or any combination thereof. For example, the common electrode 205 may include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al) calcium (Ca), ytterbium (Yb), ITO, IZO, or any combination thereof (such as, aluminum lithium (Al-Li), magnesium indium (Mg-In), magnesium silver (Mg-Ag), silver ytterbium (Ag-Yb)). The common electrode 205 may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0172] The intermediate layer 203 may include a high molecular weight material or a low molecular weight material that emits light of one color (eg, a set color or a predetermined color). In addition to various organic materials, the intermediate layer 203 may also include metal-containing compounds such as organic metal compounds and inorganic materials such as quantum dots.

[0173] According to some embodiments, the intermediate layer 203 may include a light emitting layer and a first functional layer and a second functional layer positioned below and above the light emitting layer, respectively. The first functional layer may include, for example, a hole transport layer HTL (see Fig.14 ), or may include a hole transport layer HTL and a hole injection layer HIL (see Fig.14 ). The second functional layer is a component positioned on the light-emitting layer and is optional. For example, the intermediate layer 203 may include or exclude the second functional layer. The second functional layer may include an electron transport layer ETL (see Fig.14 ) and / or electron injection layer EIL (see Fig.14 ).

[0174] According to some embodiments, the intermediate layer 203 may include two or more emission units sequentially stacked between the pixel electrode 201 and the common electrode 205, and a charge generation layer CGL (see FIG. 2 ) positioned between the two or more emission units. Fig.10 ). When the intermediate layer 203 includes an emission unit and a charge generation layer CGL, the light emitting element (eg, an organic light emitting diode) may be a tandem light emitting element. By having a stacked structure of a plurality of light emitting units, the light emitting element (eg, an organic light emitting diode) may relatively improve color purity and light emitting efficiency.

[0175] One emission unit may include a light emitting layer and a first functional layer and a second functional layer positioned below and above the light emitting layer, respectively. The charge generation layer CGL may include a negative charge generation layer nCGL (see Fig.14 ) and the positive charge generation layer pCGL (see Fig.14 ). The luminous efficiency of an organic light emitting diode as a tandem light emitting element having a plurality of light emitting layers can be further increased by a negative charge generation layer nCGL and a positive charge generation layer pCGL.

[0176] The negative charge generation layer nCGL may be an n-type charge generation layer. The negative charge generation layer nCGL may supply electrons. The negative charge generation layer nCGL may include a host and a dopant. The host may include an organic material. The dopant may include a metal material. The positive charge generation layer pCGL may be a p-type charge generation layer. The positive charge generation layer pCGL may supply holes. The positive charge generation layer pCGL may include a host and a dopant. The host may include an organic material. The dopant may include a metal material.

[0177] According to some embodiments, Fig.10 As shown in , a light-emitting element (e.g., an organic light-emitting diode) may include a first emission unit EU1 including a first light-emitting layer EL1 and a second emission unit EU2 including a second light-emitting layer EL2 stacked in sequence. The charge generation layer CGL may be positioned between the first emission unit EU1 and the second emission unit EU2. For example, a light-emitting element (e.g., an organic light-emitting diode) may include a pixel electrode 201, a first light-emitting layer EL1, a charge generation layer CGL, a second light-emitting layer EL2, and a common electrode 205 stacked in sequence. The first functional layer and the second functional layer may be positioned on the first light-emitting layer EL1 and below the first light-emitting layer EL1, respectively. The first functional layer and the second functional layer may be included below and above the second light-emitting layer EL2, respectively. The first light-emitting layer EL1 may be a blue light-emitting layer, and the second light-emitting layer EL2 may be a yellow light-emitting layer.

[0178] According to some embodiments, Fig.11 As shown in , a light emitting element (e.g., an organic light emitting diode) may include a first emission unit EU1 and a third emission unit EU3 including a first light emitting layer EL1, and a second emission unit EU2 including a second light emitting layer EL2. The first charge generation layer CGL1 may be positioned between the first emission unit EU1 and the second emission unit EU2, and the second charge generation layer CGL2 may be positioned between the second emission unit EU2 and the third emission unit EU3. For example, a light emitting element (e.g., an organic light emitting diode) may include a pixel electrode 201, a first light emitting layer EL1, a first charge generation layer CGL1, a second light emitting layer EL2, a second charge generation layer CGL2, a first light emitting layer EL1, and a common electrode 205 stacked in sequence. The first functional layer and the second functional layer may be positioned on the first light emitting layer EL1 and below the first light emitting layer EL1, respectively. The first functional layer and the second functional layer may be positioned on the second light emitting layer EL2 and below the second light emitting layer EL2, respectively. The first light emitting layer EL1 may be a blue light emitting layer, and the second light emitting layer EL2 may be a yellow light emitting layer.

[0179] According to some embodiments, in a light emitting element (e.g., an organic light emitting diode), in addition to the second light emitting layer EL2, the second emission unit EU2 may further include a third light emitting layer EL3 directly contacting the second light emitting layer EL2 below and / or above the second light emitting layer EL2 (see Fig.13 ) and / or the fourth light-emitting layer EL4 (see Fig.13 Here, direct contact may mean that no other layer is positioned between the second light-emitting layer EL2 and the third light-emitting layer EL3 and / or between the second light-emitting layer EL2 and the fourth light-emitting layer EL4. The third light-emitting layer EL3 may be a red light-emitting layer, and the fourth light-emitting layer EL4 may be a green light-emitting layer.

[0180] For example, Fig.12 As shown in , the light emitting element (e.g., an organic light emitting diode) may include a pixel electrode 201, a first light emitting layer EL1, a first charge generation layer CGL1, a third light emitting layer EL3, a second light emitting layer EL2, a second charge generation layer CGL2, a first light emitting layer EL1, and a common electrode 205 stacked in sequence. Optionally, as Fig.13 As shown in the figure, the light-emitting element (e.g., an organic light-emitting diode) may include a pixel electrode 201, a first light-emitting layer EL1, a first charge generation layer CGL1, a third light-emitting layer EL3, a second light-emitting layer EL2, a fourth light-emitting layer EL4, a second charge generation layer CGL2, a first light-emitting layer EL1 and a common electrode 205 stacked in sequence.

[0181] Fig.14 is a diagram showing some embodiments of the present invention. Fig.12 A cross-sectional view of an example of an organic light emitting diode, and Fig.15 is a diagram showing some embodiments of the present invention. Fig.13 A cross-sectional view of an example of an organic light emitting diode.

[0182] Reference Fig.14 , the light emitting element (e.g., an organic light emitting diode) may include a first emission unit EU1, a second emission unit EU2, and a third emission unit EU3 stacked in sequence. The first charge generation layer CGL1 may be positioned between the first emission unit EU1 and the second emission unit EU2, and the second charge generation layer CGL2 may be positioned between the second emission unit EU2 and the third emission unit EU3. The first charge generation layer CGL1 and the second charge generation layer CGL2 may each include a negative charge generation layer nCGL and a positive charge generation layer pCGL.

[0183] The first emission unit EU1 may include a blue light emitting layer BEML. The first emission unit EU1 may further include a hole injection layer HIL (see FIG. 1 ) between the pixel electrode 201 and the blue light emitting layer BEML. Fig.15 ) and hole transport layer HTL (see Fig.15 ). According to some embodiments, a p-doped layer may also be included between the hole injection layer HIL and the hole transport layer HTL. The p-doped layer may be formed by doping the hole injection layer HIL with a p-type doping material. According to some embodiments, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may also be included between the blue light emitting layer BEML and the hole transport layer HTL. The blue light auxiliary layer may increase the light emission efficiency of the blue light emitting layer BEML. The blue light auxiliary layer may increase the light emission efficiency of the blue light emitting layer BEML by adjusting the hole charge balance. The electron blocking layer may prevent or reduce electron injection into the hole transport layer HTL. The buffer layer may compensate for the resonance distance according to the wavelength of light emitted from the light emitting layer.

[0184] The second emission unit EU2 may include a yellow light emitting layer YEML and a red light emitting layer REML directly contacting the yellow light emitting layer YEML below the yellow light emitting layer YEML. The second emission unit EU2 may further include a hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red light emitting layer REML, and may further include an electron transport layer ETL between the yellow light emitting layer YEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0185] The third emission unit EU3 may include a blue light emitting layer BEML. The third emission unit EU3 may also include a hole transport layer HTL between the positive charge generation layer pCGL of the second charge generation layer CGL2 and the blue light emitting layer BEML. The third emission unit EU3 may also include an electron transport layer ETL and an electron injection layer EIL between the blue light emitting layer BEML and the common electrode 205. The electron transport layer ETL may have a single layer or multiple layers. According to some embodiments, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may also be included between the blue light emitting layer BEML and the hole transport layer HTL. At least one of a hole blocking layer and a buffer layer may also be included between the blue light emitting layer BEML and the electron transport layer ETL. The hole blocking layer may prevent or reduce hole injection into the electron transport layer ETL.

[0186] Fig.15 The light emitting element (eg, organic light emitting diode) shown in Fig.14 The light emitting element (eg, organic light emitting diode) shown in FIG. 1 is different in the stacking structure of the second emission unit EU2, and the other configurations are the same. Fig.15, the second emission unit EU2 may include a yellow light emitting layer YEML, a red light emitting layer REML directly contacting the yellow light emitting layer YEML below the yellow light emitting layer YEML, and a green light emitting layer GEML directly contacting the yellow light emitting layer YEML above the yellow light emitting layer YEML. The second emission unit EU2 may further include a hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red light emitting layer REML, and may further include an electron transport layer ETL between the green light emitting layer GEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0187] Fig.16 is a cross-sectional view illustrating a structure of a pixel of the display device 1000 according to some embodiments.

[0188] Reference Fig.16 , the display device 1000 may include a plurality of pixels. The plurality of pixels may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a pixel electrode 201, a common electrode 205, and an intermediate layer 203. According to some embodiments, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel.

[0189] The pixel electrode 201 may be independently provided in each of the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 .

[0190] The intermediate layer 203 of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a first emission unit EU1 and a second emission unit EU2 stacked sequentially, and a charge generation layer CGL between the first emission unit EU1 and the second emission unit EU2. The charge generation layer CGL may include a negative charge generation layer nCGL and a positive charge generation layer pCGL. The charge generation layer CGL may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0191] The first emission unit EU1 of the first pixel PX1 may include a hole injection layer HIL, a hole transport layer HTL, a red light emitting layer REML, and an electron transport layer ETL sequentially stacked on the pixel electrode 201. The first emission unit EU1 of the second pixel PX2 may include a hole injection layer HIL, a hole transport layer HTL, a green light emitting layer GEML, and an electron transport layer ETL sequentially stacked on the pixel electrode 201. The first emission unit EU1 of the third pixel PX3 may include a hole injection layer HIL, a hole transport layer HTL, a blue light emitting layer BEML, and an electron transport layer ETL sequentially stacked on the pixel electrode 201. Each of the hole injection layer HIL, the hole transport layer HTL, and the electron transport layer ETL of the first emission unit EU1 may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0192] The second emission unit EU2 of the first pixel PX1 may include a hole transport layer HTL, an auxiliary layer AXL, a red light emitting layer REML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. The second emission unit EU2 of the second pixel PX2 may include a hole transport layer HTL, a green light emitting layer GEML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. The second emission unit EU2 of the third pixel PX3 may include a hole transport layer HTL, a blue light emitting layer BEML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. Each of the hole transport layer HTL and the electron transport layer ETL of the second emission unit EU2 may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3. According to some embodiments, at least one of a hole blocking layer and a buffer layer may also be included between the light emitting layer and the electron transport layer ETL in the second emission unit EU2 of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0193] The thickness H1 of the red light emitting layer REML, the thickness H2 of the green light emitting layer GEML, and the thickness H3 of the blue light emitting layer BEML may be determined according to the resonance distance. The auxiliary layer AXL may be a layer added to adjust the resonance distance and may include a resonance auxiliary material. For example, the auxiliary layer AXL may include the same material as the hole transport layer HTL.

[0194] exist Fig.16 In the embodiment, the auxiliary layer AXL may be positioned only in the first pixel PX1, but the embodiments of the present disclosure are not limited thereto. For example, the auxiliary layer AXL may be positioned in at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3 to adjust the resonance distance of the at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0195] The display device 1000 may further include a capping layer 207 positioned outside the common electrode 205. The capping layer 207 may be used to relatively improve the luminous efficiency through the principle of constructive interference. Therefore, the light extraction efficiency of the light emitting element (e.g., organic light emitting diode) may be increased, so that the luminous efficiency of the light emitting element (e.g., organic light emitting diode) may be relatively improved.

[0196] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the disclosed embodiments without departing substantially from the spirit and scope of the embodiments disclosed herein. Therefore, the embodiments disclosed by the present invention are intended to be general and descriptive only, and not for the purpose of limitation.

Claims

1. A display device, wherein: The display device comprises: substrate; A first display layer, on a first surface of the substrate; a second display layer, on the second surface of the substrate; a first pixel of the first display layer; and a second pixel of the second display layer, The first pixel and the second pixel include different numbers of transistors.

2. The display device according to claim 1, wherein: The second pixel circuit of the second pixel includes a larger number of transistors than the number of transistors of the first pixel circuit of the first pixel.

3. The display device according to claim 2, wherein: The first pixel circuit includes five transistors, and The second pixel circuit includes eight transistors.

4. The display device according to claim 3, wherein: The first pixel circuit comprises: a first transistor including a gate electrode connected to the first node, and the first transistor is connected between the second node and a third node; a second transistor including a gate electrode connected to the first gate line, and the second transistor is connected between the data line and the first node; a third transistor including a gate electrode connected to a third gate line, and the third transistor is connected between a reference voltage line and the first node; a fourth transistor including a gate electrode connected to the second gate line, and the fourth transistor is connected between the third node and an initialization voltage line; and A fifth transistor includes a gate electrode connected to the emission line, and the fifth transistor is connected between the driving voltage line and the second node.

5. The display device according to claim 4, wherein: Each of the first to fifth transistors includes an oxide semiconductor material.

6. The display device according to claim 4, wherein: The first to fifth transistors are n-type transistors.

7. The display device according to claim 4, wherein: The second transistor further includes a counter gate electrode connected to the first gate line, The third transistor further includes a counter gate electrode connected to the third gate line, and The fourth transistor also includes a counter gate electrode connected to the second gate line.

8. The display device according to claim 4, wherein: The first pixel circuit further includes: A first capacitor connected between the first node and the third node; and The second capacitor is connected between the driving voltage line and the third node.

9. The display device according to claim 3, wherein: The second pixel circuit comprises: a first transistor including a gate electrode connected to a third node, and the first transistor is connected between the first node and the second node; a second transistor including a gate electrode connected to the first gate line, and the second transistor is connected between the data line and the first node; a third transistor including a gate electrode connected to the second gate line, and the third transistor is connected between the third node and the second node; a fourth transistor including a gate electrode connected to a third gate line, and the fourth transistor is connected between the third node and a first initialization voltage line; a fifth transistor including a gate electrode connected to the emission line, and the fifth transistor is connected between the driving voltage line and the first node; a sixth transistor including a gate electrode connected to the emitter line, and the sixth transistor is connected between the second node and a fourth node; a seventh transistor including a gate electrode connected to a fourth gate line, and the seventh transistor is connected between the fourth node and a second initialization voltage line; and An eighth transistor includes a gate electrode connected to the fourth gate line, and the eighth transistor is connected between a bias voltage line and the first node.

10. The display device according to claim 9, wherein: The first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor each include a silicon-based semiconductor material, and The third transistor and the fourth transistor each include an oxide semiconductor material.

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