Display panel and display device

Abstract

The invention relates to a display panel and a display device. The display panel includes: a base layer including: a boundary region extending in a first direction; a first pixel region adjacent to the boundary region in the second direction; and a second pixel region spaced apart from the first pixel region, and a boundary region interposed between the first pixel region and the second pixel region, a plurality of lower insulating layers over the base layer and defining valley holes corresponding to the boundary regions; a first conductive pattern including a portion inside the valley hole; a first organic layer including a portion over the plurality of lower insulating layers and a remaining portion covering the first conductive pattern and filling the valley hole; a plurality of pixel circuits overlapping the first pixel region and the second pixel region, respectively; a plurality of light emitting elements over the first organic layer, overlapping the first pixel region and the second pixel region, respectively, and electrically connected to the plurality of pixel circuits, respectively; and a second conductive pattern over the first organic layer and including a portion overlapping the boundary region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0144352 filed in the Korean Intellectual Property Office on October 26, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure herein relates to a display panel and a display device whose shape can be changed. Background Art

[0004] A multimedia electronic device such as a television, a smart phone, a tablet computer, a navigation system or a game console may be provided with a display device for displaying an image. The display device generates an image and may be provided with a display panel for supplying the generated image to a user. The display panel may include a plurality of pixels for generating an image and a driver for driving the pixels.

[0005] With recent technological developments, flexible display devices including flexible display panels are being developed. For example, various flexible display devices that are deformable, foldable, or rollable into a curved form are being developed. Flexible display devices whose shapes are variously changed can be more portable and can improve user convenience.

[0006] However, the flexible display panel may be easily affected by external impact, and some transistors of the flexible display panel may be damaged by the external impact or stress caused by folding, so that pixels of the flexible display panel may not operate normally. Summary of the invention

[0007] The present disclosure provides a display panel having improved impact resistance and reliability.

[0008] One or more embodiments of the present disclosure provide a display panel, which includes: a base layer, the base layer including: a boundary area extending in a first direction; a first pixel area adjacent to the boundary area in a second direction intersecting the first direction; and a second pixel area spaced apart from the first pixel area, with the boundary area between the first pixel area and the second pixel area; a plurality of lower insulating layers located above the base layer, and the plurality of lower insulating layers defining valleys corresponding to the boundary area; a first conductive pattern including a portion located inside the valleys; a first organic layer including a portion located above the plurality of lower insulating layers, and the first organic layer also including a remaining portion covering the first conductive pattern and filling the valleys; a plurality of pixel circuits overlapping the first pixel area and the second pixel area, respectively; a plurality of light-emitting elements located above the first organic layer, the plurality of light-emitting elements overlapping the first pixel area and the second pixel area, respectively, and the plurality of light-emitting elements being electrically connected to the plurality of pixel circuits, respectively; and a second conductive pattern located above the first organic layer, and the second conductive pattern including a portion overlapping the boundary area.

[0009] The plurality of pixel circuits may include: a first pixel transistor overlapping the first pixel region; and a second pixel transistor overlapping the second pixel region.

[0010] The second conductive pattern may electrically connect the first pixel transistor and the second pixel transistor.

[0011] The first pixel transistor may include: a first semiconductor pattern, the first semiconductor pattern including a first source region, a first drain region and a first channel region between the first source region and the first drain region, wherein the second pixel transistor includes: a second semiconductor pattern, the second semiconductor pattern including a second source region, a second drain region and a second channel region between the second source region and the second drain region, wherein one end of the second conductive pattern is electrically connected to the first source region or the first drain region, and wherein the other end of the second conductive pattern is electrically connected to the second source region or the second drain region.

[0012] Each of the plurality of pixel circuits may further include: a first connection electrode electrically connected to the first source region or the first drain region, wherein the first conductive pattern and the first connection electrode are located at the same layer, and the first conductive pattern and the first connection electrode include the same material.

[0013] Each of the plurality of pixel circuits may further include: a second connection electrode electrically connected to the first connection electrode, wherein the second conductive pattern and the second connection electrode are located at the same layer, and the second conductive pattern and the second connection electrode include the same material.

[0014] The first conductive pattern may contact an inner side surface of the valley hole.

[0015] The valley holes may penetrate at least some of the plurality of lower insulating layers, wherein an upper surface of one of the plurality of lower insulating layers of the base layer is defined as a lower surface of the valley hole covered by the first conductive pattern.

[0016] The first conductive pattern may be configured to transmit a power supply voltage.

[0017] The display panel may further include: a first barrier pattern located under the first conductive pattern, and the first barrier pattern overlaps a portion of the first conductive pattern in a plane.

[0018] The display panel may further include: a second blocking pattern overlapping a portion of the plurality of pixel circuits on a plane, wherein the first blocking pattern is located at a same layer as the second blocking pattern and includes a same material as the second blocking pattern.

[0019] A portion of the first conductive pattern may contact an upper surface of the first barrier pattern.

[0020] The first pixel region may include a (1-1)th pixel region and a (1-2)th pixel region adjacent to each other in the first direction, wherein the boundary region overlaps the (1-1)th pixel region and the (1-2)th pixel region in the second direction.

[0021] The boundary region may not be between the (1-1)th pixel region and the (1-2)th pixel region.

[0022] The first conductive pattern may completely cover the valley hole.

[0023] The first organic layer may include: a layer portion located over the plurality of lower insulating layers; and a filling portion located in the valley hole, and the filling portion has an integral shape with the layer portion.

[0024] The plurality of lower insulating layers may include a first reference insulating layer located below the first organic layer and a second reference insulating layer located below the first reference insulating layer, and wherein the valley holes penetrate the first reference insulating layer and the second reference insulating layer.

[0025] The display panel may further include: a second organic layer located above the first organic layer and covering the second conductive pattern, wherein the plurality of light emitting elements are located above the second organic layer.

[0026] In one or more embodiments of the present disclosure, a display panel includes: a base layer, the base layer including: a boundary area extending in a first direction; a first pixel area adjacent to the boundary area in a second direction intersecting the first direction; and a second pixel area spaced apart from the first pixel area, and the boundary area is between the first pixel area and the second pixel area; a plurality of lower insulating layers located above the base layer, and the plurality of lower insulating layers define valley holes corresponding to the boundary areas; a first conductive pattern including a portion located inside the valley holes; a first organic layer including a portion located above the plurality of lower insulating layers, and the first organic layer also includes a remaining portion filling the valley holes and covering the first conductive pattern; a plurality of pixel circuits overlapping the first pixel area and the second pixel area, respectively; and a plurality of light-emitting elements located above the first organic layer, the plurality of light-emitting elements overlapping the first pixel area and the second pixel area, respectively, and the plurality of light-emitting elements being electrically connected to the plurality of pixel circuits, respectively, wherein the first conductive pattern contacts the inner surface of the valley holes and is configured to transmit a power supply voltage.

[0027] In one or more embodiments of the present disclosure, a display device (which includes a first non-folding area, a folding area, and a second non-folding area arranged sequentially along a first direction) also includes: a window; a display panel located below the window; and a housing located below the display panel to accommodate the display panel, wherein the display panel includes: a base layer, the base layer including: a boundary area extending in a first direction; a first pixel area adjacent to the boundary area in a second direction intersecting the first direction; and a second pixel area spaced apart from the first pixel area, and the boundary area is between the first pixel area and the second pixel area; a plurality of lower insulating layers located above the base layer, and the plurality of lower insulating layers define valley holes corresponding to the boundary areas; a first conductive pattern including a portion located inside the valley holes; a first organic layer including a portion located above the plurality of lower insulating layers, and the first organic layer also includes a remaining portion filling the valley holes and covering the first conductive pattern; a plurality of pixel circuits overlapping the first pixel area and the second pixel area, respectively; and a plurality of light-emitting elements located above the first organic layer, the plurality of light-emitting elements overlapping the first pixel area and the second pixel area, respectively, and the plurality of light-emitting elements being electrically connected to the plurality of pixel circuits, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain aspects of the present disclosure. In the drawings:

[0029] Figure 1A is a perspective view of a display device according to one or more embodiments of the present disclosure;

[0030] Figure 1B and Figure 1C It is shown Figure 1AA perspective view of a folded state of the display device shown in ;

[0031] Figure 2 is an exploded perspective view of a display device according to one or more embodiments of the present disclosure;

[0032] Figure 3 is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure;

[0033] Figure 4 is a plan view of a display panel according to one or more embodiments of the present disclosure;

[0034] Figure 5 is a diagram showing an equivalent circuit of a pixel according to one or more embodiments of the present disclosure;

[0035] Figure 6 is an enlarged plan view of a display panel according to one or more embodiments of the present disclosure;

[0036] Figure 7 is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure;

[0037] FIG. 8A to FIG. 8G is a plan view according to a stacking order of a pattern of pixels according to one or more embodiments of the present disclosure;

[0038] Fig. 9 is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure;

[0039] Fig. 10A are plan views of some configurations of display panels according to one or more embodiments of the present disclosure; and

[0040] Fig. 10B and Fig. 10C is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0041] By referring to the detailed description and drawings of the embodiments, aspects of some embodiments of the present disclosure and methods for realizing these aspects can be more easily understood. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey aspects of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are redundant, irrelevant or unrelated to the description of the embodiments, or are not necessary for a person of ordinary skill in the art to fully understand aspects of the present disclosure can be omitted. Unless otherwise stated, throughout the drawings and written descriptions, the same reference numerals, reference numerals or combinations thereof represent the same elements, and therefore, their repeated descriptions can be omitted.

[0042] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. When describing an embodiment, "can", "may" or "may not" are used to correspond to one or more embodiments of the present disclosure. The present disclosure covers all modifications, equivalents and alternatives within the scope of the thought and technology of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various interlocks and drives are technically possible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0043] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to make the boundaries between adjacent elements clear. As such, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of an element.

[0044] Various embodiments are described herein with reference to cross-sectional views as schematic illustrations of embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are expected to occur. In addition, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the illustrated shapes of elements, layers, or regions, but will include deviations in shapes, for example, caused by manufacturing.

[0045] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0046] For ease of explanation, spatially relative terms such as "under", "below", "lower", "under", "below", "above", "on", and "upper" may be used herein to describe the relationship of an element or feature to another element (or elements) or another feature (or features) as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatially relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, the elements described as "under", "under", or "below" other elements or features will then be oriented to be "above" the other elements or features. Therefore, the example terms "under" and "under" can include both "above" and "below". The device can be oriented otherwise (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used in this article should be interpreted accordingly. Similarly, when a first component is described as being disposed “on” a second component, this means that the first component is disposed on the upper side or the lower side of the second component, and is not limited to the upper side of the second component based on the gravity direction.

[0047] In addition, the phrase "in a plan view" means when the target portion is observed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section taken by vertically cutting the target portion is observed from the side. The term "overlap" or "overlapping with..." means that the first object can be above or below or on one side of the second object, and vice versa. In addition, as will be appreciated and understood by those of ordinary skill in the art, the term "overlap" may include stacking, facing or facing, extending on..., covering or partially covering or any other suitable term. As will be appreciated and understood by those of ordinary skill in the art, the expression "non-overlapping" may include meanings such as "spaced apart from..." or "separated from..." or "deviation from..." and any other suitable equivalents. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object may be understood as being indirectly opposite to each other despite still facing each other.

[0048] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on" another element, layer, region, or component, "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, the element, layer, region, or component may be directly formed on, on, connected to, or coupled to the other element, layer, region, or component, or indirectly formed on, on, indirectly connected to, or coupled to the other element, layer, region, or component, such that there may be one or more intervening elements, layers, regions, or components. Furthermore, this may be collectively referred to as direct or indirect coupling or connection and integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, the layer, region, or component may be directly electrically connected or coupled to the other layer, region, or component, or there may be one or more intervening layers, regions, or components. The one or more intervening components may include switches, resistors, and / or capacitors, among others. When describing the embodiments, unless explicitly described as directly connected, the expression of connection indicates electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or coupled to another component, or is directly on another component without intervening components.

[0049] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "below" another part, this includes not only the case where the part is "directly below" the other part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between components such as "between...", "immediately between..." or "adjacent to..." and "directly adjacent to..." can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or two layers, the element or layer can be the only element or layer between the two elements or the two layers, or one or more intermediate elements or intermediate layers may also be present.

[0050] For the purposes of this disclosure, when expressions such as "at least one of..." or "any one of..." or "one or more of..." precede or follow a list of elements, the entire list of elements is modified without modifying the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ, or any variation thereof. Similarly, the expression "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, expressions such as “at least one of,” “a plurality of,” “one of,” and other prepositional phrases, when preceding or following a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0051] It will be understood that, although the terms "first", "second", "third", etc. can be used to describe various elements, components, areas, layers and / or parts in this article, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish an element, member, component, area, region, layer, part or part from another element, member, component, area, region, layer, part or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first area, first layer or first part described below can be referred to as the second element, second component, second area, second layer or second part. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used to distinguish between different categories or different groups of elements in this article. For simplicity, the terms "first", "second", etc. can respectively represent "first class (or first group)", "second class (or second group)", etc.

[0052] In the example, the x-axis (first direction DR1), the y-axis (second direction DR2), and / or the z-axis (third direction DR3) are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis (first direction DR1), the y-axis (second direction DR2), and the z-axis (third direction DR3) can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0053] The terms used in this article are for the purpose of describing the embodiments only and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a" and "one (kind / person)" are also intended to include the plural forms, and the plural forms are also intended to include the singular forms. It will also be understood that when the terms "comprises / comprising", "have / having" and "includes / including" are used in this specification, the stated features, wholes, steps, operations, elements and / or components are indicated, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups are not excluded.

[0054] As used herein, the terms "substantially", "approximately", "approximately" and similar terms are used as terms of approximation rather than terms of degree, and are intended to illustrate the inherent deviations in measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / -5% of the corresponding value. Taking into account the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "approximately" or "approximately" as used herein include the stated values ​​and mean within an acceptable deviation range of a particular value determined by a person of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10% or ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0056] Figure 1A is a perspective view of a display device DD according to one or more embodiments of the present disclosure. Figure 1B and Figure 1C It is shown Figure 1A 0 is a perspective view of a folded state of the display device DD shown in FIG.

[0057] The display device DD may be activated in response to an electrical signal and may display an image. The display device DD may include various embodiments. For example, the display device DD may be not only a large device such as a television or a billboard, but also a small or medium-sized device such as a monitor, a smart phone, a tablet computer, a navigation system, or a game console. These embodiments of the display device DD are examples and are not limited to any one, as long as they do not deviate from the concept of the present disclosure. A smart phone is shown as an example of a display device DD.

[0058] Reference Figure 1A , the display device DD may have a rectangular shape on a plane having short sides extending in a first direction DR1 and long sides extending in a second direction DR2 crossing the first direction DR1. However, the present disclosure is not limited thereto, and the display device DD may have various shapes on a plane, such as a circle or a polygon other than a rectangle.

[0059] The display device DD may be flexible. The wording "flexible" may indicate a bendable property and may include all ranges from a fully foldable structure to a bendable structure at the level of several nanometers. For example, the flexible display device DD may include a bendable display device, a rollable display device, a slidable display device, or a foldable display device. A foldable display device is shown as an example of a flexible display device DD.

[0060] like Figure 1A As shown in FIG. 1 , the display device DD in the unfolded state may display an image in a third direction DR3 through a display surface defined by the first direction DR1 and the second direction DR2. The third direction DR3 may be defined as a direction substantially perpendicular to the surface defined by the first direction DR1 and the second direction DR2.

[0061] The front surface (or upper surface) and the rear surface (or lower surface) of each member constituting the display device DD may be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be substantially parallel to the third direction DR3. The distance between the front surface and the rear surface and defined along the third direction DR3 may correspond to the thickness of the member (or unit).

[0062] In the present specification, the wording "on a plane" may be defined as a state seen in the third direction DR3. In the present specification, the wording "on a cross section" may be defined as a state seen in the first direction DR1 or the second direction DR2. Meanwhile, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and may be changed to other directions.

[0063] The front surface of the display device DD may be divided into a display area DA and a non-display area NDA. The display device DD may display an image through the display area DA, and a user may view the image through the display area DA. The image may include a static image and a dynamic image. Figure 1A An icon and a clock window are shown as examples of images.

[0064] The non-display area NDA may not display an image. The non-display area NDA may be adjacent to the display area DA. For example, the non-display area NDA may surround the display area DA on a plane / in a plan view, but the present disclosure is not limited thereto. The non-display area NDA may be adjacent to only one side of the display area DA, or may be positioned in a side surface of the display device DD instead of a front surface. The non-display area NDA may correspond to an area in which a printed layer having a color (e.g., a predetermined color) is formed, and may define a boundary of the display device DD.

[0065] The display area DA may include a sensing area TA. The sensing area TA may be a partial area of ​​the display area DA. The sensing area TA may have a greater transmittance than any other area of ​​the display area DA. Hereinafter, other areas of the display area DA except the sensing area TA may be defined as a normal display area.

[0066] An optical signal such as visible light or infrared light may pass through the sensing area TA. The electronic device may capture an external image through the visible light penetrating the sensing area TA, or may determine whether an external object is nearby using infrared light. Figure 1A One sensing area TA is shown, but the present disclosure is not limited thereto, and the sensing area TA may be provided in plural.

[0067] The display device DD may include a folding area FA and non-folding areas NFA1 and NFA2. The non-folding areas NFA1 and NFA2 may include a first non-folding area NFA1 and a second non-folding area NFA2. The non-folding areas NFA1 and NFA2 may be arranged along a first direction DR1 with the folding area FA interposed between the non-folding areas NFA1 and NFA2.

[0068] According to the folding operation, the folding area FA may be a flat area or an area curved with a certain curvature (eg, a predetermined curvature). Figure 1A As shown in , when the display device DD is in the unfolded state, the folding area FA may be flat. The non-folding areas NFA1 and NFA2 may be areas that remain flat in both the folded state and the unfolded state.

[0069] The display device DD can be folded about a folding axis extending in one direction. Figure 1B and Figure 1C, the folding axis FX may extend in a second direction DR2 parallel to the long side of the display device DD. However, the extending direction of the folding axis FX is not limited thereto, and the folding axis FX may extend in a direction parallel to the short side of the display device DD. In this case, the non-folding area may be arranged in the second direction DR2 with the folding area interposed therebetween.

[0070] The display device DD can be folded inwardly or outwardly with respect to the folding axis FX. The display device DD can be folded into one of the states of the inward folding and the outward folding, or can be changed from the inward folding to the outward folding. Figure 1B The display device DD is shown in an inner folded state, and Figure 1C The display device DD is shown in a completely folded-out state.

[0071] Reference Figure 1B , the folding axis FX according to one or more embodiments may be defined as facing the front surface of the display device DD. The display surface corresponding to the folding area FA in the inner folding state may be folded facing the folding axis FX, and may form a concave curved surface. The display surfaces corresponding to the first non-folding area NFA1 and the second non-folding area NFA2 of the display device DD in the inner folding state may overlap each other facing each other. The front surface of the display device DD in the inner folding state may not be exposed to the outside.

[0072] Reference Figure 1C , according to one or more embodiments, the folding axis FX may be defined as a rear surface facing the display device DD. The display surface corresponding to the folding area FA in the external folding state may be folded back to back with the folding axis FX, and a convex curved surface may be formed. In the external folding state, the display surface corresponding to the first non-folding area NFA1 and the second non-folding area NFA2 of the display device DD may be exposed outwardly. In the external folding state, the display surfaces corresponding to the non-folding areas NFA1 and NFA2 may overlap with each other on a plane, and images may be displayed in directions opposite to each other. The display area DA of the display device DD in the external folding state may be exposed to the outside to display an image, and a user may view the image in the external folding state.

[0073] The display device DD is shown as being folded inwardly or outwardly with respect to one folding axis FX, but the number of folding axes FX defined in the display device DD is not limited thereto, and the display device DD may be folded with respect to a plurality of folding axes. The folding operation of the display device DD is not limited to the illustrated embodiment, and may be designed in various forms.

[0074] Figure 2 is an exploded perspective view of a display device DD according to one or more embodiments of the present disclosure.

[0075] like Figure 2As shown in , the display device DD may include a window WM, a display panel DP, an electronic module EM', an electronic optical module ELM, a power module PSM and a housing HM. In one or more embodiments, the display device DD may further include a mechanical structure for controlling a folding operation.

[0076] The display panel DP generates an image and detects external input. The window WM supplies the front surface of the display device DD. For example, the window WM may include a thin film glass substrate. The window WM may include a frame pattern defining the non-display area NDA. The window WM may also include a functional layer such as a protective layer, a hard coating layer, or an anti-fingerprint layer.

[0077] Figure 2 Only the display panel DP positioned below the window WM is shown, but the display device DD may also include a plurality of configurations positioned on the display panel DP. For example, the display device DD may also include an input sensing layer or an anti-reflection layer.

[0078] The display panel DP is not particularly limited and may be a light-emitting display panel such as an organic light-emitting display panel or a quantum dot light-emitting display panel. The display panel DP may include ultra-small light-emitting elements such as micro light-emitting diodes (LEDs) or nano-LEDs.

[0079] The display panel DP includes a display area DA (see Figure 1A ) and non-display area NDA (see Figure 1A ) corresponds to a display area D-DA and a non-display area D-NDA. In this specification, the wording "a region / a portion corresponds to another region / another portion" may mean "the region / a portion overlaps the another region / another portion", and is not limited to two regions / two portions having the same area.

[0080] The display panel DP may include Figure 1A The sensing area D-TA corresponds to the sensing area TA in the display area. The sensing area D-TA may have a lower resolution than the display area D-DA.

[0081] like Figure 2 As shown in , the driving chip DIC may be positioned on the non-display area D-NDA of the display panel DP. The flexible circuit board FCB may be combined with the non-display area D-NDA of the display panel DP. The flexible circuit board FCB may be connected to the main circuit board. The main circuit board may be an electronic component constituting the electronic module EM'.

[0082] The driving chip DIC may include a driver for driving the pixels of the display panel DP, for example, a data driver DDV (see Figure 4 ). Figure 2A structure in which the driving chip DIC is mounted on the display panel DP is shown, but the present disclosure is not limited thereto. For example, the driving chip DIC may be mounted on a flexible circuit board FCB.

[0083] The power supply module PSM may supply power suitable for overall operations of the display device DD. The power supply module PSM may include a general battery unit.

[0084] The electronic optical module ELM may be an electronic component that outputs or receives an optical signal. The electronic optical module ELM may include a camera module and / or a proximity sensor. The camera module captures an external image through the sensing area D-TA.

[0085] Figure 2 The housing HM shown in the figure can be combined with a display device DD (such as a window WM) to accommodate the above-mentioned other modules. The housing HM is shown as including a first housing HM1 and a second housing HM2 separated from each other, but the present disclosure is not limited to this. In one or more embodiments, the display device DD may further include a hinge structure for connecting the first housing HM1 and the second housing HM2.

[0086] Figure 3 is a cross-sectional view of a display panel DP according to one or more embodiments of the present disclosure.

[0087] The display panel DP may be included in the display device DD (see Figure 1A ). The display panel DP according to one or more embodiments may be a light-emitting display panel, but is not limited thereto. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0088] Reference Figure 3 , the display panel DP may include a base layer SUB, a circuit element layer DP-CL, a display element layer DP-OLED and an encapsulation layer TFE.

[0089] The substrate layer SUB may provide a substrate surface on which the circuit element layer DP-CL is positioned. The substrate layer SUB may include a display area D-DA and a non-display area D-NDA. The display area D-DA and the non-display area D-NDA of the substrate layer SUB may be respectively connected to the display device DD (see Figure 1A ) of the display area DA (see Figure 1A ) and non-display area NDA (see Figure 1A )correspond.

[0090] The base layer SUB may include a flexible polymer material. For example, the base layer SUB may include at least one of acrylic resin, methacrylate resin, polyisoprene resin, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyamide resin, perylene resin, and polyimide resin. However, the material of the base layer SUB is not limited to the above examples.

[0091] The circuit element layer DP-CL may be positioned on the base layer SUB (as used herein, "positioned on" may mean "positioned above"). The circuit element layer DP-CL may include at least one insulating layer, a pixel circuit, a signal line, and a signal pad, which will be described later. The circuit element layer DP-CL may be formed by patterning the insulating layer, the semiconductor layer, and the conductive layer by photolithography after forming the insulating layer, the semiconductor layer, and the conductive layer on the base layer SUB by coating or deposition.

[0092] The display element layer DP-OLED may be positioned on the circuit element layer DP-CL. The display element layer DP-OLED may include a light emitting element positioned to overlap the display area D-DA. The light emitting element of the display element layer DP-OLED may be electrically connected to the pixel circuit of the circuit element layer DP-CL, and may emit light through the display area D-DA in response to a drive signal.

[0093] The encapsulation layer TFE may be positioned on the display element layer DP-OLED to seal the light emitting element. The encapsulation layer TFE may include a plurality of thin films. The thin films of the encapsulation layer TFE may improve the optical efficiency of the light emitting element, or may protect the light emitting element.

[0094] Figure 4 is a plan view of a display panel DP according to one or more embodiments of the present disclosure.

[0095] Reference Figure 4 The display panel DP may include pixels PX positioned in the display area D-DA and signal lines electrically connected to the pixels PX. The display panel DP may include a scan driver SDV, a data driver DDV, a light emitting driver EDV, and a signal pad PD positioned in the non-display area D-NDA.

[0096] Each of the pixels PX may include a light emitting element and a pixel circuit electrically connected to the light emitting element and including a transistor (eg, a switching transistor and a driving transistor, etc.) and a capacitor. Each of the pixels PX may emit light in response to an electrical signal applied thereto.

[0097] The signal lines may include scan lines SL1 to SLm, data lines DL1 to DLn, emission lines EL1 to ELm, a first control line CSL1, a second control line CSL2, and a power line PL.

[0098] Each of the pixels PX may be connected to a corresponding scan line among the scan lines SL1 to SLm, a corresponding data line among the data lines DL1 to DLn, and a corresponding emission line among the emission lines EL1 to ELm. Meanwhile, the display panel DP may be provided with other types of signal lines according to the configuration of the pixel circuit of the pixel PX.

[0099] The scan driver SDV and the light emitting driver EDV may each be positioned in the non-display area D-NDA adjacent to the long sides of the display panel DP. The data driver DDV may be positioned adjacent to the lower end of the display panel DP on a plane.

[0100] The scan lines SL1 to SLm may extend in a first direction DR1 to be electrically connected to a scan driver SDV. The emission lines EL1 to ELm may extend in the first direction DR1 to be electrically connected to a light emitting driver EDV. The scan lines SL1 to SLm and the emission lines EL1 to ELm may be arranged along a second direction DR2. The data lines DL1 to DLn may cross the scan lines SL1 to SLm and the emission lines EL1 to ELm on a plane. The data lines DL1 to DLn may extend in a second direction DR2 to be electrically connected to a data driver DDV.

[0101] The power line PL may be electrically connected to the pixel PX to supply the voltage applied to the power line PL to the pixel PX. The power line PL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion of the power line PL extending in the first direction DR1 may extend in the display area D-DA to be connected to the pixel PX, and the portion of the power line PL extending in the second direction DR2 may extend in the non-display area D-NDA to be connected to the signal pad PD. The portion of the power line PL extending in the first direction DR1 and the portion of the power line PL extending in the second direction DR2 may be connected on different layers through a contact hole, or may have an integral shape on the same layer.

[0102] The first control line CSL1 may be electrically connected to the scan driver SDV. The second control line CSL2 may be electrically connected to the light emitting driver EDV.

[0103] The signal pads PD may be arranged along the first direction DR1. The signal pads PD may be electrically connected to a circuit board, and the circuit board may include a timing controller for controlling operations of the scan driver SDV, the data driver DDV, and the emission driver EDV, and a voltage generator for generating a voltage suitable for driving the display panel DP.

[0104] The signal pads PD may be connected to corresponding signal lines, respectively. For example, the first control line CSL1, the second control line CSL2, the power line PL, and the data lines DL1 to DLn may be connected to the signal pads PD, respectively. The data lines DL1 to DLn may be electrically connected to corresponding signal pads PD, respectively, through a data driver DDV.

[0105] The scan driver SDV may generate a scan signal in response to a scan control signal. The scan signal may be applied to the pixel PX through the scan lines SL1 to SLm. The data driver DDV may generate a data voltage corresponding to the image signal in response to the data control signal. The data voltage may be applied to the pixel PX through the data lines DL1 to DLn. The light emitting driver EDV may generate a light emitting signal in response to a light emitting control signal. The light emitting signal may be applied to the pixel PX through the light emitting lines EL1 to ELm.

[0106] The pixel PX may be supplied with a data voltage in response to the scan signal. The pixel PX may display an image by emitting light having a brightness corresponding to the data voltage in response to the light emission signal. The light emission time of the pixel PX may be controlled by the light emission signal. As a result, the display panel DP may output an image in the display area D-DA through the pixel PX.

[0107] Figure 5 is a diagram showing an equivalent circuit of a pixel PXij according to one or more embodiments of the present disclosure. Figure 5 The pixel PXij connected to the i-th scan line SLi, the i-th emission line ELi (hereinafter, referred to as emission line ELi), and the j-th data line DLj (hereinafter, referred to as data line DLj) is shown. Here, i and j are natural numbers greater than 0.

[0108] Reference Figure 5 , the pixel PXij may include a light emitting element OLED and a pixel circuit PDC electrically connected to the light emitting element OLED. The pixel circuit PDC may include transistors T1, T2, T3, T4, T5, T6, and T7 and a capacitor CAP. The transistors T1, T2, T3, T4, T5, T6, and T7 and the capacitor CAP may control the amount of current flowing through the light emitting element OLED, and the light emitting element OLED may generate light having a brightness (e.g., a predetermined brightness) according to the amount of current supplied to the light emitting element OLED.

[0109] The i-th scan line SLi may include an i-th first scan line GWi, an i-th second scan line GCi, and an i-th third scan line GIi (hereinafter, referred to as the first scan line GWi, the second scan line GCi, and the third scan line GIi, respectively). The first scan line GWi receiving the i-th write scan signal GWSi (hereinafter, referred to as the write scan signal GWSi) may be defined as the write scan line GWi (hereinafter, referred to as the i-th write scan line GWi). The second scan line GCi receiving the i-th compensation scan signal GCSi (hereinafter, referred to as the compensation scan signal GCSi) may be defined as the compensation scan line GCi. The third scan line GIi receiving the i-th initialization scan signal GISi (hereinafter, referred to as the initialization scan signal GISi) may be defined as the initialization scan line GIi.

[0110] The transistors T1, T2, T3, T4, T5, T6, and T7 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may each include a source electrode, a drain electrode, and a gate electrode. Hereinafter, the source electrode may be referred to as a source, the drain electrode may be referred to as a drain, and the gate electrode may be referred to as a gate.

[0111] Meanwhile, in this specification, the wording “a transistor and a signal line, or a transistor and another transistor are electrically connected” means “an electrode of a transistor and a signal line, or an electrode of a transistor and an electrode of another transistor have an integral shape, or are connected through a connecting electrode”.

[0112] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may have an oxide semiconductor layer or a low temperature polycrystalline silicon (LTPS) semiconductor layer. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be N-type transistors or P-type transistors. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be P-channel metal oxide semiconductor (PMOS) transistors having an LTPS semiconductor layer, and the third transistor T3 and the fourth transistor T4 may be N-channel metal oxide semiconductor (NMOS) transistors having an oxide semiconductor layer. However, the embodiments of the transistors T1, T2, T3, T4, T5, T6 and T7 are not limited thereto. In addition, a pixel circuit PDC including seven transistors T1, T2, T3, T4, T5, T6 and T7 is shown, but the number of transistors included in the pixel circuit PDC is not limited thereto.

[0113] The light emitting element OLED may be defined as an organic light emitting element. The light emitting element OLED may include a first electrode AE ​​and a second electrode CE. For example, the first electrode AE ​​may be an anode, and the second electrode CE may be a cathode. The first electrode AE ​​of the light emitting element OLED may be electrically connected to a first voltage line VL1 receiving a first driving voltage ELVDD. The second electrode CE of the light emitting element OLED may be electrically connected to a second voltage line VL2 receiving a second driving voltage ELVSS.

[0114] The first transistor T1 may be electrically connected to a first voltage line VL1 receiving a first driving voltage ELVDD and the light emitting element OLED. The first transistor T1 may include a source connected to a second node ND2, a drain connected to a third node ND3, and a gate connected to a first node ND1. The first transistor T1 may be turned on by a voltage of the first node ND1. According to a switching operation of the second transistor T2, the first transistor T1 may receive a data voltage Vd transmitted by a data line DLj to supply a driving current Id to the light emitting element OLED. The first transistor T1 may be defined as a driving transistor.

[0115] The second transistor T2 may be electrically connected to the data line DLj and the first transistor T1. The second transistor T2 may include a source connected to the data line DLj, a drain connected to the second node ND2, and a gate connected to the first scan line GWi. The first transistor T1 and the second transistor T2 may be connected through the second node ND2. The second transistor T2 may be turned on by the write scan signal GWSi applied through the first scan line GWi. The turned-on second transistor T2 may transfer the data voltage Vd applied to the data line DLj to the source of the first transistor T1. The second transistor T2 may be defined as a switching transistor.

[0116] The third transistor T3 may be electrically connected to the first transistor T1 and the fourth transistor T4. The third transistor T3 may include a source connected to the first node ND1, a drain connected to the third node ND3, and a gate connected to the second scan line GCi. The first transistor T1 and the third transistor T3 may be connected through the third node ND3. The third transistor T3 may be turned on by the compensation scan signal GCSi applied through the second scan line GCi. The turned-on third transistor T3 may be electrically connected to the gate of the first transistor T1 and the drain of the first transistor T1, thereby connecting the first transistor T1 in the form of a diode. The third transistor T3 may be defined as a compensation transistor.

[0117] The fourth transistor T4 may be electrically connected to the first initialization line VIL1 receiving the first initialization voltage Vint1 and the third transistor T3. The fourth transistor T4 may include a source connected to the first initialization line VIL1, a drain connected to the first node ND1, and a gate connected to the third scan line GIi. The fourth transistor T4 may be turned on by the initialization scan signal GISi applied through the third scan line GIi. The turned-on fourth transistor T4 may transmit the first initialization voltage Vint1 to the first node ND1, and may initialize the gate voltage of the first transistor T1. The fourth transistor T4 may be defined as an initialization transistor.

[0118] The fifth transistor T5 may electrically connect the first voltage line VL1 receiving the first driving voltage ELVDD and the first transistor T1. The fifth transistor T5 may include a source connected to the first voltage line VL1, a drain connected to the second node ND2, and a gate connected to the emission line ELi.

[0119] The sixth transistor T6 may electrically connect the first transistor T1 and the light emitting element OLED. The sixth transistor T6 may include a source connected to the third node ND3, a drain connected to the first electrode AE ​​of the light emitting element OLED through the fourth node ND4, and a gate connected to the light emitting line ELi.

[0120] The fifth transistor T5 and the sixth transistor T6 may be turned on by the light emitting signal ESi applied through the light emitting line ELi. The light emitting time of the light emitting element OLED may be controlled by the light emitting signal ESi. When the fifth transistor T5 and the sixth transistor T6 are turned on, a driving current Id according to a voltage difference between a gate voltage of the gate of the first transistor T1 and the first driving voltage ELVDD may be generated and may be supplied to the light emitting element OLED through the sixth transistor T6, so that the light emitting element OLED may emit light. The fifth transistor T5 and the sixth transistor T6 may be defined as light emitting control transistors.

[0121] The seventh transistor T7 may be electrically connected to the sixth transistor T6 and the second initialization line VIL2 receiving the second initialization voltage Vint2. The seventh transistor T7 may include a source connected to the fourth node ND4, a drain connected to the second initialization line VIL2, and a gate connected to the first scan line GWi-1 (hereinafter, referred to as the (i-1)th write scan line GWi-1). The gate of the seventh transistor T7 may be connected to the (i-1)th write scan line GWi-1 which is a write scan line before the i-th write scan line GWi. However, the present disclosure is not limited thereto, and the gate of the seventh transistor T7 may be electrically connected to a separate fourth scan line.

[0122] The seventh transistor T7 may be turned on by the (i-1)th write scan signal GWSi-1 applied through the first scan line GWi-1. The turned-on seventh transistor T7 may transmit the second initialization voltage Vint2 to the fourth node ND4. The second initialization voltage Vint2 may have the same level as the first initialization voltage Vint1, but the present disclosure is not limited thereto, and the second initialization voltage Vint2 may have a level different from that of the first initialization voltage Vint1. The seventh transistor T7 may be defined as an initialization transistor.

[0123] The seventh transistor T7 can improve the black expression capability of the pixel PXij. The driving current Id can partially flow out through the seventh transistor T7 as a bypass current. When a black image is displayed, a current that is reduced from the driving current Id by the amount of the bypass current flowing out through the seventh transistor T7 can be supplied to the light emitting element OLED to clearly express the black image. That is, an accurate black brightness image can be performed through the seventh transistor T7, thereby improving the display device DD (see Figure 1A )’s contrast.

[0124] The capacitor CAP may include a first electrode receiving the first driving voltage ELVDD and a second electrode connected to the first node ND1. Charge corresponding to the voltage difference between the first electrode and the second electrode may be stored in the capacitor CAP. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing in the first transistor T1 may be determined according to the voltage stored in the capacitor CAP.

[0125] at the same time, Figure 5 The configuration of the pixel circuit PDC shown in is an example, and the configuration of the pixel circuit PDC is not limited thereto and may be changed.

[0126] Figure 6 is a display panel DP according to one or more embodiments of the present disclosure (see Figure 2 ) is an enlarged plan view of the Figure 6 The display area D-DA of the display panel DP is partially and briefly shown.

[0127] Reference Figure 6 , the display area D-DA includes a plurality of pixel areas PA and a boundary area BA positioned between the plurality of pixel areas PA. The pixel area PA may include a plurality of pixel rows PXA-1 and PXA-2 extending in a first direction DR1, and the boundary area BA may be positioned between the pixel rows PXA-1 and PXA-2.

[0128] Figure 6 2. Two pixel rows PXA-1 and PXA-2 are shown in FIG. The first pixel row PXA-1 may include a first color pixel PX1, a second color pixel PX2, a third color pixel PX3, and another second color pixel PX2 arranged in a first direction DR1. The second pixel row PXA-2 may include a second color pixel PX2, a third color pixel PX3, another second color pixel PX2, and the first color pixel PX1. Figure 6 The four color pixels of the pixel rows PXA- 1 and PXA- 2 shown in may be repeatedly positioned along the first direction DR1 . Figure 6 The color pixels of the pixel rows PXA-1 and PXA-2 shown in the figure may be repeatedly positioned along the second direction DR2. Meanwhile, in the present specification, the first pixel row PXA-1 may be described as a "first pixel area", and the second pixel row PXA-2 may be described as a "second pixel area".

[0129] The pixel circuits PC1, PC2, and PC3 of the first color pixel PX1, the second color pixel PX2, and the third color pixel PX3 may be located in the plurality of pixel areas PA, respectively. Each of the pixel circuits PC1, PC2, and PC3 may be connected to a reference Figure 5 The pixel circuit PDC described is the same. Figure 6It is illustrated that each of the pixel circuits PC1 , PC2 , and PC3 is substantially the same as the pixel area PA, but the present disclosure is not limited thereto.

[0130] The pixel area PA may be defined as an area in the display area D-DA except for the boundary area BA. The boundary area BA may be formed by valley holes VA-H (see FIG. Figure 7 ) is defined, and the display area D-DA that does not overlap with the valley hole VA-H may correspond to the pixel area PA. It is shown that any one of the first color pixel PX1, the second color pixel PX2, and the third color pixel PX3 is positioned in each of the pixel areas PA, but a plurality of color pixels may be positioned in one pixel area PA.

[0131] The first light emitting element OLED1, the second light emitting element OLED2, and the third light emitting element OLED3 may be positioned in the plurality of pixel areas PA, respectively. Figure 6 Anodes indicated by dotted lines are shown representing the first, second and third light emitting elements OLED1, OLED2 and OLED3, respectively.

[0132] Figure 6 The light emitting element and the pixel circuit included in each of the first pixel area PXA-1 and the second pixel area PXA-2 are shown, and the components such as Figure 4 The signal lines shown in FIG. 1 include scan lines SL1 to SLm, data lines DL1 to DLn, emission lines EL1 to ELm, a first control line CSL1 and a second control line CSL2 .

[0133] Figure 6 The first conductive pattern CDP1 is shown. The first conductive pattern CDP1 overlaps the boundary area BA. The first conductive pattern CDP1 may be positioned to overlap with the valley hole VA-H (see FIG. 1 ) to be described later. Figure 7 ). The first conductive pattern CDP1 and the boundary area BA extend substantially in the same direction. That is, the first conductive pattern CDP1 may extend in the first direction DR1.

[0134] The boundary area BA may extend in the first direction DR1 and may not extend in the second direction DR2. The boundary area BA may extend in the first direction DR1 to overlap / align with a plurality of pixel areas PA arranged in the first direction DR1 in the second direction DR2. In one or more embodiments, the first pixel area PXA-1 may include the (1-1)th pixel area PXA-11 and the (1-2)th pixel area PXA-12 arranged along the first direction DR1, and the boundary area BA may overlap with each of the (1-1)th pixel area PXA-11 and the (1-2)th pixel area PXA-12 in the second direction DR2. The second pixel area PXA-2 may include the (2-1)th pixel area PXA-21 and the (2-2)th pixel area PXA-22 arranged along the first direction DR1, and the boundary area BA may overlap with each of the (2-1)th pixel area PXA-21 and the (2-2)th pixel area PXA-22 in the second direction DR2.

[0135] In the display panel DP according to one or more embodiments, the boundary area BA included in the display area D-DA may not extend in the second direction DR2 so as not to overlap with any one of the pixel rows PXA-1 and PXA-2 in the first direction DR1. That is, the boundary area BA may not be positioned between a plurality of pixel areas included in any one of the pixel rows PXA-1 and PXA-2. In one or more embodiments, since the boundary area BA is not positioned between the (1-1)th pixel area PXA-11 and the (1-2)th pixel area PXA-12, the (1-1)th pixel area PXA-11 and the (1-2)th pixel area PXA-12 may be continuously arranged along the first direction DR1. Since the boundary area BA is not positioned between the (2-1)th pixel area PXA-21 and the (2-2)th pixel area PXA-22, the (2-1)th pixel area PXA-21 and the (2-2)th pixel area PXA-22 may be continuously arranged along the first direction DR1.

[0136] The first conductive pattern CDP1 may completely overlap the boundary area BA. The first conductive pattern CDP1 may be completely positioned at the boundary area BA extending in the first direction DR1. The first conductive pattern CDP1 may extend in the first direction DR1 to overlap / align with a plurality of pixel areas PA arranged in the first direction DR1 in the second direction DR2. The first conductive pattern CDP1 may completely cover the valley hole VA-H (see FIG. 1 ) to be described later. Figure 7 ).

[0137] Similar to the boundary area BA, the first conductive pattern CDP1 may not extend in the second direction DR2. In the display panel DP according to one or more embodiments, the boundary area BA may not extend in the second direction DR2, so that the valley hole VA-H (see FIG. Figure 7 ) allows for a higher resolution. The first conductive pattern CDP1 may not extend in the second direction DR2, thereby reducing or preventing a problem in which a signal line extending in the first direction DR1 overlaps with the first conductive pattern CDP1.

[0138] Figure 7 is a cross-sectional view of a display panel DP according to one or more embodiments of the present disclosure. Figure 7 Shown along Figure 6 The cross section is taken along line II'. Figure 7 The light emitting elements OLED1 and OLED2 and the pixel circuits PDC connected to the light emitting elements OLED1 and OLED2, respectively (see FIG. Figure 5 ) of some transistors T3 and T6. The above description can be applied to Figure 7 The configuration of the display panel DP shown in .

[0139] Reference Figure 7 , the display panel DP may include a base layer SUB, a circuit element layer DP-CL, a display element layer DP-OLED and an encapsulation layer TFE.

[0140] The substrate layer SUB may provide a substrate surface on which the circuit element layer DP-CL is positioned. The circuit element layer DP-CL may include insulating layers BFL, 10, 20, 30, 40, 50, 60, 70, and 80, transistors T3 and T6, and connecting electrodes CNE11, CNE12, CNE13, and CNE2. The insulating layers BFL, 10, 20, 30, 40, 50, 60, 70, and 80 may include a buffer layer BFL and a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, a fifth insulating layer 50, a sixth insulating layer 60, a seventh insulating layer 70, and an eighth insulating layer 80 positioned on the buffer layer BFL. However, the insulating layer included in the circuit element layer DP-CL is not limited thereto and may be changed according to the configuration of the pixel circuit included in the circuit element layer DP-CL and the process of manufacturing the circuit element layer DP-CL.

[0141] The buffer layer BFL may be positioned on the base layer SUB. The buffer layer BFL may include at least one inorganic layer. For example, the buffer layer BFL may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The buffer layer BFL may improve the adhesion between the semiconductor layer (e.g., the sixth semiconductor pattern SP6) or the conductive pattern layer of the circuit element layer DP-CL positioned on the base layer SUB and the base layer SUB.

[0142] The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, the sixth insulating layer 60, the seventh insulating layer 70 and the eighth insulating layer 80 may each include an inorganic layer and / or an organic layer, and may have a single layer or a multilayer structure. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide and hafnium oxide, but the material of the inorganic layer is not limited thereto. The organic layer may include at least any one of acrylic resin, methacrylate resin, polyisoprene resin, ethylene resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyamide resin and perylene resin. However, the material of the organic layer is not limited thereto.

[0143] The blocking pattern BML may be positioned on the buffer layer BFL. When the buffer layer BFL is omitted, the blocking pattern BML may be directly positioned on the base layer SUB. The blocking pattern BML may include molybdenum. The blocking pattern BML may have a shielding function. The blocking pattern BML may block the potential caused by the polarization phenomenon between the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, the sixth insulating layer 60, the seventh insulating layer 70, and the eighth insulating layer 80 positioned on the blocking pattern BML from affecting the transistors T1, T2, T3, T4, T5, T6, and T7 (see Figure 5 ).

[0144] The first semiconductor pattern layer SM1 (see Figure 8B ) may be positioned on the first insulating layer 10. The first semiconductor pattern layer may include a silicon semiconductor. For example, the first semiconductor pattern layer may include polycrystalline silicon or amorphous silicon. However, the material included in the first semiconductor pattern layer is not limited thereto, as long as the first semiconductor pattern layer has semiconductor properties.

[0145] Depending on whether the plurality of regions are doped, the first semiconductor pattern layer may include the plurality of regions having different electrical properties. The first semiconductor pattern layer may include a first region having high conductivity and a second region having low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a doped region doped with a P-type dopant, and the N-type transistor may include a doped region doped with an N-type dopant. The second region may be an undoped region, or a region doped at a concentration lower than the doping concentration of the first region.

[0146] The first region may have a higher conductivity than the second region and may be substantially used as a source and a drain of a transistor. The second region may substantially correspond to a channel (or a channel region or an active layer) of a transistor. That is, in the first semiconductor pattern layer, the first region with a higher conductivity may be a source, a drain or a connection signal line of a transistor, and the second region with a lower conductivity may be a channel of a transistor.

[0147] The sixth semiconductor pattern SP6 of the sixth transistor T6 may be formed by the first semiconductor pattern layer. The sixth semiconductor pattern SP6 may include a sixth source electrode S6, a sixth channel A6, and a sixth drain electrode D6. The sixth source electrode S6 and the sixth drain electrode D6 may extend from the sixth channel A6 in opposite directions to each other, respectively. That is, the sixth source electrode S6 and the sixth drain electrode D6 may be spaced apart from each other on a plane, with the sixth channel A6 interposed therebetween.

[0148] The first insulating layer 10 may be positioned on the buffer layer BFL. The first insulating layer 10 may cover the barrier pattern BML. The second insulating layer 20 may be positioned on the first insulating layer 10. The second insulating layer 20 may cover the first semiconductor pattern layer. For example, the second insulating layer 20 may cover the sixth semiconductor pattern SP6.

[0149] The first conductive pattern layer MP1 (see Figure 8C ) may be positioned on the second insulating layer 20. The sixth gate electrode G6 may be formed of the first conductive pattern layer, and the sixth gate electrode G6 may be positioned on the second insulating layer 20. The sixth gate electrode G6 may overlap the sixth channel A6. In one or more embodiments, the sixth gate electrode G6 may be used as a mask in a process of doping the sixth semiconductor pattern SP6.

[0150] Figure 7 The sixth transistor T6 is shown to have a top gate structure in which the sixth gate electrode G6 is positioned on the sixth semiconductor pattern SP6 , but the present disclosure is not limited thereto, and the sixth transistor T6 may have a bottom gate structure in which the sixth gate electrode G6 of the sixth transistor T6 is positioned under the sixth semiconductor pattern SP6 .

[0151] At the same time, the first transistor T1, the second transistor T2, the fifth transistor T5 and the seventh transistor T7 (see Figure 5) may be a transistor having the same structure as the sixth transistor T6. For example, the semiconductor patterns of the first transistor T1, the second transistor T2, the fifth transistor T5, and the seventh transistor T7 may be formed by a first semiconductor pattern layer similar to the sixth semiconductor pattern SP6, and the gate electrodes of the first transistor T1, the second transistor T2, the fifth transistor T5, and the seventh transistor T7 may be formed by a first conductive pattern layer similar to the sixth gate electrode G6, but one or more embodiments of the present disclosure are not necessarily limited thereto.

[0152] The third insulating layer 30 may be positioned on the second insulating layer 20. The third insulating layer 30 may cover the first conductive pattern layer. For example, the third insulating layer 30 may cover the sixth gate electrode G6.

[0153] The second conductive pattern layer MP2 (see Fig.8D ) may be positioned on the third insulating layer 30. The second conductive pattern layer may include a scan line SL. In one or more embodiments, the second conductive pattern layer may further include an upper electrode UE (see Fig.8D ). The scan line SL may be partially connected to the first scan line GWi, the second scan line GCi, and the third scan line GIi (see Figure 5 )correspond.

[0154] The fourth insulating layer 40 may be positioned on the third insulating layer 30. The fourth insulating layer 40 may cover the second conductive pattern layer. For example, the fourth insulating layer 40 may cover the scan line SL.

[0155] The second semiconductor pattern layer may be positioned on the fourth insulating layer 40. The second semiconductor pattern layer may include a semiconductor material different from the first semiconductor pattern layer. For example, the second semiconductor pattern layer may include an oxide semiconductor including a metal oxide. The oxide semiconductor may include an oxide of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) or titanium (Ti) or a mixture of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) or titanium (Ti) and / or an oxide thereof. The oxide semiconductor may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc indium oxide (ZIO), indium oxide (InO), or the like. 2 O 3 ), titanium oxide (TiO 2 ), indium zinc tin oxide (IZTO) or zinc tin oxide (ZTO), etc., but one or more embodiments of the present disclosure are not necessarily limited thereto.

[0156] The second semiconductor pattern layer may include a plurality of regions having different electrical properties depending on whether the metal oxide is reduced. The region where the metal oxide of the second semiconductor pattern layer is reduced (hereinafter, referred to as the reduction region) may have a greater conductivity than the region where the metal oxide of the second semiconductor pattern layer is not reduced (hereinafter, referred to as the non-reduction region). The reduction region may be substantially used as a source or drain of a transistor. The non-reduction region may be substantially used as a channel (or active region) of a transistor.

[0157] The third semiconductor pattern SP3 of the third transistor T3 may be formed by the second semiconductor pattern layer. The third semiconductor pattern SP3 may include a third source electrode S3, a third channel A3, and a third drain electrode D3. The third source electrode S3 and the third drain electrode D3 may extend from the third channel A3 in opposite directions to each other, respectively. That is, the third source electrode S3 and the third drain electrode D3 may be spaced apart from each other on a plane, with the third channel A3 interposed therebetween.

[0158] The fifth insulating layer 50 may be positioned on the fourth insulating layer 40. The fifth insulating layer 50 may cover the second semiconductor pattern layer. For example, the fifth insulating layer 50 may cover the third semiconductor pattern SP3.

[0159] The third conductive pattern layer MP3 (see Figure 8F ) may be positioned on the fifth insulating layer 50. The third gate electrode G3 may be formed of a third conductive pattern layer, and the third gate electrode G3 may be positioned on the fifth insulating layer 50. The third gate electrode G3 may overlap the third channel A3. In one or more embodiments, the third gate electrode G3 may be used as a mask in a process of doping the third semiconductor pattern SP3.

[0160] The third semiconductor pattern SP3 may partially overlap with the scan line SL positioned below the third semiconductor pattern SP3. The portion of the scan line SL overlapping with the third semiconductor pattern SP3 may be used together with the third gate electrode G3 as the gate of the third transistor T3. In this case, the third gate of the third transistor T3 may be doubly formed to have sufficient gate charge and may be switched at high speed. In addition, the scan line SL may be positioned to overlap with the third semiconductor pattern SP3, thereby reducing or preventing the possibility that the third semiconductor pattern SP3 is damaged by light introduced from the lower portion of the display panel DP. However, this structure of the third transistor T3 is an example, and the present disclosure is not limited thereto.

[0161] At the same time, the fourth transistor T4 (see Figure 5) may have the same structure as the third transistor T3. For example, the semiconductor pattern of the fourth transistor T4 may be formed by a second semiconductor pattern layer similar to the third semiconductor pattern SP3, and the gate electrode of the fourth transistor T4 may be formed by a third conductive pattern layer similar to the third gate electrode G3, but one or more embodiments of the present disclosure are not necessarily limited thereto.

[0162] The third semiconductor pattern SP3 of the third transistor T3 and the sixth semiconductor pattern SP6 of the sixth transistor T6 may be positioned on different layers. However, this is an example, and the pixel circuit PDC (see Figure 5 ) can be positioned on the same layer.

[0163] The sixth insulating layer 60 may be positioned on the fifth insulating layer 50. The sixth insulating layer 60 may cover the third conductive pattern layer. For example, the sixth insulating layer 60 may cover the third gate electrode G3. Meanwhile, in this specification, the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, and the sixth insulating layer 60 may be described as “a plurality of lower insulating layers”.

[0164] The fourth conductive pattern layer MP4 (see Figure 8G ) may be positioned on the sixth insulating layer 60. The connection electrodes CNE11, CNE12, and CNE13 may be formed of a fourth conductive pattern layer. The first conductive pattern CDP1 may be formed of a fourth conductive pattern layer. The connection electrodes CNE11, CNE12, and CNE13 may include a (1-1)th connection electrode CNE11, a (1-2)th connection electrode CNE12, and a (1-3)th connection electrode CNE13. The (1-1)th connection electrode CNE11, the (1-2)th connection electrode CNE12, and the (1-3)th connection electrode CNE13 and the first conductive pattern CDP1 may be spaced apart from each other on the same layer. Meanwhile, in the present specification, the sixth insulating layer 60, which is a base insulating layer on which the fourth conductive pattern layer is positioned, may be described as a “first reference insulating layer”, and the fifth insulating layer 50 positioned below the sixth insulating layer 60 may be described as a “second reference insulating layer”.

[0165] The (1-1)th connection electrode CNE11 may be connected to the sixth drain electrode D6 of the sixth transistor T6. The (1-1)th connection electrode CNE11 may be connected to the sixth drain electrode D6 through a contact hole penetrating the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, and the sixth insulating layer 60.

[0166] The (1-2)th connection electrode CNE12 may be connected to the sixth source S6 of the sixth transistor T6. The (1-2)th connection electrode CNE12 may be connected to the sixth source S6 through a contact hole penetrating the second, third, fourth, fifth, and sixth insulating layers 20, 30, 40, 50, and 60.

[0167] The (1-2)th connection electrode CNE12 may extend on a plane to overlap the third drain electrode D3 of the third transistor T3. The (1-2)th connection electrode CNE12 may be connected to the third drain electrode D3 through a contact hole penetrating the fifth insulating layer 50 and the sixth insulating layer 60. Therefore, the third semiconductor pattern SP3 of the third transistor T3 and the sixth semiconductor pattern SP6 of the sixth transistor T6, which are positioned on respective different layers, may be electrically connected to each other through the (1-2)th connection electrode CNE12.

[0168] The (1-3)th connection electrode CNE13 may be connected to the third source S3 of the third transistor T3 . The (1-3)th connection electrode CNE13 may be connected to the third source S3 through a contact hole penetrating the fifth and sixth insulating layers 50 and 60 .

[0169] The display panel DP includes a valley hole VA-H defined inside the circuit element layer DP-CL. The area in which the valley hole VA-H is located may be defined as a boundary area BA. Figure 6 and Figure 7 , the boundary area BA in which the valley hole VA-H is positioned may extend in the first direction DR1 and may be positioned between two pixel areas PXA-1 and PXA-2 adjacent to each other in the second direction DR2. The valley hole VA-H may extend in the first direction DR1 and may be positioned between two pixel areas PXA-1 and PXA-2 adjacent to each other. The valley hole VA-H may extend in the first direction DR1 and may be positioned on both sides of each of the pixel areas PXA-1 and PXA-2 relative to the second direction DR2. Inside the circuit element layer DP-CL, the valley hole VA-H may have a shape in which the pixel area PXA-1 or PXA-2 is surrounded on both sides relative to the second direction DR2, thereby absorbing an external impact applied to the area surrounded by the valley hole VA-H, and reducing or minimizing the transfer of the external impact to the adjacent pixels.

[0170] The valley hole VA-H may at least partially penetrate the lower insulating layers 10, 20, 30, 40, 50, and 60 of the circuit element layer DP-CL. The valley hole VA-H may penetrate two or more insulating layers of the lower insulating layers 10, 20, 30, 40, 50, and 60 of the circuit element layer DP-CL. In one or more embodiments, the valley hole VA-H may penetrate at least the fifth insulating layer 50 and the sixth insulating layer 60. The inside of the valley hole VA-H is filled with at least a portion of the plurality of insulating layers of the circuit element layer DP-CL.

[0171] Figure 7 The valley holes VA-H penetrating the fourth insulating layer 40, the fifth insulating layer 50, and the sixth insulating layer 60 and filled with the seventh insulating layer 70 are shown. However, the thickness penetrated by the valley holes VA-H in the thickness direction of the display panel DP is not limited thereto, and the valley holes VA-H may be formed to penetrate other insulating layers among the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, and the sixth insulating layer 60. The number and shape of the insulating layers penetrated by the valley holes VA-H may differ according to the process conditions for forming the valley holes VA-H, and are not particularly limited.

[0172] Meanwhile, as described above, since the boundary area BA is not positioned between the (1-1)th pixel area PXA-11 and the (1-2)th pixel area PXA-12, no separate valley hole VA-H is defined between the (1-1)th pixel area PXA-11 and the (1-2)th pixel area PXA-12. That is, the lower insulating layers 10, 20, 30, 40, 50, and 60 overlapping each of the (1-1)th pixel area PXA-11 and the (1-2)th pixel area PXA-12 may have a continuous shape without being cut by the valley hole VA-H.

[0173] The first conductive pattern CDP1 is positioned in the boundary area BA. The first conductive pattern CDP1 overlaps the valley hole VA-H and is at least partially positioned in the valley hole VA-H. The first conductive pattern CDP1 may be positioned inside the valley hole VA-H to contact the inner side surface defining the valley hole VA-H. The first conductive pattern CDP1 may completely cover the inner side surface of the valley hole VA-H.

[0174] The seventh insulating layer 70 may be positioned on the sixth insulating layer 60. The seventh insulating layer 70 may cover the fourth conductive pattern layer. For example, the seventh insulating layer 70 may cover the (1-1)th connection electrode CNE11, the (1-2)th connection electrode CNE12, and the (1-3)th connection electrode CNE13 and the first conductive pattern CDP1. The seventh insulating layer 70 may be filled inside the valley hole VA-H to cover the outer side surface of the first conductive pattern CDP1 positioned on the inner side surface of the valley hole VA-H. Meanwhile, in the present specification, the seventh insulating layer 70 may be described as a "first organic layer".

[0175] The fifth conductive pattern layer may be positioned on the seventh insulating layer 70. The second connection electrode CNE2 may be formed of the fifth conductive pattern layer. In addition, in one or more embodiments, a signal line included in the display panel DP may be partially formed of the fifth conductive pattern layer.

[0176] The second connection electrode CNE2 may be connected to the (1-1)th connection electrode CNE11 through a contact hole penetrating the seventh insulating layer 70. The second connection electrode CNE2 may be connected to the sixth drain electrode D6 of the sixth transistor T6 through the (1-1)th connection electrode CNE11. However, the present disclosure is not limited thereto, and the second connection electrode CNE2 may be omitted, or an additional connection electrode positioned between the second connection electrode CNE2 and the (1-1)th connection electrode CNE11 may be further positioned in the circuit element layer DP-CL.

[0177] The eighth insulating layer 80 may be positioned on the seventh insulating layer 70. The eighth insulating layer 80 may cover the fifth conductive pattern layer. For example, the eighth insulating layer 80 may cover the second connection electrode CNE2. Meanwhile, in this specification, the eighth insulating layer 80 may be described as a 'second organic layer'.

[0178] At least any one of the seventh insulating layer 70 and the eighth insulating layer 80 may include an organic layer. The organic layer may provide a substantially flat surface, cover particles present on the surface of a layer positioned below the organic layer, or cover a step between components positioned below the organic layer. In addition, the organic layer may release stress between components positioned above and below the organic layer.

[0179] The display element layer DP-OLED may be positioned on the circuit element layer DP-CL. The display element layer DP-OLED may include a pixel defining layer PDL and light emitting elements OLED1 and OLED2. The light emitting elements OLED1 and OLED2 may each include a first electrode AE, a light emitting layer EM, and a second electrode CE.

[0180] The light emitting elements OLED1 and OLED2 may include organic light emitting elements, quantum dot light emitting elements, micro LED light emitting elements or nano LED light emitting elements. However, the present disclosure is not limited thereto, and the light emitting elements OLED1 and OLED2 may include various embodiments as long as they emit light or control the amount of light in response to an electrical signal.

[0181] The light emitting elements OLED1 and OLED2 can each be electrically connected to a corresponding pixel circuit PDC (see Figure 5 ) transistor. Figure 7 It is shown that the light emitting elements OLED1 and OLED2 are electrically connected to the corresponding sixth transistor T6.

[0182] The first electrodes AE of the light emitting elements OLED1 and OLED2 may be positioned on the uppermost layer of the circuit element layer DP-CL. For example, the first electrodes AE may be positioned on the eighth insulating layer 80. The first electrodes AE may be spaced apart from each other on the eighth insulating layer 80. The first electrodes AE may be respectively connected to the corresponding second connection electrodes CNE2 through contact holes penetrating the eighth insulating layer 80. The first electrodes AE may be respectively electrically connected to the corresponding sixth drain electrode D6 through the corresponding second connection electrode CNE2 and the (1-1)th connection electrode CNE11.

[0183] The pixel defining film PDL may be positioned on the uppermost layer of the circuit element layer DP-CL. For example, the pixel defining film PDL may be positioned on the eighth insulating layer 80. Pixel openings PX-OP respectively overlapping the first electrodes AE and partially exposing the corresponding first electrodes AE may be defined in the pixel defining film PDL. The area of ​​the first electrode AE ​​exposed by the pixel opening PX-OP may correspond to the luminous area LA. That is, the display area D-DA of the display panel DP may include the luminous area LA. The area in which the pixel defining film PDL is positioned may correspond to the non-luminous area NLA. In a plane, the non-luminous area NLA may surround the luminous area LA, and the boundary of the luminous area LA may be set.

[0184] The pixel defining film PDL may include a polymer resin. For example, the pixel defining film PDL may include a polyacrylate resin or a polyimide resin. However, the present disclosure is not limited thereto, and the pixel defining film PDL may also include an inorganic material.

[0185] The pixel definition film PDL may further include a light absorbing material. For example, the pixel definition film PDL may include a black colorant such as a black pigment or a black dye. For example, the black colorant may include carbon black, a metal such as chromium, or an oxide thereof, but the present disclosure is not limited thereto.

[0186] The light-emitting layers EM1 and EM2 may be positioned on the first electrode AE. The light-emitting layers EM of the light-emitting elements OLED1 and OLED2 may be positioned corresponding to the pixel openings PX-OP, respectively, and may be formed into light-emitting patterns spaced apart from each other on a plane. However, the present disclosure is not limited thereto, and the light-emitting layers EM1 and EM2 of the light-emitting elements OLED1 and OLED2 may be formed as an integrated film and a common layer. The light-emitting layers EM1 and EM2 may include organic light-emitting materials and / or inorganic light-emitting materials. For example, the light-emitting layers EM1 and EM2 may include fluorescent materials, phosphorescent materials, organic metal complex light-emitting materials, or quantum dots. The light-emitting layers EM1 and EM2 may emit light having any one of red, green, and blue colors.

[0187] The second electrode CE may be positioned on the light emitting layers EM1 and EM2. The second electrode CE of the light emitting elements OLED1 and OLED2 may be provided as an integral common layer and may overlap the light emitting area LA and the non-light emitting area NLA. The second electrode CE may be commonly positioned on the pixel PX (see Figure 4 ) to supply a common voltage.

[0188] Meanwhile, the light emitting elements OLED1 and OLED2 may further include a light emitting control layer positioned between the first electrode AE ​​and the second electrode CE. For example, the light emitting control layer may include a hole control layer positioned between the first electrode AE ​​and the light emitting layers EM1 and EM2, or an electron control layer positioned between the light emitting layers EM1 and EM2 and the second electrode CE. The hole control layer may include at least one of a hole injection layer, a hole transport layer, and an electron blocking layer, and the electron control layer may include at least one of an electron injection layer, an electron transport layer, and a hole blocking layer.

[0189] The encapsulation layer TFE may be positioned on the display element layer DP-OLED. The encapsulation layer TFE may seal the light emitting elements OLED1 and OLED2. The encapsulation layer TFE may include at least one thin film of an inorganic film and an organic film. In one or more embodiments, the encapsulation layer TFE may include an inorganic film and an organic film positioned between the inorganic films.

[0190] The inorganic film of the encapsulation layer TFE can protect the light-emitting elements OLED1 and OLED2 from moisture and / or oxygen. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. However, the material of the inorganic film is not limited thereto.

[0191] The organic film of the encapsulation layer TFE may protect the light emitting elements OLED1 and OLED2 from foreign substances such as dust particles. The organic film may include acrylic resin. However, the material of the organic film is not limited to the above examples.

[0192] The first driving voltage ELVDD (see Figure 5 ) may be applied to the first electrode AE, and a second driving voltage ELVSS (see Figure 5 ) may be applied to the second electrode CE. When excitons are formed by recombining holes and electrons injected into the light-emitting layer EM and the excitons transition to a ground state, the light-emitting elements OLED1 and OLED2 may emit light. The light-emitting elements OLED1 and OLED2 may emit light in response to an applied electrical signal, so that the display panel DP may display an image through the display area D-DA.

[0193] FIG. 8A to FIG. 8G is a pixel PXij according to one or more embodiments of the present disclosure (see Figure 5 ) of the pattern according to the stacking order. FIG. 8A to FIG. 8G Shows Figure 6 and Figure 7 The sequential stacking structure of a portion of the pixel areas PXA-1 and PXA-2 described in the embodiment and some patterns included in the boundary area BA adjacent to the pixel areas PXA-1 and PXA-2. FIG. 8A to FIG. 8G The shapes and arrangements of the pattern layers of the pixels shown in are merely examples and are not necessarily limited thereto.

[0194] Refer to FIG. 8A to FIG. 8G , also refer to Figures 5 to 7 , circuit component layer DP-CL (see Figure 7 ) may include a semiconductor pattern layer and a conductive pattern layer. The semiconductor pattern layer and the conductive pattern layer may each include a pattern arranged in a certain rule (eg, a predetermined rule) on a plane, and the pattern may constitute a pixel circuit PDC (see Figure 5 ) and signal lines.

[0195] Reference Fig. 8A The barrier layer BM may be positioned on a base substrate (eg, a base layer SUB (see Figure 7 )). The blocking layer BM may include a blocking pattern BML. The blocking layer BM may include a metal. For example, the blocking layer BM may include molybdenum. Since the blocking layer BM is positioned below the semiconductor pattern included in each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, the blocking layer BM may play a role of shielding light incident from the outside. In addition, the blocking layer BM may block the light incident from the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, the sixth insulating layer 60, the seventh insulating layer 70, and the eighth insulating layer 80 (see Figure 7) between the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 (see Figure 5 ).

[0196] Reference Figure 8B , the first semiconductor pattern layer SM1 may be positioned at Fig. 8A The first semiconductor pattern layer SM1 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, a fifth semiconductor pattern SP5, a sixth semiconductor pattern SP6, and a seventh semiconductor pattern SP7. The insulating layer (eg, Figure 7 The first insulating layer 10 in the substrate layer may be positioned between the first semiconductor pattern layer SM1 and the barrier pattern BML. The first semiconductor pattern layer SM1 may be positioned between the substrate layer SUB (see Figure 7 ) to include a semiconductor material. For example, the first semiconductor pattern layer SM1 may include amorphous silicon or polycrystalline silicon. In this specification, the first semiconductor pattern layer SM1 including the first semiconductor pattern SP1, the second semiconductor pattern SP2, the fifth semiconductor pattern SP5, the sixth semiconductor pattern SP6, and the seventh semiconductor pattern SP7 may be referred to as a “semiconductor pattern layer”.

[0197] The first semiconductor pattern layer SM1 may include a plurality of regions having different doping concentrations. A region having greater conductivity of the first semiconductor pattern layer SM1 may correspond to a source or drain of a transistor, and a region having less conductivity of the first semiconductor pattern layer SM1 may correspond to a channel of the transistor.

[0198] The first semiconductor pattern SP1 may include a first source S1, a first drain D1, and a first channel A1. The second semiconductor pattern SP2 may include a second source S2, a second drain D2, and a second channel A2. The fifth semiconductor pattern SP5 may include a fifth source S5, a fifth drain D5, and a fifth channel A5. The sixth semiconductor pattern SP6 may include a sixth source S6, a sixth drain D6, and a sixth channel A6. The seventh semiconductor pattern SP7 may include a seventh source S7, a seventh drain D7, and a seventh channel A7. The first channel A1, the second channel A2, the fifth channel A5, the sixth channel A6, and the seventh channel A7 may be positioned between the first source S1, the second source S2, the fifth source S5, the sixth source S6, and the seventh source S7 and the first drain D1, the second drain D2, the fifth drain D5, the sixth drain D6, and the seventh drain D7, respectively. In an embodiment, the source, the drain, and the channel may also be referred to as a source region, a drain region, and a channel region, respectively. For example, the first source S1, the first drain D1 and the first channel A1 may also be referred to as the first source region S1, the first drain region D1 and the first channel region A1, respectively, and the second source S2, the second drain D2 and the second channel A2 may also be referred to as the second source region S2, the second drain region D2 and the second channel region A2, respectively.

[0199] The pixel circuit PDC (see Figure 5 ) may be arranged in the first direction DR1 and the second direction DR2 on a plane. The first semiconductor pattern SP1, the second semiconductor pattern SP2, the fifth semiconductor pattern SP5, the sixth semiconductor pattern SP6, and the seventh semiconductor pattern SP7 may be formed integrally. The first semiconductor pattern SP1, the second semiconductor pattern SP2, the fifth semiconductor pattern SP5, the sixth semiconductor pattern SP6, and the seventh semiconductor pattern SP7 may be repeatedly arranged to have a symmetrical structure in the first direction DR1. However, the present disclosure is not limited thereto, and the first semiconductor pattern SP1, the second semiconductor pattern SP2, the fifth semiconductor pattern SP5, the sixth semiconductor pattern SP6, and the seventh semiconductor pattern SP7 having the same structure may be repeatedly arranged in the first direction DR1.

[0200] The first semiconductor pattern SP1 may be connected to the second semiconductor pattern SP2, the fifth semiconductor pattern SP5, and the sixth semiconductor pattern SP6. The first source S1 of the first semiconductor pattern SP1 and the second drain D2 of the second semiconductor pattern SP2 may be integrally formed to be electrically connected to each other. The first source S1 of the first semiconductor pattern SP1 and the fifth drain D5 of the fifth semiconductor pattern SP5 may be integrally formed to be electrically connected to each other. The point at which the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the fifth semiconductor pattern SP5 are connected to each other may be connected to the second node ND2 (see Figure 5 ). The first drain electrode D1 of the first semiconductor pattern SP1 and the sixth source electrode S6 of the sixth semiconductor pattern SP6 may be integrally formed to be electrically connected to each other. The point at which the first semiconductor pattern SP1 and the sixth semiconductor pattern SP6 are connected to each other may be connected to the third node ND3 (see Figure 5 )correspond.

[0201] The sixth drain electrode D6 of the sixth semiconductor pattern SP6 and the seventh source electrode S7 of the seventh semiconductor pattern SP7 may be integrally formed to be electrically connected to each other. The point at which the sixth semiconductor pattern SP6 and the seventh semiconductor pattern SP7 are connected to each other may be connected to the fourth node ND4 (see Figure 5 )correspond.

[0202] Reference Figure 8C , the first conductive pattern layer MP1 can be positioned at Figure 8B The insulating layer (eg, Figure 7 The second insulating layer 20 in the embodiment may be positioned between the first conductive pattern layer MP1 and the first semiconductor pattern layer SM1 (see Figure 8B The first conductive pattern layer MP1 may include a first gate electrode G1, a light emitting line EL, and a first scan line GW.

[0203] The first gate electrode G1 may be positioned on the first semiconductor pattern SP1. The first gate electrode G1 may overlap the first channel A1 on a plane. The first semiconductor pattern SP1 and the first gate electrode G1 may constitute a first transistor T1, and the first gate electrode G1 may correspond to a first gate of the first transistor T1.

[0204] The light emitting line EL may extend in the first direction DR1 to overlap the fifth semiconductor pattern SP5 and the sixth semiconductor pattern SP6 on a plane. A portion of the light emitting line EL overlapping the fifth semiconductor pattern SP5 may correspond to the fifth gate electrode G5 of the fifth transistor T5, and another portion of the light emitting line EL overlapping the sixth semiconductor pattern SP6 may correspond to the sixth gate electrode G6 of the sixth transistor T6. The fifth gate electrode G5 may overlap the fifth channel A5 (see FIG. Figure 8B), and the sixth gate electrode G6 may overlap with the sixth channel A6 (see Figure 8B )overlapping.

[0205] The first scan line GW may extend in the first direction DR1 to be spaced apart from the light emitting line EL in the second direction DR2. The first scan line GW may overlap the second semiconductor pattern SP2 and the seventh semiconductor pattern SP7 on a plane. A portion of the first scan line GW may correspond to the second gate electrode G2 of the second transistor T2. Another portion of the first scan line GW overlapping the seventh semiconductor pattern SP7 may correspond to the seventh gate electrode G7 of the seventh transistor T7. On a plane, the second gate electrode G2 may overlap the second channel A2 (see Figure 8B ), and the seventh gate electrode G7 may overlap with the seventh channel A7 (see Figure 8B )overlapping.

[0206] The first conductive pattern layer MP1 may include a metal, an alloy, a conductive metal oxide, a metal nitride, or a transparent conductive material, etc. For example, the first conductive pattern layer MP1 may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), or indium zinc oxide (IZO), etc., but is not limited thereto. The description of the materials included in the first conductive pattern layer MP1 may also be applied to other conductive pattern layers to be described later.

[0207] Reference Fig.8D , the second conductive pattern layer MP2 can be positioned at Figure 8C The insulating layer (eg, Figure 7 The third insulating layer 30 in the first conductive pattern layer MP1 (see Figure 8C ) and the second conductive pattern layer MP2. The second conductive pattern layer MP2 may include an upper electrode UE, a second sub-scan line GCa, a third sub-scan line GIa, and a first initialization line VIL1.

[0208] The upper electrode UE may be connected to the first gate electrode G1 (see Figure 8C ) overlap. The upper electrode UE may form a capacitor CAP with the first gate electrode G1 (see Figure 5 ). The upper electrode UE overlapped with the first gate electrode G1 may correspond to the first electrode of the capacitor CAP, and the first gate electrode G1 may overlap with the capacitor CAP (see Figure 5 The first electrode of the capacitor CAP and the first gate electrode G1 may be formed as an integral electrode electrically connected to each other.

[0209] An opening UE-O penetrating the upper electrode UE may be defined in the upper electrode UE. The first gate electrode G1 may be partially exposed by the opening UE-O of the upper electrode UE.

[0210] The second sub-scan line GCa may extend in the first direction DR1. The second sub-scan line GCa may be connected to the compensation scan signal GCSi (see Figure 5 ) is applied to the second scan line GCi (see Figure 5 ) corresponds. In one or more embodiments, the second scan line GCi may be a line having a double layer to which the same signal is applied. The second sub-scan line GCa may be a part of the second scan line GCi. However, the present disclosure is not limited thereto, and the second scan line GCi may be provided as a single-layer line.

[0211] The third sub-scan line GIa may extend in the first direction DR1 and may be spaced apart from the second sub-scan line GCa in the second direction DR2. Figure 5 ) is applied to the third scan line GIi (see Figure 5 ). In one or more embodiments, the third scan line GIi may be a line having a double layer, and the same signal is applied to the line having the double layer. The third sub-scan line GIa may be a part of the third scan line GIi. However, the present disclosure is not limited thereto, and the third scan line GIi may be provided as a single-layer line.

[0212] The first initialization line VIL1 may extend in the first direction DR1 and may be spaced apart from the second and third sub-scan lines GCa and GIa in the second direction DR2. A first initialization voltage Vint1 may be applied to the first initialization line VIL1.

[0213] Reference Fig. 8E , the second semiconductor pattern layer SM2 may be positioned at Fig.8D The insulating layer (eg, Figure 7 The fourth insulating layer 40 in the second semiconductor pattern layer SM2 may be positioned between the second semiconductor pattern layer SM2 and the second conductive pattern layer MP2. The second semiconductor pattern layer SM2 may include a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4. The second semiconductor pattern layer SM2 may include a semiconductor material. For example, the second semiconductor pattern layer SM2 may include a semiconductor material having a first semiconductor pattern layer SM1 (see Figure 8B ) of the semiconductor material. The second semiconductor pattern layer SM2 may include a metal oxide, and the first semiconductor pattern layer SM1 (see Figure 8B ) may include silicon. However, as long as the second semiconductor pattern layer SM2 includes a semiconductor material, the present disclosure is not limited.

[0214] Depending on whether the metal oxide is reduced, the second semiconductor pattern layer SM2 may include a plurality of regions having respective different conductivities. The region having a larger conductivity of the second semiconductor pattern layer SM2 may correspond to a source or drain of a transistor, and the region having a smaller conductivity of the second semiconductor pattern layer SM2 may correspond to a channel of a transistor.

[0215] The third semiconductor pattern SP3 may include a third source S3, a third drain D3, and a third channel A3. The third channel A3 may be positioned between the third source S3 and the third drain D3. The fourth semiconductor pattern SP4 may include a fourth source S4, a fourth drain D4, and a fourth channel A4. The fourth channel A4 may be positioned between the fourth source S4 and the fourth drain D4.

[0216] The pixel circuit PDC (see Figure 5 ) may be arranged in the first direction DR1 and the second direction DR2 on a plane. The third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 may be repeatedly arranged to have a symmetrical structure in the first direction DR1. However, the present disclosure is not limited thereto, and the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 having the same structure may be repeatedly arranged in the first direction DR1.

[0217] The third semiconductor pattern SP3 may be connected to the fourth semiconductor pattern SP4. The third source electrode S3 of the third semiconductor pattern SP3 and the fourth drain electrode D4 of the fourth semiconductor pattern SP4 may be integrally formed to be electrically connected to each other. The point at which the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 are connected to each other may be connected to the first node ND1 (see Figure 5 )correspond.

[0218] The third semiconductor pattern SP3 may be at least partially aligned with the first conductive pattern layer MP1 (see Figure 8C ) or the second conductive pattern layer MP2 (see Fig.8D ). The third channel A3 of the third semiconductor pattern SP3 may overlap with the second sub-scan line GCa positioned therebelow. The second sub-scan line GCa overlapping the third channel A3 may partially correspond to the third gate electrode. In addition, portions of the first scan line GW and the second sub-scan line GCa overlapping the third semiconductor pattern SP3 may protect the third semiconductor pattern SP3 from light introduced into a lower portion thereof.

[0219] The fourth semiconductor pattern SP4 may be at least partially aligned with the first conductive pattern layer MP1 (see Figure 8C ) or the second conductive pattern layer MP2 (see Fig.8D). The fourth channel A4 of the fourth semiconductor pattern SP4 may overlap with the third sub-scan line GIa positioned therebelow. A portion of the third sub-scan line GIa overlapping with the fourth channel A4 may correspond to the fourth gate. In addition, portions of the third sub-scan line GIa and the first initialization line VIL1 overlapping with the fourth semiconductor pattern SP4 may protect the fourth semiconductor pattern SP4 from light introduced into a lower portion thereof.

[0220] Reference Figure 8F , the third conductive pattern layer MP3 can be positioned at Fig. 8E The insulating layer (eg, Figure 7 The fifth insulating layer 50 in the embodiment may be positioned between the third conductive pattern layer MP3 and the second semiconductor pattern layer SM2 (see Fig. 8E The third conductive pattern layer MP3 may include a second sub-scan line GCb and a third sub-scan line GIb.

[0221] The second sub-scan line GCb may extend in the first direction DR1. The second sub-scan line GCb may be connected to the compensation scan signal GCSi (see Figure 5 ) is applied to the second scan line GCi (see Figure 5 ) corresponds to the second sub-scanning line GCb of the third conductive pattern layer MP3 and the second conductive pattern layer MP2 (see Fig.8D ) may overlap each other on a plane. The second sub-scan lines GCa and GCb positioned on different layers may be electrically connected to each other, and the same signal may be applied to the second sub-scan lines GCa and GCb. That is, in one or more embodiments, the second scan line GCi may be a line having a double layer, the same signal is applied to the line having the double layer, and the second sub-scan line GCb may be a part of the second scan line GCi. However, the present disclosure is not limited thereto, and one of the second sub-scan lines GCa and GCb may be omitted.

[0222] The second sub-scan line GCb of the third conductive pattern layer MP3 may overlap the third semiconductor pattern SP3 on a plane. The portion of the second sub-scan line GCb overlapping the third semiconductor pattern SP3 may correspond to the third gate electrode G3 of the third transistor T3 on a plane. The third gate electrode G3 may overlap the third channel A3 (see FIG. Fig. 8E ). The third channel A3 may overlap with each of the second sub-scan line GCa positioned under the third semiconductor pattern SP3 and the second sub-scan line GCb positioned on the third semiconductor pattern SP3. The third gate of the third transistor T3 may be doubly formed to have sufficient gate charge and may be switched at a relatively high speed.

[0223] The third sub-scan line GIb may extend in the first direction DR1. The third sub-scan line GIb may be connected to the initialization scan signal GISi (see Figure 5 ) is applied to the third scan line GIi (see Figure 5 ) corresponds to the third sub-scanning line GIb of the third conductive pattern layer MP3 and the second conductive pattern layer MP2 (see Fig.8D ) may overlap each other on a plane. The third sub-scan lines GIa and GIb positioned on different layers may be electrically connected to each other, and the same signal may be applied to the third sub-scan lines GIa and GIb. That is, in one or more embodiments, the third scan line GIi (see Figure 5 ) may be a line having a double layer to which the same signal is applied, and the third sub-scan line GIb may be a part of the third scan line GIi. However, the present disclosure is not limited thereto, and one of the third sub-scan lines GIa and GIb may be omitted.

[0224] The third sub-scan line GIb of the third conductive pattern layer MP3 may overlap with the fourth semiconductor pattern SP4 on a plane. The portion of the third sub-scan line GIb overlapping with the fourth semiconductor pattern SP4 may correspond to the fourth gate electrode G4 of the fourth transistor T4. The fourth gate electrode G4 may overlap with the fourth channel A4 on a plane. The fourth channel A4 may overlap with each of the third sub-scan line GIa positioned below the fourth semiconductor pattern SP4 and the third sub-scan line GIb positioned on the fourth semiconductor pattern SP4. The fourth gate of the fourth transistor T4 may be doubly formed to have sufficient gate charge and may be switched at a relatively high speed.

[0225] Reference Figure 8G , the fourth conductive pattern layer MP4 can be positioned at Figure 8F The insulating layer (eg, Figure 7 The sixth insulating layer 60 in the embodiment of the present invention can be positioned on the third conductive pattern layer MP3 (see Figure 8F ) and the fourth conductive pattern layer MP4. The fourth conductive pattern layer MP4 may include connection electrodes CNE11, CNE12, CNE13, CNE14, CNE15, CNE16, and CNE17 spaced apart from each other on the same layer. The fourth conductive pattern layer MP4 may include a first conductive pattern CDP1.

[0226] The connection electrodes CNE11, CNE12, CNE13, CNE14, CNE15, CNE16, and CNE17 may be electrodes electrically connected to the configurations respectively connected to the connection electrodes. The connection electrodes CNE11, CNE12, CNE13, CNE14, CNE15, CNE16, and CNE17 may overlap with the configurations respectively connected to the connection electrodes, respectively. The connection electrodes CNE11, CNE12, CNE13, CNE14, CNE15, CNE16, and CNE17 may be connected by penetrating at least one insulating layer positioned between the connection electrodes CNE11, CNE12, CNE13, CNE14, CNE15, CNE16, and CNE17 and the configurations respectively connected thereto. The connection electrodes CNE11 , CNE12 , CNE13 , CNE14 , CNE15 , CNE16 , and CNE17 may include a (1-1)th connection electrode CNE11 to a (1-7)th connection electrode CNE17 .

[0227] The connection electrodes CNE11, CNE12, CNE13, CNE14, CNE15, CNE16, and CNE17 may include a metal, an alloy, a metal nitride, and / or a conductive metal oxide, etc. For example, the connection electrodes CNE11, CNE12, CNE13, CNE14, CNE15, CNE16, and CNE17 may include aluminum (Al), an alloy containing aluminum, titanium (Ti), an alloy containing titanium, silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), or indium zinc oxide (IZO), etc., but are not limited thereto. For example, the connection electrodes CNE11, CNE12, CNE13, CNE14, CNE15, CNE16, and CNE17 may include a three-layer structure of Ti / Al / Ti, but are not limited thereto.

[0228] The (1-1)th connection electrode CNE11 may be connected to the sixth semiconductor pattern SP6 (see Figure 8B ) overlap. The (1-1)th connection electrode CNE11 may be connected to the sixth drain electrode D6 of the sixth transistor T6 through a contact hole (see Figure 8B ). The (1-1)th connection electrode CNE11 may be electrically connected to the light emitting element OLED positioned on the (1-1)th connection electrode CNE11 (see Figure 5 ) of the first electrode AE ​​(see Figure 7 ) and the sixth drain D6.

[0229] The (1-2)th connection electrode CNE12 may be connected to the first semiconductor pattern SP1 (see Figure 8B) and the third semiconductor pattern SP3 of the third transistor T3 (see Fig. 8E ) overlap each of them. The (1-2)th connection electrode CNE12 may be connected to the first drain electrode D1 of the first transistor T1 through a contact hole (see Figure 8B ) and the third drain electrode D3 of the third transistor T3 (see Fig. 8E ). The first drain electrode D1 of the first transistor T1 located on each different layer (see Figure 8B ) and the third drain electrode D3 of the third transistor T3 (see Fig. 8E ) may be electrically connected to each other through the (1-2)th connection electrode CNE12. The point at which the first transistor T1, the third transistor T3, and the sixth transistor T6 are electrically connected to each other may be connected to the third node ND3 (see Figure 5 )correspond.

[0230] The (1-3)th connection electrode CNE13 may be connected to the first gate electrode G1 (see Figure 8C ) and the third semiconductor pattern SP3 of the third transistor T3 (see Fig. 8E ) overlap each of them. The (1-3)th connection electrode CNE13 may be connected to the first gate electrode G1 (see FIG. 1 ) exposed by the opening UE-O of the upper electrode UE. Figure 8C ). The (1-3)th connection electrode CNE13 may be connected to the third source electrode S3 of the third transistor T3 (see Fig. 8E ). The first gate electrode G1 of the first transistor T1 is positioned on each different layer (see Figure 8C ) and the third source S3 of the third transistor T3 (see Fig. 8E ) can be electrically connected to each other through the (1-3)th connecting electrode CNE13. The first gate electrode G1 of the first transistor T1 (see Figure 8C ) and the third source S3 of the third transistor T3 (see Fig. 8E ) at which they are electrically connected to each other may be connected to the first node ND1 (see Figure 5 )correspond.

[0231] The (1-4)th connection electrode CNE14 may be connected to the upper electrode UE and the fifth semiconductor pattern SP5 (see Figure 8C ) overlap each of them. The (1-4)th connection electrode CNE14 may be connected to the upper electrode UE and the fifth source electrode S5 of the fifth transistor T5 (see Figure 8B That is, the (1-4)th connection electrode CNE14 may be electrically connected to the capacitor CAP (see Figure 5) corresponding to the upper electrode UE of the first electrode. The (1-4)th connection electrode CNE14 may be connected to the first voltage line VL1 (see Figure 5 That is, the upper electrode UE of the fifth transistor T5 and the fifth source S5 (see Figure 8B ) can be electrically connected to the first voltage line VL1 through the (1-4)th connection electrode CNE14 (see Figure 5 ), and the first driving voltage ELVDD (see Figure 5 ) may be applied to the first voltage line VL1.

[0232] The (1-5)th connection electrode CNE15 may be connected to the seventh semiconductor pattern SP7 (see FIG. Figure 8C ) overlap. The (1-5)th connection electrode CNE15 may be connected to the seventh drain electrode D7 of the seventh transistor T7 (see Figure 8B ). The (1-5)th connection electrode CNE15 may be connected to the second initialization line VIL2 (see FIG. 1-5) positioned on the (1-5)th connection electrode CNE15. Figure 5 That is, the seventh drain electrode D7 of the seventh transistor T7 (see Figure 8B ) can be electrically connected to the second initialization line VIL2 through the (1-5)th connection electrode CNE15 (see Figure 5 ), and the second initialization voltage Vint2 (see Figure 5 ) may be applied to the second initialization line VIL2.

[0233] The (1-6)th connection electrode CNE16 may be connected to the second semiconductor pattern SP2 (see Figure 8B ) overlap. The (1-6)th connection electrode CNE16 may be connected to the second source electrode S2 of the second transistor T2 (see Figure 8B ). The (1-6)th connection electrode CNE16 may be connected to the data line DLj positioned on the (1-6)th connection electrode CNE16 (see Figure 5 That is, the second source electrode S2 of the second transistor T2 (see Figure 8B ) can be electrically connected to the data line DLj through the (1-6)th connecting electrode CNE16 (see Figure 5 ), and the data voltage Vd (see Figure 5 ) can be applied to the data line DLj.

[0234] The (1-7)th connection electrode CNE17 may be connected to the fourth semiconductor pattern SP4 (see Fig. 8E ) overlap. The (1-7)th connection electrode CNE17 may be connected to the fourth source electrode S4 of the fourth transistor T4 (see Fig. 8E). The (1-7)th connection electrode CNE17 may be connected to the first initialization line VIL1 through a line or a connection electrode positioned on the (1-7)th connection electrode CNE17. That is, the fourth source S4 of the fourth transistor T4 (see Fig. 8E ) can be electrically connected to the first initialization line VIL1 through the (1-7)th connection electrode CNE17, and the first initialization voltage Vint1 (see Figure 5 ) may be applied to the first initialization line VIL1.

[0235] At the same time, the display panel DP (see Figure 7 ) includes positioning in the pixel circuit PDC (see Figure 5 ) in the pattern. The valley holes VA-H may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The valley holes VA-H may be located in a plane included in the pixel circuit PDC (see Figure 5 ) above and below the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. As described above, the valley hole VA-H may at least partially penetrate the lower insulating layers 10, 20, 30, 40, 50 and 60 (see Figure 7 The valley hole VA-H may have a pixel circuit PDC therein (see Figure 5 ) is a shape surrounded on both sides relative to the second direction DR2, thereby absorbing external impact applied to the area surrounded by the valley hole VA-H and reducing or minimizing the transmission of external impact to the pixels positioned adjacent to it.

[0236] The first conductive pattern CDP1 is positioned to overlap the valley hole VA-H in a plane. The first conductive pattern CDP1 may extend in the first direction DR1 and may overlap the entire valley hole VA-H in a plane. The first conductive pattern CDP1 may completely cover the valley hole VA-H in a plane.

[0237] Similar to the connection electrodes CNE11, CNE12, CNE13, CNE14, CNE15, CNE16, and CNE17, the first conductive pattern CDP1 may be included in the fourth conductive pattern layer MP4. That is, the first conductive pattern CDP1 may include the same material as the connection electrodes CNE11, CNE12, CNE13, CNE14, CNE15, CNE16, and CNE17. The first conductive pattern CDP1 may be positioned on the same layer as the connection electrodes CNE11, CNE12, CNE13, CNE14, CNE15, CNE16, and CNE17, and may include the same material as the connection electrodes CNE11, CNE12, CNE13, CNE14, CNE15, CNE16, and CNE17.

[0238] Fig. 9 is a display panel DP according to one or more embodiments of the present disclosure (see Figure 7 ) cross-sectional view. Fig. 9 Shown along Figure 6 The cross section is taken along line II-II'. Fig. 9 1 and 2 show a cross section of two adjacent pixel areas PXA-1 and PXA-2 and some configurations in a boundary area BA located therebetween. Fig. 9 It is shown in Figure 7 Among the configurations of the display panel DP shown in , the configuration included in the base layer SUB and the circuit element layer DP-CL.

[0239] Reference Fig. 9 , the display panel according to one or more embodiments includes a boundary area BA positioned between two adjacent pixel areas PXA-1 and PXA-2, and the valley hole VA-H is positioned in the boundary area BA. The valley hole VA-H may at least partially penetrate the lower insulating layers 10, 20, 30, 40, 50, and 60 of the circuit element layer DP-CL. The inside of the valley hole VA-H is filled with at least a portion of the plurality of insulating layers of the circuit element layer DP-CL. For example, Fig. 9 As shown in FIG. 1 , the valley hole VA-H may penetrate the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, and the sixth insulating layer 60, and may be filled with the seventh insulating layer 70. However, the present disclosure is not limited thereto, and the valley hole VA-H may further penetrate the first insulating layer 10 and the second insulating layer 20. The valley hole VA-H may further penetrate the buffer layer BFL.

[0240] The first conductive pattern CDP1 is positioned in the boundary area BA. The first conductive pattern CDP1 overlaps the valley hole VA-H, and at least a portion of the first conductive pattern CDP1 is positioned in the valley hole VA-H. The first conductive pattern CDP1 may be positioned inside the valley hole VA-H to contact the inner side surface of the valley hole VA-H.

[0241] The first conductive pattern CDP1 may cover the valley hole lower surface VA-HS, which is a flat surface exposed by the valley hole VA-H. Fig. 9 As shown in FIG, when the valley hole VA-H penetrates only the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, and the sixth insulating layer 60 which are part of the plurality of lower insulating layers 10, 20, 30, 40, 50, and 60, the first conductive pattern CDP1 may contact the upper surface of the second insulating layer 20 exposed by the valley hole VA-H. Alternatively, when the valley hole VA-H penetrates all of the plurality of lower insulating layers 10, 20, 30, 40, 50, and 60 and the buffer layer BFL, the first conductive pattern CDP1 may contact the upper surface of the exposed base layer SUB.

[0242] Meanwhile, the display panel DP according to one or more embodiments may include a first pixel transistor Ta positioned in the first pixel area PXA-1 and a second pixel transistor Tb positioned in the second pixel area PXA-2. In an embodiment, the first pixel transistor Ta may include a first semiconductor pattern SPa and a gate electrode Ga positioned on the first semiconductor pattern SPa, the first semiconductor pattern SPa including a source Sa, a drain Da, and a channel Aa between the source Sa and the drain Da. In an embodiment, the second pixel transistor Tb may include a second semiconductor pattern SPb and a gate electrode Gb positioned on the second semiconductor pattern SPb, the second semiconductor pattern SPb including a source Sb, a drain Db, and a channel Ab between the source Sb and the drain Db. For the above-mentioned first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7 (see Figure 5 ) can be applied to each of the first pixel transistor Ta and the second pixel transistor Tb. Fig. 9 The first pixel transistor Ta and the second pixel transistor Tb are shown Figure 7 The sixth transistor T6 in FIG. 1 has the same structure and setting relationship, but the present disclosure is not limited thereto, and the first pixel transistor Ta and the second pixel transistor Tb may be connected to Figure 7 The third transistor T3 described in has the same structure and setting relationship.

[0243] The display panel DP may further include connection electrodes CNEa1, CNEa2, CNEb1, and CNEb2. The (1-a)th connection electrode CNEa1 may be connected to the drain Da of the first pixel transistor Ta. The (1-a)th connection electrode CNEa1 may be connected to the drain Da of the first pixel transistor Ta through a contact hole penetrating the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, and the sixth insulating layer 60. The (2-a)th connection electrode CNEa2 may be connected to the source Sa of the first pixel transistor Ta. The (2-a)th connection electrode CNEa2 may be connected to the source Sa of the first pixel transistor Ta through a contact hole penetrating the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, and the sixth insulating layer 60. The (1-b)th connection electrode CNEb1 may be connected to the drain Db of the second pixel transistor Tb. The (1-b)th connection electrode CNEb1 may be connected to the drain electrode Db of the second pixel transistor Tb through a contact hole penetrating the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, and the sixth insulating layer 60. The (2-b)th connection electrode CNEb2 may be connected to the source electrode Sb of the second pixel transistor Tb. The (2-b)th connection electrode CNEb2 may be connected to the source electrode Sb of the second pixel transistor Tb through a contact hole penetrating the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, and the sixth insulating layer 60.

[0244] The first conductive pattern CDP1 may be positioned on the same layer as the connection electrodes CNEa1, CNEa2, CNEb1, and CNEb2. The connection electrodes CNEa1, CNEa2, CNEb1, and CNEb2 and the first conductive pattern CDP1 may be spaced apart from each other on the same layer. The connection electrodes CNEa1, CNEa2, CNEb1, and CNEb2 and the first conductive pattern CDP1 may include the same material and may be formed by the same process. In one or more embodiments, the first conductive pattern CDP1 may include aluminum (Al), an alloy containing aluminum, titanium (Ti), an alloy containing titanium, silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), or the like.

[0245] The seventh insulating layer 70 may be positioned on the sixth insulating layer 60. The seventh insulating layer 70 may cover the connection electrodes CNEa1, CNEa2, CNEb1, and CNEb2 and the first conductive pattern CDP1. The seventh insulating layer 70 may fill the inside of the valley hole VA-H to cover the outer side surface of the first conductive pattern CDP1 positioned on the inner side surface of the valley hole VA-H.

[0246] The seventh insulating layer 70 may include a layer portion 70-2 positioned on the sixth insulating layer 60 and a filling portion 70-1 positioned inside the valley hole VA-H. The filling portion 70-1 may be positioned inside the valley hole VA-H to fill the valley hole VA-H, and may cover the outer side surface of the first conductive pattern CDP1 covering the inner side surface of the valley hole VA-H. The layer portion 70-2 and the filling portion 70-1 may have an integral shape. In the display panel according to one or more embodiments, a separate pattern for filling the inside of the valley hole VA-H may not be supplied, and in the process of forming the seventh insulating layer 70 positioned on the sixth insulating layer 60, a portion of the seventh insulating layer 70 including an organic material may fill the inside of the valley hole VA-H, and the rest of the seventh insulating layer 70 may form a layered structure on the sixth insulating layer 60.

[0247] The display panel DP may further include a second conductive pattern CDP2. At least a portion of the second conductive pattern CDP2 may overlap the boundary area BA. A portion of the second conductive pattern CDP2 may overlap the boundary area BA, and the remaining portion of the second conductive pattern CDP2 may overlap each of two adjacent pixel areas PXA-1 and PXA-2 in the second direction DR2. The second conductive pattern CDP2 may electrically connect the first pixel transistor Ta and the second pixel transistor Tb respectively positioned in the two adjacent pixel areas PXA-1 and PXA-2 in the second direction DR2. One end of the second conductive pattern CDP2 may be connected to the (1-a)th connecting electrode CNEa1 to be electrically connected to the drain Da of the first pixel transistor Ta. The other end of the second conductive pattern CDP2 may be connected to the (2-b)th connecting electrode CNEb2 to be electrically connected to the source Sb of the second pixel transistor Tb.

[0248] The second conductive pattern CDP2 may be positioned on the seventh insulating layer 70. The second conductive pattern CDP2 may be connected to the second connection electrode CNE2 (see Figure 7 ) are positioned at the same layer. The second conductive pattern CDP2 and the second connection electrode CNE2 (see Figure 7 ) may include the same materials and may be formed by the same process.

[0249] The eighth insulating layer 80 may be positioned on the seventh insulating layer 70. The eighth insulating layer 80 may cover the second conductive pattern CDP2.

[0250] The display panel according to one or more embodiments may include a boundary area in which a valley hole extending in a first direction is located, and the valley hole may have a shape in which a pixel circuit located in a pixel area is surrounded on both sides relative to a second direction, thereby absorbing an external impact applied to the area surrounded by the valley hole, and reducing or minimizing the transfer of the external impact to the pixel located adjacent thereto. At the same time, the display panel according to one or more embodiments may include a first conductive pattern covering the inner side surface of the valley hole, thereby reducing or preventing the possibility of cracks, etc. being generated in the process of forming the valley hole or in a subsequent process, and reducing or preventing external moisture from being introduced into the lower part of the valley hole. Therefore, the durability and reliability of the display panel can be improved.

[0251] Fig. 10A are plan views of some configurations of display panels according to one or more embodiments of the present disclosure. Fig. 10B and Fig. 10C is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure. Fig. 10A Shown above Fig. 8A The barrier layer BM shown in FIG. 1 is different from the planar shape of the barrier layer BM′ according to one or more embodiments. Fig. 10B and Fig. 10C The display panel according to one or more embodiments is shown. Fig. 9 The cross sections in different cross sections.

[0252] Reference Fig. 10A The barrier layer BM' may include a barrier pattern BML', and the barrier pattern BML' may include a first barrier pattern BMLa and a second barrier pattern BMLb. The barrier layer BM' may include a metal. For example, the barrier layer BM' may include molybdenum.

[0253] As described above, the second barrier pattern BMLb may be positioned below the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 to shield light incident from the outside to the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. In addition, the second barrier pattern BMLb may block light incident from the outside to the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. In addition, the second barrier pattern BMLb may block light incident from the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, the sixth insulating layer 60, the seventh insulating layer 70, and the eighth insulating layer 80 (see Figure 7 ) between the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 (see Figure 5).

[0254] The first barrier pattern BMLa may be positioned to be aligned with the boundary area BA (see Fig. 10B The first barrier pattern BMLa may be included in the same barrier layer BM′ as the second barrier pattern BMLb, may be formed by the same process, and may include the same material as the second barrier pattern BMLb. The first barrier pattern BMLa and the second barrier pattern BMLb may have an integral shape.

[0255] like Fig. 10B As shown in FIG. 1 , the first barrier pattern BMLa may be positioned in the boundary area BA and may overlap the valley hole VA-H in a plane. The first barrier pattern BMLa may overlap the first conductive pattern CDP1 in a plane. The display panel DP according to one or more embodiments (see FIG. 1 ) Figure 7 ) may further include a first barrier pattern BMLa positioned under the first conductive pattern CDP1, so that when a crack is generated in the insulating layer under the valley hole VA-H, the possibility of the crack propagating through the first barrier pattern BMLa is reduced or prevented.

[0256] At the same time, if Fig. 10C As shown in FIG. , the valley hole VA-H may penetrate all of the first to sixth insulating layers 10 , 20 , 30 , 40 , 50 , and 60 , and thus the first conductive pattern CDP1 ′ may at least partially contact the first barrier pattern BMLa.

[0257] The display panel according to one or more embodiments of the present disclosure may include a boundary area in which a valley hole extending in one direction is located, thereby reducing or minimizing the transfer of external impact to pixels located adjacent thereto, and may include a first conductive pattern covering the valley hole, thereby reducing or preventing the possibility of crack propagation or introduction of external moisture. Therefore, the impact resistance and reliability of the display panel and the display device including the display panel can be improved.

[0258] In the above, the preferred embodiments of the present disclosure have been described with reference to, but those skilled in the art or those of ordinary skill in the relevant technical field can understand that various modifications and changes can be made to the present disclosure without departing from the spirit and technical scope of the present disclosure described in the claims. Therefore, the technical scope of the present disclosure is not limited to the contents described in the detailed description of the specification, but should be determined by the claims, and their functional equivalents will be included herein.

Claims

1. A display panel, wherein: The display panel comprises: A substrate layer, the substrate layer comprising: a boundary region extending in a first direction; a first pixel region adjacent to the boundary region in a second direction intersecting the first direction; and a second pixel region spaced apart from the first pixel region, with the boundary region being between the first pixel region and the second pixel region; a plurality of lower insulating layers, located above the base layer, and the plurality of lower insulating layers define valley holes corresponding to the boundary areas; A first conductive pattern including a portion located inside the valley hole; a first organic layer including a portion located above the plurality of lower insulating layers, and the first organic layer also includes a remaining portion covering the first conductive pattern and filling the valley hole; A plurality of pixel circuits respectively overlap the first pixel area and the second pixel area; a plurality of light-emitting elements, located above the first organic layer, the plurality of light-emitting elements respectively overlapping the first pixel region and the second pixel region, and the plurality of light-emitting elements respectively electrically connected to the plurality of pixel circuits; and The second conductive pattern is located above the first organic layer, and the second conductive pattern includes a portion overlapping the boundary region.

2. The display panel according to claim 1, wherein: The plurality of pixel circuits include: a first pixel transistor overlapping the first pixel region; and The second pixel transistor overlaps with the second pixel area.

3. The display panel according to claim 2, wherein: The second conductive pattern electrically connects the first pixel transistor and the second pixel transistor.

4. The display panel according to claim 2, wherein: The first pixel transistor includes: a first semiconductor pattern, the first semiconductor pattern including a first source region, a first drain region, and a first channel region between the first source region and the first drain region, The second pixel transistor includes: a second semiconductor pattern, the second semiconductor pattern includes a second source region, a second drain region and a second channel region between the second source region and the second drain region, wherein one end of the second conductive pattern is electrically connected to the first source region or the first drain region, and The other end of the second conductive pattern is electrically connected to the second source region or the second drain region.

5. The display panel according to claim 4, wherein: Each of the plurality of pixel circuits further includes: a first connection electrode electrically connected to the first source region or the first drain region, and The first conductive pattern and the first connecting electrode are located at the same layer, and the first conductive pattern and the first connecting electrode include the same material.

6. The display panel according to claim 5, wherein: Each of the plurality of pixel circuits further includes: a second connection electrode electrically connected to the first connection electrode, and The second conductive pattern and the second connecting electrode are located at the same layer, and the second conductive pattern and the second connecting electrode include the same material.

7. The display panel according to claim 1, wherein: The first conductive pattern contacts an inner side surface of the valley hole.

8. The display panel according to claim 1, wherein: The valley holes penetrate at least some of the plurality of lower insulating layers, and The lower surface of the valley hole is defined as the upper surface of one of the plurality of lower insulating layers exposed by the valley hole, or the upper surface of the base layer. The lower surface of the valley hole is covered by the first conductive pattern.

9. A display panel, wherein: The display panel comprises: A substrate layer, the substrate layer comprising: a boundary region extending in a first direction; a first pixel region adjacent to the boundary region in a second direction intersecting the first direction; and a second pixel region spaced apart from the first pixel region, with the boundary region being between the first pixel region and the second pixel region; a plurality of lower insulating layers, located above the base layer, and the plurality of lower insulating layers define valley holes corresponding to the boundary areas; A first conductive pattern including a portion located inside the valley hole; a first organic layer including a portion located above the plurality of lower insulating layers, and the first organic layer also includes a remaining portion filling the valley holes and covering the first conductive pattern; a plurality of pixel circuits respectively overlapping the first pixel region and the second pixel region; and a plurality of light-emitting elements, located above the first organic layer, the plurality of light-emitting elements overlap the first pixel region and the second pixel region respectively, and the plurality of light-emitting elements are electrically connected to the plurality of pixel circuits respectively, The first conductive pattern contacts the inner surface of the valley hole and is configured to transmit a power supply voltage.

10. A display device, wherein: The display device includes a first non-folding area, a folding area, and a second non-folding area sequentially arranged along a first direction, and the display device further includes: window; A display panel located below the window; and a housing, located below the display panel to accommodate the display panel, Wherein, the display panel comprises: A base layer, the base layer comprising: a boundary region extending in the first direction; a first pixel region adjacent to the boundary region in a second direction intersecting the first direction; and a second pixel region spaced apart from the first pixel region, and the boundary region is between the first pixel region and the second pixel region; a plurality of lower insulating layers, located above the base layer, and the plurality of lower insulating layers define valley holes corresponding to the boundary areas; A first conductive pattern including a portion located inside the valley hole; a first organic layer including a portion located above the plurality of lower insulating layers, and the first organic layer also includes a remaining portion filling the valley holes and covering the first conductive pattern; a plurality of pixel circuits respectively overlapping the first pixel region and the second pixel region; and A plurality of light emitting elements are located above the first organic layer, the plurality of light emitting elements overlap with the first pixel region and the second pixel region respectively, and the plurality of light emitting elements are electrically connected to the plurality of pixel circuits respectively.

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