Display panel, preparation method thereof and display device

Abstract

The invention provides a display panel, a preparation method thereof and a display device, the display panel comprises a substrate, and a metal layer, a first flat layer, a conductive layer, a second flat layer and a first electrode layer which are stacked in sequence, and the first flat layer comprises a first via hole; the conductive layer is at least partially located in the first via hole; the second flat layer is at least partially located in the first via hole; the first electrode layer is electrically connected with the metal layer through the conductive layer. According to the display panel, the conductive layer and the second flat layer are added, so that the first electrode layer stacked on the second flat layer can extend more flatly, the problem that a film layer of the first electrode layer is easy to break can be solved, and the display quality of the display panel is effectively improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for preparing the same, and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) is an active light-emitting device with a sandwich structure consisting of multiple organic layers and electrodes on both sides. At present, display screens based on AMOLED (Active-matrix organic Light-Emitting Diode) have been commercialized in the fields of smart phones, watches and laptops.

[0003] However, existing display panels are prone to dark spot problems, which affects the display effect. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a display panel and a method for preparing the same, as well as a display device, which are helpful to improve the dark spot abnormality caused by anode breakage and enhance the display quality.

[0005] Based on the above purpose, a first aspect of the present application provides a display panel, including:

[0006] substrate;

[0007] A metal layer is disposed on one side of the substrate,

[0008] A first flat layer, disposed on a side of the metal layer away from the substrate, the first flat layer comprising a first via hole;

[0009] A conductive layer, disposed on a side of the first flat layer away from the substrate, wherein at least a portion of the conductive layer is located in the first via hole;

[0010] A second flat layer is disposed on a side of the conductive layer away from the substrate, and at least a portion of the second flat layer is located in the first via hole;

[0011] The first electrode layer is arranged on a side of the second flat layer away from the substrate, and the first electrode layer is electrically connected to the metal layer through the conductive layer.

[0012] According to an embodiment of the first aspect of the present application, the distance between the surface of the second flat layer away from the substrate and the substrate is greater than or equal to the maximum distance between the surface of the conductive layer away from the substrate and the substrate;

[0013] Preferably, the conductive layer and the second planar layer fill the first via hole.

[0014] According to an implementation of the first aspect of the present application, the first via hole exposes a portion of the metal layer, and a portion of the conductive layer located in the first via hole is electrically connected to the metal layer;

[0015] Preferably, the first via hole comprises a side wall, and the conductive layer covers the side wall;

[0016] Preferably, the orthographic projection of the first via hole on the substrate is located within the orthographic projection of the conductive layer on the substrate;

[0017] Preferably, the material of the conductive layer includes indium tin oxide.

[0018] According to an implementation of the first aspect of the present application, a portion of the conductive layer located outside the first via hole is electrically connected to the first electrode layer;

[0019] Preferably, the orthographic projection of the first via hole on the substrate is located within the orthographic projection of the first electrode layer on the substrate;

[0020] Preferably, an orthographic projection of the first electrode layer on the substrate overlaps with an orthographic projection of the conductive layer on the substrate.

[0021] According to an implementation of the first aspect of the present application, the first electrode layer includes a plurality of first electrodes arranged at intervals, the conductive layer includes a plurality of conductive portions arranged at intervals, the second planar layer includes a plurality of planar portions arranged at intervals, and the orthographic projection of the first via on the substrate is located within the orthographic projection of the planar portion on the substrate;

[0022] Preferably, the orthographic projection of the flat portion on the substrate is located within the orthographic projection of the conductive portion on the substrate, and the orthographic projection of the flat portion on the substrate is located within the orthographic projection of the first electrode on the substrate;

[0023] Preferably, the first via holes correspond to the flat portions one by one;

[0024] Preferably, the number of the first via holes corresponds to the number of the first electrodes;

[0025] Preferably, the first electrode comprises an anode.

[0026] According to an implementation scheme of the first aspect of the present application, the metal layer package is a fifth metal layer; the display panel includes a first metal layer, a second metal layer, a third metal layer and a fourth metal layer stacked in sequence in a direction away from the substrate, and the fifth metal layer is located on a side of the fourth metal layer away from the substrate.

[0027] An embodiment of a second aspect of the present application provides a method for preparing a display panel, including:

[0028] forming a metal layer on one side of the substrate;

[0029] forming a first flat layer on a side of the metal layer away from the substrate, wherein the first flat layer comprises a first via hole;

[0030] forming a conductive layer on a side of the first planar layer away from the substrate, wherein at least a portion of the conductive layer is located in the first via hole;

[0031] forming a second flat layer on a side of the conductive layer away from the substrate, wherein at least a portion of the second flat layer is located in the first via hole;

[0032] A first electrode layer is formed on a side of the second planar layer away from the substrate, and the first electrode layer is electrically connected to the metal layer through the conductive layer.

[0033] According to an implementation of the second aspect of the present application, forming a conductive layer on a side of the first flat layer away from the substrate includes:

[0034] Forming a conductive layer on a side of the first flat layer away from the substrate through a first mask;

[0035] Preferably, forming a first electrode layer on a side of the second flat layer away from the substrate comprises:

[0036] forming a first electrode layer on a side of the second flat layer away from the substrate through the first mask, wherein an orthographic projection of the first electrode layer on the substrate overlaps with an orthographic projection of the conductive layer on the substrate;

[0037] Alternatively, forming a first electrode layer on a side of the second flat layer away from the substrate comprises:

[0038] A first electrode layer is formed on a side of the second planar layer away from the substrate through a second mask.

[0039] According to an implementation of the second aspect of the present application, forming a first flat layer on a side of the metal layer away from the substrate includes:

[0040] Forming a first flat layer on a side of the metal layer away from the substrate by using a third mask and a first photoresist;

[0041] Preferably, forming a second flat layer on a side of the conductive layer away from the substrate comprises:

[0042] Forming a second flat layer on a side of the conductive layer away from the substrate by using the third mask and the second photoresist;

[0043] Wherein, the first photoresist comprises one of a positive photoresist and a negative photoresist, and the second photoresist comprises the other of a positive photoresist and a negative photoresist;

[0044] Alternatively, forming a second flat layer on a side of the conductive layer away from the substrate comprises:

[0045] A second planar layer is formed on a side of the conductive layer away from the substrate through a fourth mask.

[0046] An embodiment of the third aspect of the present application provides a display device, which includes a display panel according to any of the above embodiments, or a display panel prepared according to any of the above embodiments.

[0047] According to the display panel, the method for manufacturing the display panel, and the display device provided by the present application, by adding a conductive layer and a second flat layer, and at least a portion of the conductive layer and the second flat layer are filled in the first via hole, the first electrode layer stacked on the second flat layer can be extended relatively flat, which can improve the problem of easy fracture of the film layer of the first electrode layer, and effectively improve the stability and reliability of the display of the display panel. In addition, the first electrode layer can also be electrically connected to the metal layer through the conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0049] Figure 1 is a schematic diagram of a cross-sectional structure of a related display panel;

[0050] Figure 2 This is a schematic diagram of the cross-sectional structure of a display panel in some embodiments of the present application;

[0051] Figure 3 A schematic diagram of a process for preparing a display panel in some embodiments of the present application;

[0052] Figure 4 A schematic diagram of a cross-sectional structure of a display panel during the preparation process in some embodiments of the present application;

[0053] Figure 5 A schematic diagram of a cross-sectional structure of a display panel during the preparation process in some embodiments of the present application;

[0054] Figure 6 A schematic diagram of a cross-sectional structure of a display panel during the preparation process in some embodiments of the present application;

[0055] Figure 7 A schematic diagram showing a panel during preparation in some embodiments of the present application;

[0056] Figure 8 Schematic diagrams showing the manufacturing process of a display panel in other embodiments of the present application;

[0057] Fig. 9 A schematic cross-sectional view of a display panel during the preparation process in some embodiments of the present application;

[0058] Fig.10 A schematic cross-sectional view of a display panel during the preparation process in some embodiments of the present application;

[0059] Fig.11 A schematic diagram of a planar structure of a display panel during the preparation process in some embodiments of the present application;

[0060] Fig.12 A schematic diagram of a planar structure of a display panel during the preparation process in some embodiments of the present application;

[0061] Fig.13 A schematic diagram of a planar structure of a display panel during the preparation process in some embodiments of the present application;

[0062] Fig.14 A schematic diagram of a planar structure of a display panel during the preparation process in some embodiments of the present application;

[0063] Fig.15 A schematic diagram of a planar structure of a display panel during the preparation process in some embodiments of the present application;

[0064] Fig.16 Schematic diagram of the planar structure of the display panel during the preparation process in other embodiments of the present application;

[0065] Fig.17 Schematic diagram of the planar structure of the display panel during the preparation process in some embodiments of the present application.

[0066] Marking description: 100, display panel;

[0067] 1. Substrate; 2. Metal layer; 3. First flat layer; 31. First via hole; 4. Conductive layer; 5. First electrode layer; 51. First electrode; 6. Second flat layer; 7. Second photoresist; 8. Third mask; 81. Light-transmitting area; 82. Light-shielding area. DETAILED DESCRIPTION

[0068] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0069] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0070] With the continuous development of display technology, the market demand for high PPI (Pixels Per Inch) products is growing. However, high PPI means that the pixel design space is reduced, which leads to a series of technical problems.

[0071] Reference Figure 1 As shown, a related display panel 100 includes a substrate 1 and a metal layer 2, a first flat layer 3 and a first electrode layer 5 stacked in sequence. The first flat layer 3 includes a first via hole 31 for exposing the metal layer 2, and the first electrode layer 5 is electrically connected to the metal layer 2 through the first via hole 31.

[0072] After long-term research, the inventors found that in the related art, the metal layer 2 may not completely cover the edge of the first via hole 31, causing the first via hole 31 to deviate outward (such as Figure 1 If the first electrode layer 5 is formed later, that is, the anode film is formed, the film layer is prone to breakage, resulting in dark spots and affecting the display effect.

[0073] Based on this, the present application provides a display panel solution to solve the above problems.

[0074] Reference Figure 2As shown, a display panel 100 provided in some embodiments of the present application is provided. The display panel 100 includes a substrate 1, a metal layer 2, a first flat layer 3, a conductive layer 4, a second flat layer 6 and a first electrode layer 5. The metal layer 2 is arranged on one side of the substrate 1, the first flat layer 3 is arranged on the side of the metal layer 2 away from the substrate 1, and the first flat layer 3 includes a first via hole 31. The conductive layer 4 is arranged on the side of the first flat layer 3 away from the substrate 1, and the conductive layer 4 is at least partially located in the first via hole 31. The second flat layer 6 is arranged on the side of the conductive layer 4 away from the substrate 1, and the second flat layer 6 is at least partially located in the first via hole 31. The first electrode layer 5 is arranged on the side of the second flat layer 6 away from the substrate 1, and the first electrode layer 5 is electrically connected to the metal layer 2 through the conductive layer 4.

[0075] Specifically, the first via hole 31 penetrates the first planar layer 3 in a direction perpendicular to the substrate 1 (i.e., the thickness direction of the display panel 100), and the first via hole 31 can expose a portion of the metal layer 2. The portion of the conductive layer 4 located in the first via hole 31 contacts the portion of the metal layer 2 exposed in the first via hole 31 to form an electrical connection. At the same time, the conductive layer 4 also contacts the first electrode layer 5 to form an electrical connection. In addition, the conductive layer 4 and the second planar layer 6 partially fill or completely fill the first via hole 31.

[0076] The display panel 100 provided in the present application adds a conductive layer 4 and a second flat layer 6, and at least a portion of the conductive layer 4 and the second flat layer 6 are filled in the first via hole 31, so that the first electrode layer 5 stacked on the second flat layer 6 can extend relatively flatly, which can improve the problem of easy fracture of the film layer of the first electrode layer 5, and effectively improve the stability and reliability of the display panel 100. In addition, the conductive layer 4 can also meet the electrical connection requirements of the first electrode layer 5 and the metal layer 2.

[0077] Reference Figure 2 As shown, in some embodiments, the distance between the surface of the second flat layer 6 away from the substrate 1 and the substrate 1 is equal to the maximum distance between the surface of the conductive layer 4 away from the substrate 1 and the substrate 1. Fig.10 As shown, in some other embodiments, the distance between the surface of the second flat layer 6 away from the substrate 1 and the substrate 1 is greater than the maximum distance between the surface of the conductive layer 4 away from the substrate 1 and the substrate 1 .

[0078] Optionally, the conductive layer 4 and the second planar layer 6 fill the first via hole 31 .

[0079] The first via hole 31 can be filled by utilizing the hole-filling function of the second planar layer 6 , thereby ensuring the flatness and insulation performance of the surface and providing a good foundation for the formation of the first electrode layer.

[0080] Reference Figure 2As shown, in some embodiments, the first via hole 31 exposes a portion of the metal layer 2 , and a portion of the conductive layer 4 located in the first via hole 31 is electrically connected to the metal layer 2 .

[0081] Optionally, the first via hole 31 includes a side wall, and the conductive layer 4 covers the side wall.

[0082] Optionally, the orthographic projection of the first via hole 31 on the substrate 1 is located within the orthographic projection of the conductive layer 4 on the substrate 1 .

[0083] Specifically, the first via hole 31 has a bottom, and the side plate is located around the bottom. The bottom of the first via hole 31 exposes a portion of the metal layer 2, thereby contacting the conductive layer 4 to form an electrical connection. The first via hole 31 is located within the coverage of the conductive layer 4, and the conductive layer 4 covers the bottom and side walls of the first via hole 31. A portion of the conductive layer 4 contacts the metal layer 2, a portion contacts the side walls of the first via hole 31, and another portion covers the outside of the first via hole 31 on the first planar layer 3 and contacts the first electrode layer 5.

[0084] Optionally, the material of the conductive layer 4 includes indium tin oxide (ITO).

[0085] Reference Figure 2 As shown, in some embodiments, the portion of the conductive layer 4 outside the first via hole 31 is electrically connected to the first electrode layer 5 .

[0086] Optionally, the orthographic projection of the first via hole 31 on the substrate 1 is located within the orthographic projection of the first electrode layer 5 on the substrate 1 .

[0087] Optionally, the orthographic projection of the first electrode layer 5 on the substrate 1 overlaps with the orthographic projection of the conductive layer 4 on the substrate 1. The coverage of the first electrode layer 5 is the same as that of the conductive layer 4, and the same mask can be used in the preparation process.

[0088] Reference Fig.15 As shown, in some embodiments, the first electrode layer 5 includes a plurality of first electrodes 51 disposed at intervals. 5 / 51 in the figure refers to both the first electrode layer 5 and the first electrode 51. At the same time, the conductive layer 4 includes a plurality of conductive portions disposed at intervals, the second flat layer 6 includes a plurality of flat portions disposed at intervals, and the orthographic projection of the first via 31 on the substrate 1 is located within the orthographic projection of the flat portion on the substrate 1.

[0089] Optionally, the orthographic projection of the flat portion on the substrate 1 is located within the orthographic projection of the conductive portion on the substrate 1 , and the orthographic projection of the flat portion on the substrate 1 is located within the orthographic projection of the first electrode 51 on the substrate 1 .

[0090] Optionally, the first via holes 31 correspond to the flat portions one by one. Optionally, the first via holes 31 correspond to the first electrodes 51 one by one.

[0091] Optionally, the first electrode 51 includes an anode.

[0092] Specifically, the first electrode layer 5 can be used to form a first electrode 51, which is the anode of the light-emitting device and can cooperate with the cathode to drive the light-emitting layer of the light-emitting device to emit light. The anode plays an important role in realizing the display function, and its stability will directly affect the display effect.

[0093] In some embodiments, the metal layer 2 is a fifth metal layer, and the display panel 100 includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer stacked in sequence in a direction away from the substrate 1, and the fifth metal layer is located on a side of the fourth metal layer away from the substrate 1. An insulating layer is provided between any two metal layers, that is, an insulating layer is provided between the first metal layer and the second metal layer, between the second metal layer and the third metal layer, between the third metal layer and the fourth metal layer, and between the fourth metal layer and the fifth metal layer.

[0094] Exemplarily, the first metal layer M1 can be used to form the gate of the thin film transistor, the second metal layer M2 can be used to form one of the plates (such as the upper plate) of the storage capacitor, the third metal layer M3 can be used to form the connection structure of the source and / or drain of the thin film transistor, and the fourth metal layer M4 can be used to form the signal routing. The fifth metal layer M5 can be used to transmit power signals or other signals.

[0095] In some embodiments, the metal layer 2 may include a stacked structure of Ti, Al, and Ti, which may provide a stable electrical basis and support for the overall structure. The first flat layer 3 and the second flat layer 6 may be conventional organic film layers, for example, including polyimide (PI) materials. Polyimide has good insulation, mechanical strength, and thermal stability, and can effectively fill the surface to ensure good contact and flatness between the layers, providing a stable basis for subsequent film formation. The first electrode layer 5 may include a stacked structure of ITO, Ag, and ITO, wherein indium tin oxide (ITO) has both good conductivity and transparency, and can achieve effective charge transfer. Silver (Ag) has high conductivity, which optimizes the electrical properties of the anode.

[0096] Based on the same inventive concept, Figure 3 As shown, some other embodiments of the present application provide a method for preparing a display panel, which can be used to prepare the display panel 100 provided in the above embodiment. The method for preparing a display panel includes:

[0097] Step S10: forming a metal layer 2 on one side of the substrate 1, as shown in FIG. Fig.11 .

[0098] Step S20: forming a first flat layer 3 on the side of the metal layer 2 away from the substrate 1. The first flat layer 3 includes a first via hole 31. Figure 4 and Fig.12 .

[0099] Step S30: forming a conductive layer 4 on a side of the first flat layer 3 away from the substrate 1, wherein the conductive layer 4 is at least partially located in the first via hole 31. Figure 5 and Fig.13 .

[0100] Step S40: forming a second flat layer 6 on the side of the conductive layer 4 away from the substrate 1, wherein at least a portion of the second flat layer 6 is located in the first via hole 31. Fig.10 and Fig.14 .

[0101] Step S50: forming a first electrode layer 5 on the side of the second flat layer 6 away from the substrate 1. The first electrode layer 5 is electrically connected to the metal layer 2 through the conductive layer 4. Figure 2 and Fig.15 .

[0102] The manufacturing method of the display panel 100 provided in the present application adds a conductive layer 4 and a second flat layer 6, and at least a portion of the conductive layer 4 and the second flat layer 6 are filled in the first via hole 31, so that the first electrode layer 5 stacked on the second flat layer 6 can extend relatively flatly, which can improve the problem of easy fracture of the film layer of the first electrode layer 5, and effectively improve the stability and reliability of the display panel 100. In addition, the conductive layer 4 can also meet the electrical connection requirements of the first electrode layer 5 and the metal layer 2.

[0103] In some embodiments, step S30, forming a conductive layer 4 on a side of the first planar layer 3 away from the substrate 1, comprises:

[0104] A conductive layer 4 is formed on a side of the first planar layer 3 away from the substrate 1 through a first mask.

[0105] Optionally, step S50, forming a first electrode layer 5 on a side of the second planar layer 6 away from the substrate 1, comprises:

[0106] Through the first mask, a first electrode layer 5 is formed on the side of the second flat layer 6 away from the substrate 1. The orthographic projection of the formed first electrode layer 5 on the substrate 1 overlaps with the orthographic projection of the conductive layer 4 on the substrate 1. Fig.16 .

[0107] The conductive layer 4 and the first electrode layer 5 share a first mask, which can reduce costs.

[0108] Alternatively, in some other embodiments, step S50, forming the first electrode layer 5 on a side of the second planar layer 6 away from the substrate 1, comprises:

[0109] Through the second mask, a first electrode layer 5 is formed on the side of the second flat layer 6 away from the substrate 1, which can be referred to Fig.15 .

[0110] Among them, adding a conductive layer 4 and a second mask plate at the same time can better ensure the pattern accuracy.

[0111] In some embodiments, step S20, forming a first flat layer 3 on a side of the metal layer 2 away from the substrate 1, comprises:

[0112] A first planar layer 3 is formed on the side of the metal layer away from the substrate 1 by using the third mask 8 and the first photoresist.

[0113] Optionally, step S40, forming a second planar layer 6 on a side of the conductive layer 4 away from the substrate 1, comprises:

[0114] Through the fourth mask, a second flat layer 6 is formed on the side of the conductive layer 4 away from the substrate 1. The second flat layer 6 is added, and a fourth mask is added at the same time, which can better ensure the pattern accuracy.

[0115] Alternatively, in some other embodiments, step S40, forming the second planar layer 6 on the side of the conductive layer 4 away from the substrate 1, comprises:

[0116] A second planarization layer 6 is formed on the side of the conductive layer 4 away from the substrate 1 by means of a third mask 8 and a second photoresist 7 .

[0117] The first photoresist includes one of a positive photoresist and a negative photoresist, and the second photoresist 7 includes the other of a positive photoresist and a negative photoresist.

[0118] Exemplarily, the third mask 8 includes a light-transmitting region 81 and a light-shielding region 82 .

[0119] refer to Figure 6 , Figure 7 , Fig. 9 In some embodiments, the orthographic projection of the light-transmitting region 81 on the substrate 1 at least partially overlaps with the orthographic projection of the first via hole 31 on the substrate 1. That is, the position of the light-transmitting region 81 corresponds to the first via hole 31, and the light-shielding region 82 at least partially surrounds the light-transmitting region 81. Accordingly, the first photoresist uses a positive photoresist, and the second photoresist 7 uses a negative photoresist. When the negative photoresist is exposed, the portion corresponding to the light-transmitting region 81 undergoes a cross-linking or polymerization reaction, so that the photoresist is hardened and retained, and the unexposed region is removed during development, thereby retaining the second photoresist 7 and the portion of the second planar layer 6 corresponding to the first via hole 31.

[0120] refer to Figure 6 , Figure 8 , Fig. 9 In other embodiments, the position of the light shielding region 82 corresponds to the first via hole 31, and the light-transmitting region 81 at least partially surrounds the light shielding region 82. Accordingly, the first photoresist uses a negative photoresist, and the second photoresist 7 uses a positive photoresist. After exposure, the positive photoresist will undergo reactions such as decomposition or dissolution in the portion exposed to light, causing this portion of the film layer to be removed in the subsequent development process, thereby retaining the second photoresist 7 and the portion of the second planar layer 6 corresponding to the first via hole 31.

[0121] In some preferred embodiments, a first mask is shared during the manufacturing process of the conductive layer 4 and the first electrode layer 5, which can reduce costs. A third mask 8 is shared during the manufacturing process of the first flat layer 3 and the second flat layer 6, and the first photoresist and the second photoresist 7 use photoresists with opposite characteristics, which further reduces costs. Therefore, in the present application, four masks can be used during the manufacturing process of the first flat layer 3, the conductive layer 4, the first electrode layer 5, and the second flat layer 6, or three masks or two masks can be used, which provides solutions with different focuses for the problem of anode fracture of high PPI products.

[0122] The specific structure, materials, mechanism, etc. of the display panel 100 prepared in the method for preparing the display panel of this embodiment can refer to the above-mentioned display panel embodiment, and will not be described in detail here.

[0123] Another embodiment of the present application provides a display device, which includes the display panel 100 in the above embodiment. The display device can be on a smart device (such as a mobile phone, VR device, computer, television, car display, etc.).

[0124] The display device provided in the present application has a display panel 100 with an additional conductive layer 4 and a second flat layer 6, and at least a portion of the conductive layer 4 and the second flat layer 6 are filled in the first via hole 31, so that the first electrode layer 5 stacked on the second flat layer 6 can extend relatively flatly, which can improve the problem of easy breakage of the film layer of the first electrode layer 5, and effectively improve the stability and reliability of the display panel 100. In addition, the conductive layer 4 can also meet the electrical connection requirements of the first electrode layer 5 and the metal layer 2.

[0125] Although the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description.

[0126] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0127] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises: substrate; A metal layer is disposed on one side of the substrate, A first flat layer, disposed on a side of the metal layer away from the substrate, the first flat layer comprising a first via hole; A conductive layer, disposed on a side of the first flat layer away from the substrate, wherein at least a portion of the conductive layer is located in the first via hole; A second flat layer is disposed on a side of the conductive layer away from the substrate, and at least a portion of the second flat layer is located in the first via hole; The first electrode layer is arranged on a side of the second flat layer away from the substrate, and the first electrode layer is electrically connected to the metal layer through the conductive layer.

2. The display panel according to claim 1, characterized in that: The distance between the surface of the second flat layer away from the substrate and the substrate is greater than or equal to the maximum distance between the surface of the conductive layer away from the substrate and the substrate; Preferably, the conductive layer and the second planar layer fill the first via hole.

3. The display panel according to claim 1, characterized in that: The first via hole exposes a portion of the metal layer, and a portion of the conductive layer located in the first via hole is electrically connected to the metal layer; Preferably, the first via hole comprises a side wall, and the conductive layer covers the side wall; Preferably, the orthographic projection of the first via hole on the substrate is located within the orthographic projection of the conductive layer on the substrate; Preferably, the material of the conductive layer includes indium tin oxide.

4. The display panel according to claim 1, characterized in that: The portion of the conductive layer outside the first via hole is electrically connected to the first electrode layer; Preferably, the orthographic projection of the first via hole on the substrate is located within the orthographic projection of the first electrode layer on the substrate; Preferably, an orthographic projection of the first electrode layer on the substrate overlaps with an orthographic projection of the conductive layer on the substrate.

5. The display panel according to claim 1, characterized in that: The first electrode layer includes a plurality of first electrodes arranged at intervals, the conductive layer includes a plurality of conductive portions arranged at intervals, the second flat layer includes a plurality of flat portions arranged at intervals, and the orthographic projection of the first via on the substrate is located within the orthographic projection of the flat portion on the substrate; Preferably, the orthographic projection of the flat portion on the substrate is located within the orthographic projection of the conductive portion on the substrate, and the orthographic projection of the flat portion on the substrate is located within the orthographic projection of the first electrode on the substrate; Preferably, the first via holes correspond to the flat portions one by one; Preferably, the first via holes correspond to the first electrodes one by one; Preferably, the first electrode comprises an anode.

6. The display panel according to claim 1, characterized in that: The metal layer is a fifth metal layer; The display panel includes a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are sequentially stacked in a direction away from the substrate, and the fifth metal layer is located on a side of the fourth metal layer away from the substrate.

7. A method for preparing a display panel, characterized in that: The method comprises: forming a metal layer on one side of the substrate; forming a first flat layer on a side of the metal layer away from the substrate, wherein the first flat layer comprises a first via hole; forming a conductive layer on a side of the first planar layer away from the substrate, wherein at least a portion of the conductive layer is located in the first via hole; forming a second flat layer on a side of the conductive layer away from the substrate, wherein at least a portion of the second flat layer is located in the first via hole; A first electrode layer is formed on a side of the second planar layer away from the substrate, and the first electrode layer is electrically connected to the metal layer through the conductive layer.

8. The method for preparing a display panel according to claim 7, characterized in that: The forming of a conductive layer on a side of the first flat layer away from the substrate comprises: Forming a conductive layer on a side of the first flat layer away from the substrate through a first mask; Preferably, forming a first electrode layer on a side of the second flat layer away from the substrate comprises: forming a first electrode layer on a side of the second flat layer away from the substrate through the first mask, wherein an orthographic projection of the first electrode layer on the substrate overlaps with an orthographic projection of the conductive layer on the substrate; Alternatively, forming a first electrode layer on a side of the second flat layer away from the substrate comprises: A first electrode layer is formed on a side of the second planar layer away from the substrate through a second mask.

9. The method for preparing a display panel according to claim 7, characterized in that: The step of forming a first flat layer on a side of the metal layer away from the substrate comprises: Forming a first flat layer on a side of the metal layer away from the substrate by using a third mask and a first photoresist; Preferably, forming a second flat layer on a side of the conductive layer away from the substrate comprises: Forming a second flat layer on a side of the conductive layer away from the substrate by using the third mask and the second photoresist; Wherein, the first photoresist comprises one of a positive photoresist and a negative photoresist, and the second photoresist comprises the other of a positive photoresist and a negative photoresist; Alternatively, forming a second flat layer on a side of the conductive layer away from the substrate comprises: A second planar layer is formed on a side of the conductive layer away from the substrate through a fourth mask.

10. A display device, characterized in that: A display panel comprising any one of claims 1-6, or a display panel obtained by the preparation method according to any one of claims 7-9.

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