Display device

Abstract

There is provided a display device including: a substrate including a display area in which a display element is arranged; a first thin film transistor disposed in the display area and including a first semiconductor layer including silicon and a first control electrode insulated from the first semiconductor layer; a first interlayer insulating layer covering the first control electrode; a second thin film transistor disposed on the first interlayer insulating layer and including a second semiconductor layer including an oxide semiconductor and a second control electrode insulated from the second semiconductor layer; a second interlayer insulating layer covering the second control electrode; a node connection line disposed on the second interlayer insulating layer and connected to the first control electrode via the first contact hole; a first planarization layer covering the node connection lines; and a shield electrode disposed on the first planarization layer to overlap the node connection line.

Description

[0001] This application is a divisional application of a patent application with an application date of July 22, 2020, application number 202010712686.2, and title “Display Device”. Technical Field

[0002] The present invention relates to a display device, and more particularly, to a display device driven by using a thin film transistor including a silicon semiconductor layer and a thin film transistor including an oxide semiconductor layer. Background Art

[0003] A display device typically includes a display element and a driving circuit that controls an electrical signal applied to the display element. The driving circuit includes a thin film transistor (TFT), a storage capacitor, and a plurality of lines.

[0004] In order to precisely control whether or not a display element emits light or the degree of light emission, the number of thin film transistors electrically connected to one display element has increased. Therefore, research on solving the high integration and high power consumption of display devices is actively being conducted. Summary of the invention

[0005] One or more embodiments include a display device driven by a thin film transistor including a silicon semiconductor and a thin film transistor including an oxide semiconductor to reduce power consumption of the display device while allowing high integration.

[0006] However, the above-mentioned objects are exemplary, and the scope of the present disclosure is not limited thereto.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosed presented embodiments.

[0008] According to an exemplary embodiment of the present invention, a display device includes: a substrate including a display area in which a display element is arranged; a first thin film transistor arranged in the display area and including a first semiconductor layer including silicon and a first control electrode insulated from the first semiconductor layer; a first interlayer insulating layer covering the first control electrode; a second thin film transistor arranged on the first interlayer insulating layer and including a second semiconductor layer including an oxide semiconductor and a second control electrode insulated from the second semiconductor layer; a second interlayer insulating layer covering the second control electrode; a node connection line arranged on the second interlayer insulating layer and connected to the first control electrode via a first contact hole; a first planarization layer covering the node connection line; and a shielding electrode arranged on the first planarization layer to overlap with the node connection line.

[0009] According to an exemplary embodiment of the present invention, a display device includes: a substrate including a display area in which a display element is arranged; a first thin film transistor arranged in the display area and including a silicon semiconductor layer and a first control electrode insulated from the silicon semiconductor layer; a first interlayer insulating layer covering the first control electrode; a second thin film transistor arranged on the first interlayer insulating layer and including an oxide semiconductor layer and a second control electrode insulated from the oxide semiconductor layer; and a boost capacitor including a lower electrode and an upper electrode. The lower electrode and the first control electrode are arranged on a first layer and the upper electrode and the oxide semiconductor layer are arranged on a second layer different from the first layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the disclosed specific embodiments will become more apparent through the following description taken in conjunction with the accompanying drawings, in which: Figure 1 is a schematic diagram of a display device according to an embodiment; Figure 2 is a schematic diagram of a display device according to an embodiment; Figure 3 is an equivalent circuit diagram of a pixel included in a display device according to an embodiment; Figure 4 is a layout diagram showing positions of a plurality of thin film transistors and storage capacitors arranged in a pixel; Figure 5A yes Figure 4 An extract layout diagram of some of the components shown in; Figure 5B is an excerpted layout diagram of some components of a display device according to an embodiment; Figure 5C is an excerpted layout diagram of some components of a display device according to an embodiment; Figure 6 yes Figure 4 A schematic cross-sectional view taken along line II'; Figure 7 yes Figure 4 A schematic cross-sectional view taken along line II-II'; Figure 8 is a cross-sectional view of a display device according to an embodiment; and Fig. 9 is a cross-sectional view of a display device according to an embodiment. DETAILED DESCRIPTION

[0011] Now will be referred to in detail embodiment, the example of embodiment is shown in the accompanying drawings, and the same reference numerals in the accompanying drawings always represent the same elements. In this regard, the present embodiment can have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiment is described below only by reference to the accompanying drawings to explain the aspects of the description given. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. Throughout the disclosure, the expression "at least one / kind of a, b and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c or their combination.

[0012] The embodiments will be described in more detail below with reference to the accompanying drawings. Regardless of the figure numbers, those components that are the same or corresponding are denoted by the same reference numerals, and repeated descriptions thereof will be omitted.

[0013] It will be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component.

[0014] Unless otherwise defined by the context, a singular expression also includes a plural expression.

[0015] In the following embodiments, it will also be understood that the terms “including” and / or “having” used herein specify the presence of stated features or components, but do not exclude the presence or addition of one or more other features or components.

[0016] In the following embodiments, it will be understood that when a part such as a layer, region or element is referred to as being “on” or “over” another part, it may be directly on or over the other part or intervening parts may also be present.

[0017] In addition, in the drawings, the size of the elements may be exaggerated or reduced for convenience of description. In other words, since the size and thickness of the elements in the drawings are arbitrarily shown for convenience of explanation, the following embodiments are not limited thereto.

[0018] When the embodiment is implemented in another manner, the predetermined process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or may be performed in a sequence opposite to the described sequence.

[0019] In the following embodiments, when a layer, region, or element is "connected", it can be interpreted that the layer, region, or element is not only directly connected, but also indirectly connected through other constituent elements therebetween. For example, when a layer, region, element, etc. is described as being electrically connected, the layer, region, element, etc. can be not only directly electrically connected, but also indirectly electrically connected through another layer, region, element, etc. therebetween.

[0020] Figure 1 and Figure 2 is a schematic diagram of a display device according to an embodiment.

[0021] The substrate 110 may be divided into a display area DA displaying an image and a peripheral area PA disposed around the display area DA.

[0022] The substrate 110 may include various materials such as glass, metal or plastic. According to an embodiment, the substrate 110 may include a flexible material. The flexible material refers to a substrate that is easily bent and curved or folded or rolled. The substrate 110 formed of the flexible material as described above may include ultra-thin glass, metal or plastic.

[0023] In the display area DA of the substrate 110, pixels PX including various display elements such as organic light emitting diodes (OLEDs) may be arranged. A plurality of pixels PX are included and may be arranged in various forms such as stripe arrangement, pentile arrangement, mosaic arrangement, etc. to realize an image.

[0024] In a plan view, the display area DA may have a Figure 1 The rectangular shape shown in or Figure 2 According to another embodiment, the display area DA may have a polygonal shape such as a triangle, a pentagon, a hexagon, etc., or an elliptical shape, an irregular shape, etc.

[0025] The peripheral area PA of the substrate 110 is arranged around the display area DA and may be an area where no image is displayed. In the peripheral area PA, pads ("pads", or referred to as pads) on which various lines transmitting electrical signals to be applied to the display area DA, a printed circuit board, or a driving integrated circuit (IC) chip are attached may be located.

[0026] Hereinafter, for convenience, a display device including an organic light emitting diode as a display element will be described. However, the embodiment may be applied to various types of display devices such as a liquid crystal display device, an electrophoretic display device, an inorganic electroluminescent (EL) display device, etc.

[0027] Figure 3 is an equivalent circuit diagram of a pixel included in the display device according to the embodiment.

[0028] Reference Figure 3 , the pixel PX includes signal lines SL1, SL2, SLp, SLn, 133 and 171, a plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7 connected to the signal lines SL1, SL2, SLp, SLn, 133 and 171, a storage capacitor Cst, a boost capacitor Cbt, an initialization voltage line VIL, a driving voltage line 165 and an organic light emitting diode OLED as a display element. In some embodiments, at least one of the signal lines SL1, SL2, SLp, SLn, 133 and 171 and the initialization voltage line VIL or / and the driving voltage line 165 may be shared between adjacent pixels PX.

[0029] The thin film transistors may include a driving thin film transistor T1 , a switching thin film transistor T2 , a compensation thin film transistor T3 , a first initialization thin film transistor T4 , an operation control thin film transistor T5 , an emission control thin film transistor T6 , and a second initialization thin film transistor T7 .

[0030] Some of the plurality of thin film transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 may be n-channel metal oxide semiconductor field effect transistors (MOSFET) (NMOS), and the others may be p-channel metal oxide semiconductor field effect transistors (MOSFET) (PMOS).

[0031] For example, Figure 3 As shown in FIG. 1 , the compensation thin film transistor T3 and the first initialization thin film transistor T4 from among the plurality of thin film transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 may be NMOS, and the other thin film transistors may be PMOS.

[0032] According to another embodiment, the compensation thin film transistor T3, the first initialization thin film transistor T4, and the second initialization thin film transistor T7 from among the plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7 may be NMOS, and the other thin film transistors may be PMOS. Alternatively, only one of the plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7 may be NMOS, and the other thin film transistors may be PMOS. Alternatively, all of the plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7 may be NMOS.

[0033] The signal lines SL1, SL2, SLp, SLn, 133 and 171 may include a first scan line SL1 that transmits a first scan signal Sn, a second scan line SL2 that transmits a second scan signal Sn', a previous scan line SLp that transmits a previous scan signal Sn-1 to a first initialization thin film transistor T4, an emission control line 133 that transmits an emission control signal En to an operation control thin film transistor T5 and an emission control thin film transistor T6, a next scan line SLn that transmits a next scan signal Sn+1 to a second initialization thin film transistor T7, and a data line 171 that crosses the first scan line SL1 and transmits a data signal Dm.

[0034] The driving voltage line 165 transmits the driving voltage ELVDD to the driving thin film transistor T1 , and the initialization voltage line VIL transmits the initialization voltage Vint for initializing the driving thin film transistor T1 and the pixel electrode.

[0035] Each of the thin film transistors T1 to T7 may include a control electrode, a first electrode, and a second electrode. The control electrode may be a gate electrode. In addition, one of the first electrode and the second electrode may correspond to a source electrode, and the other may correspond to a drain electrode.

[0036] The driving control electrode of the driving thin film transistor T1 is connected to the storage capacitor Cst, the driving first electrode of the driving thin film transistor T1 is electrically connected to the driving voltage line 165 via the operation control thin film transistor T5, and the driving second electrode of the driving thin film transistor T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm according to the switching operation of the switching thin film transistor T2 to supply the driving current I through the organic light emitting diode OLED. OLED .

[0037] A switch control electrode of the switching thin film transistor T2 is connected to the first scan line SL1, a switch first electrode of the switching thin film transistor T2 is connected to the data line 171, a switch second electrode of the switching thin film transistor T2 is connected to the driving first electrode of the driving thin film transistor T1 and is connected to the driving voltage line 165 via the operation control thin film transistor T5. The switching thin film transistor T2 is turned on according to the first scan signal Sn received via the first scan line SL1 to perform a switching operation of transmitting the data signal Dm transmitted to the data line 171 to the driving first electrode of the driving thin film transistor T1.

[0038] The compensation control electrode of the compensation thin film transistor T3 is connected to the second scan line SL2. The compensation second electrode of the compensation thin film transistor T3 is connected to the driving second electrode of the driving thin film transistor T1 and is electrically connected to the pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6. The compensation first electrode of the compensation thin film transistor T3 is connected to the first electrode CE1 of the storage capacitor Cst and the driving control electrode of the driving thin film transistor T1 via the node connection line 166. In addition, the compensation first electrode is connected to the first initialization second electrode of the first initialization thin film transistor T4.

[0039] The compensation thin film transistor T3 is turned on according to the second scan signal Sn′ received via the second scan line SL2 to electrically connect the driving control electrode of the driving thin film transistor T1 to the driving second electrode of the driving thin film transistor T1 , thereby making the driving thin film transistor T1 diode-connected.

[0040] The first initialization control electrode of the first initialization thin film transistor T4 is connected to the previous scan line SLp. The first initialization first electrode of the first initialization thin film transistor T4 is connected to the second initialization first electrode of the second initialization thin film transistor T7 and the initialization voltage line VIL. The first initialization second electrode of the first initialization thin film transistor T4 is connected to the first electrode CE1 of the storage capacitor Cst, the compensation first electrode of the compensation thin film transistor T3, and the driving control electrode of the driving thin film transistor T1. The first initialization thin film transistor T4 is turned on according to the previous scan signal Sn-1 received via the previous scan line SLp to perform an initialization operation of transmitting the initialization voltage Vint to the driving control electrode of the driving thin film transistor T1 so that the voltage of the driving control electrode of the driving thin film transistor T1 is initialized.

[0041] An operation control electrode of the operation control thin film transistor T5 is connected to the emission control line 133, an operation control first electrode of the operation control thin film transistor T5 is connected to the driving voltage line 165, and an operation control second electrode of the operation control thin film transistor T5 is connected to the driving first electrode of the driving thin film transistor T1 and the switching second electrode of the switching thin film transistor T2.

[0042] The emission control electrode of the emission control thin film transistor T6 is connected to the emission control line 133, the emission control first electrode of the emission control thin film transistor T6 is connected to the driving second electrode of the driving thin film transistor T1 and the compensation second electrode of the compensation thin film transistor T3, and the emission control second electrode of the emission control thin film transistor T6 is electrically connected to the second initialization second electrode of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0043] The operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on according to the emission control signal En received via the emission control line 133, so that the driving voltage ELVDD is transmitted to the organic light emitting diode OLED, thereby making the driving current I OLED Flow through the organic light emitting diode OLED.

[0044] The second initialization control electrode of the second initialization thin film transistor T7 is connected to the next scan line SLn, the second initialization second electrode of the second initialization thin film transistor T7 is connected to the emission control second electrode of the emission control thin film transistor T6 and the pixel electrode of the organic light emitting diode OLED, and the second initialization first electrode of the second initialization thin film transistor T7 is connected to the first initialization first electrode of the first initialization thin film transistor T4 and the initialization voltage line VIL. The second initialization thin film transistor T7 is turned on according to the next scan signal Sn+1 received via the next scan line SLn to initialize the pixel electrode of the organic light emitting diode OLED.

[0045] The second initialization thin film transistor T7 may be Figure 3 According to another embodiment, the second initialization thin film transistor T7 may be connected to the emission control line 133 to be driven according to the emission control signal En. Figure 3 The positions of the first electrode and the second electrode may be exchanged depending on the type (p-type or n-type) of the transistor.

[0046] The storage capacitor Cst includes a first electrode CE1 and a second electrode CE2. The first electrode CE1 of the storage capacitor Cst is connected to the driving control electrode of the driving thin film transistor T1, and the second electrode CE2 of the storage capacitor Cst is connected to the driving voltage line 165. The storage capacitor Cst may store a voltage corresponding to a difference between a voltage of the driving control electrode of the driving thin film transistor T1 and the driving voltage ELVDD.

[0047] The boosting capacitor Cbt includes a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 may be connected to the switch control electrode of the switching thin film transistor T2 and the first scan line SL1, and the fourth electrode CE4 may be connected to the compensation first electrode of the compensation thin film transistor T3 and the node connection line 166. The boosting capacitor Cbt may boost the voltage of the first node N1 when the first scan signal Sn supplied to the first scan line SL1 is turned off. When the voltage of the first node N1 is boosted, a black grayscale may be clearly represented.

[0048] The first node N1 may be a region at which a driving control electrode of the driving thin film transistor T1 , a first electrode of the compensation thin film transistor T3 , a second electrode of the first initialization thin film transistor T4 , and a fourth electrode CE4 of the boosting capacitor Cbt are connected.

[0049] A detailed operation of each pixel PX according to an embodiment is as follows.

[0050] During the initialization period, when the previous scan signal Sn-1 is supplied through the previous scan line SLp, the first initialization thin film transistor T4 is turned on according to the previous scan signal Sn-1, and the driving thin film transistor T1 is initialized by the initialization voltage Vint supplied through the initialization voltage line VIL.

[0051] During the data programming period, when the first scan signal Sn and the second scan signal Sn' are supplied via the first scan line SL1 and the second scan line SL2, the switching thin film transistor T2 and the compensation thin film transistor T3 are turned on in response to the first scan signal Sn and the second scan signal Sn', respectively. The driving thin film transistor T1 is diode-connected via the turned-on compensation thin film transistor T3 and biased in the forward direction.

[0052] Then, a compensation voltage (Dm+Vth, Vth having a (−) value) which is a result of subtracting the threshold voltage Vth of the driving thin film transistor T1 from the data signal Dm supplied through the data line 171 is applied to the driving control electrode of the driving thin film transistor T1 .

[0053] The driving voltage ELVDD and the compensation voltage (Dm+Vth) are applied to the opposite electrodes of the storage capacitor Cst, and charges corresponding to a voltage difference between the opposite electrodes of the storage capacitor Cst are stored in the storage capacitor Cst.

[0054] During the emission period, the operation control thin film transistor T5 and the emission control thin film transistor T6 are turned on according to the emission control signal En supplied from the emission control line 133. The driving current I OLED The driving current I is generated according to the voltage difference between the voltage of the driving control electrode of the driving thin film transistor T1 and the driving voltage ELVDD. OLED The electric current flows through the organic light emitting diode OLED and the emission control thin film transistor T6.

[0055] In this embodiment, at least one of the plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7 includes a semiconductor layer including oxide (ie, an oxide semiconductor layer), and the other thin film transistors include a semiconductor layer including silicon (ie, a silicon semiconductor layer).

[0056] In detail, a driving thin film transistor directly affecting the brightness of a display device is configured to include a semiconductor layer formed of polysilicon having high reliability, and a high-resolution display device can be implemented in this way.

[0057] Oxide semiconductors have high carrier mobility and low leakage current, so although the driving period is relatively long, the voltage drop of oxide semiconductors is not large. That is, even during low-frequency driving, the color change of the image due to the voltage drop is not large, so low-frequency driving can be performed.

[0058] Since oxide semiconductors have low leakage current, at least one of the compensation thin film transistor T3 and the first initialization thin film transistor T4 connected to the driving control electrode of the driving thin film transistor T1 may include an oxide semiconductor to thereby prevent leakage current from flowing to the driving control electrode and simultaneously reduce power consumption.

[0059] Figure 4 is a layout diagram showing positions of a plurality of thin film transistors and a storage capacitor arranged in a pixel circuit of a display device according to an embodiment. Figure 5A and Figure 5C yes Figure 4 An excerpt layout diagram of some of the components shown in FIG. Figure 5B is an excerpted layout diagram of some components of a display device according to an embodiment. Figure 6 It is along Figure 4 A schematic cross-sectional view taken along line II'. Figure 7 It is along Figure 4 A schematic cross-sectional view taken along line II-II'.

[0060] First, refer to Figure 4 and Figure 5A , the pixel circuit of the display device according to the embodiment may include a first scan line SL1, a second scan line SL2, a previous scan line SLp, a next scan line SLn, an emission control line 133, and an initialization voltage line VIL extending in a first direction, and a data line 171 and a driving voltage line 165 extending in a second direction crossing the first direction. The initialization voltage line VIL may include a first initialization voltage line 125 and a second initialization voltage line 145.

[0061] In addition, the pixel circuit may include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6, a second initialization thin film transistor T7, a storage capacitor Cst and a boost capacitor Cbt.

[0062] According to an embodiment, the driving thin film transistor T1 , the switching thin film transistor T2 , the operation control thin film transistor T5 , the emission control thin film transistor T6 , and the second initialization thin film transistor T7 may be thin film transistors including a silicon semiconductor (eg, silicon or polysilicon).

[0063] In addition, the compensation thin film transistor T3 and the first initialization thin film transistor T4 may be thin film transistors including an oxide semiconductor.

[0064] The semiconductor layers of the driving thin film transistor T1 , the switching thin film transistor T2 , the operation control thin film transistor T5 , the emission control thin film transistor T6 and the second initialization thin film transistor T7 are arranged on the same layer and include the same material. For example, the semiconductor layer may include polysilicon.

[0065] The semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the operation control thin film transistor T5, the emission control thin film transistor T6 and the second initialization thin film transistor T7 may be disposed on a buffer layer 111 disposed on the substrate 110 (see Figure 6 )superior.

[0066] Semiconductor layers of the driving thin film transistor T1 , the switching thin film transistor T2 , the operation control thin film transistor T5 , the emission control thin film transistor T6 , and the second initialization thin film transistor T7 may be connected to each other and may be bent in various shapes.

[0067] The semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the operation control thin film transistor T5, the emission control thin film transistor T6 and the second initialization thin film transistor T7 may each include a channel region and a source region and a drain region on two opposite sides of the channel region. For example, the source region and the drain region may be doped with impurities, and the impurities may include N-type impurities or P-type impurities. The source region and the drain region may correspond to the first electrode and the second electrode, respectively. The source region and the drain region may be exchanged according to the properties of the transistor. In the following, the terms "source region" and "drain region" will be used instead of the first electrode or the second electrode.

[0068] The driving thin film transistor T1 includes a driving semiconductor layer AS1 (see Figure 6) and a driving control electrode G1. The driving semiconductor layer AS1 includes a driving channel region A1 and a driving source region S1 and a driving drain region D1 on two opposite sides of the driving channel region A1. The driving semiconductor layer AS1 has a curved shape so that the driving channel region A1 is longer than the other channel regions A2 to A7. For example, since the driving semiconductor layer AS1 has a shape including a plurality of bends such as an Ω shape or the letter "S", a long channel length can be set in a relatively narrow space. Since the driving channel region A1 has a relatively long length, the driving range of the gate voltage applied to the driving control electrode G1 is expanded, thereby finely controlling the grayscale of the light emitted from the organic light emitting diode OLED and improving the display quality. In some embodiments, the driving semiconductor layer AS1 may not be set in a curved shape but in a linear shape. The driving control electrode G1 may be an island type and is included to overlap with the driving channel region A1, and the first gate insulating layer 112 (see Figure 6 ) between the driving control electrode G1 and the driving channel area A1.

[0069] The storage capacitor Cst may be arranged to overlap with the driving thin film transistor T1. The storage capacitor Cst includes a first electrode CE1 and a second electrode CE2. The driving control electrode G1 may be used not only as a control electrode of the driving thin film transistor T1 but also as a first electrode CE1 of the storage capacitor Cst. That is, the driving control electrode G1 and the first electrode CE1 may be understood as a single entity. The second electrode CE2 of the storage capacitor Cst is arranged to overlap with the first electrode CE1, and the second gate insulating layer 113 (see Figure 6 ) between the second electrode CE2 and the first electrode CE1. In this case, the second gate insulating layer 113 may serve as a dielectric layer of the storage capacitor Cst.

[0070] The second electrode CE2 may include a storage opening portion SOP. The storage opening portion SOP is formed by removing a portion of the second electrode CE2 and may have a closed shape. The node connection line 166 may be connected to the first electrode CE1 via a first contact hole CNT1 disposed in the storage opening portion SOP. The second electrode CE2 may be connected to the driving voltage line 165 via a seventh contact hole CNT7. The second electrode CE2 may extend in the first direction to transmit the driving voltage ELVDD in the first direction (see Figure 3 ). Therefore, the plurality of driving voltage lines 165 and the plurality of second electrodes CE2 may form a mesh structure in the display area DA.

[0071] The switching thin film transistor T2 includes a switching semiconductor layer and a switching control electrode G2. The switching semiconductor layer includes a switching channel region A2 and a switching source region S2 and a switching drain region D2 on both sides of the switching channel region A2. The switching source region S2 is connected to the data line 171 via a contact hole and a connecting electrode, and the switching drain region D2 is connected to the driving source region S1. The switching control electrode G2 is included as a part of the first scan line SL1.

[0072] The operation control thin film transistor T5 includes an operation control semiconductor layer and an operation control control electrode G5. The operation control semiconductor layer includes an operation control channel region A5 and an operation control source region S5 and an operation control drain region D5 on both sides of the operation control channel region A5. The operation control source region S5 is connected to the driving voltage line 165 via the eighth contact hole CNT8, and the operation control drain region D5 can be connected to the driving source region S1. The operation control control electrode G5 is included as a part of the emission control line 133.

[0073] The emission control thin film transistor T6 includes an emission control semiconductor layer and an emission control electrode G6. The emission control semiconductor layer includes an emission control channel region A6 and an emission control source region S6 and an emission control drain region D6 on both sides of the emission control channel region A6. The emission control source region S6 is connected to the drive drain region D1, and the emission control drain region D6 may be connected to the first connection electrode 167 via a sixth contact hole CNT6. The first connection electrode 167 may be connected to the pixel electrode 310 (see FIG. 3 ) of the organic light emitting diode OLED via an upper connection electrode 177 disposed in another layer different from the first connection electrode 167. Figure 7 ). The emission control electrode G6 is included as a part of the emission control line 133.

[0074] The second initialization thin film transistor T7 includes a second initialization semiconductor layer and a second initialization control electrode G7. The second initialization semiconductor layer includes a second initialization channel region A7 and a second initialization source region S7 and a second initialization drain region D7 on both sides of the second initialization channel region A7. The second initialization source region S7 may be connected to a first initialization voltage line 125 arranged in the same layer as the second initialization semiconductor layer, and the second initialization drain region D7 may be connected to the emission control drain region D6. The second initialization control electrode G7 is included as part of the next scan line SLn.

[0075] The first interlayer insulating layer 114 (see Figure 6 ) are arranged on the thin film transistors T1, T2, T5, T6 and T7 including a silicon semiconductor, and the thin film transistors T3 and T4 including an oxide semiconductor may be arranged on the first interlayer insulating layer 114.

[0076] The semiconductor layers of the compensation thin film transistor T3 and the first initialization thin film transistor T4 may be disposed on the same layer and include the same material. For example, the semiconductor layer may include an oxide semiconductor.

[0077] The semiconductor layer may include a channel region and a source region and a drain region on both sides of the channel region. For example, the source region and the drain region may be regions having a carrier concentration increased by plasma treatment. The source region and the drain region may correspond to the first electrode and the second electrode, respectively. Hereinafter, the terms "source region" and "drain region" will be used instead of the first electrode or the second electrode.

[0078] The compensation thin film transistor T3 includes a compensation semiconductor layer AO3 (see Figure 7 ) and the compensation control electrode G3. The compensation semiconductor layer AO3 includes a compensation channel region A3 and a compensation source region S3 and a compensation drain region D3 on both sides of the compensation channel region A3. The compensation source region S3 may be bridge-grounded to the drive control electrode G1 via a node connection line 166. One end of the node connection line 166 may be connected to the compensation source region S3 via a second contact hole CNT2, and the other end of the node connection line 166 may be connected to the drive control electrode G1 via a first contact hole CNT1. In addition, the compensation source region S3 may be connected to a first initialization drain region D4 arranged in the same layer. The compensation drain region D3 may be connected to the drive semiconductor layer AS1 of the drive thin film transistor T1 and the emission control semiconductor layer of the emission control thin film transistor T6 via a second connection electrode 168. The compensation control electrode G3 is included as part of the second scan line SL2.

[0079] The first initialization thin film transistor T4 includes a first initialization semiconductor layer AO4 (see FIG. Figure 6 ) and a first initialization control electrode G4. The first initialization semiconductor layer AO4 includes a first initialization channel region A4 and a first initialization source region S4 and a first initialization drain region D4 on both sides of the first initialization channel region A4. The first initialization source region S4 may be connected to the second initialization voltage line 145 via a ninth contact hole CNT9, and the first initialization drain region D4 may be bridge-grounded to the driving control electrode G1 via a node connection line 166. The first initialization control electrode G4 is included as a part of a previous scan line SLp.

[0080] The third gate insulating layer 115 (see Figure 6 ) are arranged between the compensation semiconductor layer AO3 and the compensation control electrode G3 and between the first initialization semiconductor layer AO4 and the first initialization control electrode G4 to correspond to the respective channel regions.

[0081] The third electrode CE3 as an electrode of the boost capacitor Cbt is included as a part of the first scan line SL1 to be connected to the switch control electrode G2. The fourth electrode CE4 of the boost capacitor Cbt is arranged to overlap with the third electrode CE3 and may include an oxide semiconductor. The fourth electrode CE4 may be arranged on the same layer as the compensation semiconductor layer AO3 of the compensation thin film transistor T3 and the first initialization semiconductor layer AO4 of the first initialization thin film transistor T4 to be included as a region between the compensation semiconductor layer AO3 and the first initialization semiconductor layer AO4. Optionally, the fourth electrode CE4 may extend from the first initialization semiconductor layer AO4. Optionally, the fourth electrode CE4 may extend from the compensation semiconductor layer AO3.

[0082] The second interlayer insulating layer 116 (see Figure 6 ) may be disposed on the compensation thin film transistor T3 and the first initialization thin film transistor T4 including an oxide semiconductor, and the driving voltage line 165, the node connection line 166, and the first and second connection electrodes 167 and 168 may be disposed on the second interlayer insulating layer 116.

[0083] In this embodiment, the first planarization layer 118 (see Figure 6 ) may be arranged to cover the driving voltage line 165 , and the data line 171 and the shielding electrode 173 may be arranged on the first planarization layer 118 .

[0084] The shielding electrode 173 may be disposed above the node connection line 166. When the shielding electrode 173 is not disposed above the node connection line 166, the node connection line 166 may be connected to the data line 171 and / or the display element (see FIG. Figure 6 ) forms a coupling capacitor. Therefore, the thin film transistor connected to the node connection line 166 is affected by the coupling capacitor.

[0085] According to the present embodiment, the shielding electrode 173 may be arranged above the node connection line 166 and a constant voltage may be applied to the shielding electrode 173 to minimize the influence caused by the coupling capacitance. In some embodiments, the shielding electrode 173 may be connected to the driving voltage line 165 via the third contact hole CNT3. Therefore, the driving voltage ELVDD may be applied to the shielding electrode 173.

[0086] In some embodiments, the shielding electrode 173 may be formed to completely cover the node connection line 166. In some embodiments, the shielding electrode 173 may be arranged to overlap at least a portion of the driving thin film transistor T1, the compensation thin film transistor T3, and / or the first initialization thin film transistor T4.

[0087] In addition, if Figure 5AAs shown in , in some embodiments, the driving voltage line 165 may be arranged to at least partially overlap with the data line 171. In addition, a portion of the driving voltage line 165 may be between the data line 171 and the node connection line 166. Since the driving voltage line 165 is arranged to overlap with and below the data line 171, components arranged below or beside the data line 171 may be prevented from being affected by the data signal of the data line 171.

[0088] In some embodiments, Figure 5B , the driving voltage line 165 may be arranged not to overlap with the data line 171. Even when the driving voltage line 165 does not overlap with the data line 171, since the driving voltage line 165 is arranged between the data line 171 and the node connection line 166 in a plan view, it is possible to prevent the data signal from having an influence in the lateral direction of the node connection line 166. In addition, since the shielding electrode 173 is arranged on the upper surface of the node connection line 166, it is possible to prevent the data signal from having an influence from above the node connection line 166.

[0089] According to an embodiment, the first scan line SL1 , the next scan line SLn, and the emission control line 133 may be included in the same layer as the driving control electrode G1 and include the same material as the driving control electrode G1 .

[0090] According to an embodiment, some of the lines may be included as two conductive layers arranged in layers different from each other. For example, the second scan line SL2 may include a lower scan line 143 and an upper scan line 153 arranged on layers different from each other. The lower scan line 143 may be included in the same layer as the second electrode CE2 of the storage capacitor Cst and include the same material as the second electrode CE2 of the storage capacitor Cst, and the upper scan line 153 may be arranged on the third gate insulating layer 115 (see Figure 6 ). The lower scan line 143 may be arranged to at least partially overlap the upper scan line 153. Since the lower scan line 143 and the upper scan line 153 correspond to a portion of the compensation control electrode of the compensation thin film transistor T3, the compensation thin film transistor T3 may have two control electrodes G3a and G3b respectively disposed in the lower and upper portions of its semiconductor layer (see Figure 7 For example, the two control electrodes G3a and G3b correspond to the lower scan line 143 and the upper scan line 153 respectively.

[0091] In addition, the previous scan line SLp may include a lower previous scan line 141 and an upper previous scan line 151 disposed on different layers from each other. The lower previous scan line 141 may be included in the same layer and include the same material as the second electrode CE2 of the storage capacitor Cst, and the upper previous scan line 151 may be disposed on the third gate insulating layer 115 (see Figure 6 ). The lower previous scan line 141 may be arranged to at least partially overlap the upper previous scan line 151. Since the lower previous scan line 141 and the upper previous scan line 151 correspond to a portion of the first initialization control electrode G4 of the first initialization thin film transistor T4, the first initialization thin film transistor T4 may have two control electrodes G4a and G4b respectively disposed in the lower and upper portions of its semiconductor layer (see Figure 6 For example, the two control electrodes G4a and G4b correspond to the lower previous scan line 141 and the upper previous scan line 151, respectively.

[0092] Reference Figure 5C , the lower previous scan line 141 may protrude to correspond to the first initialization thin film transistor T4. The protruding portion may also serve as the second lower control electrode G4a of the first initialization thin film transistor T4 (see Figure 6 ). The protruding portion is arranged to completely cover the channel region of the first initialization semiconductor layer AO4 under the first initialization semiconductor layer AO4, and thus, light that may be applied from below the substrate 110 may be blocked by the protruding portion.

[0093] Likewise, the lower scan line 143 may protrude to correspond to the compensation thin film transistor T3. The protruding portion may serve as the first lower control electrode G3a (see Figure 7 ). As described above, since the compensation thin film transistor T3 includes the first upper control electrode G3b and the first lower control electrode G3a to which the same signal is applied, the compensation semiconductor layer AO3 can be stably driven. In addition, the protruding portion is arranged to completely cover the channel region of the compensation semiconductor layer AO3 under the compensation semiconductor layer AO3, and therefore, light that may be applied from below the substrate 110 may be blocked by the protruding portion.

[0094] The initialization voltage line VIL may include a first initialization voltage line 125 and a second initialization voltage line 145 disposed on different layers from each other. The first initialization voltage line 125 may be included on the same layer as the semiconductor layer of the driving thin film transistor T1 and include the same material as the semiconductor layer of the driving thin film transistor T1, and the second initialization voltage line 145 may be included on the same layer as the second electrode CE2 of the storage capacitor Cst and include the same material as the second electrode CE2 of the storage capacitor Cst.

[0095] In the following, reference will be made to Figure 6 and Figure 7 The structure of the display device according to the embodiment is described in detail according to the stacking order. Figure 6 and Figure 7 , structures of the driving thin film transistor T1, the compensation thin film transistor T3, the first initialization thin film transistor T4, the emission control thin film transistor T6, the storage capacitor Cst and the boosting capacitor Cbt are mainly shown, and some components may be omitted.

[0096] Reference Figure 6 and Figure 7 The display device according to the embodiment includes a substrate 110, a first thin film transistor including a silicon semiconductor (for example, a driving thin film transistor T1), a second thin film transistor including an oxide semiconductor (for example, a first initialization thin film transistor T4), a node connection line 166 connecting a first control electrode of the first thin film transistor to a second semiconductor layer of the second thin film transistor, and a shielding electrode 173 arranged above the node connection line 166 to overlap the node connection line 166. The shielding electrode 173 may be connected to the driving voltage line 165 via a contact hole (for example, a third contact hole CNT3). The first thin film transistor may be the driving thin film transistor T1, and the second thin film transistor may be the first initialization thin film transistor T4. The second thin film transistor may also be a compensation thin film transistor T3 having a semiconductor layer including an oxide semiconductor. The semiconductor layer of the compensation thin film transistor T3 may be connected to the driving control electrode G1 of the driving thin film transistor T1 via the node connection line 166.

[0097] In addition, the display device may further include various insulating layers, such as a buffer layer 111 , a first gate insulating layer 112 , a second gate insulating layer 113 , a third gate insulating layer 115 , a first interlayer insulating layer 114 , a second interlayer insulating layer 116 , a first planarizing layer 118 , and a second planarizing layer 119 .

[0098] The substrate 110 may include a glass material, a ceramic material, a metal material, or a flexible or bendable material. When the substrate 110 is flexible or bendable, the substrate 110 may include a polymer resin such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). The substrate 110 may have a single-layer structure or a multi-layer structure of the above materials, and may also include an inorganic layer in the case of a multi-layer structure. In some embodiments, the substrate 110 may have a structure of organic material / inorganic material / organic material.

[0099] The buffer layer 111 may perform a function of increasing the smoothness of the upper surface of the substrate 110, and the buffer layer 111 may include a material such as silicon oxide (SiO x ) oxide layer and / or an oxide layer such as silicon nitride (SiN x ) or a nitride layer of silicon oxynitride (SiON).

[0100] A barrier layer (not shown) may be further included between the substrate 110 and the buffer layer 111. The barrier layer may prevent or minimize the penetration of impurities from the substrate 110 into the silicon semiconductor layer. The barrier layer may include an inorganic material and / or an organic material such as an oxide or a nitride, and have a single-layer structure or a multi-layer structure including the inorganic material and the organic material.

[0101] A driving semiconductor layer AS1 and an emission control semiconductor layer AS6 , which are semiconductor layers including a silicon semiconductor, may be disposed on the buffer layer 111 .

[0102] The driving semiconductor layer AS1 may include a driving source region S1 and a driving drain region D1 doped with impurities to have conductivity and spaced apart from each other, and a driving channel region A1 disposed between the driving source region S1 and the driving drain region D1. The driving source region S1 and the driving drain region D1 may correspond to the first electrode and the second electrode of the driving thin film transistor T1, respectively, and positions of the driving source region S1 and the driving drain region D1 may be interchanged.

[0103] The emission control semiconductor layer AS6 may include an emission control source region S6 and an emission control drain region D6 doped with impurities to have conductivity and arranged to be separated from each other, and an emission control channel region A6 arranged between the emission control source region S6 and the emission control drain region D6. The emission control source region S6 and the emission control drain region D6 may correspond to the first electrode and the second electrode of the emission control thin film transistor T6, respectively, and the positions of the emission control source region S6 and the emission control drain region D6 may be interchanged.

[0104] The driving control electrode G1 is disposed on the driving semiconductor layer AS1, and the emission control electrode G6 is disposed on the emission control semiconductor layer AS6. The first gate insulating layer 112 may be disposed between the driving semiconductor layer AS1 and the driving control electrode G1 and between the emission control semiconductor layer AS6 and the emission control electrode G6.

[0105] The first gate insulating layer 112 may include an inorganic material including oxide or nitride. For example, the first gate insulating layer 112 may include silicon oxide (SiO 2 )、Silicon Nitride(SiN x )、Silicon Oxynitride (SiON), Aluminum Oxide (Al 2 O 3), titanium oxide (TiO 2 )、Tantalum oxide(Ta 2 O 5 )、HfO 2 ) and zinc peroxide (ZnO 2 The driving control electrode G1 is arranged to overlap the driving channel region A1, and may include a single layer or a multilayer including at least one of molybdenum (Mo), copper (Cu), and titanium (Ti).

[0106] The storage capacitor Cst may be disposed on the driving semiconductor layer AS1 of the driving thin film transistor T1. The storage capacitor Cst includes a first electrode CE1 and a second electrode CE2. The second gate insulating layer 113 may be disposed between the first electrode CE1 and the second electrode CE2. The driving control electrode G1 may be used not only as a control electrode of the driving thin film transistor T1 but also as a first electrode CE1 of the storage capacitor Cst. That is, the driving control electrode G1 and the first electrode CE1 may be understood as a single entity.

[0107] The second gate insulating layer 113 may include an inorganic material including oxide or nitride. For example, the second gate insulating layer 113 may include silicon oxide (SiO 2 )、Silicon Nitride(SiN x )、Silicon Oxynitride (SiON), Aluminum Oxide (Al 2 O 3 ), titanium oxide (TiO 2 )、Tantalum oxide(Ta 2 O 5 )、HfO 2 ) and zinc peroxide (ZnO 2 ) at least one of the following.

[0108] The second electrode CE2 is arranged on the second gate insulating layer 113 to overlap with the first electrode CE1. The second electrode CE2 may include a storage opening portion SOP. The storage opening portion SOP is formed by removing a portion of the second electrode CE2 and may have a closed shape. The first contact hole CNT1 defined in the second gate insulating layer 113 may be arranged in the storage opening portion SOP. The driving control electrode G1 and the node connection line 166 may be connected to each other via the first contact hole CNT1. The second electrode CE2 may include at least one of molybdenum (Mo), copper (Cu), and titanium (Ti) and include a single layer or a multilayer.

[0109] The first interlayer insulating layer 114 may be disposed on the second electrode CE2. The first interlayer insulating layer 114 may include an inorganic material including oxide or nitride. For example, the first interlayer insulating layer 114 may include silicon oxide (SiO 2)、Silicon Nitride(SiN x )、Silicon Oxynitride (SiON), Aluminum Oxide (Al 2 O 3 ), titanium oxide (TiO 2 )、Tantalum oxide(Ta 2 O 5 )、HfO 2 ) and zinc peroxide (ZnO 2 ) at least one of the following.

[0110] The compensation semiconductor layer AO3 including an oxide semiconductor and the first initialization semiconductor layer AO4 may be disposed on the first interlayer insulating layer 114. The compensation semiconductor layer AO3 may include a compensation source region S3 and a compensation drain region D3 having conductivity and spaced apart from each other and a compensation channel region A3 therebetween.

[0111] The first initialization semiconductor layer AO4 may include a first initialization source region S4 and a first initialization drain region D4 having conductivity and spaced apart from each other, and a first initialization channel region A4 between the first initialization source region S4 and the first initialization drain region D4.

[0112] The compensation semiconductor layer AO3 and the first initialization semiconductor layer AO4 may include a Zn oxide-based material, and may include, for example, Zn oxide, In-Zn oxide, Ga-In-Zn oxide, etc. In some embodiments, the compensation semiconductor layer AO3 and the first initialization semiconductor layer AO4 may include In-Ga-Zn-O (IGZO), In-Sn-Zn-O (ITZO), or In-Ga-Sn-Zn-O (IGTZO) semiconductor containing metals such as In, Ga, and tin (Sn) in ZnO.

[0113] The compensation source region S3, the compensation drain region D3, the first initialization source region S4, and the first initialization drain region D4 may be formed to have conductivity by adjusting the carrier concentration in the oxide semiconductor. For example, the compensation source region S3 and the compensation drain region D3 and the first initialization source region S4 and the first initialization drain region D4 may be formed by increasing the carrier concentration of the oxide semiconductor by performing plasma treatment on the oxide semiconductor using a hydrogen (H)-based gas, a fluorine (F)-based gas, or a combination thereof.

[0114] The first lower control electrode G3a may be disposed below the compensation semiconductor layer AO3, and the first upper control electrode G3b may be disposed on the compensation semiconductor layer AO3. That is, the compensation thin film transistor T3 may include a double control electrode. As described above, since the compensation thin film transistor T3 includes the first upper control electrode G3b and the first lower control electrode G3a, each of which is applied with the same signal, the compensation semiconductor layer AO3 may be stably driven. In addition, light that may be applied from below the substrate 110 may be blocked by using the first lower control electrode G3a.

[0115] The second lower control electrode G4a may be arranged below the first initialization semiconductor layer AO4, and the second upper control electrode G4b may be arranged on the first initialization semiconductor layer AO4. That is, the first initialization thin film transistor T4 may include a double control electrode. As described above, since the first initialization thin film transistor T4 includes the second upper control electrode G4b and the second lower control electrode G4a, each of which is applied with the same signal, the first initialization semiconductor layer AO4 may be stably driven. In addition, light that may be applied from below the substrate 110 may be blocked by using the second lower control electrode G4a.

[0116] The first interlayer insulating layer 114 may be disposed between the first lower control electrode G3a and the compensation semiconductor layer AO3 and between the second lower control electrode G4a and the first initialization semiconductor layer AO4. The first lower control electrode G3a and the second lower control electrode G4a may be disposed on the same layer (e.g., the second gate insulating layer 113) as the second electrode CE2 of the storage capacitor Cst and include the same material as the second electrode CE2 of the storage capacitor Cst.

[0117] The third gate insulating layer 115 may be disposed between the compensation semiconductor layer AO3 and the first upper control electrode G3b and between the first initialization semiconductor layer AO4 and the second upper control electrode G4b. The first upper control electrode G3b is disposed to overlap the compensation channel region A3 and is insulated from the compensation semiconductor layer AO3 by the third gate insulating layer 115. The second upper control electrode G4b is disposed to overlap the first initialization channel region A4 and is insulated from the first initialization semiconductor layer AO4 by the third gate insulating layer 115.

[0118] The third gate insulating layer 115 may be formed by the same mask process as the first and second upper control electrodes G3b and G4b. In this case, the third gate insulating layer 115 may be formed in the same shape as the first and second upper control electrodes G3b and G4b.

[0119] The third gate insulating layer 115 may include an inorganic material including oxide or nitride. For example, the third gate insulating layer 115 may include silicon oxide (SiO 2 )、Silicon Nitride(SiN x )、Silicon Oxynitride (SiON), Aluminum Oxide (Al 2 O 3 ), titanium oxide (TiO 2 )、Tantalum oxide(Ta 2 O 5 )、HfO 2 ) and zinc peroxide (ZnO 2 The first upper control electrode G3b and the second upper control electrode G4b may be disposed on the third gate insulating layer 115 and include at least one of molybdenum (Mo), copper (Cu), and titanium (Ti) and include a single layer or a multilayer.

[0120] The boost capacitor Cbt includes a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 and the driving control electrode G1 may be arranged on the same layer (e.g., the first gate insulating layer 112). The fourth electrode CE4 may extend from the first initialization semiconductor layer AO4 or the compensation semiconductor layer AO3. That is, the fourth electrode CE4 may include an oxide semiconductor and be arranged on the first interlayer insulating layer 114. The second gate insulating layer 113 and the first interlayer insulating layer 114 may be arranged between the third electrode CE3 and the fourth electrode CE4, and the second gate insulating layer 113 and the first interlayer insulating layer 114 may be used as a dielectric layer of the boost capacitor Cbt.

[0121] The fourth electrode CE4 of the boosting capacitor Cbt may be connected to the node connection line 166 to be electrically connected to the driving control electrode G1. Therefore, since the boosting capacitor Cbt boosts the first node N1 when the first scan signal Sn supplied to the first scan line SL1 is turned off (see Figure 3 ) voltage, so the black grayscale can be clearly displayed.

[0122] The second interlayer insulating layer 116 covers the thin film transistors including oxide semiconductors (such as the compensation thin film transistor T3, the first initialization thin film transistor T4, etc.). The second interlayer insulating layer 116 may be disposed on the first upper control electrode G3b and the second upper control electrode G4b, and the driving voltage line 165, the node connection line 166, and the first connection electrode 167 and the second connection electrode 168 may be disposed on the second interlayer insulating layer 116.

[0123] The second interlayer insulating layer 116 may include an inorganic material including oxide or nitride. For example, the second interlayer insulating layer 116 may include silicon oxide (SiO 2 )、Silicon Nitride(SiNx )、Silicon Oxynitride (SiON), Aluminum Oxide (Al 2 O 3 ), titanium oxide (TiO 2 )、Tantalum oxide(Ta 2 O 5 )、HfO 2 ) and zinc peroxide (ZnO 2 ) at least one of the following.

[0124] The driving voltage line 165, the node connection line 166, and the first connection electrode 167 and the second connection electrode 168 may be a highly conductive material such as a metal or a conductive oxide. For example, the driving voltage line 165, the node connection line 166, and the first connection electrode 167 and the second connection electrode 168 may include a single layer or multiple layers including at least one of aluminum (Al), copper (Cu), and titanium (Ti). In some embodiments, the driving voltage line 165, the node connection line 166, and the first connection electrode 167 and the second connection electrode 168 may include three layers including Ti, Al, and Ti (Ti / Al / Ti) arranged in sequence.

[0125] One end of the node connection line 166 may be connected to the driving control electrode G1 via the first contact hole CNT1. The first contact hole CNT1 may pass through the second interlayer insulating layer 116, the first interlayer insulating layer 114, and the second gate insulating layer 113, and expose the driving control electrode G1. Since a portion of the node connection line 166 is inserted into the first contact hole CNT1, the node connection line 166 may be electrically connected to the driving control electrode G1.

[0126] Meanwhile, the first contact hole CNT1 may be arranged to be separated from the edge of the storage opening portion SOP in the storage opening portion SOP of the second electrode CE2 , and thus the node connection wire 166 inserted into the first contact hole CNT1 may be electrically insulated from the second electrode CE2 .

[0127] The other end of the node connection line 166 may be connected to the oxide semiconductor layer (eg, the fourth electrode CE4 of the boosting capacitor Cbt or the first initialization semiconductor layer AO4) via the second contact hole CNT2. The second contact hole CNT2 may pass through the second interlayer insulating layer 116 to be connected to the oxide semiconductor layer of the first initialization thin film transistor T4.

[0128] Reference Figure 7, the first connection electrode 167 may be connected to the emission control semiconductor layer AS6 via the sixth contact hole CNT6. The sixth contact hole CNT6 may pass through the second interlayer insulating layer 116, the first interlayer insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112, and expose a portion of the emission control semiconductor layer AS6. Since a portion of the first connection electrode 167 is inserted into the sixth contact hole CNT6, the first connection electrode 167 may be electrically connected to the emission control semiconductor layer AS6. The first connection electrode 167 may be connected to the pixel electrode 310 to transmit a signal applied via the emission control thin film transistor T6 to the pixel electrode 310.

[0129] One end of the second connection electrode 168 may be connected to the emission control semiconductor layer AS6 via the fourth contact hole CNT4. The other end of the second connection electrode 168 may be connected to the compensation semiconductor layer AO3 via the fifth contact hole CNT5.

[0130] The first planarization layer 118 is arranged on the node connection line 166, the driving voltage line 165, and the first connection electrode 167 and the second connection electrode 168. The first planarization layer 118 may include an organic material such as acryl, benzocyclobutene (BCB), PI, or hexamethyldisiloxane (HMDSO). Alternatively, the first planarization layer 118 may include an inorganic material. The first planarization layer 118 serves as a protective layer covering the thin film transistors T1 to T7, and the upper portion of the first planarization layer 118 is planarized. The first planarization layer 118 may include a single layer or a multilayer.

[0131] The data line 171, the shielding electrode 173, and the upper connection electrode 177 may be arranged on the first planarization layer 118. The data line 171 may partially overlap with the driving voltage line 165. In a plan view, a portion R1 of the driving voltage line 165 may be between the data line 171 and the node connection line 166. For example, the portion R1 of the driving voltage line 165 may overlap with a region between the data line 171 and the node connection line 166. Therefore, the driving voltage line 165 may reduce coupling between the node connection line 166 and the data line 171 in a horizontal direction.

[0132] The shielding electrode 173 may be disposed above the node connection line 166 to overlap the node connection line 166. Therefore, the shielding electrode 173 may reduce coupling between the node connection line 166 and the data line 171 in a vertical direction.

[0133] The upper connection electrode 177 may be connected to the first connection electrode 167 via a contact hole defined in the first planarization layer 118. The data line 171, the shielding electrode 173, and the upper connection electrode 177 may include a conductive material such as a metal. For example, the data line 171, the shielding electrode 173, and the upper connection electrode 177 may include Al, Cu, and Ti, and may include a single layer or multiple layers.

[0134] An organic light emitting diode OLED including a pixel electrode 310 , an opposing electrode 330 , and an intermediate layer 320 disposed between the pixel electrode 310 and the opposing electrode 330 and including an emission layer may be on the second planarization layer 119 .

[0135] The pixel electrode 310 may be connected to the upper connection electrode 177 via a contact hole defined in the second planarization layer 119 , and may be connected to the emission control drain region D6 of the emission control thin film transistor T6 via the upper connection electrode 177 and the first connection electrode 167 .

[0136] The pixel defining layer 120 may be disposed on the second planarization layer 119. The pixel defining layer 120 has an opening corresponding to each sub-pixel (i.e., an opening exposing at least the central portion of the pixel electrode 310), thereby defining a pixel. In addition, the pixel defining layer 120 may increase the distance between the edge of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310 to prevent arcing at the edge of the pixel electrode 310, etc. The pixel defining layer 120 may include an organic material such as PI or HMDSO.

[0137] The intermediate layer 320 of the organic light emitting diode OLED may include a low molecular weight material or a polymer material. When the intermediate layer 320 includes a low molecular weight material, the intermediate layer 320 may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), an electron injection layer (EIL), etc. are stacked in a single structure or a composite structure, and may include various organic materials including copper phthalocyanine (CuPc), N,N-di(naphthalene-1-yl)-N,N'-diphenyl-benzidine (NPB), tri-8-hydroxyquinoline aluminum (Alq3), etc. The above layers may be formed using a vacuum deposition method.

[0138] When the intermediate layer 320 includes a polymer material, the intermediate layer 320 may typically have a structure including an HTL and an EML. The HTL may include poly(3,4-ethylenedioxythiophene) (PEDOT), and the EML may include a polymer material such as a polyphenylene vinylene (PPV)-based material or a polyfluorene-based material. The intermediate layer 320 may be formed using, for example, a screen printing method, an inkjet printing method, or a laser induced thermal imaging (LITI) method.

[0139] The intermediate layer 320 is not limited thereto and may also have other various structures. The intermediate layer 320 may include a layer formed as a single integral body with respect to the plurality of pixel electrodes 310 or may include layers patterned to correspond to the plurality of pixel electrodes 310 , respectively.

[0140] The counter electrode 330 may be integrally formed with respect to the plurality of organic light emitting diodes to correspond to the plurality of pixel electrodes 310 .

[0141] Since the organic light emitting diode OLED is likely to be damaged by moisture or oxygen from the outside, a thin film encapsulation layer (not shown) or an encapsulation substrate (not shown) may be arranged on the organic light emitting diode OLED to cover and protect the organic light emitting diode OLED. The thin film encapsulation layer (not shown) may cover the display area DA and extend beyond the display area DA. The thin film encapsulation layer may include an inorganic encapsulation layer including at least one inorganic material and an organic encapsulation layer including at least one organic material. In some embodiments, the thin film encapsulation layer may have a structure in which a first inorganic encapsulation layer / organic encapsulation layer / second inorganic encapsulation layer are stacked. The encapsulation substrate (not shown) may be arranged to face the substrate 110, and may be provided in the peripheral area PA (see FIG. 1 ) by using an encapsulation member such as a sealant or glass frit. Figure 1 ) is bonded to the substrate 110.

[0142] In addition, spacers may be further included on the pixel defining layer 120 to prevent damage caused by the mask, and various functional layers (such as a polarizing layer, a black matrix, a color filter and / or a touch screen layer including a touch electrode) that reduce external light reflection may be provided on the thin film encapsulation layer.

[0143] Figure 8 is a schematic cross-sectional view of a display device according to an embodiment. Figure 8 In, with Figure 6 Like reference numerals denote like elements, and thus redundant descriptions thereof will be omitted.

[0144] Reference Figure 8The display device according to the embodiment includes a substrate 110, a first thin film transistor including a silicon semiconductor (for example, a driving thin film transistor T1), a second thin film transistor including an oxide semiconductor (for example, a first initialization thin film transistor T4), a node connection line 166 connecting a first control electrode of the first thin film transistor to a second semiconductor layer of the second thin film transistor, and a shielding electrode 173 arranged above the node connection line 166 to overlap the node connection line 166. The shielding electrode 173 may be connected to the driving voltage line 165 via a contact hole. The first thin film transistor may be the driving thin film transistor T1, and the second thin film transistor may be the first initialization thin film transistor T4. The second thin film transistor may also be a compensation thin film transistor T3 having a semiconductor layer including an oxide semiconductor. The semiconductor layer of the compensation thin film transistor T3 may be connected to the driving control electrode G1 of the driving thin film transistor T1 via the node connection line 166.

[0145] In the present embodiment, the data line 161 may be arranged on the same layer (e.g., the second interlayer insulating layer 116) as the driving voltage line 165 and the node connection line 166. In this case, the driving voltage line 165 may be arranged to be separated from each of the data line 161 and the node connection line 166 between the data line 161 and the node connection line 166. Since the driving voltage line 165 to which a constant voltage is applied is arranged between the data line 161 and the node connection line 166, the coupling effect that would occur between the data line 161 and the node connection line 166 can be minimized.

[0146] Furthermore, in the present embodiment, since the shielding electrode 173 is disposed above the node connection line 166 , a coupling effect that may occur between the node connection line 166 and the pixel electrode 310 or the like may be minimized.

[0147] Meanwhile, in the present embodiment, the first initialization thin film transistor T4 may have a top gate structure including the first initialization control electrode G4 disposed on the third gate insulating layer 115 .

[0148] Fig. 9 is a schematic cross-sectional view of a display device according to an embodiment. Fig. 9 In, with Figure 6 Like reference numerals denote like elements, and thus redundant descriptions thereof will be omitted.

[0149] Reference Fig. 9The display device according to the embodiment includes a substrate 110, a first thin film transistor including a silicon semiconductor (for example, a driving thin film transistor T1), a second thin film transistor including an oxide semiconductor (for example, a first initialization thin film transistor T4), a node connection line 166 connecting a first control electrode of the first thin film transistor to a second semiconductor layer of the second thin film transistor, and a shielding electrode 173 arranged above the node connection line 166 to overlap the node connection line 166. The shielding electrode 173 may be connected to the driving voltage line 165 via a contact hole. The first thin film transistor may be the driving thin film transistor T1, and the second thin film transistor may be the first initialization thin film transistor T4. The second thin film transistor may also be a compensation thin film transistor T3 having a semiconductor layer including an oxide semiconductor. The semiconductor layer of the compensation thin film transistor T3 may be connected to the driving control electrode G1 of the driving thin film transistor T1 via the node connection line 166.

[0150] According to the present embodiment, the data line may include a lower data line 161' and an upper data line 171' arranged on different layers from each other. The lower data line 161' may be arranged on the same layer (e.g., the second interlayer insulating layer 116) as the node connection line 166. The upper data line 171' may be arranged on the same layer (e.g., the first planarization layer 118) as the shielding electrode 173. The upper data line 171' may be connected to the lower data line 161' via a contact hole.

[0151] In the present embodiment, the driving voltage line 165 may be arranged to be separated from each of the lower data line 161' and the node connection line 166 between the lower data line 161' and the node connection line 166. Since the driving voltage line 165 to which a constant voltage is applied is arranged between the lower data line 161' and the node connection line 166, a coupling effect that would occur between the lower data line 161' and the node connection line 166 may be minimized.

[0152] Furthermore, in the present embodiment, since the shielding electrode 173 is disposed above the node connection line 166 , the coupling effect that may occur between the node connection line 166 and the upper data line 171 ′ and / or the pixel electrode 310 , etc., may be minimized.

[0153] According to the embodiments described above, a driving circuit for driving a display element is configured to include a first thin film transistor including a silicon semiconductor and a second thin film transistor including an oxide semiconductor, and thus a high-resolution display device with low power consumption can be provided.

[0154] Furthermore, due to the shielding electrode overlapping the node connection line connected to the first thin film transistor, the influence caused by the coupling capacitance can be minimized.

[0155] Additionally, thanks to the boost capacitor, black grayscale can be clearly achieved.

[0156] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. The description of features or aspects within each embodiment should typically be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the claims.

Claims

1. A display device, comprising: substrate; A display element is disposed on the substrate; as well as a pixel circuit disposed between the substrate and the display element and connected to the display element through a connecting electrode; The pixel circuit includes: a first thin film transistor, including a first semiconductor layer and a first control electrode, the first semiconductor layer includes silicon; a second thin film transistor, including a second semiconductor layer and a second control electrode, the second semiconductor layer includes an oxide semiconductor; and a shielding electrode, which is arranged on the same layer as the connecting electrode.

2. The display device according to claim 1, wherein the pixel circuit further comprises: A first scanning line extending in a first direction; as well as a data line extending in a second direction intersecting the first direction, Wherein, the data line and the shielding electrode are arranged in the same layer.

3. The display device according to claim 1, wherein the pixel circuit further comprises: a node connection line connected to the first control electrode via a first contact hole; A first scanning line extending in a first direction and arranged in the same layer as the first control electrode; as well as a second scanning line extending in the first direction and arranged in the same layer as the second control electrode, Wherein, the node connection line overlaps with the first scan line and the second scan line.

4. The display device according to claim 3, wherein: The shielding electrode overlaps the node connection line.

5. The display device according to claim 3, wherein the pixel circuit further comprises: A first interlayer insulating layer is provided between the first control electrode and the second semiconductor layer; as well as The second interlayer insulating layer is disposed between the second semiconductor layer and the node connection line.

6. The display device according to claim 5, wherein: The node connection line is connected to the first control electrode via a first contact hole, and is connected to the second semiconductor layer via a second contact hole, and The first contact hole penetrates the first interlayer insulating layer and the second interlayer insulating layer, and the second contact hole penetrates the second interlayer insulating layer.

7. The display device according to claim 5, further comprising a driving voltage line, wherein the driving voltage line is arranged on the second interlayer insulating layer, in, The shielding electrode is connected to the driving voltage line via a third contact hole.

8. The display device according to claim 7, further comprising a data line, wherein the data line and the shielding electrode are arranged on the same layer, in, The driving voltage line at least partially overlaps the data line.

9. The display device according to claim 1, wherein: The first control electrode and the second control electrode are arranged in different layers.

10. The display device according to claim 1, wherein: The second thin film transistor further includes a third control electrode disposed below the second semiconductor layer to overlap the second semiconductor layer.

11. A display device, comprising: substrate; A display element is disposed on the substrate; as well as a pixel circuit disposed between the substrate and the display element and connected to the display element through a connecting electrode; The pixel circuit includes: a first thin film transistor, including a first semiconductor layer and a first control electrode, the first semiconductor layer includes silicon; a second thin film transistor, including a second semiconductor layer and a second control electrode, the second semiconductor layer includes an oxide semiconductor; a node connection line, connected to the first control electrode via a first contact hole, and connected to the second semiconductor layer via a second contact hole; and a shielding electrode, which is arranged on the same layer as the connection electrode. The first contact hole has a height different from that of the second contact hole.

12. The display device according to claim 11, wherein the pixel circuit further comprises: A first interlayer insulating layer is provided between the first control electrode and the second semiconductor layer; as well as The second interlayer insulating layer is disposed between the second semiconductor layer and the node connection line.

13. The display device according to claim 12, wherein: The first contact hole penetrates the first interlayer insulating layer and the second interlayer insulating layer, and the second contact hole penetrates the second interlayer insulating layer.

14. The display device according to claim 11, wherein the pixel circuit further comprises: A first scanning line extending in a first direction; as well as a data line extending in a second direction intersecting the first direction, Wherein, the data line and the shielding electrode are arranged in the same layer.

15. The display device according to claim 11, wherein the pixel circuit further comprises: A first scanning line extending in a first direction and arranged in the same layer as the first control electrode; as well as a second scanning line extending in the first direction and arranged in the same layer as the second control electrode, Wherein, the node connection line overlaps with the first scan line and the second scan line.

16. The display device according to claim 11, wherein: The shielding electrode overlaps the node connection line.

17. The display device according to claim 11, further comprising a driving voltage line, wherein the driving voltage line and the node connection line are arranged in the same layer, in, The shielding electrode is connected to the driving voltage line via a third contact hole.

18. The display device according to claim 17, further comprising a data line, wherein the data line and the shielding electrode are arranged on the same layer. in, The driving voltage line at least partially overlaps the data line.

19. The display device according to claim 11, wherein: The first control electrode and the second control electrode are arranged in different layers.

20. The display device according to claim 11, wherein: The second thin film transistor further includes a third control electrode disposed below the second semiconductor layer to overlap the second semiconductor layer.

21. A display device, comprising: substrate; A display element is disposed on the substrate; as well as a pixel circuit disposed between the substrate and the display element and connected to the display element through a connecting electrode; The pixel circuit includes: a first thin film transistor, including a first semiconductor layer and a first control electrode; a second thin film transistor, which is arranged on a different layer from the first thin film transistor and includes a second semiconductor layer and a second control electrode; and a shielding electrode, which is arranged on the same layer as the connecting electrode.

22. The display device according to claim 21, wherein the pixel circuit further comprises: A first scanning line extending in a first direction; as well as a data line extending in a second direction intersecting the first direction, Wherein, the data line and the shielding electrode are arranged in the same layer.

23. The display device according to claim 21, wherein the pixel circuit further comprises a storage capacitor, wherein the storage capacitor comprises a first electrode and a second electrode on the first electrode. in, The second control electrode includes a lower control electrode disposed below the second semiconductor layer and an upper control electrode disposed above the second semiconductor layer, and The lower control electrode and the second electrode are arranged on the same layer.

24. The display device according to claim 21, wherein the pixel circuit further comprises: a node connection line connected to the first control electrode via a first contact hole; A first scanning line extending in a first direction and arranged in the same layer as the first control electrode; as well as a second scanning line extending in the first direction and arranged in the same layer as the second control electrode, Wherein, the node connection line overlaps with the first scan line and the second scan line.

25. The display device according to claim 24, wherein: The shielding electrode overlaps the node connection line.

26. A display device, comprising: substrate; A display element is disposed on the substrate; as well as a pixel circuit disposed between the substrate and the display element and connected to the display element through a connecting electrode; The pixel circuit includes: a first thin film transistor, including a first semiconductor layer and a first control electrode; a second thin film transistor, which is arranged at a different layer from the first thin film transistor and includes a second semiconductor layer and a second control electrode; a node connection line, which is connected to the first control electrode via a first contact hole and connected to the second semiconductor layer via a second contact hole; and a shielding electrode, which is arranged at the same layer as the connection electrode. The first contact hole has a height different from that of the second contact hole.

27. The display device according to claim 26, wherein the pixel circuit further comprises: A first interlayer insulating layer is provided between the first control electrode and the second semiconductor layer; as well as A second interlayer insulating layer is provided between the second semiconductor layer and the node connection line, The first contact hole penetrates the first interlayer insulating layer and the second interlayer insulating layer, and the second contact hole penetrates the second interlayer insulating layer.

28. The display device according to claim 26, wherein the pixel circuit further comprises a storage capacitor, wherein the storage capacitor comprises a first electrode and a second electrode on the first electrode. in, The second control electrode includes a lower control electrode disposed below the second semiconductor layer and an upper control electrode disposed above the second semiconductor layer, and The lower control electrode and the second electrode are arranged on the same layer.

29. The display device according to claim 26, wherein the pixel circuit further comprises: a node connection line connected to the first control electrode via a first contact hole; A first scanning line extending in a first direction and arranged in the same layer as the first control electrode; as well as a second scanning line extending in the first direction and arranged in the same layer as the second control electrode, Wherein, the node connection line overlaps with the first scan line and the second scan line.

30. The display device according to claim 26, wherein: The shielding electrode overlaps the node connection line.

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