Display device

Abstract

A display device is provided. The display device includes: a substrate; a pixel circuit layer, which is arranged on the substrate; a first conductive layer on the pixel circuit layer and including a plurality of data lines; a (1-1) th pixel electrode on the first conductive layer; a second conductive layer between the first conductive layer and the (1-1) th pixel electrode, and including: a plurality of power lines; and a (1-1)-th shielding portion that overlaps the (1-1)-th pixel electrode in a plan view. And a (1-1) th light emitting element on the (1-1) th pixel electrode. The plurality of power lines and the (1-1)-th shielding portion are integrated with each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0145930 filed in the Korean Intellectual Property Office on October 27, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] One or more embodiments of the present disclosure relate to a display device. Background Art

[0004] The display device is a device that receives information about an image and displays the image. The display device may be used as a display unit of a small-sized product such as a mobile phone, or may be used as a display unit of a large-sized product such as a television.

[0005] The display device includes a plurality of pixels that receive an electrical signal to emit light to display an image to the outside. Each pixel includes a light-emitting element, such as an organic light-emitting diode (OLED) as a light-emitting element of an organic light-emitting display device. Generally, an organic light-emitting display device includes a thin film transistor and an OLED on a substrate, and the OLED operates by emitting light by itself.

[0006] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art. Summary of the invention

[0007] The display device may have image quality degradation due to the parasitic capacitor, for example, such as a non-uniformity phenomenon that may occur due to the parasitic capacitor.

[0008] One or more embodiments of the present disclosure may be directed to a display device capable of reducing image quality degradation caused by a parasitic capacitor. However, aspects and features of the present disclosure are not limited thereto.

[0009] Additional aspects and features will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of one or more of the presented embodiments of the disclosure.

[0010] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a pixel circuit layer on the substrate; a first conductive layer on the pixel circuit layer and including a plurality of data lines; a 1-1 pixel electrode on the first conductive layer; a second conductive layer between the first conductive layer and the 1-1 pixel electrode and including: a plurality of power lines; and a 1-1 shielding portion overlapping the 1-1 pixel electrode in a plan view; and a 1-1 light-emitting element on the 1-1 pixel electrode. The plurality of power lines and the 1-1 shielding portion are integrated with each other.

[0011] In an embodiment, the display device may further include: a 2-1th pixel electrode, which is on the first conductive layer and at the same layer as the 1-1th pixel electrode; a 2-1th light-emitting element, which is on the 2-1st pixel electrode; a 3-1st pixel electrode, which is on the first conductive layer and at the same layer as the 2-1st pixel electrode; and a 3-1st light-emitting element, which is on the 3-1st pixel electrode.

[0012] In an embodiment, the second conductive layer may further include a 2-1 th shielding portion at the same layer as that of the 1-1 th shielding portion and between the first conductive layer and the 2-1 th pixel electrode.

[0013] In an embodiment, the plurality of power lines, the 1-1th shielding portion, and the 2-1th shielding portion may be integrated with each other.

[0014] In an embodiment, the plurality of power lines may include: a first vertical power line extending in a first direction; and a first horizontal power line extending in a second direction crossing the first direction and integrated with the first vertical power line.

[0015] In an embodiment, the second conductive layer may further include a 3-1 th shielding portion at the same layer as that of the 1-1 th shielding portion and between the first conductive layer and the 2-1 th pixel electrode.

[0016] In an embodiment, a shape of the 1-1th shielding portion may correspond to a shape of the 1-1th light emitting element in a plan view.

[0017] In an embodiment, in a plan view, an area of ​​the 1-1th light emitting element may be smaller than an area of ​​the 1-1th shielding portion.

[0018] In an embodiment, the 1-1th shielding portion may be located between at least one of the plurality of data lines and the 1-1th pixel electrode, and at least one of the plurality of data lines overlaps the 1-1th pixel electrode in a plan view.

[0019] In an embodiment, the shape of the 2-1st shielding portion may correspond to the shape of the 2-1st light emitting element in a plan view.

[0020] In an embodiment, in a plan view, an area of ​​the 2-1 th light emitting element may be smaller than an area of ​​the 2-1 th shielding portion.

[0021] In an embodiment, the 2-1 th shielding portion may be located between at least one of the plurality of data lines and the 2-1 th pixel electrode, and at least one of the plurality of data lines overlaps the 2-1 th pixel electrode in a plan view.

[0022] In an embodiment, the shape of the 3-1st shielding portion may correspond to the shape of the 3-1st light emitting element in a plan view.

[0023] In an embodiment, in a plan view, an area of ​​the 3-1st light emitting element may be smaller than an area of ​​the 3-1st shielding portion.

[0024] In an embodiment, the 3-1 th shielding portion may be located between at least one of the plurality of data lines and the 3-1 th pixel electrode, and at least one of the plurality of data lines overlaps the 3-1 th pixel electrode in a plan view.

[0025] In an embodiment, the first conductive layer may further include: a first vertical data line surrounding the plurality of data lines and extending in a first direction; and a first horizontal data line extending in a second direction crossing the first direction and electrically connected to the first vertical data line.

[0026] In an embodiment, the first horizontal data line may include a 1-1th horizontal data line and a 1-2th horizontal data line spaced apart from the 1-1th horizontal data line. The 1-1th horizontal data line and the 1-2th horizontal data line may be electrically connected to each other through a 1-1th bridge line at the same layer as the second conductive layer.

[0027] In an embodiment, the 1-1th bridge line may include the same material as that of the second conductive layer.

[0028] In an embodiment, the 1-1 th bridge line may be spaced apart from the plurality of power lines and the 1-1 th shielding portion in a plan view.

[0029] In an embodiment, in a plan view, an area of ​​the 1-1th pixel electrode may be greater than an area of ​​the 1-1th shielding portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings, in which:

[0031] Figure 1 is a plan view schematically illustrating a display panel of a display device according to an embodiment;

[0032] Figure 2 It is shown Figure 1 An equivalent circuit diagram of an example of a pixel of a display panel;

[0033] Figure 3 It is shown Figure 1 An equivalent circuit diagram of an example of a pixel of a display panel;

[0034] Figure 4 It is a schematic diagram Figure 1 A cross-sectional view showing an example of a cross-section of a pixel of a display panel;

[0035] Figure 5 It is a schematic diagram Figure 1 A cross-sectional view of another example of a cross-section of a pixel of a display panel;

[0036] Figure 6 It is a graphic Figure 1 A schematic plan view of an enlarged example of a region A;

[0037] Figure 7 yes Figure 6 A schematic plan view of a second conductive layer;

[0038] Figure 8 The main icon Figure 1 A schematic plan view of another enlarged example of region A;

[0039] Figures 9 to 16 It is a schematic diagram Figure 1 An example layout diagram of various layers of components in a portion of area A;

[0040] Fig.17 It is a schematic diagram Figures 9 to 16 an example layout diagram of an overlap of the layout diagrams; and

[0041] Fig.18 is an enlarged view schematically illustrating an example of a stack layout of a second conductive layer, a light emitting element, and a pixel electrode according to an embodiment. DETAILED DESCRIPTION

[0042] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings, wherein similar reference numerals refer to similar elements throughout. However, the present disclosure may be embodied in various forms and should not be construed as being limited only to the embodiments illustrated herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand aspects and features of the present disclosure may not be described. Unless otherwise stated, similar reference numerals represent similar elements throughout the accompanying drawings and written descriptions, and therefore their redundant descriptions may not be repeated.

[0043] When a specific embodiment can be implemented in different ways, the specific process order may be different from the described order. For example, two processes described in succession may be performed simultaneously or substantially simultaneously, or may be performed in the reverse order of the described order.

[0044] In the accompanying drawings, for the sake of clarity, the relative size, thickness and ratio of elements, layers and zones can be amplified and / or simplified. For ease of explanation, spatial relative terms such as "beneath", "below", "lower", "under", "above", "upper" etc. can be used in this article to describe the relationship between an element or feature and another (some) element or feature as illustrated in the figure. It will be understood that, in addition to the orientation depicted in the figure, spatial relative terms are intended to also include different orientations of the device in use or in operation. For example, if the device in the figure is flipped, the element described as "below", "below" or "below" of other elements or features will be subsequently oriented to "above" of other elements or features. Therefore, the example term "below" can include both the orientations of the top and bottom. The device can be oriented in other ways (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article should be interpreted accordingly.

[0045] In the figure, the x-axis, y-axis and z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis may be perpendicular or substantially perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0046] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, the first element, component, region, layer or section discussed below may be referred to as a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure.

[0047] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer can be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected to" another layer, region, or element, it may be directly electrically connected to the other layer, region, or element, and / or may be indirectly electrically connected with one or more intervening layers, regions, or elements therebetween. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0048] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the present disclosure. Unless otherwise clearly indicated in the context, the singular forms "a" and "an" as used herein are also intended to include the plural forms. It will also be understood that the terms "comprise", "comprising", "include", "including", "has", "have" and "having" when used in this specification specify the presence of stated features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" means A, B or A and B. When a statement such as "at least one of..." is before a column of elements, it modifies the entire column of elements, rather than the individual elements in the list. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0049] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than terms of degree, and are intended to take into account the inherent deviations in measurements or calculations that one of ordinary skill in the art will recognize. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0050] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0051] Figure 1 is a plan view schematically illustrating a display panel of a display device according to an embodiment.

[0052] like Figure 1 As shown in , the display device according to the embodiment may include the display panel 10. Any suitable display device may be implemented as long as it includes the display panel 10. For example, the display device may be various suitable devices such as a smart phone, a tablet computer, a notebook computer, a television, a billboard, etc. The display device according to the embodiment includes a thin film transistor, a capacitor, etc., and the thin film transistor, the capacitor, etc. may be implemented by a conductive layer and an insulating layer.

[0053] The display panel 10 includes a display area DA and a peripheral area PA positioned outside the display area DA. Figure 1 In the embodiment, the display area DA is shown as having a rectangular shape. However, the present disclosure is not limited thereto. The display area DA may have various suitable shapes, such as a circular shape, an elliptical shape, a polygonal shape, a shape of a specific figure, etc.

[0054] The display area DA is a portion for displaying an image, and a plurality of pixels PX may be arranged in the display area DA. Each of the plurality of pixels PX may include a display element, such as an organic light emitting diode. Each pixel PX may emit, for example, red light, green light, or blue light. The pixel PX may be connected to a pixel circuit including a thin film transistor (TFT), a storage capacitor, and the like. The pixel circuit may be connected to a scan line SL for transmitting a scan signal, a data line DL that crosses the scan line SL and transmits a data signal, and a drive voltage line PL for supplying a drive voltage. The scan line SL may extend in an x ​​direction (hereinafter referred to as a second direction x), and the data line DL and the drive voltage line PL may extend in a y direction (hereinafter referred to as a first direction y).

[0055] The pixel PX may emit light having a brightness corresponding to an electrical signal from a pixel circuit electrically connected to the pixel PX. The display area DA may display an image (e.g., a specific or predetermined image) by light emitted from the pixel PX. As described above, the pixel PX may be defined as an emission area for emitting light of any one color of red, green, and blue.

[0056] The peripheral area PA is an area in which the pixels PX are not arranged, and may be an area in which no image is displayed. Power lines for driving the pixels PX and the like may be positioned in the peripheral area PA. In addition, a plurality of pads may be arranged in the peripheral area PA. A printed circuit board including a driving circuit unit (e.g., a driving circuit) or an integrated circuit device (such as a driver integrated circuit (IC)) may be arranged in the peripheral area PA to be electrically connected to the plurality of pads.

[0057] Since the display panel 10 includes the substrate 100, the substrate 100 may be understood as having a display area DA and a peripheral area PA. The substrate 100 is described in more detail below.

[0058] exist Figure 1 In the embodiment, region A may refer to a partial region of display region DA. For convenience, region A is mainly described in more detail below, and the structure of display region DA may be understood to have a repeated structure of region A or to be similar to the structure of region A.

[0059] A plurality of transistors may be arranged in the display area DA. Depending on the type of transistor (e.g., N-type or P-type) and / or operating conditions, the first terminal of each of the plurality of transistors may be a source electrode or a drain electrode, and the second terminal thereof may be an electrode different from the first terminal. For example, when the first terminal is a source electrode, the second terminal may be a drain electrode.

[0060] The plurality of transistors may include a driving transistor, a data writing transistor, a compensation transistor, an initialization transistor, an emission control transistor, etc. The driving transistor may be connected between a driving voltage line PL and an organic light emitting diode OLED (eg, referring to Figure 2 The data write transistor may be connected to the data line DL and the driving transistor, and may perform a switching operation for transmitting a data signal transmitted through the data line DL.

[0061] The compensation transistor may be turned on in response to a scan signal received through the scan line SL, and may connect the driving transistor to the organic light emitting diode OLED to compensate for a threshold voltage of the driving transistor.

[0062] The initialization transistor may be turned on in response to a scan signal received through the scan line SL and transmit an initialization voltage to the gate electrode of the driving transistor to initialize the gate electrode of the driving transistor. The scan line connected to the compensation transistor may be a separate scan line from the scan line SL connected to the initialization transistor.

[0063] The emission control transistor may be turned on in response to an emission control signal received through the emission control line, and thus, a driving current may flow to the organic light emitting diode OLED.

[0064] The organic light emitting diode OLED may include a pixel electrode (eg, an anode) and an opposing electrode (eg, a cathode). The opposing electrode 170 (eg, referring to Figure 4 ) can receive the second power supply voltage ELVSS (for example, refer to Figure 2 ). The organic light emitting diode OLED may display an image by emitting light by receiving a driving current from a driving transistor.

[0065] Hereinafter, an organic light-emitting display device will be described in more detail as a representative example of a display device according to an embodiment, but the present disclosure is not limited thereto. In another embodiment, the display device may be an inorganic light-emitting display device (e.g., an inorganic light-emitting display or an inorganic electroluminescent display device) or a quantum dot light-emitting display device. For example, an emission layer of a display element included in a display device may include an organic material or an inorganic material. In addition, the display device may include an emission layer and quantum dots positioned on a path of light emitted by the emission layer.

[0066] Figure 2 It is shown Figure 1 FIG. 1 is an equivalent circuit diagram of an example of a pixel of a display panel.

[0067] like Figure 2 As shown in FIG. 1 , each pixel PX includes a pixel circuit PC connected to a corresponding scan line SL and a corresponding data line DL, and an organic light emitting diode OLED connected to the pixel circuit PC.

[0068] The pixel circuit PC includes a driving thin film transistor Td, a switching thin film transistor Ts and a storage capacitor Cst. The switching thin film transistor Ts is connected to the scan line SL and the data line DL, and transmits a data signal Dm input through the data line DL to the driving thin film transistor Td in response to a scan signal Sn input through the scan line SL.

[0069] The storage capacitor Cst is connected to the switching thin film transistor Ts and the driving voltage line PL, and stores a voltage corresponding to a difference between a voltage received from the switching thin film transistor Ts and a first power source voltage ELVDD supplied to the driving voltage line PL.

[0070] The second power voltage ELVSS may be a driving voltage having a relatively low level compared to the first power voltage ELVDD. The level of the driving voltage supplied to each pixel PX may be a difference between the levels of the first power voltage ELVDD and the second power voltage ELVSS.

[0071] The driving thin film transistor Td may be connected to the driving voltage line PL and the storage capacitor Cst, and may control the driving current to flow from the driving voltage line PL to the organic light emitting diode OLED according to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light having a desired brightness (e.g., a specific or predetermined brightness) according to the driving current.

[0072] Although Figure 2 The pixel circuit PC is illustrated as including two thin film transistors and one storage capacitor, but the present disclosure is not limited thereto. The pixel circuit PC may also include two or more storage capacitors.

[0073] Figure 3 It is shown Figure 1 FIG. 1 is an equivalent circuit diagram of an example of a pixel of a display panel.

[0074] In the following, reference is made to Figure 3 , you don’t need to repeat the above reference Figure 2 The same redundant description as the description of . In addition, Figure 3 The pixel circuit PC is illustrated as including eight thin film transistors and one storage capacitor, but the present disclosure is not limited thereto. The pixel circuit PC may also include two or more storage capacitors.

[0075] Reference Figure 3 , the pixel circuit PC may include first to eighth transistors T1 to T8. Depending on the transistor type (e.g., P-type or N-type) and / or operating conditions, the first terminal of each of the first to eighth transistors T1 to T8 may be a source terminal or a drain terminal, and the second terminal thereof may be a terminal different from the first terminal.

[0076] For example, when the first terminal is a source terminal, the second terminal may be a drain terminal. The first transistor T1 may be a driving transistor having a magnitude of its source-drain current determined according to its gate-source voltage. The second transistor T2 to the eighth transistor T8 may all be used as a switching transistor that is turned on / off in response to its gate-source voltage or its gate voltage or substantially the gate voltage.

[0077] The pixel circuit PC can be connected to a first gate line GWL transmitting a first gate signal GW, a second gate line GIL transmitting a second gate signal GI, a third gate line GCL transmitting a third gate signal GC, a fourth gate line GBL transmitting a fourth gate signal GB, an emission control line EML transmitting an emission control signal EM, a data line DL transmitting a data signal Dm, a driving voltage line PL transmitting a first power supply voltage ELVDD, a first initialization voltage line VIL1 transmitting a first initialization voltage VINT, and a second initialization voltage line VIL2 transmitting a second initialization voltage VAINT.

[0078] The first transistor T1 may include a gate and a source terminal S / drain terminal D. The first transistor T1 receives a data signal Dm according to a switching operation of the second transistor T2 and supplies a driving current to the light emitting element. The light emitting element may be an organic light emitting diode OLED. The gate of the first transistor T1 may be a first electrode CE1 of the storage capacitor Cst.

[0079] The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first transistor T1 and the eighth transistor T8. The second transistor T2 may be turned on in response to the first gate signal GW received through the first gate line GWL, and may perform a switching operation for providing the data signal Dm provided to the data line DL to the first transistor T1. For example, the second transistor T2 may be a data write transistor.

[0080] The third transistor T3 may include a gate connected to a third gate line GCL. The third transistor T3 may be turned on to diode-connect the first transistor T1 in response to a third gate signal GC received through the third gate line GCL. For example, the third transistor T3 may be a compensation transistor.

[0081] The fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the first initialization voltage line VIL1, and a second terminal connected to the first electrode CE1 of the storage capacitor Cst. The fourth transistor T4 may be turned on in response to the second gate signal GI received through the second gate line GIL, and transmit the first initialization voltage VINT to the gate of the first transistor T1 to initialize the gate voltage of the first transistor T1. For example, the fourth transistor T4 may be a first initialization transistor.

[0082] The fifth transistor T5 may include a gate connected to the emission control line EML, a first terminal connected to the driving voltage line PL, and a second terminal connected to the first transistor T1. For example, the fifth transistor T5 may be a first emission control transistor.

[0083] The sixth transistor T6 may include a gate connected to the emission control line EML, a first terminal connected to the first transistor T1 and the third transistor T3, and a second terminal connected to the pixel electrode of the organic light emitting diode OLED. The sixth transistor T6 may be a second emission control transistor.

[0084] The fifth transistor T5 and the sixth transistor T6 may be turned on simultaneously or substantially simultaneously in response to the emission control signal EM received through the emission control line EML, and thus, a driving current may flow to the organic light emitting diode OLED.

[0085] The seventh transistor T7 may include a gate connected to the fourth gate line GBL, a first terminal connected to the sixth transistor T6 and the pixel electrode of the organic light emitting diode OLED, and a second terminal connected to the second initialization voltage line VIL2. The seventh transistor T7 may be turned on in response to the fourth gate signal GB received through the fourth gate line GBL, and transmit the second initialization voltage VAINT to the pixel electrode of the organic light emitting diode OLED to initialize the pixel electrode of the organic light emitting diode OLED. For example, the seventh transistor T7 may be a second initialization transistor. However, the seventh transistor T7 may be omitted as needed or desired.

[0086] The eighth transistor T8 may include a gate connected to the fourth gate line GBL, a first terminal connected to the first transistor T1, and a second terminal connected to the bias voltage line VL3 transmitting the conduction bias voltage VOBS. The eighth transistor T8 may be turned on in response to the fourth gate signal GB received through the fourth gate line GBL, and send the conduction bias voltage VOBS to the first transistor T1. In this case, the first transistor T1 may be in a conduction bias state, and the threshold voltage characteristic of the first transistor T1 may be changed. Therefore, in low-frequency driving, the characteristic of the first transistor T1 may be fixed (e.g., changed) to a specific state to prevent or substantially prevent degradation.

[0087] The storage capacitor Cst may include a first electrode CE1 connected to the gate electrode of the first transistor T1 and a second electrode CE2 connected to the driving voltage line PL.

[0088] The organic light emitting diode OLED may include a pixel electrode and a common electrode facing the pixel electrode, and the common electrode may receive the second power voltage ELVSS. The organic light emitting diode OLED may receive a driving current from the first transistor T1 and may emit light having a specific color to display an image.

[0089] exist Figure 2 and Figure 3 , the driving thin film transistor Td, the switching thin film transistor Ts, the first transistor T1, the second transistor T2, and the fifth transistor T5 to the eighth transistor T8 of the pixel circuit PC are shown as P-type transistors, but the present disclosure is not limited thereto. For example, the first transistor T1 to the eighth transistor T8 of the pixel circuit PC may be an N-type transistor, or some of the first transistor T1 to the eighth transistor T8 may be a P-type transistor, and the other of the first transistor T1 to the eighth transistor T8 may be an N-type transistor.

[0090] Figure 4 It is a schematic diagram Figure 1 A cross-sectional view of an example of a cross-section of a pixel of a display panel.

[0091] In the following, reference is made to Figure 4 , you don’t need to repeat the above reference Figures 1 to 3 Redundant description of those components described that are identical or substantially identical.

[0092] The substrate 100 may include an area corresponding to the display area DA and a peripheral area PA outside the display area DA. The substrate 100 may include various suitable materials that are flexible or bendable. For example, the substrate 100 may include glass, metal, or a polymer resin. The substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 may have a multilayer structure including two layers and a barrier layer arranged between the two layers, the two layers each including a polymer resin, the barrier layer including an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). However, the present disclosure is not limited thereto, and various modifications may be made.

[0093] In some embodiments, in order to achieve ultra-high resolution, the substrate 100 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The substrate 100 may include a silicon layer. In other words, the substrate 100 may be a semiconductor substrate including a semiconductor material. The substrate 100 may include a silicon wafer formed by using a semiconductor process. In this case, an active layer may be formed inside the substrate 100 including the silicon wafer, and a gate line, a data line, and a transistor may be arranged on the upper surface of the substrate 100. Therefore, the organic light emitting diode OLED using the substrate 100 including the silicon wafer may be referred to as a silicon-based organic light emitting diode (OLEDoS). For example, in the case of OLEDoS, a complementary metal oxide semiconductor (CMOS) process may be used to form a finer pixel PX, and an organic light emitting diode device may be formed on an electrode formed by a CMOS process. In order to respectively realize the colors of red (R), green (G), and blue (B) in OLEDoS, a white organic light emitting diode may be generally made, and a color filter may be arranged on the white organic light emitting diode to realize the colors of red (R), green (G), and blue (B). OLEDoS can be mainly used for extended reality (XR), and can achieve ultra-high image quality of 8K or more in a small area of ​​about 1 inch to 2 inches. When a semiconductor substrate is used, the pixels PX arranged at ultra-high resolution can be precisely controlled. However, the present disclosure is not limited thereto.

[0094] The buffer layer 101 may be positioned on the substrate 100. The buffer layer 101 may be used as a barrier layer and / or a blocking layer to prevent or substantially prevent diffusion of impurity ions, prevent or substantially prevent penetration of moisture and / or external air, and planarize or substantially planarize the surface of the substrate 100. The buffer layer 101 may include silicon oxide, silicon nitride, or silicon oxynitride. In addition, the buffer layer 101 may adjust a heat supply rate during a crystallization process for forming the semiconductor layer 110 so that the semiconductor layer 110 is uniformly or substantially uniformly crystallized.

[0095] The semiconductor layer 110 may be positioned on the buffer layer 101. The semiconductor layer 110 may include polysilicon or an oxide semiconductor. The semiconductor layer 110 may include a channel region that is not doped (or more lightly doped) with impurities and a source region and a drain region formed by doping impurities on both sides (e.g., opposite sides) of the channel region, respectively. Here, the impurities may vary depending on the type of thin film transistor to be implemented, and may be N-type impurities or P-type impurities.

[0096] For example, the display device according to an embodiment may include a plurality of transistors, and at least one of the plurality of transistors may include an oxide semiconductor.

[0097] The gate insulating film 102 may be positioned on the semiconductor layer 110. The gate insulating film 102 may ensure insulation between the semiconductor layer 110 and the first gate layer 120a. The gate insulating film 102 may include an inorganic material, such as silicon oxide, silicon nitride and / or silicon oxynitride, and may be arranged between the semiconductor layer 110 and the first gate layer 120a. In addition, the gate insulating film 102 may have a shape corresponding to the entire or substantially the entire surface of the substrate 100, and may have a structure in which a contact hole is formed in a portion thereof (e.g., a predetermined portion) (e.g., penetrating a portion thereof (e.g., a predetermined portion)). Therefore, the insulating film including the inorganic material may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The above content may be similarly applied to the embodiments and modified examples described in more detail below.

[0098] The first gate layer 120a may be positioned on the gate insulating film 102. The first gate layer 120a may be disposed at a position vertically overlapping the semiconductor layer 110, and may include at least one metal among molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), titanium (Ti), tungsten (W), and copper (Cu).

[0099] The first interlayer insulating film 103a may be positioned on the first gate layer 120a. The first interlayer insulating film 103a may cover the first gate layer 120a. The first interlayer insulating film 103a may include an inorganic material. For example, the first interlayer insulating film 103a may include a metal oxide or a metal nitride, and the inorganic material may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), zinc oxide (ZnO 2 ) etc. In some embodiments, the first interlayer insulating film 103a may include SiO x / SiN y or SiN x / SiO y The dual structure.

[0100] The second gate layer 120b may be positioned on the first interlayer insulating film 103a. The second gate layer 120b may be arranged at a position vertically overlapping the first gate layer 120a, and may include at least one metal among Mo, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Ti, W, and Cu.

[0101] In some embodiments, the second gate layer 120b may form the above reference 10 with the first gate layer 120a. Figure 3 The first gate layer 120a may be one electrode of the storage capacitor Cst, and the second gate layer 120b may be the other electrode of the storage capacitor Cst.

[0102] The second interlayer insulating film 103b may be positioned on the second gate layer 120b. The second interlayer insulating film 103b may cover the second gate layer 120b. The second interlayer insulating film 103b may include an inorganic material. For example, the second interlayer insulating film 103b may include a metal oxide or a metal nitride, and the inorganic material may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), zinc oxide (ZnO 2 ) etc. In some embodiments, the second interlayer insulating film 103b may include SiO x / SiN y or SiN x / SiO y The dual structure.

[0103] The first conductive layer 130 may be positioned on the second interlayer insulating film 103b. The first conductive layer 130 may be used as an electrode connected to the source / drain region of the semiconductor layer 110 through a through hole included in the second interlayer insulating film 103b (e.g., penetrating the second interlayer insulating film 103b). The first conductive layer 130 may include at least one metal selected from Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu. For example, the first conductive layer 130 may include a Ti layer, an Al layer, and / or a Cu layer.

[0104] The first organic insulating layer 104 may be positioned on the first conductive layer 130. The first organic insulating layer 104 may be an organic insulating layer that covers an upper portion of the first conductive layer 130 and has a flat or substantially flat upper surface to serve as a planarization film. The first organic insulating layer 104 may include, for example, an organic material such as acrylic acid, benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), etc. The first organic insulating layer 104 may be variously modified as needed or desired, such as having a single-layer structure or a multi-layer structure as an example.

[0105] The second conductive layer 140 may be positioned on the first organic insulating layer 104. The second conductive layer 140 may be used as an electrode connected to the source / drain region of the semiconductor layer 110 through a through hole included in the first organic insulating layer 104 (e.g., penetrating the first organic insulating layer 104). The second conductive layer 140 may include at least one metal selected from Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu. For example, the second conductive layer 140 may include a Ti layer, an Al layer, and / or a Cu layer.

[0106] The second organic insulating layer 105 may be positioned on the second conductive layer 140. The second organic insulating layer 105 may be an organic insulating layer that covers an upper portion of the second conductive layer 140 and has a flat or substantially flat upper surface to serve as a planarization film. The second organic insulating layer 105 may include, for example, an organic material such as acrylic acid, BCB, HMDSO, etc. The second organic insulating layer 105 may be variously modified as needed or desired, such as having a single-layer structure or a multi-layer structure as an example.

[0107] In addition, in some embodiments, an additional conductive layer and an additional insulating layer may be arranged between the conductive layer and the pixel electrode 150, and this may be applicable to various embodiments of the present disclosure. In this case, the additional conductive layer may include the same material as the conductive layer described above, and may have the same layer structure. The additional insulating layer may include the same material as the organic insulating layer described above, and may have the same layer structure.

[0108] The pixel electrode 150 may be positioned on the second organic insulating layer 105. The pixel electrode 150 may be connected to the second conductive layer 140 through a contact hole formed in (eg, penetrating) the second organic insulating layer 105. The display element may be positioned on the pixel electrode 150.

[0109] The organic light emitting diode OLED may be used as a display element. In other words, the organic light emitting diode OLED may be arranged on, for example, the pixel electrode 150. The pixel electrode 150 may include a material including, for example, ITO, In 2 O 3The pixel electrode 150 may include a transparent conductive layer of a transparent conductive oxide such as ITO, IZO, etc. and a reflective layer including a metal such as Al, Ag, etc. For example, the pixel electrode 150 may have a triple-layer structure of ITO / Ag / ITO.

[0110] The pixel defining layer 106 may be positioned on the second organic insulating layer 105, and may be arranged to cover the edge of the pixel electrode 150. In other words, the pixel defining layer 106 may cover the edge of the pixel electrode 150. The pixel defining layer 106 may have an opening portion corresponding to the pixel PX, and the opening portion may be formed to expose at least a central portion of the pixel electrode 150. The pixel defining layer 106 may include, for example, an organic material such as polyimide or HMDSO, or may include, for example, a silicon compound (e.g., SiN x 、SiO x etc.) of inorganic materials.

[0111] In some embodiments, a spacer may be further disposed on the pixel defining layer 106. The spacer may be positioned in the peripheral area PA and may also be positioned in the display area DA. The spacer may prevent or substantially prevent the organic light emitting diode OLED from being damaged due to sagging of the mask during a manufacturing process using the mask. The spacer may include an organic insulating material and may be formed as a single layer or multiple layers.

[0112] Hereinafter, for convenience, the first organic insulating layer 104 , the second organic insulating layer 105 , and the pixel defining layer 106 may be referred to as a plurality of organic insulating films or layers OL.

[0113] The intermediate layer 160 may be disposed on the pixel electrode 150. For example, the intermediate layer 160 may be positioned in the opening portion of the pixel defining layer 106. For example, the intermediate layer 160 and the opposite electrode 170 may be positioned in the opening portion of the pixel defining layer 106.

[0114] The intermediate layer 160 may include a low molecular weight material or a polymer material. The intermediate layer 160 may include a hole injection layer, a hole transport layer, an emission layer, an electron transport layer, and / or an electron injection layer, etc.

[0115] The counter electrode 170 may include a material such as ITO, In 2 O 3 , IZO, etc. As another example, the opposing electrode 170 may be a conductive layer containing Ag and / or Mg. The pixel electrode 150 serves as an anode, and the opposing electrode 170 serves as a cathode. The polarity of the electrodes may be reversely applied.

[0116] However, the structure of the intermediate layer 160 is not limited thereto and may have various suitable structures. For example, at least one of the plurality of layers constituting the intermediate layer 160 may be integrally formed with the opposing electrode 170. As another example, the intermediate layer 160 may include a layer patterned to correspond to each of the plurality of pixel electrodes 150.

[0117] The opposing electrode 170 may be arranged in the display area DA and may cover the entire or substantially the entire surface of the display area DA. For example, the opposing electrode 170 may be integrated to cover a plurality of pixels PX. The opposing electrode 170 may be in electrical contact with a power line arranged in the peripheral area PA. In an embodiment, the opposing electrode 170 may extend to the blocking wall.

[0118] The thin film encapsulation layer TFE may be disposed on the opposite electrode 170. The thin film encapsulation layer TFE may be disposed to completely cover the display area DA, and may extend toward the peripheral area PA to cover at least a portion of the peripheral area PA.

[0119] The thin film encapsulation layer TFE may include a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include at least one inorganic material among aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0120] The organic encapsulation layer 320 may include a monomer-based material or a polymer-based material. The polymer-based material may include acrylic resin, epoxy resin, polyimide, polyethylene, etc. In an embodiment, the organic encapsulation layer 320 may include acrylate.

[0121] The barrier wall may be positioned in the peripheral area PA of the substrate 100. In an implementation, the barrier wall may include a portion of the first organic insulating layer 104, a portion of the second organic insulating layer 105, a portion of the pixel defining layer 106, and a portion of the spacer, but the disclosure is not limited thereto.

[0122] In some cases, the barrier wall may be arranged to surround the display area DA (eg, around the periphery of the display area DA), and may prevent or substantially prevent the organic encapsulation layer 320 of the thin film encapsulation layer TFE from overflowing to the outside of the substrate 100 .

[0123] Figure 5 It is a schematic diagram Figure 1 A cross-sectional view of another example of a cross-section of a pixel of a display panel.

[0124] In the following, reference is made to Figure 5 , you don’t need to repeat the above reference Figures 1 to 4Redundant description of components that are identical or substantially identical to the components described.

[0125] Reference Figure 5 The display device according to the embodiment may further include a bottom metal layer BML between the substrate 100 and the semiconductor layer 110. The display device may include (eg, may include only) one bottom metal layer BML, or two or more bottom metal layers BML. The bottom metal layer BML may cover at least a portion of the display area DA.

[0126] The bottom metal layer BML may be arranged to correspond to the lower portion of the wires of the display device and the lower portion of the plurality of transistors. The bottom metal layer BML may prevent or substantially prevent external light from reaching the wires. In addition, the bottom metal layer BML may prevent or substantially prevent external light from reaching the semiconductor layer 110. The bottom metal layer BML may include a metal such as silver, copper, aluminum, etc.

[0127] As used herein, external light may refer to light entering from outside the rear surface of the display device, or light reaching the rear surface through the front surface of the display device, which is reflected back to the display device by the rear surface of the display device.

[0128] like Figure 5 As shown in FIG. 1 , the buffer layer 101 may be disposed between the bottom metal layer BML and the semiconductor layer 110 . The buffer layer 101 may cover the upper surface of the bottom metal layer BML. An additional insulating layer 100 ′ including an inorganic material may be further included between the bottom metal layer BML and the substrate 100 .

[0129] like Figure 5 As shown in , the display device may further include an additional semiconductor layer 110'. The additional semiconductor layer 110' may be arranged on the second interlayer insulating film 103b. The additional semiconductor layer 110' may include polycrystalline silicon or an oxide semiconductor. The additional semiconductor layer 110' may include a channel region that is not doped (or more lightly doped) with impurities and a source region and a drain region formed by doping impurities on both sides (e.g., opposite sides) of the channel region, respectively. Here, the impurity may be variously modified according to the type of thin film transistor to be implemented, and may be an N-type impurity or a P-type impurity.

[0130] For example, the display device according to the embodiment may include a plurality of transistors, and at least one of the plurality of transistors may be configured by the additional semiconductor layer 110 ′ including an oxide semiconductor.

[0131] The additional gate insulating film 103c may be arranged on the additional semiconductor layer 110'. The additional gate insulating film 103c may cover the additional semiconductor layer 110'. The additional gate insulating film 103c may ensure insulation between the additional semiconductor layer 110' and the third gate layer 120c. The additional gate insulating film 103c may include an inorganic material, such as silicon oxide, silicon nitride and / or silicon oxynitride, and may be arranged between the additional semiconductor layer 110' and the third gate layer 120c. In addition, similar to the additional gate insulating film 103c, an insulating film including an inorganic material may be formed by CVD or ALD. The above description is similar to the embodiment and its modified example to be described below.

[0132] The third gate layer 120c may be disposed on the additional gate insulating film 103c. The third gate layer 120c may be disposed at a position vertically overlapping the additional semiconductor layer 110', and may include at least one metal among Mo, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Ti, W, and Cu.

[0133] The third interlayer insulating film 103d may be disposed on the third gate layer 120c. The third interlayer insulating film 103d may cover the third gate layer 120c. The third interlayer insulating film 103d may include an inorganic material. For example, the third interlayer insulating film 103d may be a metal oxide or a metal nitride. For example, the inorganic material may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO 2 ) etc. In some embodiments, the third interlayer insulating film 103d may include SiO x / SiN y or SiN x / SiO y The dual structure.

[0134] The first conductive layer 130 may be electrically connected to a portion of the semiconductor layer 110 and a portion of the additional semiconductor layer 110' through a through hole. For example, the first conductive layer 130 may be electrically connected to a portion of the semiconductor layer 110 through one through hole. For example, the first conductive layer 130 may be electrically connected to a portion of the additional semiconductor layer 110' through another through hole.

[0135] As described above, the first organic insulating layer 104 and the like may be disposed on the first conductive layer 130. The second conductive layer 140 may be disposed on the first organic insulating layer 104. The second organic insulating layer 105 may be disposed on the second conductive layer 140. The pixel electrode 150, the intermediate layer 160, and the opposite electrode 170 may be disposed on the second organic insulating layer 105, and the thin film encapsulation layer TFE may be disposed on the opposite electrode 170.

[0136] Figure 6 It is a graphic Figure 1 Schematic plan view of an enlarged example of region A.

[0137] In the following, reference is made to Figure 6 , you don’t need to repeat the above reference Figures 1 to 5 Redundant description of components that are identical or substantially identical to the components described.

[0138] In addition, for the sake of convenience, Figure 6 Some of the components are shown in the figures, and other components may be more clearly understood with reference to some of the other drawings.

[0139] Reference Figure 6 , the display device according to the embodiment may include a first data line DL1, a second data line DL2, a third data line DL3, and a fourth data line DL4. Each of the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4 may be formed by a portion of the first conductive layer 130 described above and may have the same or substantially the same characteristics as those of the first conductive layer 130 described above.

[0140] The display device according to the embodiment may include a substrate 100, a pixel circuit layer, a first conductive layer 130, a pixel electrode 150, a second conductive layer 140, and a 1-1 th light emitting element PX-G1. The pixel circuit layer may be defined as Figure 4 or Figure 5 Among the components shown in FIG. 1 , a plurality of layers positioned between the substrate 100 and the first conductive layer 130 are shown. For example, according to Figure 4 The pixel circuit layer of the embodiment illustrated in FIG. 1 may include a semiconductor layer 110, a first gate layer 120a, and a second gate layer 120b. Figure 5 The pixel circuit layer of the embodiment illustrated in FIG. 1 may include a bottom metal layer BML, a semiconductor layer 110 , a first gate layer 120 a , a second gate layer 120 b , an additional semiconductor layer 110 ′, and a third gate layer 120 c .

[0141] The first conductive layer 130 may be disposed on the pixel circuit layer and may include a plurality of data lines. The plurality of data lines may include a first data line DL1, a second data line DL2, a third data line DL3, a fourth data line DL4, and in addition, the plurality of data lines may further include an nth data line, etc. (where n is a natural number greater than 1).

[0142] The pixel electrode 150 may include a plurality of pixel electrodes respectively corresponding to the plurality of pixels PX arranged in the display area DA. For example, the plurality of pixel electrodes may include a first pixel electrode, a second pixel electrode, and a third pixel electrode. The first pixel electrode corresponds to a first light emitting element for emitting light in a first wavelength band, the second pixel electrode corresponds to a second light emitting element for emitting light in a second wavelength band, and the third pixel electrode corresponds to a third light emitting element for emitting light in a third wavelength band.

[0143] The second conductive layer 140 may be arranged between the first conductive layer 130 and the pixel electrode, and may include a plurality of power supply lines. In a plan view, the second conductive layer 140 may include a 1-1 shielding portion SH1-1 overlapping the first pixel electrode. In a plan view, the second conductive layer 140 may include a 2-1 shielding portion SH2-1 overlapping the second pixel electrode. In a plan view, the second conductive layer 140 may include a 3-1 shielding portion SH3-1 overlapping the third pixel electrode.

[0144] The second conductive layer 140 may further include a 1-2 shielding portion SH1-2, a 1-3 shielding portion SH1-3, a 1-4 shielding portion SH1-4, a 1-5 shielding portion SH1-5, a 1-6 shielding portion SH1-6, etc. The second conductive layer 140 may further include a 2-2 shielding portion SH2-2, a 3-2 shielding portion SH3-2, etc.

[0145] For example, the pixel electrode arranged on the 1-1 shielding portion SH1-1 may be referred to as the 1-1 pixel electrode. The pixel electrode arranged on the 1-2 shielding portion SH1-2 may be referred to as the 1-2 pixel electrode. The pixel electrode arranged on the 1-3 shielding portion SH1-3 may be referred to as the 1-3 pixel electrode. The pixel electrode arranged on the 1-4 shielding portion SH1-4 may be referred to as the 1-4 pixel electrode. The pixel electrode arranged on the 1-5 shielding portion SH1-5 may be referred to as the 1-5 pixel electrode. The pixel electrode arranged on the 1-6 shielding portion SH1-6 may be referred to as the 1-6 pixel electrode.

[0146] For example, a pixel electrode disposed on a 2-1th shielding portion SH2 - 1 may be referred to as a 2-1th pixel electrode, and a pixel electrode disposed on a 2-2nd shielding portion SH2 - 2 may be referred to as a 2-2nd pixel electrode.

[0147] For example, the 2-1st shielding portion SH2-1 may be disposed between the first conductive layer 130 and the 2-1st pixel electrode, and may be disposed at the same layer as that of the 1-1st shielding portion SH1-1 (e.g., in the middle or on top). Therefore, a plurality of power lines, the 1-1st shielding portion SH1-1, and the 2-1st shielding portion SH2-1 may be integrated with each other.

[0148] For example, a pixel electrode disposed on a 3-1th shielding portion SH3-1 may be referred to as a 3-1th pixel electrode, and a pixel electrode disposed on a 3-2nd shielding portion SH3-2 may be referred to as a 3-2nd pixel electrode.

[0149] The 3-1st shielding portion SH3-1 may be disposed between the first conductive layer 130 and the 3-1st pixel electrode, and may be disposed at the same layer as that of the 1-1st shielding portion SH1-1 (e.g., in the middle or on top). Therefore, a plurality of power lines, the 1-1st shielding portion SH1-1, the 2-1st shielding portion SH2-1, and the 3-1st shielding portion SH3-1 may be integrated with each other.

[0150] Thus, the plurality of shielding portions and the plurality of power lines may all be arranged at the same layer (eg, in or on) as one another, and may include the same material as one another, so that they may all be integrated with one another.

[0151] For example, each of the plurality of shielding portions may have a shielding shape in a plan view.

[0152] For example, the shape of each of the plurality of shielding portions in a plan view may be identical to the shape of each of the plurality of light emitting elements in a plan view (eg, the shape of an emission region defined by a pixel defining layer in a plan view).

[0153] For example, the area of ​​each of the plurality of shielding portions in a plan view may be larger than the area of ​​each of the plurality of light emitting elements in a plan view (eg, the area of ​​an emission region defined by a pixel defining layer in a plan view).

[0154] The first vertical power line VL1 may be integrated with the 1-1 shielding portion SH1-1, the 1-2 shielding portion SH1-2, the 1-3 shielding portion SH1-3, etc., and may be electrically connected to the 1-1 shielding portion SH1-1, the 1-2 shielding portion SH1-2, the 1-3 shielding portion SH1-3, etc. The second vertical power line VL2 may be integrated with the 1-4 shielding portion SH1-4, the 1-5 shielding portion SH1-5, the 1-6 shielding portion SH1-6, etc., and may be electrically connected to the 1-4 shielding portion SH1-4, the 1-5 shielding portion SH1-5, the 1-6 shielding portion SH1-6, etc.

[0155] The first horizontal power line VH1 may be integrated with the 2-1st shielding portion SH2-1, the 3-2nd shielding portion SH3-2, etc., and may be electrically connected to the 2-1st shielding portion SH2-1, the 3-2nd shielding portion SH3-2, etc. The second horizontal power line VH2 may be integrated with the 3-1st shielding portion SH3-1, the 2-2nd shielding portion SH2-2, etc., and may be electrically connected to the 3-1st shielding portion SH3-1, the 2-2nd shielding portion SH2-2, etc.

[0156] Multiple power lines may be included in Figure 2 and Figure 3 The driving voltage line PL for transmitting the first power supply voltage ELVDD shown in FIG. A plurality of power lines may be integrated with each other. A plurality of power lines may be formed integrally with each other and may be formed simultaneously or substantially simultaneously in the same process as each other. A plurality of power lines may be arranged at the same layer as each other (e.g., in or on) and may include the same material as each other.

[0157] The plurality of power lines may include a first vertical power line VL1 and a second vertical power line VL2 extending in a first direction y. The plurality of power lines may include a first horizontal power line VH1 and a second horizontal power line VH2 extending in a second direction x intersecting the first direction y. In addition, the plurality of power lines may further include an nth vertical power line extending in the first direction y, and may further include an nth horizontal power line extending in the second direction x (where n is a natural number greater than 1).

[0158] The 1-1 shielding portion SH1-1 may be formed integrally with the plurality of power lines. In other words, the 1-1 shielding portion SH1-1 may be arranged at the same layer as that of the plurality of power lines (e.g., in or above), and may include the same material as that of the plurality of power lines. The 1-1 shielding portion SH1-1 may be electrically connected to the plurality of power lines, and the first power supply voltage ELVDD may be applied to the plurality of power lines.

[0159] The 1-1 shielding portion SH1-1 may be used to block parasitic capacitors that may occur between the plurality of data lines and the 1-1 pixel electrode. Therefore, the 1-1 shielding portion SH1-1 may be disposed below the 1-1 pixel electrode, and in a plan view, the 1-1 shielding portion SH1-1 and the 1-1 pixel electrode may overlap each other.

[0160] A plurality of shielding portions (e.g., 1-1 shielding portion SH1-1 to 3-2 shielding portion SH3-2, etc.) may be used to block parasitic capacitors that may occur between pixel electrodes (e.g., 1-1 pixel electrodes to 3-2 pixel electrodes, etc.) and a plurality of data lines. Therefore, a plurality of shielding portions may be arranged between the pixel electrode and the plurality of data lines, and each of the plurality of shielding portions may be arranged to overlap with a corresponding pixel electrode in a plan view.

[0161] like Figure 6 As shown in , the display device according to the embodiment may include first light emitting elements including 1-1 light emitting elements PX-G1 to 1-6 light emitting elements PX-G6, etc., second light emitting elements including 2-1 light emitting elements PX-R1 and 2-2 light emitting elements PX-R2, etc., and third light emitting elements including 3-1 light emitting elements PX-B1 and 3-2 light emitting elements PX-B2, etc. For example, the first light emitting element may be a pixel PX for emitting light in a first wavelength band, the second light emitting element may be a pixel PX for emitting light in a second wavelength band, and the third light emitting element may be a pixel PX for emitting light in a third wavelength band.

[0162] For example, the 1-1th light-emitting element PX-G1 may be arranged on the 1-1th pixel electrode, the 1-2th light-emitting element PX-G2 may be arranged on the 1-2th pixel electrode, the 1-3rd light-emitting element PX-G3 may be arranged on the 1-3rd pixel electrode, the 1-4th light-emitting element PX-G4 may be arranged on the 1-4th pixel electrode, the 1-5th light-emitting element PX-G5 may be arranged on the 1-5th pixel electrode, and the 1-6th light-emitting element PX-G6 may be arranged on the 1-6th pixel electrode.

[0163] For example, the 2-1st light-emitting element PX-R1 may be arranged on the 2-1st pixel electrode, the 2-2nd light-emitting element PX-R2 may be arranged on the 2-2nd pixel electrode, the 3-1st light-emitting element PX-B1 may be arranged on the 3-1st pixel electrode, and the 3-2nd light-emitting element PX-B2 may be arranged on the 3-2nd pixel electrode.

[0164] For example, the shape of the 1-1th shielding portion SH1-1 may correspond to the shape of the 1-1th light emitting element PX-G1 in a plan view. The area of ​​the 1-1th light emitting element PX-G1 may be smaller than the area of ​​the 1-1th shielding portion SH1-1 in a plan view.

[0165] For example, the 1-1th shielding portion SH1-1 may be disposed between at least one of the plurality of data lines and the 1-1th pixel electrode, and in a plan view, at least one of the plurality of data lines overlaps the 1-1th pixel electrode.

[0166] For example, the shape of the 2-1st shielding portion SH2-1 may correspond to the shape of the 2-1st light emitting element PX-R1 in plan view. The area of ​​the 2-1st light emitting element PX-R1 may be smaller than the area of ​​the 2-1st shielding portion SH2-1 in plan view.

[0167] For example, the 2-1 th shielding portion SH2 - 1 may be disposed between at least one of the plurality of data lines and the 2-1 th pixel electrode, and in a plan view, at least one of the plurality of data lines overlaps the 2-1 th pixel electrode.

[0168] For example, the shape of the 3-1st shielding portion SH3-1 may correspond to the shape of the 3-1st light emitting element PX-B1 in plan view. The area of ​​the 3-1st light emitting element PX-B1 may be smaller than the area of ​​the 3-1st shielding portion SH3-1 in plan view.

[0169] For example, the 3-1 th shielding portion SH3-1 may be disposed between at least one of the plurality of data lines and the 3-1 th pixel electrode, and in a plan view, at least one of the plurality of data lines overlaps the 3-1 th pixel electrode.

[0170] For example, the shape of the 1-2nd shielding portion SH1-2 may correspond to the shape of the 1-2nd light emitting element PX-G2 in a plan view. The area of ​​the 1-2nd light emitting element PX-G2 may be smaller than the area of ​​the 1-2nd shielding portion SH1-2 in a plan view.

[0171] For example, the shape of the 1-3rd shielding portion SH1-3 may correspond to the shape of the 1-3rd light emitting element PX-G3 in a plan view. The area of ​​the 1-3rd light emitting element PX-G3 may be smaller than the area of ​​the 1-3rd shielding portion SH1-3 in a plan view.

[0172] For example, the shape of the 1-4th shielding portion SH1-4 may correspond to the shape of the 1-4th light emitting element PX-G4 in a plan view. The area of ​​the 1-4th light emitting element PX-G4 may be smaller than the area of ​​the 1-4th shielding portion SH1-4 in a plan view.

[0173] For example, the shape of the 1-5th shielding portion SH1-5 may correspond to the shape of the 1-5th light emitting element PX-G5 in a plan view. The area of ​​the 1-5th light emitting element PX-G5 may be smaller than the area of ​​the 1-5th shielding portion SH1-5 in a plan view.

[0174] For example, the shape of the 1-6th shielding portion SH1-6 may correspond to the shape of the 1-6th light emitting element PX-G6 in a plan view. The area of ​​the 1-6th light emitting element PX-G6 may be smaller than the area of ​​the 1-6th shielding portion SH1-6 in a plan view.

[0175] For example, the shape of the 2-2nd shielding portion SH2-2 may correspond to the shape of the 2-2nd light emitting element PX-R2 in plan view. The area of ​​the 2-2nd light emitting element PX-R2 may be smaller than the area of ​​the 2-2nd shielding portion SH2-2 in plan view.

[0176] For example, the shape of the 3-2nd shielding portion SH3-2 may correspond to the shape of the 3-2nd light emitting element PX-B2 in plan view. The area of ​​the 3-2nd light emitting element PX-B2 may be smaller than the area of ​​the 3-2nd shielding portion SH3-2 in plan view.

[0177] like Figure 6 As shown in FIG. 1 , the plurality of power lines included in the second conductive layer 140 may include a first vertical power line VL1 , a second vertical power line VL2 , and the like extending in the first direction y.

[0178] For example, in a plan view, the first vertical power line VL1 may overlap the 1-1st light emitting element PX-G1. In a plan view, the first vertical power line VL1 may overlap the 1-2nd light emitting element PX-G2. In a plan view, the first vertical power line VL1 may overlap the 1-3rd light emitting element PX-G3.

[0179] For example, in a plan view, the second vertical power line VL2 may overlap the 1st-4th light emitting element PX-G4. In a plan view, the second vertical power line VL2 may overlap the 1st-5th light emitting element PX-G5. In a plan view, the second vertical power line VL2 may overlap the 1st-6th light emitting element PX-G6.

[0180] For example, in a plan view, the first horizontal power line VH1 may overlap with the 2-1st light emitting element PX-R1. In a plan view, the first horizontal power line VH1 may overlap with the 3-2nd light emitting element PX-B2. In a plan view, the second horizontal power line VH2 may overlap with the 3-1st light emitting element PX-B1. In a plan view, the second horizontal power line VH2 may overlap with the 2-2nd light emitting element PX-R2.

[0181] For example, in a plan view, the first data line DL1 may cross or intersect the first horizontal power line VH1 and the second horizontal power line VH2. In a plan view, the second data line DL2 may cross or intersect the first horizontal power line VH1 and the second horizontal power line VH2. In a plan view, the third data line DL3 may cross or intersect the first horizontal power line VH1 and the second horizontal power line VH2. In a plan view, the fourth data line DL4 may cross or intersect the first horizontal power line VH1 and the second horizontal power line VH2.

[0182] Figure 7 yes Figure 6 Schematic plan view of the second conductive layer.

[0183] In the following, reference is made to Figure 7 , you don’t need to repeat the above reference Figures 1 to 6 Redundant description of components that are identical or substantially identical to the components described.

[0184] Reference Figure 7 , the width W1 of the first horizontal power line VH1 may be equal to or approximately equal to the width W1' of the second horizontal power line VH2. The width W2 of the first vertical power line VL1 may be equal to or approximately equal to the width W2' of the second vertical power line VL2. For example, the width W1 of the first horizontal power line VH1 may be greater than the width W2 of the first vertical power line VL1. The width W1' of the second horizontal power line VH2 may be greater than the width W2' of the second vertical power line VL2.

[0185] Figure 7 The second conductive layer 140 may also be used as described in more detail below. Figure 8 display device.

[0186] like Figure 7 As shown in , the first horizontal power line VH1 , the second horizontal power line VH2 , the first vertical power line VL1 , and the second vertical power line VL2 may be integrated with each other.

[0187] The first horizontal power line VH1 , the second horizontal power line VH2 , the first vertical power line VL1 , and the second vertical power line VL2 may be formed simultaneously or substantially simultaneously in the same process.

[0188] The first horizontal power line VH1 , the second horizontal power line VH2 , the first vertical power line VL1 , and the second vertical power line VL2 may be positioned at the same layer (eg, in or above) as each other, and may include the same material as each other.

[0189] In other words, the plurality of vertical power lines and the plurality of horizontal power lines may be integrated with each other.The plurality of vertical power lines and the plurality of horizontal power lines may be positioned at the same layer (eg, in or above) as each other, and may include the same material as each other.

[0190] like Figure 7 As shown in , the 1-1 shielding portion SH1-1 to the 3-2 shielding portion SH3-2 can be integrated with multiple vertical power lines and multiple horizontal power lines. The 1-1 shielding portion SH1-1 to the 3-2 shielding portion SH3-2 can be positioned at the same layer as the layer of the multiple vertical power lines and the multiple horizontal power lines (for example, in the middle or above), and may include the same material as the material of the multiple vertical power lines and the multiple horizontal power lines.

[0191] In other words, multiple shielding parts, multiple vertical power lines, and multiple horizontal power lines may be integrated with each other. Multiple shielding parts, multiple vertical power lines, and multiple horizontal power lines may be positioned at the same layer (e.g., middle or upper) as each other, and may include the same material as each other.

[0192] Figure 8 The main icon Figure 1 A schematic plan view of another enlarged example of region A.

[0193] In the following, reference is made to Figure 8 , you don’t need to repeat the above reference Figures 1 to 7 Redundant description of components that are identical or substantially identical to the components described.

[0194] Reference Figure 8 The first conductive layer 130 may further include a first vertical data line BRS_V1 and a second vertical data line BRS_V2. In addition, the first conductive layer 130 may further include a first horizontal data line BRS_H1 and a second horizontal data line BRS_H2.

[0195] The first vertical data line BRS_V1 may be arranged around a plurality of data lines (e.g., adjacent to a plurality of data lines) and may extend in the first direction y. The second vertical data line BRS_V2 may be arranged around a plurality of data lines (e.g., adjacent to a plurality of data lines) and may extend in the first direction y. In a plan view, the second vertical data line BRS_V2 may be spaced apart from the first vertical data line BRS_V1. For example, in a plan view, the first data line DL1 and the second data line DL2 may be arranged between the first vertical data line BRS_V1 and the second vertical data line BRS_V2. For example, the first data line DL1 and the second data line DL2 may be arranged at the same layer as the first vertical data line BRS_V1 and the second vertical data line BRS_V2 (e.g., in or above), and may include the same material as the first vertical data line BRS_V1 and the second vertical data line BRS_V2.

[0196] The third vertical data line BRS_V3 may be arranged around a plurality of data lines (e.g., adjacent to a plurality of data lines) and may extend in the first direction y. The fourth vertical data line BRS_V4 may be arranged around a plurality of data lines and may extend in the first direction y. In a plan view, the fourth vertical data line BRS_V4 may be spaced apart from the third vertical data line BRS_V3. For example, in a plan view, the third data line DL3 and the fourth data line DL4 may be arranged between the third vertical data line BRS_V3 and the fourth vertical data line BRS_V4. For example, the third data line DL3 and the fourth data line DL4 may be arranged at the same layer as the third vertical data line BRS_V3 and the fourth vertical data line BRS_V4 (e.g., in or above), and may include the same material as the third vertical data line BRS_V3 and the fourth vertical data line BRS_V4.

[0197] The first horizontal data line BRS_H1 may extend in a second direction x crossing the first direction y and may be electrically connected to the first and second vertical data lines BRS_V1 and BRS_V2. The first horizontal data line BRS_H1 may be electrically connected to the third and fourth vertical data lines BRS_V3 and BRS_V4.

[0198] The second horizontal data line BRS_H2 may extend in a second direction x crossing the first direction y and may be electrically connected to the first and second vertical data lines BRS_V1 and BRS_V2. The second horizontal data line BRS_H2 may be electrically connected to the third and fourth vertical data lines BRS_V3 and BRS_V4.

[0199] For example, in a plan view, the first horizontal data line BRS_H1 and the second horizontal data line BRS_H2 may be spaced apart from each other. In a plan view, the first horizontal power line VH1 may be disposed between the first horizontal data line BRS_H1 and the second horizontal data line BRS_H2. For example, in a plan view, the 2-1st shielding portion SH2-1 and the 3-2nd shielding portion SH3-2 may be disposed between the first horizontal data line BRS_H1 and the second horizontal data line BRS_H2.

[0200] In addition, for convenience of explanation, first to fourth vertical data lines BRS_V1 to BRS_V4 , first horizontal data lines BRS_H1 , and second horizontal data lines BRS_H2 are illustrated, but the present disclosure is not limited thereto and may include more vertical data lines and more horizontal data lines.

[0201] like Figure 8 As shown in , the first horizontal data line BRS_H1 may include a 1-1st horizontal data line SV1-1, a 1-2nd horizontal data line SV1-2, and a 1-3rd horizontal data line SV1-3. The 1-1st horizontal data line SV1-1, the 1-2nd horizontal data line SV1-2, and the 1-3rd horizontal data line SV1-3 may be arranged at the same layer as each other (e.g., in the middle or on the top), but may be electrically separated from each other. In order to electrically connect the 1-1st horizontal data line SV1-1, the 1-2nd horizontal data line SV1-2, and the 1-3rd horizontal data line SV1-3 to each other, the second conductive layer 140 may further include a 1-1st bridge wire BRG1-1 and a 1-2nd bridge wire BRG1-2.

[0202] For example, the first horizontal data line BRS_H1 may include a 1-1st horizontal data line SV1-1, a 1-2nd horizontal data line SV1-2, and a 1-3rd horizontal data line SV1-3 that are electrically separated from each other, and the 1-1st horizontal data line SV1-1 and the 1-2nd horizontal data line SV1-2 may be electrically connected to each other through a 1-1st bridge wire BRG1-1 formed at the same layer (e.g., in the middle or on) as that of the second conductive layer 140. The 1-1st bridge wire BRG1-1 may include the same material as that of the second conductive layer 140. In a plan view, the 1-1st bridge wire BRG1-1 may be spaced apart from a plurality of power lines and a plurality of shielding portions.

[0203] For example, the first horizontal data line BRS_H1 may include a 1-1st horizontal data line SV1-1, a 1-2nd horizontal data line SV1-2, and a 1-3rd horizontal data line SV1-3 that are electrically separated from each other, and the 1-2nd horizontal data line SV1-2 and the 1-3rd horizontal data line SV1-3 may be electrically connected to each other through a 1-2nd bridge line BRG1-2 formed at the same layer (e.g., in the middle or on) as that of the second conductive layer 140. The 1-2nd bridge line BRG1-2 may include the same material as that of the second conductive layer 140. In a plan view, the 1-2nd bridge line BRG1-2 may be spaced apart from a plurality of power lines and a plurality of shielding portions.

[0204] like Figure 8 As shown in , the second horizontal data line BRS_H2 may include a 2-1st horizontal data line SV2-1, a 2-2nd horizontal data line SV2-2, and a 2-3rd horizontal data line SV2-3. The 2-1st horizontal data line SV2-1, the 2-2nd horizontal data line SV2-2, and the 2-3rd horizontal data line SV2-3 may be arranged at the same layer as each other (e.g., in the middle or on the top), but may be electrically separated from each other. In order to electrically connect the 2-1st horizontal data line SV2-1, the 2-2nd horizontal data line SV2-2, and the 2-3rd horizontal data line SV2-3 to each other, the second conductive layer 140 may further include a 2-1st bridge wire BRG2-1 and a 2-2nd bridge wire BRG2-2.

[0205] For example, the second horizontal data line BRS_H2 may include a 2-1st horizontal data line SV2-1, a 2-2nd horizontal data line SV2-2, and a 2-3rd horizontal data line SV2-3 that are electrically separated from each other, and the 2-1st horizontal data line SV2-1 and the 2-2nd horizontal data line SV2-2 may be electrically connected to each other through a 2-1st bridge wire BRG2-1 formed at the same layer (e.g., in the middle or on) as that of the second conductive layer 140. The 2-1st bridge wire BRG2-1 may include the same material as that of the second conductive layer 140. In a plan view, the 2-1st bridge wire BRG2-1 may be spaced apart from a plurality of power lines and a plurality of shielding portions.

[0206] For example, the second horizontal data line BRS_H2 may include a 2-1st horizontal data line SV2-1, a 2-2nd horizontal data line SV2-2, and a 2-3rd horizontal data line SV2-3 that are electrically separated from each other, and the 2-2nd horizontal data line SV2-2 and the 2-3rd horizontal data line SV2-3 may be electrically connected to each other through a 2-2nd bridge wire BRG2-2 formed at the same layer (e.g., in the middle or on) as that of the second conductive layer 140. The 2-2nd bridge wire BRG2-2 may include the same material as that of the second conductive layer 140. In a plan view, the 2-2nd bridge wire BRG2-2 may be spaced apart from a plurality of power lines and a plurality of shielding portions.

[0207] For example, in a plan view, the first horizontal power line VH1 may be arranged to cross or intersect the first and second vertical data lines BRS_V1 and BRS_V2. In a plan view, the first horizontal power line VH1 may be arranged to cross or intersect the third and fourth vertical data lines BRS_V3 and BRS_V4.

[0208] For example, in a plan view, the second horizontal power line VH2 may be arranged to cross or intersect the first and second vertical data lines BRS_V1 and BRS_V2. In a plan view, the second horizontal power line VH2 may be arranged to cross or intersect the third and fourth vertical data lines BRS_V3 and BRS_V4.

[0209] For example, the width of the first horizontal power line VH1 (eg, refer to Figure 7 The width W1) may be greater than the width of the first vertical power line VL1 (eg, referring to Figure 7 The width of the first horizontal power line VH1 (for example, refer to Figure 7 The width W1) may be greater than the width of the second vertical power line VL2 (eg, referring to Figure 7 Width W2').

[0210] The first horizontal power line VH1 may pass through the lower portion of the 2-1st light emitting element PX-R1 and the lower portion of the 3-2nd light emitting element PX-B2. The second horizontal power line VH2 may pass through the lower portion of the 3-1st light emitting element PX-B1 and the lower portion of the 2-2nd light emitting element PX-R2.

[0211] The first vertical power line VL1 may pass through the lower portion of the 1-1 light emitting element PX-G1 and the lower portion of the 1-2 light emitting element PX-G2. The second vertical power line VL2 may pass through the lower portion of the 1-4 light emitting element PX-G4 and the lower portion of the 1-5 light emitting element PX-G5.

[0212] In a plan view, the area of ​​each of the 2-1st light-emitting element PX-R1, the 3-2nd light-emitting element PX-B2, the 3-1st light-emitting element PX-B1, and the 2-2nd light-emitting element PX-R2 may be greater than the area of ​​each of the 1-1st light-emitting element PX-G1, the 1-2nd light-emitting element PX-G2, the 1-4th light-emitting element PX-G4, and the 1-5th light-emitting element PX-G5.

[0213] Therefore, the width W1 of the first horizontal power line VH1 and the width W1' of the second horizontal power line VH2 passing through the lower portion of the light emitting element having a relatively large area may be greater than the width W2 of the first vertical power line VL1 and the width W2' of the second vertical power line VL2. Therefore, the density of the amount of charge passing through the shielding portion may be maintained or substantially maintained constant.

[0214] In other words, the ratio of the width W1 of the first horizontal power line VH1 to the width W2 of the first vertical power line VL1 may be the ratio between the area of ​​the luminous pixel through which the first horizontal power line VH1 passes in a plan view and the area of ​​the luminous pixel through which the first vertical power line VL1 passes in a plan view.

[0215] In other words, the ratio of the width W1 of the first horizontal power line VH1 to the width W2' of the second vertical power line VL2 may be the ratio between the area of ​​the luminous pixel through which the first horizontal power line VH1 passes in a plan view and the area of ​​the luminous pixel through which the second vertical power line VL2 passes in a plan view.

[0216] In other words, the ratio of the width W1' of the second horizontal power line VH2 to the width W2 of the first vertical power line VL1 may be the ratio between the area of ​​the luminous pixel through which the second horizontal power line VH2 passes in a plan view and the area of ​​the luminous pixel through which the first vertical power line VL1 passes in a plan view.

[0217] In other words, the ratio of the width W1' of the second horizontal power line VH2 to the width W2' of the second vertical power line VL2 may be the ratio between the area of ​​the luminous pixel through which the second horizontal power line VH2 passes in the plan view and the area of ​​the luminous pixel through which the second vertical power line VL2 passes in the plan view.

[0218] For example, the width of the second horizontal power line VH2 (eg, refer to Figure 7 The width W1′) may be greater than the width of the first vertical power line VL1 (eg, referring to Figure 7 The width of the second horizontal power line VH2 (for example, refer to Figure 7 The width W1') may be greater than the width of the second vertical power line VL2 (eg, referring to Figure 7 Width W2').

[0219] like Figures 6 to 8 As shown in , the display device according to one or more embodiments includes a plurality of shielding portions integrally formed with a plurality of power lines configuring a second conductive layer, and thus, parasitic capacitors that may be formed between data lines and pixel electrodes may be reduced or prevented.

[0220] As the plurality of shielding portions are integrally formed with the plurality of power lines, the first power voltage ELVDD may be applied to each of the plurality of shielding portions. Therefore, the plurality of shielding portions to which the first power voltage ELVDD is applied may more effectively prevent or reduce parasitic capacitors that may be formed between the data line and the pixel electrode.

[0221] Along with preventing or reducing parasitic capacitors, non-uniformity that may occur in the display device or display panel 10 may also be prevented or reduced.

[0222] Table 1 (where the unit is F):

[0223]

[0224] Table 2 (where the unit is F):

[0225]

[0226] Unlike the display device according to the embodiment, the display device according to the comparative example does not include a plurality of shielding parts separately, but includes the same components except for a plurality of shielding parts that are the same as the plurality of shielding parts of the display device according to the embodiment. The display device of the comparative example and the display device according to the embodiment are display devices having the same specifications as each other, and have no difference in components except for the presence or absence of a plurality of shielding parts.

[0227] Referring to Tables 1 and 2 above, it is shown that Figure 8 The difference between the parasitic capacitor measured in the display device illustrated in FIG. 1 and the parasitic capacitor measured in the display device according to the comparative example. As shown in Table 1 and Table 2, Figure 8 The display device including the plurality of shielding portions illustrated in FIG. 4 may have a parasitic capacitor having a much smaller size than that of the display device according to the comparative example.

[0228] In addition, when only the parasitic capacitor (1) is compared, it is clear that Figure 6 The display device illustrated in FIG. 4 may have a parasitic capacitor having a much smaller size than that of the display device according to the comparative example.

[0229] In addition, in a plan view, the area of ​​each of the plurality of shielding portions may be larger than the area of ​​the corresponding pixel electrode. Therefore, the viewing angle of the display device may be improved. In other words, compared with the viewing angle of the display device according to the comparative example, Figures 6 to 8 The viewing angle of the display device shown in FIG. 5 can be improved.

[0230] Figures 9 to 16 It is a schematic diagram Figure 1 An example layout diagram of various layers of components in a portion of area A. Fig.17 It is a schematic diagram Figures 9 to 16 An example of an overlay of a layout diagram is shown in FIG.

[0231] In the following, reference is made to Figures 9 to 17 , you don’t need to repeat the above reference Figures 1 to 8 Redundant description of components that are identical or substantially identical to the components described.

[0232] Reference Fig. 9 , a portion of the bottom metal layer BML may have a shape corresponding to the shape of the first electrode CE1 of the storage capacitor Cst described in more detail below. The bottom metal layer BML may prevent or substantially prevent external light from reaching the line. In addition, the bottom metal layer BML may prevent or substantially prevent external light from reaching the semiconductor layer 110. The bottom metal layer BML may include a metal such as silver, copper, aluminum, etc.

[0233] Reference Fig.10 , the semiconductor layer 110 may include a first drain region D1, a first channel region A1, and a first source region S1 of a first transistor. The semiconductor layer 110 may include a second drain region D2, a second channel region A2, and a second source region S2 of a second transistor. The semiconductor layer 110 may include a fifth drain region D5, a fifth channel region A5, and a fifth source region S5 of a fifth transistor. The semiconductor layer 110 may include a sixth drain region D6, a sixth channel region A6, and a sixth source region S6 of a sixth transistor. The semiconductor layer 110 may include a seventh drain region D7, a seventh channel region A7, and a seventh source region S7 of a seventh transistor. The semiconductor layer 110 may include an eighth drain region D8, an eighth channel region A8, and an eighth source region S8 of an eighth transistor.

[0234] Reference Fig.11 The first gate layer 120a may include a first gate line GWL for transmitting a first gate signal GW, a second gate line GIL for transmitting a second gate signal GI, and a fourth gate line GBL for transmitting a fourth gate signal GB. The first gate layer 120a may also include a bias voltage line VL3 for transmitting a turn-on bias voltage VOBS.

[0235] The first gate layer 120a may include a first gate region G1 of the first transistor, a second gate region G2 of the second transistor, a fifth gate region G5 of the fifth transistor, a sixth gate region G6 of the sixth transistor, a seventh gate region G7 of the seventh transistor, and an eighth gate region G8 of the eighth transistor. The first gate layer 120a may also include a first electrode CE1 of the storage capacitor Cst.

[0236] Reference Fig.12 , the second gate layer 120b may include a third gate line GCL for transmitting a third gate signal GC and a first initialization voltage line VL1 for transmitting a first initialization voltage VINT. The second gate layer 120b may also include a driving voltage line PL for transmitting a first power supply voltage ELVDD. The second gate layer 120b may also include a second electrode CE2 included in the storage capacitor Cst. The second electrode CE2 may have a through hole Ho.

[0237] Reference Fig.13 The additional semiconductor layer 110' may include a third drain region D3, a third channel region A3, and a third source region S3 of the third transistor. The additional semiconductor layer 110' may include a fourth drain region D4, a fourth channel region A4, and a fourth source region S4 of the fourth transistor.

[0238] Reference Fig.14 The third gate layer 120c may include a third gate region G3 of the third transistor and a fourth gate region G4 of the fourth transistor. The third gate layer 120c may also include a second initialization voltage line VL2 for transmitting a second initialization voltage VAINT and an emission control line EML for transmitting an emission control signal EM.

[0239] The third gate layer 120c may further include 1-1th through holes TH1-1 arranged around the fourth gate region G4, 1-2th through holes TH1-2 arranged around the third gate region G3, 1-4th through holes TH1-4 and 1-5th through holes TH1-5 formed in the emission control line EML, and 1-6th through holes TH1-6 formed in the second initialization voltage line VL2.

[0240] Reference Fig.15 The first conductive layer 130 may include a 1-1 conductive portion 130-1, a 1-2 conductive portion 130-2, a 1-3 conductive portion 130-3, a 1-4 conductive portion 130-4, and a 1-5 conductive portion 130-5. The first conductive layer 130 may further include a data line DL for transmitting a data signal.

[0241] The first conductive layer 130 may further include a 2-1st through hole TH2-1 formed in the data line DL, a 2-2nd through hole TH2-2 and a 2-3rd through hole TH2-3 formed in the 1-2nd conductive portion 130-2, a 2-4th through hole TH2-4 and a 2-5th through hole TH2-5 formed in the 1-3rd conductive portion 130-3, a 2-6th through hole TH2-6 and a 2-7th through hole TH2-7 formed in the 1-4th conductive portion 130-4, a 2-8th through hole TH2-8 and a 2-9th through hole TH2-9 formed in the 1-5th conductive portion 130-5, and a 2-10th through hole TH2-10 formed in the 1-1st conductive portion 130-1.

[0242] Reference Fig.16 , the second conductive layer 140 may include a 2-1st conductive portion 140-1, a 2-2nd conductive portion 140-2, a 2-3rd conductive portion 140-3, a 2-4th conductive portion 140-4, and a 2-5th conductive portion 140-5. For example, a portion of the 2-1st conductive portion 140-1 may be a 3-2nd shielding portion SH3-2. For example, a portion of the 2-5th conductive portion 140-5 may be a 1-2nd shielding portion SH1-2.

[0243] The second conductive layer 140 may further include a 3-1st through hole TH3-1 formed in the 2-2nd conductive portion 140-2, a 3-2nd through hole TH3-2 and a 3-4th through hole TH3-4 formed in the 2-3rd conductive portion 140-3, a 3-3rd through hole TH3-3 formed in the 2-1st conductive portion 140-1, and a 3-5th through hole TH3-5 formed in the 2-4th conductive portion 140-4.

[0244] Therefore, the bottom metal layer BML, the semiconductor layer 110, the first gate layer 120a, the second gate layer 120b, the additional semiconductor layer 110′, the third gate layer 120c, the first conductive layer 130 and the second conductive layer 140 may be formed as shown in FIG. Fig.17 shown stacked on top of each other.

[0245] Fig.18 is an example enlarged layout diagram schematically illustrating a stack layout of a second conductive layer, a light emitting element, and a pixel electrode according to an embodiment.

[0246] In the following, reference is made to Fig.18 , you don’t need to repeat the above reference Figures 1 to 17 Redundant description of components that are identical or substantially identical to the components described.

[0247] Reference Fig.18 , in a plan view, an area of ​​one pixel electrode may be larger than an area of ​​a shielding portion corresponding to the one pixel electrode.

[0248] For example, in a plan view, an area of ​​the 2-1st shielding portion SH2 - 1 may be smaller than an area of ​​the 2-1st pixel electrode 150R corresponding to the 2-1st shielding portion SH2 - 1 .

[0249] For example, in a plan view, an area of ​​the 3-2 th shielding portion SH3 - 2 may be smaller than an area of ​​the 3-2 th pixel electrode 150B corresponding to the 3-2 th shielding portion SH3 - 2 .

[0250] For example, in a plan view, an area of ​​the 1-2 th shielding portion SH1 - 2 may be smaller than an area of ​​the 1-2 th pixel electrode 150G corresponding to the 1-2 th shielding portion SH1 - 2 .

[0251] According to one or more embodiments of the present disclosure as described above, a display device capable of reducing the influence of a parasitic capacitor may be realized. However, aspects and features of the present disclosure are not limited thereto.

[0252] The foregoing is an explanation of some embodiments of the present disclosure and is not to be construed as limiting thereof. Although some embodiments have been described, it will be readily understood by those skilled in the art that it is possible to make various modifications to the embodiments without departing from the spirit and scope of the present disclosure. It will be understood that, unless otherwise described, the description of the features or aspects within each embodiment should generally be considered as other similar features or aspects that can be used in other embodiments. Therefore, as will be apparent to those of ordinary skill in the art, unless otherwise explicitly indicated, the features, characteristics and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it is to be understood that the foregoing is an explanation of various example embodiments and is not to be construed as being limited to the specific embodiments disclosed herein, and modifications to the disclosed embodiments and other example embodiments are intended to be included in the spirit and scope of the present disclosure as defined in the accompanying claims and their equivalents.

Claims

1. A display device, comprising: substrate; A pixel circuit layer, the pixel circuit layer is on the substrate; a first conductive layer, the first conductive layer being on the pixel circuit layer and comprising a plurality of data lines; a 1-1 pixel electrode, the 1-1 pixel electrode being on the first conductive layer; A second conductive layer, the second conductive layer is between the first conductive layer and the 1-1 pixel electrode, and includes: multiple power lines; and The 1-1 shielding portion is parallel to the 1-1 shielding portion in a plan view. Pixel electrodes overlap; and A 1-1st light emitting element, the 1-1st light emitting element is on the 1-1st pixel electrode, Wherein, the plurality of power lines and the 1-1th shielding portion are integrated with each other.

2. The display device according to claim 1, further comprising: a 2-1st pixel electrode, the 2-1st pixel electrode being on the first conductive layer and at the same layer as that of the 1-1st pixel electrode; a 2-1st light-emitting element, wherein the 2-1st light-emitting element is on the 2-1st pixel electrode; a 3-1st pixel electrode, the 3-1st pixel electrode being on the first conductive layer and at the same layer as that of the 2-1st pixel electrode; as well as The 3-1st light-emitting element is on the 3-1st pixel electrode.

3. The display device according to claim 2, wherein: The second conductive layer further comprises: A 2-1st shielding portion, the 2-1st shielding portion is at the same layer as that of the 1-1st shielding portion and is located between the first conductive layer and the 2-1st pixel electrode.

4. The display device according to claim 3, wherein: The plurality of power lines, the 1-1th shielding portion, and the 2-1th shielding portion are integrated with each other.

5. The display device according to claim 4, wherein: The plurality of power lines include: first vertical electric force lines extending in a first direction; and A first horizontal power line extends in a second direction crossing the first direction and is integrated with the first vertical power line.

6. The display device according to claim 4, wherein: The second conductive layer further comprises: The 3-1st shielding portion is at the same layer as that of the 1-1st shielding portion and is located between the first conductive layer and the 2-1st pixel electrode.

7. The display device according to claim 1, wherein: In a plan view, the shape of the 1-1th shielding portion corresponds to the shape of the 1-1th light emitting element.

8. The display device according to claim 1, wherein: In a plan view, an area of ​​the 1-1th light emitting element is smaller than an area of ​​the 1-1th shielding portion.

9. The display device according to claim 8, wherein: The 1-1th shielding portion is located between at least one of the plurality of data lines and the 1-1th pixel electrode, and the at least one of the plurality of data lines overlaps with the 1-1th pixel electrode in a plan view.

10. The display device according to claim 3, wherein: In a plan view, the shape of the 2-1st shielding portion corresponds to the shape of the 2-1st light emitting element.

11. The display device according to claim 3, wherein: In a plan view, an area of ​​the 2-1th light emitting element is smaller than an area of ​​the 2-1th shielding portion.

12. The display device according to claim 11, wherein: The 2-1st shielding portion is located between at least one of the plurality of data lines and the 2-1st pixel electrode, and the at least one of the plurality of data lines overlaps with the 2-1st pixel electrode in a plan view.

13. The display device according to claim 6, wherein: In a plan view, the shape of the 3-1st shielding portion corresponds to the shape of the 3-1st light emitting element.

14. The display device according to claim 6, wherein: In a plan view, the area of ​​the 3-1st light emitting element is smaller than the area of ​​the 3-1st shielding portion.

15. The display device according to claim 14, wherein: The 3-1st shielding portion is located between at least one of the plurality of data lines and the 3-1st pixel electrode, and the at least one of the plurality of data lines overlaps with the 3-1st pixel electrode in a plan view.

16. The display device according to claim 1, wherein: The first conductive layer further comprises: a first vertical data line surrounding the plurality of data lines and extending in a first direction; and A first horizontal data line extends in a second direction crossing the first direction and is electrically connected to the first vertical data line.

17. The display device according to claim 16, wherein: The first horizontal data lines include a 1-1th horizontal data line and a 1-2th horizontal data line spaced apart from the 1-1th horizontal data line, and The 1-1th horizontal data line and the 1-2th horizontal data line are electrically connected to each other through a 1-1th bridge line at the same layer as the second conductive layer.

18. The display device according to claim 17, wherein: The 1-1th bridge line includes the same material as that of the second conductive layer.

19. The display device according to claim 18, wherein: In a plan view, the 1-1th bridge line is spaced apart from the plurality of power lines and the 1-1th shielding portion.

20. The display device according to claim 1, wherein: In a plan view, an area of ​​the 1-1th pixel electrode is larger than an area of ​​the 1-1th shielding portion.

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