Display panel, preparation method thereof and display device

Abstract

The invention provides a display panel, a preparation method thereof and a display device. The display panel comprises a substrate; the first wiring layer is arranged on one side of the substrate, and at least part of the first wiring layer is located in the bonding area; at least part of the second wiring layer is located in the display area, and the second wiring layer is electrically connected with the first wiring layer; the isolation layer is located on the side, away from the substrate, of the first wiring layer, the isolation layer located in the display area forms an isolation structure, the isolation structure defines an isolation opening used for containing the light-emitting unit, and the isolation structure is located on the side, away from the substrate, of the second wiring layer; the orthographic projection, on the substrate, of at least part of the first wiring layer located in the bonding area is located in the orthographic projection, on the substrate, of the isolation layer, and the isolation layer located in the bonding area is electrically connected with the first wiring layer. According to the display panel, the isolation layer is adopted in the bonding area to replace the second wiring layer, damage caused by etching is reduced, and the electrical performance and reliability of a product are improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for preparing the same, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, current OLED display panels are prone to etching damage during the pixel patterning process, and product reliability needs to be improved. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a display panel and a manufacturing method thereof, as well as a display device that improves etching damage and enhances reliability.

[0005] Based on the above purpose, the present application provides a display panel, the display panel includes a display area and a non-display area, the non-display area at least partially surrounds the display area, the non-display area includes a bonding area, and the display panel also includes:

[0006] substrate;

[0007] A first wiring layer is disposed on one side of the substrate, and at least a portion of the first wiring layer is located in the bonding area;

[0008] A second wiring layer is disposed on one side of the substrate, at least a portion of the second wiring layer is located in the display area, and the second wiring layer is electrically connected to the first wiring layer;

[0009] An isolation layer, the isolation layer is located in the display area and the bonding area, and is located on a side of the first wiring layer away from the substrate, the isolation layer located in the display area forms an isolation structure, the isolation structure defines an isolation opening for accommodating a light-emitting unit, and the isolation structure is located on a side of the second wiring layer away from the substrate;

[0010] The orthographic projection of at least a portion of the first wiring layer located in the bonding area on the substrate is located within the orthographic projection of the isolation layer on the substrate, and the isolation layer located in the bonding area is electrically connected to the first wiring layer.

[0011] In one embodiment, the display panel further includes:

[0012] A pixel definition layer is located in a display area and a bonding area. In the display area, the pixel definition layer is located on a side of the second wiring layer away from the substrate. The pixel definition layer located in the display area includes a pixel opening. The isolation opening corresponds to and is connected to the pixel opening. The orthographic projection of the pixel definition layer located in the bonding area on the substrate overlaps with the orthographic projection of the first wiring layer on the substrate.

[0013] Preferably, the isolation layer is located on a side of the pixel defining layer away from the substrate;

[0014] Preferably, in the bonding area, the orthographic projection of the pixel defining layer on the substrate overlaps with the orthographic projection of the isolation layer on the substrate;

[0015] Preferably, the second wiring layer is located on a side of the first wiring layer away from the substrate;

[0016] Preferably, the first wiring layer is located in the display area and the non-display area;

[0017] Preferably, the light-emitting unit comprises a first electrode, a light-emitting functional layer and a second electrode stacked on the substrate and sequentially away from the substrate, the light-emitting functional layer and the second electrode are located in the isolation opening; and a portion of the first electrode is exposed to the pixel opening.

[0018] In one embodiment, the pixel definition layer includes a bonding opening located in the bonding area, and at least a portion of the first wiring layer is exposed to the bonding opening;

[0019] Preferably, the portion of the first wiring layer exposed to the bonding opening is electrically connected to the isolation layer;

[0020] Preferably, in the bonding area, the pixel definition layer is at least partially disposed on a surface of the first wiring layer facing away from the substrate;

[0021] Preferably, in the bonding area, the pixel defining layer at least partially covers a side surface of the first wiring layer away from the bonding opening.

[0022] In one embodiment, the substrate includes an insulating layer;

[0023] In the bonding area, at least a portion of the pixel definition layer and at least a portion of the first wiring layer are respectively in contact with a surface of the insulating layer facing away from the substrate.

[0024] In one embodiment, the first routing layer includes a plurality of routing portions located in the bonding area, and the pixel defining layer covers the gaps between adjacent routing portions;

[0025] Preferably, the pixel definition layer located in the bonding area includes an extension portion, and the extension portion covers the edge of the routing portion;

[0026] Preferably, in the bonding area, an orthographic projection of the extension portion on the substrate is located within an orthographic projection of the isolation layer on the substrate.

[0027] In one embodiment, the isolation layer located in the bonding area includes a plurality of sub-portions arranged at intervals, and the orthographic projection of the routing portion on the substrate is located within the orthographic projection of the corresponding sub-portion on the substrate.

[0028] Based on the same inventive concept, the present application also provides a method for preparing a display panel, wherein the display panel includes a display area and a non-display area, wherein the non-display area at least partially surrounds the display area, and the non-display area includes a bonding area, and the preparation method includes:

[0029] forming a first wiring layer on one side of the substrate, wherein at least a portion of the first wiring layer is located in the bonding area;

[0030] forming a second wiring layer on one side of the substrate, wherein at least a portion of the second wiring layer is located in the display area, and the second wiring layer is electrically connected to the first wiring layer;

[0031] An isolation layer is formed on a side of the second routing layer and the first routing layer away from the substrate, wherein the isolation layer is located in the display area and the bonding area, the isolation layer located in the display area forms an isolation structure, and the isolation structure encloses an isolation opening for accommodating the light-emitting unit; at least a portion of the first routing layer located in the bonding area has its orthographic projection on the substrate located within the orthographic projection of the isolation layer on the substrate, and the isolation layer located in the bonding area is electrically connected to the first routing layer.

[0032] In one embodiment, after the step of forming a second wiring layer on a side of the first wiring layer away from the substrate, the preparation method further includes:

[0033] A pixel definition layer is formed on a side of the second wiring layer away from the substrate, wherein the pixel definition layer is located in the display area and the bonding area, a pixel opening is etched in the pixel definition layer located in the display area, and a bonding opening is etched in the pixel definition layer located in the bonding area, and at least a portion of the first wiring layer is exposed to the bonding opening;

[0034] The isolation structure is formed on a side of the pixel defining layer away from the substrate, and the isolation opening corresponds to and is connected with the pixel opening;

[0035] Preferably, the second wiring layer is located on a side of the first wiring layer away from the substrate;

[0036] Preferably, the first wiring layer is located in the display area and the non-display area.

[0037] In one embodiment,

[0038] The first routing layer includes a plurality of routing portions located in the bonding area;

[0039] After the step of forming an isolation layer on the second wiring layer and the first wiring layer on a side away from the substrate, the preparation method further includes:

[0040] forming the light emitting unit in the display area;

[0041] The isolation layer located in the bonding area is patterned to form a plurality of sub-portions; wherein the orthographic projection of the routing portion on the substrate is located within the orthographic projection of the corresponding sub-portion on the substrate.

[0042] Based on the same inventive concept, the present application also provides a display device, which includes the above-mentioned display panel.

[0043] Compared with the prior art, the display panel provided by the present application uses an isolation layer in the bonding area to replace the second wiring layer, covers and electrically connects the first wiring layer, and during the pixel patterning process in the display area, the isolation layer is used to protect the first wiring layer below. In addition, there is no second wiring layer in the bonding area, which can reduce the step difference of the wiring edge, thereby reducing the damage caused by etching and improving the electrical performance and reliability of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 A schematic diagram of the structure of a display panel provided in one embodiment of the present application;

[0046] Figure 2 A schematic diagram of the hierarchical structure of a display area of ​​a display panel provided in an embodiment of the present application;

[0047] Figure 3 A schematic diagram of the hierarchical structure of the bonding area of ​​a display panel provided in one embodiment of the present application;

[0048] Figure 4 A schematic diagram of the hierarchical structure of the bonding area of ​​a display panel provided in another embodiment of the present application;

[0049] Figure 5 A schematic diagram of the hierarchical structure of the bonding area of ​​a display panel during the preparation process provided by another embodiment of the present application;

[0050] Figure 6 A schematic diagram of the hierarchical structure of the bonding area of ​​a display panel during the preparation process provided by another embodiment of the present application;

[0051] Figure 7 A flow chart of a method for preparing a display panel provided in another embodiment of the present application.

[0052] Marking Description:

[0053] 100, display panel; 101, display area; 102, bonding area;

[0054] 10. Substrate; 11. Insulating layer; 20. First routing layer; 21. Routing portion; 30. Second routing layer; 40. Pixel defining layer; 401. Pixel opening; 402. Bonding opening; 41. Extension portion; 50. Isolation layer; 51. Isolation structure; 510. Isolation opening; 52. Sub-portion; 60. Light-emitting unit; 61. First electrode; 62. Light-emitting functional layer; 63. Second electrode. DETAILED DESCRIPTION

[0055] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0056] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0057] In the related art, the display panel includes a display area and a non-display area, and the non-display area includes a bonding area. The display panel includes a substrate and a first wiring layer, a second wiring layer, and a pixel definition layer stacked in sequence on the substrate. In the bonding area, the second wiring layer covers the first wiring layer, and the pixel definition layer forms a bonding opening. The second wiring layer includes a plurality of metal wiring parts, and some of the metal wiring parts are exposed from the bonding opening of the pixel definition layer to establish an electrical connection with an external circuit.

[0058] The inventors have found through research that at the bonding opening, the edge of the pixel definition layer covers part of the second wiring layer and the first wiring layer, thereby forming a high step difference area. The film layer formed in the high step difference area is relatively weak, and during the pixel patterning process of the display area 101, the pixel definition layer in the high step difference area and the metal wiring part covered by it will be over-etched, which may reduce the effective cross-sectional area of ​​the metal wiring part, resulting in large impedance and affecting the reliability of the product.

[0059] Based on this, the present application provides a display panel solution, as detailed in the following embodiments.

[0060] Reference Figure 1 , Figure 2 and Figure 3 As shown, an embodiment of the present application provides a display panel 100, which includes a display area 101 and a non-display area, wherein the non-display area at least partially surrounds the display area 101, and the non-display area includes a bonding area 102. The display panel 100 includes a substrate 10, a first wiring layer 20, a second wiring layer 30, and an isolation layer 50. The first wiring layer 20 and the second wiring layer 30 are arranged on the same side of the substrate 10, and at least part of the first wiring layer 20 is located in the bonding area 102. At least part of the second wiring layer 30 is located in the display area 101, and in the display area 101, the second wiring layer 30 is electrically connected to the first wiring layer 20. The isolation layer 50 is located in the display area 101 and the bonding area 102, and the isolation layer 50 is located on the side of the first wiring layer 20 away from the substrate 10. The isolation layer 50 in the display area 101 forms an isolation structure 51, which defines an isolation opening 510 for accommodating the light-emitting unit 60, and the isolation structure 51 is located on the side of the second wiring layer 30 away from the substrate 10. The orthographic projection of at least part of the first wiring layer 20 located in the bonding area 102 on the substrate 10 is located within the orthographic projection of the isolation layer 50 on the substrate 10, and the isolation layer 50 located in the bonding area 102 is electrically connected to the first wiring layer 20.

[0061] The display panel 100 provided in the present application replaces the second wiring layer 30 with an isolation layer 50 in the bonding area 102 to cover the first wiring layer 20 and achieve electrical connection. During the pixel patterning process of the display area 101, the isolation layer 50 protects the first wiring layer 20 below, and the second wiring layer 30 does not exist in the bonding area 102, which can reduce the step difference of the wiring edge, thereby reducing the over-etching damage to the metal wiring caused by etching, and improving the electrical performance and reliability of the product.

[0062] Specifically, in the bonding area 102, the orthographic projection of the first wiring layer 20 on the substrate 10 is located within the orthographic projection of the isolation layer 50 on the substrate 10. The isolation layer 50 covers a portion of the first wiring layer 20, and the isolation layer 50 is in direct contact with the surface of the first wiring layer 20 that is away from the substrate 10.

[0063] Reference Figure 4 As shown, in one embodiment, the display panel 100 further includes a pixel defining layer 40, and the pixel defining layer 40 is located in the display area 101 and the bonding area 102. In the display area 101, the pixel defining layer 40 is located on the side of the second wiring layer 30 away from the substrate 10, and the pixel defining layer 40 located in the display area 101 includes a pixel opening 401, so that the isolation opening 510 corresponds to and communicates with the pixel opening 401. The orthographic projection of the pixel defining layer 40 located in the bonding area 102 on the substrate 10 overlaps with the orthographic projection of the first wiring layer 20 on the substrate 10.

[0064] Preferably, the pixel defining layer 40 is located on a side of the isolation layer 50 close to the substrate 10 .

[0065] Preferably, in the bonding area 102 , the orthographic projection of the pixel defining layer 40 on the substrate 10 overlaps with the orthographic projection of the isolation layer 50 on the substrate 10 . In other words, the isolation layer 50 located in the bonding area 102 covers at least a portion of the pixel defining layer 40 .

[0066] Among them, the portion of the pixel defining layer 40 located in the display area 101 can physically isolate adjacent pixels and insulate the isolation layer 50 from other conductive layers. The portion of the pixel defining layer 40 located in the bonding area 102 overlaps with the first wiring layer 20, and the pixel defining layer 40 can protect the edge portion of the first wiring layer 20.

[0067] In addition, the isolation layer 50 can protect the portion of the pixel definition layer 40 covered by it from being over-etched. In the bonding area 102, the isolation layer 50 is in direct contact with the surface of the portion of the pixel definition layer 40 that is away from the substrate 10. The isolation layer 50 in the bonding area 102 also covers a portion of the first wiring layer 20, and the first wiring layer 20 is located on the inner side of the pixel definition layer 40. In this way, in the bonding area 102, the pixel definition layer 40, the isolation layer 50 and the substrate 10 form a closed structure to fully protect the first wiring layer 20.

[0068] Preferably, the second wiring layer 30 is located on a side of the first wiring layer 20 away from the substrate 10 .

[0069] Preferably, the first wiring layer 20 is located in the display area 101 and the bonding area 102 .

[0070] Reference Figure 2 As shown, preferably, the light-emitting unit 60 includes a first electrode 61, a light-emitting functional layer 62 and a second electrode 63 which are stacked on the substrate 10 and are sequentially away from the substrate 10, the light-emitting functional layer 62 and the second electrode 63 are located in the isolation opening 510, and the first electrode 61 is partially exposed to the pixel opening.

[0071] Specifically, the pixel defining layer 40 covers the gaps between adjacent first electrodes 61 and the edges of the first electrodes 61 to expose the first electrodes 61 at the pixel openings.

[0072] Specifically, the first electrode 61 is one of the anode and the cathode, and the second electrode 63 is the other of the anode and the cathode. In the embodiment of the present application, the first electrode 61 is preferably an anode, and the second electrode 63 is preferably a cathode. The light-emitting functional layer 62 may include one or more of an electron injection layer, an electron transport layer, a hole blocking layer, an electron blocking layer, a hole transport layer, and a hole injection layer.

[0073] In other embodiments, in the bonding area 102 , the isolation layer 50 may also cover the entire first wiring layer 20 .

[0074] Reference Figure 4 As shown, in one embodiment, in the bonding area 102 , the pixel definition layer 40 includes a bonding opening 402 , and at least a portion of the first wiring layer 20 is exposed in the bonding opening 402 .

[0075] Preferably, the portion of the first wiring layer 20 exposed to the bonding opening 402 is electrically connected to the isolation layer 50 .

[0076] Preferably, in the bonding area 102 , the pixel definition layer 40 is at least partially disposed on a surface of the first wiring layer 20 facing away from the substrate 10 .

[0077] Preferably, in the bonding area 102 , the pixel definition layer 40 at least partially covers the side surface of the first wiring layer 20 away from the bonding opening 402 .

[0078] Among them, in the bonding area 102, part of the first wiring layer 20 is exposed from the bonding opening 402 of the pixel definition layer 40 and contacts the isolation layer 50, the edge of the first wiring layer 20 is covered by the pixel definition layer 40, and the pixel definition layer 40 and the isolation layer 50 fully cover the first wiring layer 20, thereby improving the reliability and stability of the electrical connection.

[0079] Reference Figure 4 As shown, in one embodiment, the substrate 10 includes an insulating layer 11. In the bonding area 102, at least a portion of the pixel definition layer 40 and at least a portion of the first wiring layer 20 are in contact with a surface of the insulating layer 11 facing away from the substrate 10.

[0080] The pixel defining layer 40 and the first wiring layer 20 are both in contact with the surface of the insulating layer 11 which is away from the substrate 10. Thus, a low step difference region can be formed at the position where the pixel defining layer 40 and the first wiring layer 20 overlap.

[0081] Reference Figure 4 As shown, in one embodiment, the first wiring layer 20 includes a plurality of wiring portions 21 located in the bonding area 102 , and the pixel definition layer 40 covers the gaps between adjacent wiring portions.

[0082] Among them, in the bonding area 102, the wiring part can provide an electrical connection point, allowing signals and power to be transmitted to the chip or display panel. Adjacent wiring parts are blocked by the pixel definition layer 40, thereby improving the electrical performance and reliability of the product.

[0083] Preferably, the pixel definition layer 40 located in the bonding area 102 includes an extension portion 41 , and the extension portion 41 covers an edge of the routing portion 21 .

[0084] Specifically, the extension portion 41 covers the sidewall of the routing portion 21 and a portion of the surface facing away from the substrate.

[0085] Preferably, in the bonding area 102 , the orthographic projection of the extension portion 41 on the substrate 10 is located within the orthographic projection of the isolation layer 50 on the substrate 10 .

[0086] The extension portion 41 can serve as a barrier to the wiring portion 21 , thereby achieving electrical insulation and preventing external moisture and oxygen from penetrating, thereby improving the electrical performance of the product and extending its service life.

[0087] Reference Figure 4As shown, in one embodiment, the isolation layer 50 located in the bonding area 102 includes a plurality of sub-portions 52 arranged at intervals, and the orthographic projection of the routing portion 21 on the substrate 10 is located within the orthographic projection of the corresponding sub-portion 52 on the substrate 10 .

[0088] Specifically, after the display area 101 and the bonding area 102 are entirely coated to form the isolation layer 50, in addition to preparing the isolation layer 50 of the display area 101 to form an isolation structure, the isolation layer 50 of the bonding area 102 is also patterned to disconnect the isolation layer 50 between adjacent routing portions 21 to form sub-portions 52 corresponding to the routing portions 21 one by one, so as to avoid short circuits in the sub-portions 52 and affect the electrical performance.

[0089] Based on the same inventive concept, Figure 7 As shown, another embodiment of the present application provides a method for preparing a display panel, wherein the display panel 100 prepared by the preparation method can refer to Figure 4 The display panel 100 includes a display area 101 and a non-display area, the non-display area at least partially surrounds the display area 101, and the non-display area includes a bonding area 102. The method for preparing the display panel 100 includes the following steps:

[0090] Step S1, forming a first wiring layer 20 on one side of the substrate 10, wherein at least a portion of the first wiring layer 20 is located in the bonding area 102;

[0091] Step S2, forming a second wiring layer 30 on one side of the substrate 10, wherein at least a portion of the second wiring layer 30 is located in the display area 101, and the second wiring layer 30 is electrically connected to the first wiring layer 20;

[0092] Step S3, forming an isolation layer 50 on the side of the second wiring layer 30 and the first wiring layer 20 away from the substrate 10, wherein the isolation layer 50 is located in the display area 101 and the bonding area 102, the isolation layer 50 located in the display area 101 forms an isolation structure 51, the isolation structure 51 encloses an isolation opening 510 for accommodating the light-emitting unit 60, and the isolation structure 51 is located on the side of the second wiring layer 30 away from the substrate 10; the orthographic projection of at least part of the first wiring layer 20 located in the bonding area 102 on the substrate 10 is located within the orthographic projection of the isolation layer 50 on the substrate 10, and the isolation layer 50 located in the bonding area 102 is electrically connected to the first wiring layer 20.

[0093] The manufacturing method of the display panel 100 provided in the present application replaces the second wiring layer 30 with an isolation layer 50 in the bonding area 102 to cover the first wiring layer 20 and achieve electrical connection. During the pixel patterning process of the display area 101, the isolation layer 50 protects the first wiring layer 20 below, and since the second wiring layer 30 does not exist in the bonding area 102, the etching times of the wiring layer in the bonding area 102 can be reduced, thereby reducing the damage caused by etching, improving the electrical performance of the product, and reducing the reliability risk.

[0094] In one embodiment, after step S2, the preparation method further comprises:

[0095] A pixel definition layer 40 is formed on a side of the second wiring layer 30 away from the substrate 10, wherein the pixel definition layer 40 is located in the display area 101 and the bonding area 102, and a pixel opening 401 is etched in the pixel definition layer 40 located in the display area 101; and a bonding opening is etched in the pixel definition layer 40 located in the bonding area 102;

[0096] An isolation structure 51 is formed on a side of the pixel defining layer 40 away from the substrate 10 , and an isolation opening 510 corresponds to and is connected to the pixel opening 401 .

[0097] Preferably, the first wiring layer 20 is located in the display area 101 and the bonding area 102 .

[0098] Preferably, the second wiring layer 30 is located on a side of the first wiring layer 20 away from the substrate 10 .

[0099] Among them, the pixel defining layer 40 is located on the side of the isolation layer 50 close to the substrate 10, the portion of the pixel defining layer 40 located in the display area 101 can physically isolate adjacent pixels and insulate the isolation layer 50 from other conductive layers, and the portion of the pixel defining layer 40 located in the bonding area 102 overlaps with the first wiring layer 20, and can protect the corresponding portion of the first wiring layer 20.

[0100] In one embodiment, the first routing layer 20 includes a plurality of routing portions 21 located in the bonding area 102 .

[0101] After step S3, the preparation method further comprises:

[0102] A light emitting unit 60 is formed in the display area 101;

[0103] The isolation layer 50 in the bonding area 102 is patterned to form a plurality of sub-portions 52 , wherein the orthographic projection of the routing portion 21 on the substrate 10 is located within the orthographic projection of the corresponding sub-portion 52 on the substrate 10 .

[0104] Specifically, for the display area 101, a light-emitting unit 60 capable of emitting light of different colors can be formed in the isolation opening 510. First, the entire surface is evaporated to complete the deposition of the first color full set of OLED light-emitting layers and functional layers, and then the entire surface is encapsulated with thin films, and then the unnecessary parts on the substrate 10 are selectively removed through processes such as gluing, exposure, development, etching, and peeling, so as to complete the first color patterning; then the above process is repeated twice to complete the full color pixel patterning.

[0105] Specifically, after the pixels are patterned, the isolation layer in the bonding area 102 is patterned so that the outer edge of the isolation layer 50 is located inside the outer edge of the pixel definition layer 40, so that the isolation layers 50 corresponding to different routing parts are disconnected to avoid affecting the electrical performance.

[0106] Another embodiment of the present application provides a display device, which includes the display panel 100 in the above embodiment. The display device can be located in a smart device (such as a mobile phone, VR device, computer, TV, car display, etc.).

[0107] The display device provided by the present application has a display panel 100 in which the isolation layer 50 is used to replace the second wiring layer 30 in the bonding area 102 to cover the first wiring layer 20 and achieve electrical connection. During the pixel patterning process of the display area 101, the isolation layer 50 is used to protect the first wiring layer 20 below, and the second wiring layer 30 does not exist in the bonding area 102, which can reduce the number of etching times of the wiring layer in the bonding area 102, thereby reducing the damage caused by etching, improving the electrical performance of the product, and reducing the reliability risk.

[0108] The above-mentioned isolation structure is recorded in patents CN118251982A, 202410864269.8, PCT / CN2024 / 098407, PCT / CN2024 / 102783, PCT / CN2024 / 098217, PCT / CN2024 / 099419, PCT / CN2024 / 099072, CN117979755A, CN117998900A, CN117062489A, CN117580403A, CN116583155A, CN116669477A, ​​CN117396039A, CN116669480A, CN116600606A, CN117500332A, please refer to them.

[0109] Although the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description.

[0110] It should be noted that the above is a description of an embodiment of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0111] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a non-display area, wherein the non-display area at least partially surrounds the display area, and the non-display area includes a bonding area. The display panel further includes: substrate; A first wiring layer is disposed on one side of the substrate, and at least a portion of the first wiring layer is located in the bonding area; A second wiring layer is disposed on one side of the substrate, at least a portion of the second wiring layer is located in the display area, and the second wiring layer is electrically connected to the first wiring layer; An isolation layer, the isolation layer is located in the display area and the bonding area, and is located on a side of the first wiring layer away from the substrate, the isolation layer located in the display area forms an isolation structure, the isolation structure defines an isolation opening for accommodating a light-emitting unit, and the isolation structure is located on a side of the second wiring layer away from the substrate; The orthographic projection of at least a portion of the first wiring layer located in the bonding area on the substrate is located within the orthographic projection of the isolation layer on the substrate, and the isolation layer located in the bonding area is electrically connected to the first wiring layer.

2. The display panel according to claim 1, characterized in that: The display panel further includes: a pixel defining layer, located in the display area and the bonding area; in the display area, the pixel defining layer is located on a side of the second wiring layer away from the substrate; the pixel defining layer located in the display area includes a pixel opening, and the isolation opening corresponds to and is connected to the pixel opening; an orthographic projection of the pixel defining layer located in the bonding area on the substrate overlaps with an orthographic projection of the first wiring layer on the substrate; Preferably, the isolation layer is located on a side of the pixel defining layer away from the substrate; Preferably, in the bonding area, the orthographic projection of the pixel defining layer on the substrate overlaps with the orthographic projection of the isolation layer on the substrate; Preferably, the second wiring layer is located on a side of the first wiring layer away from the substrate; Preferably, the first wiring layer is located in the display area and the non-display area; Preferably, the light-emitting unit comprises a first electrode, a light-emitting functional layer and a second electrode stacked on the substrate and sequentially away from the substrate, the light-emitting functional layer and the second electrode are located in the isolation opening; the first electrode is partially exposed to the pixel opening.

3. The display panel according to claim 2, characterized in that: The pixel definition layer includes a bonding opening located in the bonding area, and at least a portion of the first wiring layer is exposed to the bonding opening; Preferably, the portion of the first wiring layer exposed to the bonding opening is electrically connected to the isolation layer; Preferably, in the bonding area, the pixel definition layer is at least partially disposed on a surface of the first wiring layer facing away from the substrate; Preferably, in the bonding area, the pixel defining layer at least partially covers a side surface of the first wiring layer away from the bonding opening.

4. The display panel according to claim 2, characterized in that: The substrate comprises an insulating layer; In the bonding area, at least a portion of the pixel definition layer and at least a portion of the first wiring layer are respectively in contact with a surface of the insulating layer facing away from the substrate.

5. The display panel according to claim 2, characterized in that: The first routing layer includes a plurality of routing portions located in the bonding area, and the pixel defining layer covers the gaps between adjacent routing portions; Preferably, the pixel definition layer located in the bonding area includes an extension portion, and the extension portion covers the edge of the routing portion; Preferably, in the bonding area, an orthographic projection of the extension portion on the substrate is located within an orthographic projection of the isolation layer on the substrate.

6. The display panel according to claim 5, characterized in that: The isolation layer located in the bonding area includes a plurality of sub-portions arranged at intervals, and the orthographic projection of the routing portion on the substrate is located within the orthographic projection of the corresponding sub-portion on the substrate.

7. A method for preparing a display panel, characterized in that: The display panel includes a display area and a non-display area, wherein the non-display area at least partially surrounds the display area, and the non-display area includes a bonding area. The preparation method includes: forming a first wiring layer on one side of the substrate, wherein at least a portion of the first wiring layer is located in the bonding area; forming a second wiring layer on one side of the substrate, wherein at least a portion of the second wiring layer is located in the display area, and the second wiring layer is electrically connected to the first wiring layer; An isolation layer is formed on a side of the second routing layer and the first routing layer away from the substrate, wherein the isolation layer is located in the display area and the bonding area, the isolation layer located in the display area forms an isolation structure, and the isolation structure encloses an isolation opening for accommodating the light-emitting unit; at least a portion of the first routing layer located in the bonding area has its orthographic projection on the substrate located within the orthographic projection of the isolation layer on the substrate, and the isolation layer located in the bonding area is electrically connected to the first routing layer.

8. The method for preparing a display panel according to claim 7, characterized in that: After the step of forming a second wiring layer on a side of the first wiring layer away from the substrate, the preparation method further comprises: A pixel definition layer is formed on a side of the second wiring layer away from the substrate, wherein the pixel definition layer is located in the display area and the bonding area, a pixel opening is etched in the pixel definition layer located in the display area, and a bonding opening is etched in the pixel definition layer located in the bonding area, and at least a portion of the first wiring layer is exposed to the bonding opening; The isolation structure is formed on a side of the pixel defining layer away from the substrate, and the isolation opening corresponds to and is connected with the pixel opening; Preferably, the second wiring layer is located on a side of the first wiring layer away from the substrate; Preferably, the first wiring layer is located in the display area and the non-display area.

9. The method for preparing a display panel according to claim 8, characterized in that: The first routing layer includes a plurality of routing portions located in the bonding area; After the step of forming an isolation layer on the second wiring layer and the first wiring layer on a side away from the substrate, the preparation method further comprises: forming the light emitting unit in the display area; The isolation layer located in the bonding area is patterned to form a plurality of sub-portions; wherein the orthographic projection of the routing portion on the substrate is located within the orthographic projection of the corresponding sub-portion on the substrate.

10. A display device, characterized in that: A display panel comprising any one of claims 1 to 6.

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