Display panel, preparation method thereof and display device

Abstract

The invention relates to a display panel, a preparation method thereof and a display device. The display panel comprises a substrate and a signal line arranged on one side of the substrate; the first insulating layer is arranged on one side of the substrate, a via hole is formed in the first insulating layer, and a part of the signal line is exposed from the via hole; the first electrode is arranged on one side, far away from the substrate, of the first insulating layer; the second insulating layer is arranged on one side, far away from the substrate, of the first electrode; wherein the second insulating layer comprises a first flat part, the size of the first flat part in the thickness direction of the substrate is a first size H1, and the distance between the surface of the side, close to the substrate, of the first insulating layer and the surface of the side, away from the substrate, of the first insulating layer is a first distance L1, the ratio of the first size H1 to the first distance L1 is not less than 0.8. By adopting the scheme, the yield of display panel finished products can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for preparing the same, and a display device. Background Art

[0002] OLED (Organic Light Emitting Diode) display panel is one of the hot topics in the current display panel research field. Compared with liquid crystal display panels, OLED display panels have the advantages of low energy consumption, low cost, self-luminescence, wide viewing angle and fast response speed. The sub-pixels of OLED display panels are usually made by FMM (Fine Metal Mask) evaporation.

[0003] Currently, an evaporation process that eliminates FMM has become the focus of attention in the industry. However, the yield rate of OLED display panels made by this preparation process is currently low. Summary of the invention

[0004] Based on this, it is necessary to provide a display panel and a preparation method thereof, and a display device that can improve the yield rate of the finished display panel in order to address the above technical problems.

[0005] In a first aspect, the present application provides a display panel, comprising:

[0006] substrate,

[0007] A signal line is arranged on one side of the substrate;

[0008] A first insulating layer is disposed on one side of the substrate, and a portion of the first insulating layer is located on a side of the signal line away from the substrate, a via hole is provided on the first insulating layer, and a portion of the signal line is exposed from the via hole;

[0009] A first electrode is disposed on a side of the first insulating layer away from the substrate, and an orthographic projection of the first electrode on the first insulating layer covers the via hole, wherein the first electrode includes a first electrode portion connected to a signal line portion, and an orthographic projection of the first electrode portion on the first insulating layer covers a bottom wall of the via hole;

[0010] A second insulating layer is disposed on a side of the first electrode away from the substrate, wherein an orthographic projection of the second insulating layer on the first insulating layer covers the via hole;

[0011] Among them, the second insulating layer includes a first flat portion, the orthographic projection of the first flat portion on the substrate overlaps with the orthographic projection of the via on the substrate, the size of the first flat portion along the thickness direction of the substrate is a first size H1, the distance between the side surface of the first insulating layer close to the substrate and the side surface of the first insulating layer away from the substrate is a first distance L1, and the ratio of the first size H1 to the first distance L1 is not less than 0.8.

[0012] In this embodiment, the ratio of the first dimension H1 to the first distance L1 is not less than 0.8. In this way, the step difference between the second insulating layer at the via hole and the non-via hole is reduced, so that a film with uniform thickness can be formed on the second insulating layer, such as the formation of an isolation structure, thereby avoiding the problem of dark spots in pixels caused by the isolation structure being easily damaged during the pixel opening stage, thereby improving the yield of the finished product of the display panel.

[0013] In one embodiment, the ratio of the first size H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.2;

[0014] Optionally, the first electrode further includes a second electrode portion, and an orthographic projection of the second electrode portion on the first insulating layer does not overlap with the via hole; the second insulating layer further includes a second flat portion disposed on a side of the second electrode portion of the first electrode away from the substrate;

[0015] The dimension of the second flat portion along the thickness direction of the substrate is a second dimension H2, and the second dimension H2 is smaller than the first dimension H1;

[0016] Optionally, the second size H2 is greater than or equal to 3000A and less than or equal to 5000A;

[0017] Optionally, a distance between a side surface of the first flat portion away from the substrate and a side surface of the substrate close to the signal line is a second distance L2, a distance between a side surface of the second flat portion away from the substrate and a side surface of the substrate close to the signal line is a third distance L3, and a ratio of the second distance L2 to the third distance L3 is not less than 0.8;

[0018] Optionally, a ratio of the second distance L2 to the third distance L3 is greater than or equal to 0.8 and less than or equal to 1.2.

[0019] In one embodiment, the second insulating layer defines a pixel opening, and a portion of the first electrode is exposed from the pixel opening;

[0020] Optionally, the display panel further comprises an isolation structure, wherein the isolation structure is disposed on a side of the second insulating layer away from the substrate, the orthographic projection of the isolation structure on the first insulating layer covers the via hole, and the isolation structure defines an isolation opening, and the isolation opening is connected to the pixel opening;

[0021] Optionally, the surface of the isolation structure away from the substrate has no step difference;

[0022] Optionally, the orthographic projection outer contour of the isolation opening on the substrate is located at the periphery of the orthographic projection outer contour of the pixel opening on the substrate;

[0023] Optionally, the orthographic projection of the isolation structure on the substrate is in a grid shape;

[0024] Optionally, the isolation structure comprises a first isolation portion and a second isolation portion stacked in a direction away from the substrate, and an orthographic projection of the second isolation portion on the substrate covers an orthographic projection of the first isolation portion on the substrate;

[0025] Optionally, the first isolation portion comprises a conductive material;

[0026] Optionally, the first isolation portion includes at least one metal layer;

[0027] Optionally, the first isolation portion includes a first metal layer and a second metal layer stacked in a direction away from the substrate, and an orthographic projection outer contour of the first metal layer on the substrate is located outside an orthographic projection outer contour of the second metal layer on the substrate;

[0028] Optionally, the material of the second isolation portion includes titanium or molybdenum; the material of the first metal layer includes molybdenum or titanium; and the material of the second metal layer includes aluminum or copper or silver.

[0029] In one embodiment, the second insulating layer further includes a third flat portion, and an orthographic projection of the third flat portion on the substrate does not overlap with an orthographic projection of the first electrode on the substrate;

[0030] The dimension of the third flat portion along the thickness direction of the substrate is a third dimension H3, and the third dimension H3 is greater than the second dimension H2;

[0031] Optionally, a distance between a side surface of the third flat portion away from the substrate and a side surface of the substrate close to the signal line is a fourth distance L4, and the fourth distance L4 is equal to the third distance L3;

[0032] Optionally, a surface of the second insulating layer away from the substrate has no step difference.

[0033] In one of the embodiments, the display panel further includes a light-emitting functional layer and a second electrode;

[0034] The light-emitting functional layer is arranged on a side of the first electrode away from the substrate and at the pixel opening;

[0035] The second electrode is arranged on a side of the light-emitting functional layer away from the substrate;

[0036] Optionally, the second electrode is electrically connected to the first isolation portion.

[0037] In one of the embodiments, the display panel further includes an encapsulation layer, and the encapsulation layer is disposed on a side of the second electrode away from the substrate.

[0038] In one embodiment, the sidewall of the via hole is a plane or a curved surface.

[0039] In a second aspect, the present application provides a display panel, including:

[0040] substrate,

[0041] A signal line is arranged on one side of the substrate;

[0042] A first insulating layer is disposed on one side of the substrate, and a portion of the first insulating layer is located on a side of the signal line away from the substrate, a via hole is provided on the first insulating layer, and a portion of the signal line is exposed from the via hole;

[0043] A first electrode is disposed on a side of the first insulating layer away from the signal line, and an orthographic projection of the first electrode on the first insulating layer covers the via hole, wherein the first electrode includes a first electrode portion connected to a portion of the signal line, and an orthographic projection of the first electrode portion on the first insulating layer covers a bottom wall of the via hole;

[0044] A pixel definition layer is disposed on a side of the first electrode away from the substrate, wherein an orthographic projection of the pixel definition layer on the first insulating layer covers the via hole, and the pixel definition layer defines a pixel opening, and a portion of the first electrode is exposed from the pixel opening;

[0045] An isolation structure is disposed on a side of the pixel definition layer away from the substrate, wherein the orthographic projection of the isolation structure on the first insulating layer covers the via hole, and the isolation structure defines an isolation opening, which is connected to the pixel opening;

[0046] A light-emitting functional layer is arranged on a side of the first electrode away from the substrate and at the pixel opening;

[0047] In which, the pixel definition layer includes a first flat portion and a second flat portion in contact with the first electrode portion of the first electrode, the orthographic projection of the second flat portion on the substrate does not overlap with the orthographic projection of the first electrode portion on the substrate, and the size of the first flat portion along the thickness direction of the substrate is larger than the size of the second flat portion along the thickness direction of the substrate.

[0048] In this embodiment, the dimension of the first flat portion along the thickness direction of the substrate is greater than the dimension of the second flat portion along the thickness direction of the substrate. In this way, the step difference between the pixel definition layer at the via hole and the non-via hole is reduced, so that the film forming area of ​​the isolation structure is relatively flat. In this way, the film thickness of the isolation structure is uniform, thereby avoiding the problem of pixel dark spots caused by the isolation structure being easily damaged during the pixel opening stage, thereby improving the finished product yield of the display panel.

[0049] In one embodiment, the dimension of the first flat portion along the thickness direction of the substrate is a first dimension H1, the distance between a surface of the first insulating layer close to the substrate and a surface of the first insulating layer away from the substrate is a first distance L1, and the ratio of the first dimension H1 to the first distance L1 is not less than 0.8;

[0050] Optionally, a ratio of the first size H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.2;

[0051] Optionally, the first electrode further includes a second electrode portion, an orthographic projection of the second electrode portion on the first insulating layer does not overlap with the via hole; the second flat portion contacts the second electrode portion of the first electrode;

[0052] The dimension of the second flat portion along the thickness direction of the substrate is a second dimension H2, and the second dimension H2 is smaller than the first dimension H1;

[0053] Optionally, the second size H2 is greater than or equal to 3000A and less than or equal to 5000A;

[0054] Optionally, a distance between a side surface of the first flat portion away from the substrate and a side surface of the substrate close to the signal line is a second distance L2, a distance between a side surface of the second flat portion away from the substrate and a side surface of the substrate close to the signal line is a third distance L3, and a ratio of the second distance L2 to the third distance L3 is not less than 0.8;

[0055] Optionally, a ratio of the second distance L2 to the third distance L3 is greater than or equal to 0.8 and less than or equal to 1.2.

[0056] In one embodiment, the surface of the isolation structure away from the substrate has no step difference;

[0057] Optionally, the orthographic projection outer contour of the isolation opening on the substrate is located at the periphery of the orthographic projection outer contour of the pixel opening on the substrate;

[0058] Optionally, the orthographic projection of the isolation structure on the substrate is in a grid shape;

[0059] Optionally, the isolation structure comprises a first isolation portion and a second isolation portion stacked in a direction away from the substrate, and an orthographic projection of the second isolation portion on the substrate covers an orthographic projection of the first isolation portion on the substrate;

[0060] Optionally, the first isolation portion comprises a conductive material;

[0061] Optionally, the first isolation portion includes at least one metal layer;

[0062] Optionally, the first isolation portion includes a first metal layer and a second metal layer stacked in a direction away from the substrate, and an orthographic projection outer contour of the first metal layer on the substrate is located outside an orthographic projection outer contour of the second metal layer on the substrate;

[0063] Optionally, the material of the second isolation portion includes titanium or molybdenum; the material of the first metal layer includes molybdenum or titanium; and the material of the second metal layer includes aluminum or copper or silver.

[0064] In one embodiment, the pixel definition layer further includes a third flat portion, and an orthographic projection of the third flat portion on the substrate does not overlap with an orthographic projection of the first electrode on the substrate;

[0065] The dimension of the third flat portion along the thickness direction of the substrate is a third dimension H3, and the third dimension H3 is greater than the second dimension H2;

[0066] Optionally, a distance between a side surface of the third flat portion away from the substrate and a side surface of the substrate close to the signal line is a fourth distance L4, and the fourth distance L4 is equal to the third distance L3;

[0067] Optionally, a surface of the second insulating layer away from the substrate has no step difference.

[0068] In one embodiment, the display panel further includes a light-emitting functional layer and a second electrode, wherein the light-emitting functional layer is disposed on a side of the first electrode away from the substrate and disposed at the pixel opening; and the second electrode is disposed on a side of the light-emitting functional layer away from the substrate;

[0069] Optionally, the second electrode is electrically connected to the first isolation portion.

[0070] In one of the embodiments, the display panel further includes an encapsulation layer, and the encapsulation layer is disposed on a side of the second electrode away from the substrate.

[0071] In a third aspect, the present application provides a display panel, including:

[0072] substrate,

[0073] A signal line is arranged on one side of the substrate;

[0074] A first insulating layer is disposed on one side of the substrate, and a portion of the first insulating layer is located on a side of the signal line away from the substrate, a via hole is provided on the first insulating layer, and a portion of the signal line is exposed from the via hole;

[0075] A first electrode is disposed on a side of the first insulating layer away from the substrate, an orthographic projection of the first electrode on the first insulating layer covers the via hole, wherein the first electrode comprises a first electrode portion and a second electrode portion connected to the signal line portion, an orthographic projection of the first electrode portion on the first insulating layer covers a bottom wall of the via hole, and an orthographic projection of the second electrode portion on the first insulating layer does not overlap with the via hole;

[0076] A second insulating layer is disposed on a side of the first electrode away from the substrate, wherein an orthographic projection of the second insulating layer on the first insulating layer covers the via hole;

[0077] In which, the second insulating layer includes a first flat portion and a second flat portion which are respectively in contact with the first electrode portion and the second electrode portion of the first electrode; a distance between a surface of the first flat portion away from a side of the substrate and a surface of the substrate close to the signal line is a second distance L2, a distance between a surface of the second flat portion away from a side of the substrate and a surface of the substrate close to the signal line is a third distance L3, and a ratio of the second distance L2 to the third distance L3 is not less than 0.8.

[0078] In this embodiment, the ratio of the second distance L2 to the third distance L3 is not less than 0.8. In this way, the step difference between the second insulating layer at the via and the non-via is reduced, so that a film with uniform thickness can be formed on the second insulating layer, such as the formation of an isolation structure, thereby avoiding the problem of dark spots in pixels caused by the isolation structure being easily damaged during the pixel opening stage, thereby improving the finished product yield of the display panel.

[0079] In one embodiment, the ratio of the second distance L2 to the third distance L3 is greater than or equal to 0.8 and less than or equal to 1.2;

[0080] Optionally, a dimension of the first flat portion along a thickness direction of the substrate is a first dimension H1, a distance between a surface of a side of the first insulating layer close to the substrate and a surface of a side of the first insulating layer away from the substrate is a first distance L1, and a ratio of the first dimension H1 to the first distance L1 is not less than 0.8;

[0081] Optionally, a ratio of the first size H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.2;

[0082] Optionally, a dimension of the second flat portion along a thickness direction of the substrate is a second dimension H2, and the second dimension H2 is smaller than the first dimension H1;

[0083] Optionally, the second size H2 is greater than or equal to 3000A and less than or equal to 5000A.

[0084] In a fourth aspect, the present application provides a method for preparing a display panel, the method comprising:

[0085] Providing a substrate,

[0086] forming a signal line on one side of the substrate,

[0087] A first insulating layer is formed on one side of the substrate, and a portion of the first insulating layer is located on a side of the signal line away from the substrate, a via hole is formed on the first insulating layer, and a portion of the signal line is exposed from the via hole;

[0088] forming a first electrode on a side of the first insulating layer away from the substrate, wherein an orthographic projection of the first electrode on the first insulating layer covers the via hole, the first electrode comprises a first electrode portion connected to the signal line portion, and an orthographic projection of the first electrode portion on the first insulating layer covers a bottom wall of the via hole;

[0089] forming a second insulating layer on a side of the first electrode away from the substrate, wherein an orthographic projection of the second insulating layer on the first insulating layer covers the via hole;

[0090] Among them, the second insulating layer includes a first flat portion, the orthographic projection of the first flat portion on the substrate overlaps with the orthographic projection of the via on the substrate, the size of the first flat portion along the thickness direction of the substrate is a first size H1, the distance between the side surface of the first insulating layer close to the substrate and the side surface of the first insulating layer away from the substrate is a first distance L1, and the ratio of the first size H1 to the first distance L1 is not less than 0.8.

[0091] In one embodiment, the ratio of the first size H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.2;

[0092] Optionally, the first electrode further includes a second electrode portion, and an orthographic projection of the second electrode portion on the first insulating layer does not overlap with the via hole; the second insulating layer further includes a second flat portion disposed on a side of the second electrode portion of the first electrode away from the substrate;

[0093] The dimension of the second flat portion along the thickness direction of the substrate is a second dimension H2, and the second dimension H2 is smaller than the first dimension H1;

[0094] Optionally, the second size H2 is greater than or equal to 3000A and less than or equal to 5000A;

[0095] Optionally, a distance between a side surface of the first flat portion away from the substrate and a side surface of the substrate close to the signal line is a second distance L2, a distance between a side surface of the second flat portion away from the substrate and a side surface of the substrate close to the signal line is a third distance L3, and a ratio of the second distance L2 to the third distance L3 is not less than 0.8;

[0096] Optionally, a ratio of the second distance L2 to the third distance L3 is greater than or equal to 0.8 and less than or equal to 1.2.

[0097] In one embodiment, forming a second insulating layer on a side of the first electrode away from the substrate includes:

[0098] forming an insulating material layer on a side of the first electrode away from the substrate; and forming a photoresist layer on the insulating material layer;

[0099] The photoresist layer is exposed using a half-tone mask, wherein the half-tone mask comprises a first area, a second area and a third area; the transmittance of the first area is less than the transmittance of the second area; the transmittance of the second area is less than the transmittance of the third area;

[0100] Performing a development process on the photoresist layer so that the photoresist layer forms a first partial removal area, a second partial removal area and a complete removal area, wherein the first partial removal area corresponds to the first area, the second partial removal area corresponds to the second area, and the complete removal area corresponds to the third area;

[0101] Removing the photoresist in the completely removed area, removing part of the photoresist in the first partially removed area, and removing part of the photoresist in the second partially removed area, wherein the thickness of the remaining photoresist in the first partially removed area is greater than the thickness of the remaining photoresist in the second partially removed area;

[0102] Etching the insulating material layer exposed in the completely removed area to form a pixel opening;

[0103] Removing part of the remaining photoresist in the first partial removal area, and retaining the insulating material layer covered by the photoresist in the first partial removal area to form the first flat portion;

[0104] The photoresist in the second partial removal area is removed by etching, and the insulating material layer in the second partial removal area is further etched to form the second flat portion.

[0105] In one embodiment, forming a second insulating layer on a side of the first electrode away from the substrate includes:

[0106] forming an insulating material layer on a side of the first electrode away from the substrate, and a ratio of a dimension of the insulating material layer on the first electrode portion of the first electrode along a thickness direction of the substrate to the first distance L1 is not less than 0.8;

[0107] forming a photoresist layer on the insulating material layer;

[0108] Expose the photoresist layer using a first mask, wherein the first mask comprises a shielding area and a light-transmitting area; the shielding area corresponds to the first electrode portion, and the light-transmitting area corresponds to the second electrode portion;

[0109] Performing a development process on the photoresist layer so that the photoresist layer forms a reserved area and a removed area, wherein the reserved area corresponds to the first electrode portion, and the removed area corresponds to the second electrode portion;

[0110] removing the photoresist in the removal area, and etching the insulating material layer in the removal area to form the second flat portion and a pixel opening;

[0111] The photoresist in the reserved area is retained to form the first flat portion.

[0112] In one embodiment, forming a second insulating layer on a side of the first electrode away from the substrate includes:

[0113] forming a first insulating material layer on a side of the first electrode portion of the first electrode away from the substrate, wherein a ratio of a dimension of the first insulating material layer on the first electrode portion along a thickness direction of the substrate to the first distance L1 is not less than 0.8, so as to form the first flat portion;

[0114] A second insulating material layer is formed on the side of the second electrode portion of the first electrode away from the substrate, and a dimension of the second insulating material layer on the second electrode portion along the thickness direction of the substrate is smaller than a dimension of the first insulating material layer on the first electrode portion along the thickness direction of the substrate to form the second flat portion.

[0115] In a fifth aspect, the present application provides a display device, which includes the display panel described in any one of the first aspect, the second aspect or the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0116] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments of the present application or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0117] Figure 1 is a schematic cross-sectional view of a display panel in one embodiment;

[0118] Figure 2 is a cross-sectional schematic diagram of a display panel in another embodiment;

[0119] Figure 3 is a schematic cross-sectional view of a display panel in yet another embodiment;

[0120] Figure 4 is a schematic cross-sectional view of an isolation structure in one embodiment;

[0121] Figure 5 is a schematic top view of an isolation structure in one embodiment;

[0122] Figure 6 is a schematic cross-sectional view of an isolation structure in another embodiment;

[0123] Figure 7 is a schematic cross-sectional view of a sub-pixel in one embodiment;

[0124] Figure 8 is a schematic cross-sectional view of an encapsulation layer in one embodiment;

[0125] Fig. 9 FIG. 1 is a schematic diagram of a process for preparing a display panel in an embodiment.

[0126] Description of reference numerals:

[0127] 101, substrate; 102, signal line; 103, first insulating layer; P, via hole;

[0128] 104a, first electrode; 1041, first electrode portion; 1042, second electrode portion; 104b, light emitting functional layer; 104c, second electrode;

[0129] 105, second insulating layer; 1051, first flat portion; 1052, second flat portion; 105a-pixel opening;

[0130] 401, isolation structure; 4011, first isolation part; 4012, second isolation part; 401a, isolation opening; 4011a, first metal layer; 4011b, second metal layer; 801, packaging layer. DETAILED DESCRIPTION

[0131] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0132] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, they do not represent any order, quantity or importance, but are only used to distinguish different components. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present application, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. "Include" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0133] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0134] In the related art, the OLED display panel uses a photolithography process to achieve pixel-level packaging, without the need for an FMM evaporation process, thereby improving the pixel aperture ratio of the display panel. In order to further achieve a design that maximizes the pixel aperture ratio, the via holes corresponding to the anodes of the first sub-pixel (e.g., red R), the second sub-pixel (e.g., green G), and the third sub-pixel (e.g., blue B) are usually designed under the isolation column.

[0135] However, the applicant found that the step difference of the via hole is large, and the isolation structure is thinner here. In addition, when the encapsulation layer of the first sub-pixel is dry-etched, the over-etching process in the dry-etching process easily causes the top layer Ti of the isolation structure to be damaged. When the second and third sub-pixels are subsequently opened, the liquid in the wet-etching process easily enters through the over-etching, destroying the isolation structure, resulting in Al voids in the isolation structure, thereby causing pixel dark spots, resulting in a low yield of the finished OLED display panel.

[0136] Furthermore, the applicant thickens the pixel definition layer at the via hole to make the film-forming area of ​​the isolation structure relatively flat, so that the film thickness of the isolation structure is uniform, thereby avoiding the problem of pixel dark spots caused by the isolation structure being easily damaged during the pixel opening stage, thereby improving the finished product yield of the display panel.

[0137] The composition, preparation and other contents of the isolation structure mentioned below are further described in patents CN118251982A, 202410864269.8, PCT / CN2024 / 098407, PCT / CN2024 / 102783, PCT / CN2024 / 098217, PCT / CN2024 / 100935, PCT / CN2024 / 102785, PCT / CN2024 / 099419, PCT / CN2024 / 099072, and CN116685174A for reference.

[0138] Specifically, refer to Figure 1 As shown, an embodiment of the present application provides a display panel, which may be an OLED display panel or a QLED (Quantum Dot Light Emitting Diodes) display panel.

[0139] The display panel includes a substrate 101 , a signal line 102 , a first insulating layer 103 , a first electrode 104 a and a second insulating layer 105 .

[0140] The signal line 102 is disposed on one side of the substrate 101. The first insulating layer 103 is disposed on one side of the substrate 101, and a portion of the first insulating layer 103 is located on the side of the signal line 102 away from the substrate 101. A via P is formed on the first insulating layer 103, and a portion of the signal line 102 is exposed from the via P.

[0141] The first electrode 104a is arranged on a side of the first insulating layer 103 away from the substrate 101, and the orthographic projection of the first electrode 104a on the first insulating layer 103 covers the via P, wherein the first electrode 104a includes a first electrode portion 1041 partially connected to the signal line 102, and the orthographic projection of the first electrode portion 1041 on the first insulating layer 103 covers the bottom wall of the via P.

[0142] The second insulating layer 105 is disposed on a side of the first electrode 104 a away from the substrate 101 , and an orthographic projection of the second insulating layer 105 on the first insulating layer 103 covers the via hole P.

[0143] Among them, the second insulating layer 105 includes a first flat portion 1051, the orthographic projection of the first flat portion 1051 on the substrate 101 overlaps with the orthographic projection of the via P on the substrate 101, the size of the first flat portion 1051 along the thickness direction of the substrate 101 is a first size H1, the distance between the side surface of the first insulating layer 103 close to the substrate 101 and the side surface of the first insulating layer 103 away from the substrate 101 is a first distance L1, and the ratio of the first size H1 to the first distance L1 is not less than 0.8.

[0144] Among them, the first dimension H1 may be the average distance or the maximum distance of the first flat portion 1051 away from the side of the substrate 101; the first distance L1 may be the average distance of the surface of one side of the first insulating layer 103 away from the substrate 101; when the first dimension H1 is the average distance, the first distance L1 is also the average distance, and when the first dimension H1 is the maximum distance, the first distance L1 is also the maximum distance.

[0145] The substrate 101 includes a driving circuit composed of multiple metal layers and multiple insulating layers. The signal line 102 is electrically connected to the first electrode 104a, and the side of the signal line 102 away from the first electrode 104a is connected to the output end of the driving circuit to transmit an electrical signal to the first electrode 104a.

[0146] The first insulating layer 103 may be a planarization layer to achieve planarization. The material of the first insulating layer 103 may be an insulating material such as silicon nitride, silicon oxide, silicon oxynitride or a combination thereof, or a resin material such as photoresist. The stacked substrate 101, signal line 102 and first insulating layer 103 constitute an array substrate. A via P is provided on the first insulating layer 103 so that part of the signal line 102 is exposed from the via P, so that the first electrode 104a can be electrically connected to the signal line 102 through the via P. The side wall of the via P may be a plane or a curved surface, which is not limited here. Figure 1 In the figure, the side wall of the via hole P is taken as an example of a curved surface.

[0147] The first electrode 104a may be an anode, and the first electrode 104a includes a first electrode portion 1041, a second electrode portion 1042, and a third electrode portion (not shown in the figure). The orthographic projection of the first electrode portion 1041 on the first insulating layer 103 covers the bottom wall of the via P, the orthographic projection of the second electrode portion 1042 on the first insulating layer 103 does not overlap with the via P, the second electrode portion 1042 is mainly in contact with the light-emitting functional layer, and the third electrode portion is an electrode portion connecting the first electrode portion 1041 and the second electrode portion 1042, that is, an electrode portion attached to the side wall of the via P. It should be noted that in order to facilitate a clear description of the first electrode portion 1041, the second electrode portion 1042, and the third electrode portion, in Figure 1 In the figure, the first electrode portion 1041, the second electrode portion 1042 and the third electrode portion are distinguished by isolating them with dotted lines.

[0148] The second insulating layer 105 may be a pixel definition layer, and the material of the second insulating layer 105 may be an inorganic material. The second insulating layer 105 defines the light emitting area of ​​each sub-pixel, and avoids diffusion of light emitting functional materials and color mixing between sub-pixels.

[0149] The second insulating layer 105 includes a first flat portion 1051, a second flat portion 1052 and a third insulating portion (not shown in the figure). The first flat portion 1051 refers to the portion in contact with the first electrode portion 1041 of the first electrode 104a, and is also the portion where the orthographic projection on the substrate 101 overlaps with the orthographic projection of the via P on the substrate 101; the second flat portion 1052 refers to the portion of the second electrode portion 1042 of the first electrode 104a that is arranged on the side away from the substrate, and is also the portion in contact with the second electrode portion 1042 of the first electrode 104a. The third insulating portion refers to a portion attached to the third electrode portion, connecting the first flat portion 1051 and the second flat portion 1052. It should be noted that in order to facilitate a clear description of the first flat portion 1051, the second flat portion 1052 and the third insulating portion, Figure 1 In the figure, the first flat portion 1051, the second flat portion 1052 and the third insulating portion are distinguished by means of dotted line isolation.

[0150] In addition, Figure 1 The first dimension H1 and the first distance L1 are marked in FIG. The first dimension H1 is the dimension of the first flat portion 1051 along the thickness direction of the substrate 101, that is, the thickness of the second insulating layer 105 at the via P. The first distance L1 is the distance between the surface of the first insulating layer 103 close to the substrate 101 and the surface of the first insulating layer 103 away from the substrate 101, that is, the maximum thickness of the first insulating layer 103.

[0151] The ratio of the first size H1 to the first distance L1 is not less than 0.8. Specifically, the ratio of the first size H1 to the first distance L1 may be 0.8, 0.9, 1.1, 1.2, 1.3, 1.4, 1.5, or other specific values, or a range with any two of the above specific values ​​as endpoints.

[0152] In this embodiment, the ratio of the first dimension H1 to the first distance L1 is not less than 0.8. In this way, the step difference between the second insulating layer 105 at the via P and the non-via is reduced, so that a film with uniform thickness can be formed on the second insulating layer 105, such as the formation of an isolation structure, thereby avoiding the problem of dark spots in pixels caused by the isolation structure being easily damaged during the pixel opening stage, thereby improving the finished product yield of the display panel.

[0153] In one embodiment, the ratio of the first dimension H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.2, that is, the ratio of the first dimension H1 to the first distance L1 is close to 1, which can reduce the step difference between the second insulating layer 105 at the via hole P and the non-via hole. Figure 2 , which shows a cross-sectional schematic diagram of the display panel when the ratio of the first size H1 to the first distance L1 is 1.1.

[0154] In addition, the ratio of the first size H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.2 means that the ratio of the first size H1 to the first distance L1 is specific values ​​such as 0.8, 0.9, 1.1, 1.2, and a range with any two of the above specific values ​​as endpoints.

[0155] In one embodiment, referring to Figure 2 As shown, the dimension of the second flat portion 1052 along the thickness direction of the substrate 101 is a second dimension H2, and the second dimension H2 is smaller than the first dimension H1, so that the step difference between the second insulating layer 105 at the via P and the non-via can be reduced. Preferably, the second dimension H2 is greater than or equal to 3000A and less than or equal to 5000A, which can reduce the thickness of the display panel. The second dimension H2 is greater than or equal to 3000A and less than or equal to 5000A means that the second dimension H2 is 3000A, 3500A, 4000A, 4500A, 5000A and other specific values ​​and a range with any two of the above specific values ​​as endpoints.

[0156] In one embodiment, referring to Figure 3As shown, the distance between the side surface of the first flat portion 1051 away from the substrate 101 and the side surface of the substrate 101 close to the signal line 102 is a second distance L2, the distance between the side surface of the second flat portion 1052 away from the substrate 101 and the side surface of the substrate 101 close to the signal line 102 is a third distance L3, and the ratio of the second distance L2 to the third distance L3 is not less than 0.8. In this way, the step difference between the second insulating layer 105 at the via P and the non-via is reduced, so that a film with uniform thickness can be formed on the second insulating layer 105, for example, a film is formed on the isolation structure, thereby avoiding the problem of dark spots in pixels caused by the isolation structure being easily damaged during the pixel opening stage, thereby improving the yield rate of the finished product of the display panel.

[0157] Preferably, the ratio of the second distance L2 to the third distance L3 is greater than or equal to 0.8 and less than or equal to 1.2, that is, the ratio of the second distance L2 to the third distance L3 is close to 1, which can reduce the step difference between the second insulating layer 105 at the via P and the non-via. In addition, the ratio of the second distance L2 to the third distance L3 is between 0.8 and 1.2, which means that the ratio of the second distance L2 to the third distance L3 is 0.8, 0.9, 1.1, 1.2, etc., and a range with any two of the above specific values ​​as endpoints.

[0158] In one embodiment, referring to Figure 4 As shown, the second insulating layer 105 defines a pixel opening 105a, and a portion of the first electrode 104a is exposed from the pixel opening 105a. Further, the second electrode portion 1042 of the first electrode 104a is exposed from the pixel opening 105a. The sidewall of the pixel opening 105a can be a flat surface or a curved surface. Figure 4 A plane is used as an example.

[0159] In one embodiment, the second insulating layer 105 further includes a third flat portion, and the orthographic projection of the third flat portion on the substrate 101 does not overlap with the orthographic projection of the first electrode 104a on the substrate 101; the third flat portion is arranged between adjacent first electrodes 104a and is in direct contact with the first insulating layer 103; the dimension of the third flat portion along the thickness direction of the substrate 101 is a third dimension H3, and the third dimension H3 is greater than the second dimension H2, and the second dimension H2 is the dimension of the second flat portion 1052 along the thickness direction of the substrate 101, so that the step difference between the third flat portion and the second flat portion 1052 caused by the first electrode 104a can be reduced.

[0160] In one of the embodiments, the distance between the surface of the third flat portion away from the substrate 101 and the surface of the substrate 101 close to the signal line 102 is a fourth distance L4, and the fourth distance L4 is equal to the third distance L3, so that the surface of the third flat portion away from the substrate 101 and the surface of the second flat portion 1052 away from the substrate 101 are in the same plane, and there is no step difference between the third flat portion 1052.

[0161] In one embodiment, the surface of the second insulating layer 105 away from the substrate 101 has no step difference, so that a film with uniform thickness can be formed on the second insulating layer 105 .

[0162] In one embodiment, referring to Figure 4 As shown, the display panel also includes an isolation structure 401, which is arranged on a side of the second insulating layer 105 away from the substrate. The isolation structure 401's orthographic projection on the first insulating layer 103 covers the via P, and the isolation structure 401 defines an isolation opening 401a, which is connected to the pixel opening 105a, so that part of the first electrode 104a is also exposed from the isolation opening 401a.

[0163] The orthographic projection outer contour of the isolation opening 401 a on the substrate 101 is located at the periphery of the orthographic projection outer contour of the pixel opening 105 a on the substrate.

[0164] The orthographic projection of the isolation structure 401 on the substrate covers the first flat portion 1051 of the second insulating layer 105, the portion of the second flat portion 1052 close to the first flat portion 1051, the orthographic projection of the third insulating portion on the substrate, and the orthographic projection of the third flat portion on the substrate; the isolation opening 401a exposes part of the second flat portion 1052.

[0165] In this embodiment, the isolation structure 401 refers to a structure that can isolate the light-emitting functional layers of adjacent sub-pixels when the light-emitting functional layers of the sub-pixels are evaporated. In the embodiment of the present application, by setting the isolation structure 401, the light-emitting functional layers of adjacent sub-pixels can be isolated when the light-emitting functional layers of the sub-pixels are evaporated, which is conducive to making sub-pixels through pixel patterning technology and getting rid of the constraints of FMM. In one example, the isolation structure 401 can be a single-layer structure, and in another example, the isolation structure 401 can also be a stacked structure.

[0166] In one embodiment, referring to Figure 5 As shown, the orthographic projection of the isolation structure 401 on the substrate 101 is in a grid shape, so that the light-emitting functional layer of the adjacent sub-pixels is isolated when the light-emitting functional layer of the sub-pixels is evaporated. In addition, it should be noted that the arrangement of the sub-pixels R, G, and B is not limited in this application. Figure 5is just an example.

[0167] In one embodiment, referring to Figure 4 As shown, the isolation structure 401 includes a first isolation portion 4011 and a second isolation portion 4012 stacked in a direction away from the substrate 101 , and the orthographic projection of the second isolation portion 4012 on the substrate covers the orthographic projection of the first isolation portion 4011 on the substrate.

[0168] The material of the second isolation portion 4012 includes metal, for example, the material of the second isolation portion 4012 is titanium (Ti) or molybdenum (Mo).

[0169] The first isolation portion 4011 includes a conductive material. In one example, the materials constituting the first isolation portion 4011 are all conductive materials. In another example, the materials constituting the first isolation portion 4011 include an insulating material and a conductive material.

[0170] Specifically, the first isolation portion 4011 includes at least one metal layer. Figure 4 As shown, the first isolation portion 4011 includes a first metal layer 4011a and a second metal layer 4011b stacked in a direction away from the substrate 101. In one example, the orthographic projection outer contour of the first metal layer 4011a on the substrate 101 is located outside the orthographic projection outer contour of the second metal layer 4011b on the substrate 101, wherein the material of the first metal layer 4011a includes molybdenum or titanium; the material of the second metal layer 4011b includes aluminum, copper or silver.

[0171] It can be understood that the first metal layer 4011a and the second metal layer 4011b in the second isolation part 4012 and the first isolation part 4011 form an I-shaped structure. By setting up three stacked metal layers, the resistance of the isolation structure 401 can be reduced, thereby reducing the power consumption of the display panel.

[0172] It is understood that the isolation structure 401 may be as follows Figure 4 As shown, the first isolation portion 4011 and the second isolation portion 4012 are both curved surfaces away from the substrate 101. The isolation structure 401 may also be as follows: Figure 6 As shown, the surfaces of the first isolation portion 4011 and the second isolation portion 4012 away from the substrate 101 are both plane, that is, the surface of the isolation structure 401 away from the substrate 101 has no step difference.

[0173] In one embodiment, referring to Figure 7As shown, the display panel also includes a light-emitting functional layer 104b and a second electrode 104c; the light-emitting functional layer 104b is arranged on the side of the first electrode 104a away from the substrate 101 and is arranged at the pixel opening 105a; the second electrode 104c is arranged on the side of the light-emitting functional layer 104b away from the substrate 101.

[0174] The stacked first electrode 104a, the light-emitting functional layer 104b and the second electrode 104c constitute a sub-pixel. Each sub-pixel is disposed in the isolation opening 401a, and the area to which the isolation opening 401a belongs is also referred to as a light-emitting area.

[0175] It is understood that the first electrode 104a may be an anode, and the second electrode 104c may be a cathode. The light-emitting functional layer 104b includes at least a light-emitting layer (Emission layer, EML), and may also include one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron injection layer (EIL), an electron transport layer (ETL), a hole blocking layer (HBL) and an electron blocking layer (EBL). Alternatively, the light-emitting functional layer 104b may also be a stacked light-emitting layer, that is, including at least two light-emitting layers and a charge generation layer (CGL) located between each adjacent light-emitting layer.

[0176] In one example, the second electrode 104c is electrically connected to the first isolation portion 4011. Figure 7 As shown, the second electrode 104c includes a lap portion (not marked in the figure), which covers at least a portion of the side wall of the first isolation portion 4011. Specifically, the lap portion is connected to both the first metal layer 4011a and the second metal layer 4011b in the first isolation portion 4011. It can be understood that the second electrode 104c also includes a main body portion (not marked in the figure), which at least covers the light-emitting functional layer 104b.

[0177] By making the overlapping portion cover the side wall of the first isolation portion 4011, the electrical connection resistance between the overlapping portion and the first isolation portion 4011 can be reduced, and the electrical connection resistance between the overlapping portion and the isolation structure 401 can be reduced, which is beneficial to improving display uniformity.

[0178] In one embodiment, referring to Figure 8As shown, the display panel further includes an encapsulation layer 801 , and the encapsulation layer 801 is disposed on a side of the second electrode 104 c away from the substrate 101 .

[0179] Optionally, the encapsulation layer 801 may be a single-layer inorganic film layer or a multi-layer inorganic film layer, and the inorganic film layer may be a silicon oxide layer, a silicon nitride layer, etc. The encapsulation layer 801 may also be a mixture of an organic film layer and an inorganic film layer. The encapsulation layer 801 may prevent the sub-pixel from being corroded by water vapor.

[0180] Since the ratio of the first dimension H1 to the first distance L1 is not less than 0.8, the step difference between the second insulating layer 105 at the via P and the non-via is reduced, so that the film forming area of ​​the isolation structure 401 is relatively flat. In this way, the film thickness of the isolation structure is uniform, so the film layer of the encapsulation layer 801 is also relatively continuous, which can effectively protect the film layer below.

[0181] In one embodiment, Fig. 9 As shown, the present application also provides a method for preparing a display panel, and the method for preparing a display panel can be used to prepare the display panel in the above display panel embodiment.

[0182] The method for preparing the display panel includes:

[0183] Step 901, providing a substrate 101,

[0184] Step 902, forming a signal line 102 on one side of the substrate 101,

[0185] Step 903, forming a first insulating layer 103 on one side of the substrate 101, and a portion of the first insulating layer 103 is located on a side of the signal line 102 away from the substrate 101, and a via P is opened on the first insulating layer 103, and a portion of the signal line 102 is exposed from the via P;

[0186] Step 904, forming a first electrode 104a on a side of the first insulating layer 103 away from the substrate 101, wherein the orthographic projection of the first electrode 104a on the first insulating layer 103 covers the via hole P, and the first electrode 104a includes a first electrode portion 1041 connected to a portion of the signal line 102, and the orthographic projection of the first electrode portion 1041 on the first insulating layer 103 covers the bottom wall of the via hole P;

[0187] Step 905 , forming a second insulating layer 105 on a side of the first electrode 104 a away from the substrate 101 , wherein the orthographic projection of the second insulating layer 105 on the first insulating layer 103 covers the via P;

[0188] Among them, the second insulating layer 105 includes a first flat portion 1051, the orthographic projection of the first flat portion 1051 on the substrate 101 overlaps with the orthographic projection of the via P on the substrate 101, the size of the first flat portion 1051 along the thickness direction of the substrate 101 is a first size H1, the distance between the side surface of the first insulating layer 103 close to the substrate 101 and the side surface of the first insulating layer 103 away from the substrate 101 is a first distance L1, and the ratio of the first size H1 to the first distance L1 is not less than 0.8.

[0189] Optionally, a ratio of the first size H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.2.

[0190] Optionally, the first electrode 104a further includes a second electrode portion 1042, and the orthographic projection of the second electrode portion 1042 on the first insulating layer 103 does not overlap with the via P; the second insulating layer 105 further includes a second flat portion 1052 in contact with the second electrode portion 1042 of the first electrode 104a; the size of the second flat portion 1052 along the thickness direction of the substrate 101 is a second size H2, and the second size H2 is smaller than the first size H1;

[0191] Optionally, the second size H2 is greater than or equal to 3000A and less than or equal to 5000A;

[0192] Optionally, a distance between a side surface of the first flat portion 1051 away from the substrate 101 and a side surface of the substrate 101 close to the signal line 102 is a second distance L2, a distance between a side surface of the second flat portion 1052 away from the substrate 101 and a side surface of the substrate 101 close to the signal line 102 is a third distance L3, and a ratio of the second distance L2 to the third distance L3 is not less than 0.8;

[0193] Optionally, the ratio of the second distance L2 to the third distance L3 is greater than or equal to 0.8 and less than or equal to 1.2.

[0194] In this embodiment, the ratio of the first dimension H1 to the first distance L1 is not less than 0.8. In this way, the step difference between the second insulating layer 105 at the via P and the non-via is reduced, so that a film with uniform thickness can be formed on the second insulating layer 105, such as the formation of an isolation structure, thereby avoiding the problem of dark spots in pixels caused by the isolation structure being easily damaged during the pixel opening stage, thereby improving the finished product yield of the display panel.

[0195] In one embodiment, the second insulating layer 105 is formed on the side of the first electrode 104a away from the substrate 101 in the following ways:

[0196] In one example, forming the second insulating layer 105 on a side of the first electrode 104a away from the substrate 101 includes the following steps:

[0197] Step 11, forming an insulating material layer on a side of the first electrode 104a away from the substrate 101; and forming a photoresist layer on the insulating material layer;

[0198] Step 12, using a half-tone mask to perform exposure processing on the photoresist layer, wherein the half-tone mask includes a first area, a second area and a third area; the transmittance of the first area is less than the transmittance of the second area; the transmittance of the second area is less than the transmittance of the third area;

[0199] Step 13, developing the photoresist layer so that the photoresist layer forms a first partial removal area, a second partial removal area and a complete removal area, wherein the first partial removal area corresponds to the first area, the second partial removal area corresponds to the second area, and the complete removal area corresponds to the third area;

[0200] Step 14, removing the photoresist in the completely removed area, removing part of the photoresist in the first partial removal area, and removing part of the photoresist in the second partial removal area, wherein the thickness of the photoresist remaining in the first partial removal area is greater than the thickness of the photoresist remaining in the second partial removal area;

[0201] Step 15, etching the insulating material layer exposed in the completely removed area to form a pixel opening 105a;

[0202] Step 16, removing part of the remaining photoresist in the first partial removal area, and retaining the insulating material layer covered by the photoresist in the first partial removal area to form a first flat portion 1051;

[0203] Step 17 , etching away the photoresist in the second partial removal area, and continuing to etch the insulating material layer in the second partial removal area to form a second flat portion 1052 .

[0204] In this embodiment, the half-tone mask is designed with different transmittances, so that different film thicknesses can be achieved in different regions. Therefore, when the second insulating layer 105 is formed, the insulating material layer is formed thicker in the hole region by applying photoresist → using the half-tone mask for exposure → developing → etching, thereby obtaining the second insulating layer 105. The second insulating layer is obtained by using the half-tone mask, which does not increase the manufacturing of the display panel.

[0205] In another example, forming the second insulating layer 105 on a side of the first electrode 104a away from the substrate 101 includes the following steps:

[0206] Step 21, forming an insulating material layer on the side of the first electrode 104a away from the substrate 101, and the ratio of the size of the insulating material layer on the first electrode portion 1041 of the first electrode 104a along the thickness direction of the substrate 101 to the first distance L1 is not less than 0.8. In other words, the thickness of the insulating material layer at the via P is not less than 0.8.

[0207] Step 22, forming a photoresist layer on the insulating material layer;

[0208] In step 23, the photoresist layer is exposed using a first mask plate, wherein the first mask plate includes a shielding area and a light-transmitting area; the shielding area corresponds to the first electrode portion 1041, and the light-transmitting area corresponds to the second electrode portion 1042; wherein the first mask plate is an ordinary mask plate, that is, a mask plate that does not have different transmittances.

[0209] Step 24, developing the photoresist layer so that the photoresist layer forms a reserved area and a removed area, wherein the reserved area corresponds to the first electrode portion 1041 and the removed area corresponds to the second electrode portion 1042;

[0210] Step 25, cleaning the photoresist in the removal area, and etching the insulating material layer in the removal area to form a second flat portion 1052 and a pixel opening 105a;

[0211] Step 25 , retaining the photoresist in the reserved area to form a first flat portion 1051 .

[0212] Among them, the first mask plate is an ordinary mask plate other than a halftone mask plate. In this embodiment, an ordinary mask plate is used to expose only the non-via area, that is, the area where the second electrode portion 1042 is located, so that only the non-via area is etched to obtain the second insulating layer 105.

[0213] In another example, forming the second insulating layer 105 on a side of the first electrode 104a away from the substrate 101 includes the following steps:

[0214] Step 31, forming a first insulating material layer on the side of the first electrode portion 1041 of the first electrode 104a away from the substrate 101, and the ratio of the dimension of the first insulating material layer on the first electrode portion 1041 along the thickness direction of the substrate 101 to the first distance L1 is not less than 0.8, so as to form a first flat portion 1051;

[0215] In step 32, a second insulating material layer is formed on the side of the second electrode portion 1042 of the first electrode 104a away from the substrate 101, and the size of the second insulating material layer on the second electrode portion 1042 along the thickness direction of the substrate 101 is smaller than the size of the first insulating material layer on the first electrode portion 1041 along the thickness direction of the substrate 101, so as to form a second flat portion 1052.

[0216] In this embodiment, the second insulating layer 105 is manufactured step by step by forming the first flat portion 1051 on the first electrode portion 1041 and then forming the second flat portion 1052 on the second electrode portion 1042 .

[0217] In another example, forming the second insulating layer 105 on a side of the first electrode 104a away from the substrate 101 includes the following steps:

[0218] Step 41, forming a first insulating material layer on a side of the first electrode portion 1041 of the first electrode 104a away from the substrate 101;

[0219] Step 42, forming a third insulating material layer (i.e., forming a whole insulating material layer) on a side of the first electrode portion 1041 away from the substrate 101 and a side of the second electrode portion 1042 away from the substrate 101 to form a first flat portion 1051 and a second flat portion 1052;

[0220] Step 43: etching a pixel opening 105 a on the third insulating material layer by patterning.

[0221] In one embodiment, the method further includes: forming an isolation structure 401 on a side of the second insulating layer 105 away from the substrate 101 , wherein the isolation structure 401 defines an isolation opening 401 a .

[0222] In one embodiment, the present application provides a display device, which includes the display panel described in any of the above display panel embodiments.

[0223] The display device can be a laptop computer, a mobile phone, a wireless device, a personal digital assistant (PDA), a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a camcorder, a game console, a watch, a clock, a calculator, a television monitor, a flat-panel display, a computer monitor, a car display (e.g., an odometer display, etc.), a navigator, a cockpit controller and / or display, a display of a camera view (e.g., a display of a rearview camera in a vehicle), an electronic photo, an electronic billboard or sign, a projector, etc.

[0224] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0225] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0226] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: include: substrate, A signal line is arranged on one side of the substrate; A first insulating layer is disposed on one side of the substrate, and a portion of the first insulating layer is located on a side of the signal line away from the substrate, a via hole is provided on the first insulating layer, and a portion of the signal line is exposed from the via hole; A first electrode is disposed on a side of the first insulating layer away from the substrate, and an orthographic projection of the first electrode on the first insulating layer covers the via hole, wherein the first electrode includes a first electrode portion connected to the signal line portion, and an orthographic projection of the first electrode portion on the first insulating layer covers a bottom wall of the via hole; A second insulating layer is disposed on a side of the first electrode away from the substrate, wherein an orthographic projection of the second insulating layer on the first insulating layer covers the via hole; The second insulating layer includes a first flat portion, the orthographic projection of the first flat portion on the substrate overlaps with the orthographic projection of the via on the substrate, the dimension of the first flat portion along the thickness direction of the substrate is a first dimension H1, the distance between a side surface of the first insulating layer close to the substrate and a side surface of the first insulating layer away from the substrate is a first distance L1, and the ratio of the first dimension H1 to the first distance L1 is not less than 0.

8.

2. The display panel according to claim 1, characterized in that: The ratio of the first size H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.2; Optionally, the first electrode further includes a second electrode portion, and an orthographic projection of the second electrode portion on the first insulating layer does not overlap with the via hole; the second insulating layer further includes a second flat portion disposed on a side of the second electrode portion of the first electrode away from the substrate; The dimension of the second flat portion along the thickness direction of the substrate is a second dimension H2, and the second dimension H2 is smaller than the first dimension H1; Optionally, the second size H2 is greater than or equal to 3000A and less than or equal to 5000A; Optionally, a distance between a side surface of the first flat portion away from the substrate and a side surface of the substrate close to the signal line is a second distance L2, a distance between a side surface of the second flat portion away from the substrate and a side surface of the substrate close to the signal line is a third distance L3, and a ratio of the second distance L2 to the third distance L3 is not less than 0.8; Optionally, a ratio of the second distance L2 to the third distance L3 is greater than or equal to 0.8 and less than or equal to 1.

2.

3. The display panel according to claim 1, characterized in that: The second insulating layer defines a pixel opening, and a portion of the first electrode is exposed from the pixel opening; Optionally, the display panel further comprises an isolation structure, wherein the isolation structure is disposed on a side of the second insulating layer away from the substrate, the orthographic projection of the isolation structure on the first insulating layer covers the via hole, and the isolation structure defines an isolation opening, and the isolation opening is connected to the pixel opening; Optionally, the surface of the isolation structure away from the substrate has no step difference; Optionally, the orthographic projection outer contour of the isolation opening on the substrate is located at the periphery of the orthographic projection outer contour of the pixel opening on the substrate; Optionally, the orthographic projection of the isolation structure on the substrate is in a grid shape; Optionally, the isolation structure comprises a first isolation portion and a second isolation portion stacked in a direction away from the substrate, and an orthographic projection of the second isolation portion on the substrate covers an orthographic projection of the first isolation portion on the substrate; Optionally, the first isolation portion comprises a conductive material; Optionally, the first isolation portion includes at least one metal layer; Optionally, the first isolation portion includes a first metal layer and a second metal layer stacked in a direction away from the substrate, and an orthographic projection outer contour of the first metal layer on the substrate is located outside an orthographic projection outer contour of the second metal layer on the substrate; Optionally, the material of the second isolation portion includes titanium or molybdenum; the material of the first metal layer includes molybdenum or titanium; and the material of the second metal layer includes aluminum or copper or silver.

4. The display panel according to claim 2, characterized in that: The second insulating layer further includes a third flat portion, and an orthographic projection of the third flat portion on the substrate does not overlap with an orthographic projection of the first electrode on the substrate; The dimension of the third flat portion along the thickness direction of the substrate is a third dimension H3, and the third dimension H3 is greater than the second dimension H2; Optionally, a distance between a side surface of the third flat portion away from the substrate and a side surface of the substrate close to the signal line is a fourth distance L4, and the fourth distance L4 is equal to the third distance L3; Optionally, a surface of the second insulating layer away from the substrate has no step difference.

5. The display panel according to claim 3, characterized in that: The display panel further includes a light-emitting functional layer and a second electrode; The light-emitting functional layer is arranged on a side of the first electrode away from the substrate and at the pixel opening; The second electrode is arranged on a side of the light-emitting functional layer away from the substrate; Optionally, the second electrode is electrically connected to the first isolation portion.

6. The display panel according to claim 5, characterized in that: The display panel further includes an encapsulation layer, and the encapsulation layer is disposed on a side of the second electrode away from the substrate.

7. The display panel according to claim 1, characterized in that: The side wall of the via hole is a plane or a curved surface.

8. A display panel, characterized in that: include: substrate, A signal line is arranged on one side of the substrate; A first insulating layer is disposed on one side of the substrate, and a portion of the first insulating layer is located on a side of the signal line away from the substrate, a via hole is provided on the first insulating layer, and a portion of the signal line is exposed from the via hole; A first electrode is disposed on a side of the first insulating layer away from the signal line, and an orthographic projection of the first electrode on the first insulating layer covers the via hole, wherein the first electrode includes a first electrode portion connected to a portion of the signal line, and an orthographic projection of the first electrode portion on the first insulating layer covers a bottom wall of the via hole; A pixel definition layer is disposed on a side of the first electrode away from the substrate, wherein an orthographic projection of the pixel definition layer on the first insulating layer covers the via hole, and the pixel definition layer defines a pixel opening, and a portion of the first electrode is exposed from the pixel opening; An isolation structure is arranged on a side of the pixel definition layer away from the substrate, the orthographic projection of the isolation structure on the first insulating layer covers the via hole, and the isolation structure defines an isolation opening, and the isolation opening is connected to the pixel opening; wherein the pixel definition layer includes a first flat portion and a second flat portion in contact with the first electrode portion of the first electrode, the orthographic projection of the second flat portion on the substrate does not overlap with the orthographic projection of the first electrode portion on the substrate, and the size of the first flat portion along the thickness direction of the substrate is larger than the size of the second flat portion along the thickness direction of the substrate.

9. The display panel according to claim 8, characterized in that: The dimension of the first flat portion along the thickness direction of the substrate is a first dimension H1, the distance between a side surface of the first insulating layer close to the substrate and a side surface of the first insulating layer away from the substrate is a first distance L1, and the ratio of the first dimension H1 to the first distance L1 is not less than 0.8; Optionally, a ratio of the first size H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.2; Optionally, the first electrode further includes a second electrode portion, an orthographic projection of the second electrode portion on the first insulating layer does not overlap with the via hole; the second flat portion contacts the second electrode portion of the first electrode; The dimension of the second flat portion along the thickness direction of the substrate is a second dimension H2, and the second dimension H2 is greater than or equal to 3000A and less than or equal to 5000A; Optionally, a distance between a side surface of the first flat portion away from the substrate and a side surface of the substrate close to the signal line is a second distance L2, a distance between a side surface of the second flat portion away from the substrate and a side surface of the substrate close to the signal line is a third distance L3, and a ratio of the second distance L2 to the third distance L3 is not less than 0.8; Optionally, a ratio of the second distance L2 to the third distance L3 is greater than or equal to 0.8 and less than or equal to 1.

2.

10. The display panel according to claim 8, characterized in that: The surface of the isolation structure away from the substrate has no step difference; Optionally, the orthographic projection outer contour of the isolation opening on the substrate is located at the periphery of the orthographic projection outer contour of the pixel opening on the substrate; Optionally, the orthographic projection of the isolation structure on the substrate is in a grid shape; Optionally, the isolation structure comprises a first isolation portion and a second isolation portion stacked in a direction away from the substrate, and an orthographic projection of the second isolation portion on the substrate covers an orthographic projection of the first isolation portion on the substrate; Optionally, the first isolation portion comprises a conductive material; Optionally, the first isolation portion includes at least one metal layer; Optionally, the first isolation portion includes a first metal layer and a second metal layer stacked in a direction away from the substrate, and an orthographic projection outer contour of the first metal layer on the substrate is located outside an orthographic projection outer contour of the second metal layer on the substrate; Optionally, the material of the second isolation portion includes titanium or molybdenum; the material of the first metal layer includes molybdenum or titanium; and the material of the second metal layer includes aluminum or copper or silver.

11. The display panel according to claim 9, characterized in that: The pixel definition layer further includes a third flat portion, the orthographic projection of the third flat portion on the substrate does not overlap with the orthographic projection of the first electrode on the substrate; The dimension of the third flat portion along the thickness direction of the substrate is a third dimension H3, and the third dimension H3 is greater than the second dimension H2; Optionally, a distance between a side surface of the third flat portion away from the substrate and a side surface of the substrate close to the signal line is a fourth distance L4, and the fourth distance L4 is equal to the third distance L3; Optionally, a surface of the second insulating layer away from the substrate has no step difference.

12. The display panel according to claim 10, characterized in that: The display panel further includes a light-emitting functional layer and a second electrode; The light-emitting functional layer is arranged on a side of the first electrode away from the substrate and at the pixel opening; The second electrode is arranged on a side of the light-emitting functional layer away from the substrate; Optionally, the second electrode is electrically connected to the first isolation portion.

13. The display panel according to claim 12, characterized in that: The display panel further includes an encapsulation layer, and the encapsulation layer is disposed on a side of the second electrode away from the substrate.

14. A display panel, characterized in that: include: substrate, A signal line is arranged on one side of the substrate; A first insulating layer is disposed on one side of the substrate, and a portion of the first insulating layer is located on a side of the signal line away from the substrate, a via hole is provided on the first insulating layer, and a portion of the signal line is exposed from the via hole; A first electrode is disposed on a side of the first insulating layer away from the substrate, an orthographic projection of the first electrode on the first insulating layer covers the via hole, wherein the first electrode comprises a first electrode portion and a second electrode portion connected to the signal line portion, an orthographic projection of the first electrode portion on the first insulating layer covers a bottom wall of the via hole, and an orthographic projection of the second electrode portion on the first insulating layer does not overlap with the via hole; A second insulating layer is disposed on a side of the first electrode away from the substrate, wherein an orthographic projection of the second insulating layer on the first insulating layer covers the via hole; In which, the second insulating layer includes a first flat portion and a second flat portion which are respectively in contact with the first electrode portion and the second electrode portion of the first electrode; a distance between a surface of the first flat portion away from a side of the substrate and a surface of the substrate close to the signal line is a second distance L2, a distance between a surface of the second flat portion away from a side of the substrate and a surface of the substrate close to the signal line is a third distance L3, and a ratio of the second distance L2 to the third distance L3 is not less than 0.

8.

15. The display panel according to claim 14, characterized in that: The ratio of the second distance L2 to the third distance L3 is greater than or equal to 0.8 and less than or equal to 1.2; Optionally, a dimension of the first flat portion along a thickness direction of the substrate is a first dimension H1, a distance between a surface of a side of the first insulating layer close to the substrate and a surface of a side of the first insulating layer away from the substrate is a first distance L1, and a ratio of the first dimension H1 to the first distance L1 is not less than 0.8; Optionally, a ratio of the first size H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.2; Optionally, a dimension of the second flat portion along a thickness direction of the substrate is a second dimension H2, and the second dimension H2 is smaller than the first dimension H1; Optionally, the second size H2 is greater than or equal to 3000A and less than or equal to 5000A.

16. A method for preparing a display panel, characterized in that: The method comprises: providing a substrate; forming a signal line on one side of the substrate; A first insulating layer is formed on one side of the substrate, and a portion of the first insulating layer is located on a side of the signal line away from the substrate, a via hole is formed on the first insulating layer, and a portion of the signal line is exposed from the via hole; forming a first electrode on a side of the first insulating layer away from the substrate, wherein an orthographic projection of the first electrode on the first insulating layer covers the via hole, the first electrode comprises a first electrode portion connected to the signal line portion, and an orthographic projection of the first electrode portion on the first insulating layer covers a bottom wall of the via hole; forming a second insulating layer on a side of the first electrode away from the substrate, wherein an orthographic projection of the second insulating layer on the first insulating layer covers the via hole; The second insulating layer includes a first flat portion, the orthographic projection of the first flat portion on the substrate overlaps with the orthographic projection of the via on the substrate, the dimension of the first flat portion along the thickness direction of the substrate is a first dimension H1, the distance between a side surface of the first insulating layer close to the substrate and a side surface of the first insulating layer away from the substrate is a first distance L1, and the ratio of the first dimension H1 to the first distance L1 is not less than 0.

8.

17. The preparation method according to claim 16, characterized in that: The ratio of the first size H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.2; Optionally, the first electrode further includes a second electrode portion, and an orthographic projection of the second electrode portion on the first insulating layer does not overlap with the via hole; the second insulating layer further includes a second flat portion disposed on a side of the second electrode portion of the first electrode away from the substrate; The dimension of the second flat portion along the thickness direction of the substrate is a second dimension H2, and the second dimension H2 is smaller than the first dimension H1; Optionally, the second size H2 is greater than or equal to 3000A and less than or equal to 5000A; Optionally, a distance between a side surface of the first flat portion away from the substrate and a side surface of the substrate close to the signal line is a second distance L2, a distance between a side surface of the second flat portion away from the substrate and a side surface of the substrate close to the signal line is a third distance L3, and a ratio of the second distance L2 to the third distance L3 is not less than 0.8; Optionally, a ratio of the second distance L2 to the third distance L3 is greater than or equal to 0.8 and less than or equal to 1.

2.

18. The preparation method according to claim 17, characterized in that: The second insulating layer is formed on a side of the first electrode away from the substrate, comprising: forming an insulating material layer on a side of the first electrode away from the substrate; and forming a photoresist layer on the insulating material layer; The photoresist layer is exposed using a half-tone mask, wherein the half-tone mask comprises a first area, a second area and a third area; the transmittance of the first area is less than the transmittance of the second area; the transmittance of the second area is less than the transmittance of the third area; Performing a development process on the photoresist layer so that the photoresist layer forms a first partial removal area, a second partial removal area and a complete removal area, wherein the first partial removal area corresponds to the first area, the second partial removal area corresponds to the second area, and the complete removal area corresponds to the third area; Removing the photoresist in the completely removed area, removing part of the photoresist in the first partially removed area, and removing part of the photoresist in the second partially removed area, wherein the thickness of the remaining photoresist in the first partially removed area is greater than the thickness of the remaining photoresist in the second partially removed area; Etching the insulating material layer exposed in the completely removed area to form a pixel opening; Removing part of the remaining photoresist in the first partial removal area, and retaining the insulating material covered by the photoresist in the first partial removal area to form the first flat portion; The photoresist in the second partial removal area is removed by etching, and the insulating material layer in the second partial removal area is further etched to form the second flat portion.

19. The preparation method according to claim 17, characterized in that: The second insulating layer is formed on a side of the first electrode away from the substrate, comprising: forming an insulating material layer on a side of the first electrode away from the substrate, and a ratio of a dimension of the insulating material layer on the first electrode portion of the first electrode along a thickness direction of the substrate to the first distance L1 is not less than 0.8; forming a photoresist layer on the insulating material layer; Expose the photoresist layer using a first mask, wherein the first mask comprises a shielding area and a light-transmitting area; the shielding area corresponds to the first electrode portion, and the light-transmitting area corresponds to the second electrode portion; Performing a development process on the photoresist layer so that the photoresist layer forms a reserved area and a removed area, wherein the reserved area corresponds to the first electrode portion, and the removed area corresponds to the second electrode portion; removing the photoresist in the removal area, and etching the insulating material layer in the removal area to form the second flat portion and a pixel opening; The photoresist in the reserved area is retained to form the first flat portion.

20. The preparation method according to claim 17, characterized in that: The second insulating layer is formed on a side of the first electrode away from the substrate, comprising: forming a first insulating material layer on a side of the first electrode portion of the first electrode away from the substrate, wherein a ratio of a dimension of the first insulating material layer on the first electrode portion along a thickness direction of the substrate to the first distance L1 is not less than 0.8, so as to form the first flat portion; A second insulating material layer is formed on the side of the second electrode portion of the first electrode away from the substrate, and a dimension of the second insulating material layer on the second electrode portion along the thickness direction of the substrate is smaller than a dimension of the first insulating material layer on the first electrode portion along the thickness direction of the substrate to form the second flat portion.

21. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 15.

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