Display mother board, preparation method of display panel and display device

Abstract

The embodiment of the invention provides a display mother board, a preparation method of a display panel and a display device.The display mother board is provided with a removal area and a panel area; the display panel further comprises a substrate. In the removal area, the display mother board further comprises a first isolation structure located on one side of the substrate and a plurality of virtual pixels, and each virtual pixel comprises a light-emitting function layer and a second electrode which are sequentially arranged in a stacked mode in the direction away from the substrate. In the panel area, the display mother board further comprises a second isolation structure and a plurality of display pixels, the second isolation structure, the first isolation structure and the virtual pixels are located on the same side of the substrate, and each display pixel comprises a first electrode, a light-emitting function layer and a second electrode which are sequentially arranged in a stacked mode in the direction away from the substrate. According to the embodiment of the invention, the etching uniformity is effectively improved, so that the processing performance of the display mother board is improved.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of display technology, and in particular, to a display motherboard, a display panel preparation method, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the process performance of current OLED display products needs to be improved. Summary of the invention

[0004] In view of this, embodiments of the present application provide a display motherboard, a method for manufacturing a display panel, and a display device to at least partially solve the above problems.

[0005] According to a first aspect of an embodiment of the present application, a display motherboard is provided, comprising a removal area and a panel area; comprising:

[0006] substrate;

[0007] In the removal area, the display motherboard further includes a first isolation structure and a plurality of virtual pixels located on one side of the substrate, wherein the first isolation structure encloses a plurality of first isolation openings, the plurality of virtual pixels are respectively at least partially located in the corresponding first isolation openings, and the virtual pixels include a light-emitting functional layer and a second electrode sequentially stacked in a direction away from the substrate;

[0008] In the panel area, the display motherboard also includes a second isolation structure and a plurality of display pixels located on the same side of the substrate as the first isolation structure and the plurality of virtual pixels, wherein the second isolation structure encloses a plurality of second isolation openings, and the plurality of display pixels are respectively at least partially located in the corresponding second isolation openings, and the display pixels include a first electrode, a light-emitting functional layer, and a second electrode which are sequentially stacked in a direction away from the substrate.

[0009] In an optional embodiment, in the removal area, the first isolation structure is a mesh structure, and the closed grids of the mesh structure form the first isolation openings.

[0010] In an optional embodiment, in the removal area and the panel area, the substrate further comprises: a planarization layer;

[0011] In the removal area, the planarization layer is located on a side of the substrate close to the first isolation structure, and the planarization layer is in contact with the light-emitting function layer in the virtual pixel;

[0012] In the panel region, the planarization layer contacts the first electrode in the display pixel.

[0013] In an optional embodiment, the removal area and the panel area further include: a pixel defining layer, the pixel defining layer is located on a side of the planarization layer away from the substrate, the pixel defining layer includes a plurality of pixel defining portions;

[0014] In the removal area, the pixel defining portion encloses a virtual pixel opening, the orthographic projection of the virtual pixel opening on the substrate is located within the orthographic projection of the first isolation opening on the substrate, and the planarization layer contacts the light-emitting function layer in the virtual pixel through the virtual pixel opening;

[0015] In the panel area, the pixel defining portion is located between the first electrode and the second electrode, the pixel defining portion encloses a display pixel opening, the orthographic projection of the display pixel opening on the substrate is located within the orthographic projection of the second isolation opening on the substrate, the display pixel opening exposes a portion of the first electrode, and the first electrode in the display pixel contacts the light-emitting function layer through the display pixel opening;

[0016] The first isolation structure and the second isolation structure are disposed on a side of the pixel defining portion away from the substrate.

[0017] In an optional embodiment, the shape of the display pixel opening is gradually increased in a direction away from the substrate;

[0018] Preferably, the shape of the virtual pixel opening is the same as the shape of the display pixel opening.

[0019] In an optional embodiment, in the panel area, the second isolation structure includes a first sub-isolation structure and a second sub-isolation structure which are sequentially stacked in a direction close to the substrate;

[0020] The orthographic projection of the second sub-isolation structure on the substrate is inside the orthographic projection of the first sub-isolation structure on the substrate.

[0021] In an optional embodiment, the material of the first sub-isolation structure includes titanium, and / or the material of the second sub-isolation structure includes aluminum.

[0022] In an optional embodiment, the second isolation structure further includes a third sub-isolation structure;

[0023] The third sub-isolation structure is disposed on a side of the second sub-isolation structure close to the substrate;

[0024] The orthographic projection of the second sub-isolation structure on the substrate is inside the orthographic projection of the third sub-isolation structure on the substrate;

[0025] Preferably, the orthographic projection of the third sub-isolation structure on the substrate is inside the orthographic projection of the first sub-isolation structure on the substrate;

[0026] Preferably, the material of the third sub-isolation structure includes molybdenum.

[0027] In an optional embodiment, the second isolation structure includes a conductive material, and the second electrode in the display pixel is electrically connected to the second isolation structure;

[0028] Preferably, the first isolation structure has the same structure as the second isolation structure.

[0029] In an optional embodiment, in the removal area and the panel area, the display motherboard further includes a first encapsulation layer, and the first encapsulation layer includes a plurality of encapsulation parts;

[0030] In the removal area, the encapsulation portion is disposed on a side of the dummy pixel away from the substrate;

[0031] In the panel area, the packaging portion is disposed on a side of the display pixel away from the substrate;

[0032] Preferably, the material of the first encapsulation layer includes an inorganic material.

[0033] In an optional embodiment, in the removal area, the encapsulation portion extends to a side of the first isolation structure away from the substrate, and a partial structure of the encapsulation portion is located below the first sub-isolation structure of the first isolation structure; the virtual pixel is encapsulated in the first isolation opening by the encapsulation portion;

[0034] In the panel area, the encapsulation part extends to a side of the second isolation structure away from the substrate, and a partial structure of the encapsulation part is located below the first sub-isolation structure of the second isolation structure; the display pixel is encapsulated in the second isolation opening by the encapsulation part.

[0035] In an optional embodiment, in the panel area, the display motherboard further includes a second encapsulation layer and a third encapsulation layer;

[0036] The second encapsulation layer is located on a side of the first encapsulation layer away from the substrate;

[0037] The third encapsulation layer is located on a side of the second encapsulation layer away from the substrate;

[0038] Preferably, the material of the second encapsulation layer includes an organic material, and the material of the third encapsulation layer includes an inorganic material.

[0039] According to a second aspect of an embodiment of the present application, a method for preparing a display panel is provided, comprising:

[0040] Providing a substrate, the substrate comprising a removal area and a panel area;

[0041] forming a first electrode in the panel region;

[0042] After forming the first electrode, a first isolation structure is formed on the substrate in the removal area, and a second isolation structure is formed on the substrate in the panel area; wherein the first isolation structure encloses a first isolation opening, and the second isolation structure encloses a second isolation opening,

[0043] In the first isolation opening and the second isolation opening, a light-emitting functional layer and a second electrode are sequentially formed in a direction away from the substrate; the display pixel is at least partially located in the corresponding second isolation opening, and the display pixel includes the first electrode, the light-emitting functional layer and the second electrode; the virtual pixel is at least partially located in the corresponding first isolation opening, and the virtual pixel includes the light-emitting functional layer and the second electrode;

[0044] The removal area structure is removed by cutting.

[0045] In an optional embodiment, the substrate includes a planarization layer; the planarization layer is located on a side of the first electrode close to the substrate;

[0046] In the removal area, the planarization layer contacts the light-emitting function layer in the dummy pixel; in the panel area, the planarization layer contacts the first electrode in the display pixel.

[0047] In an optional embodiment, before forming the first isolation structure on the substrate in the removal area and forming the second isolation structure on the substrate in the panel area, the method further includes:

[0048] forming a pixel defining layer on a side of the planarization layer away from the substrate, wherein the pixel defining layer includes a plurality of pixel defining portions;

[0049] In the removal area, the pixel defining portion encloses a virtual pixel opening, and in the panel area, the pixel defining portion is located between the first electrode and the second electrode, the pixel defining portion encloses a display pixel opening, and the virtual pixel opening is formed simultaneously with the display pixel opening.

[0050] In an optional embodiment, the method further includes: forming a first encapsulation layer in the removal area and the panel area, the first encapsulation layer including a plurality of encapsulation parts;

[0051] In the removal area, the encapsulation part is arranged on a side of the virtual pixel away from the substrate; in the panel area, the encapsulation part is arranged on a side of the display pixel away from the substrate; the encapsulation part in the removal area and the encapsulation part in the panel area are formed simultaneously;

[0052] Preferably, the material of the first encapsulation layer includes an inorganic material.

[0053] In an optional embodiment, the shape of the display pixel opening is gradually increased in a direction away from the substrate;

[0054] Preferably, the shape of the virtual pixel opening is the same as the shape of the display pixel opening.

[0055] According to a third aspect of an embodiment of the present application, a display device is provided, comprising: a display panel prepared using the display motherboard as described in any one of the first aspects or prepared using the method as described in the second aspect.

[0056] According to the solution provided in the embodiment of the present application, while each film layer in the panel area is patterned accordingly, the corresponding film layer in the removal area is also patterned. During the etching process, the local etching rate changes caused by the uneven feature size or pattern density of the surface of the etched pattern are reduced, thereby reducing the phenomenon of uneven etching of the panel area, thereby improving the process performance of the display motherboard. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0058] Figure 1 A schematic diagram of dividing a panel area in a display motherboard;

[0059] Figure 2 A schematic diagram of dividing a display motherboard according to an embodiment of the present application;

[0060] Figure 2a for Figure 2 The partial cross-sectional schematic diagram of the film structure of the motherboard in the area framed by the dotted line is shown in FIG.

[0061] Figure 2b for Figure 2A partial cross-sectional schematic diagram of another film layer structure in the area of ​​the motherboard framed by a dotted line is shown in FIG.

[0062] Figure 3 for Figure 2a A partial cross-sectional schematic diagram of the membrane structure in the removal area not framed by the dotted line is enlarged;

[0063] Figure 4 for Figure 2a A partial cross-sectional schematic diagram of the membrane structure of the panel area framed by a dotted line is enlarged;

[0064] Figure 5 for Figure 2b An enlarged schematic diagram of a partial cross-section of another film structure in a removal area not framed by a dotted line;

[0065] Figure 6 for Figure 2b A partial cross-sectional schematic enlarged view of another membrane layer structure in the panel area framed by a dotted line;

[0066] Figure 7 is a flowchart of a method for preparing a display panel according to an embodiment of the present application;

[0067] Figure 8 It is a partial cross-sectional schematic diagram of a film layer structure during a preparation method of a display panel according to an embodiment of the present application. DETAILED DESCRIPTION

[0068] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the embodiments of the present application should fall within the scope of protection of the embodiments of the present application.

[0069] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in the embodiments of the present application refers to and includes any or all possible combinations of one or more associated listed items.

[0070] It should be understood that in the description of the embodiments of the present application, the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the schemes of the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0071] In addition, when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0072] The terms first, second, etc. are used to describe various elements, components, regions, layers and / or parts, but these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer and / or part from another element, component, region, layer and / or part.

[0073] Unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0074] The specific implementation of the embodiment of the present application is further explained below in conjunction with the accompanying drawings of the embodiment of the present application.

[0075] The corresponding structural parts mentioned below, such as the isolation structure (or isolation column or partition structure), are described in patents CN118251982A, 202410864269.8, PCT / CN2024 / 098407, PCT / CN2024 / 102783, PCT / CN2024 / 098217, PCT / CN2024 / 099419, PCT / CN2024 / 099072, CN117979755A, CN117998900A, CN117062489A, CN117580403A, CN116583155A, CN116669477A, ​​CN117396039A, CN116669480A, CN116600606A, and CN117500332A are further described for reference.

[0076] Etching loading refers to the phenomenon that the etching rate changes during the etching process due to changes in the characteristic size and pattern density of the etched surface. Due to the change in etching rate, the etching depth of different areas may be inconsistent, which in turn affects the structure and performance of the device. For example, the following problems exist in the related art: Figure 1 A schematic diagram showing the division of a panel area in a display motherboard in the prior art is shown. Figure 1 As shown, a display motherboard is divided into a plurality of panel areas 201. During the patterning process, due to the large etching load of some film layers in the panel area 201, the etching uniformity is poor, and the reliability of the produced display product is low.

[0077] Based on this, the technical solution of the first aspect of the embodiment of the present application provides a display motherboard, such as Figure 2 As shown, in the display motherboard of this embodiment, a substrate 10 is included. The substrate 10 can be implemented as a TFT (Thin Film Transistor) array substrate. The array substrate includes a plurality of TFTs. Each TFT includes an active layer, a gate insulating film, a gate electrode, and other parts. The display motherboard has a removal area 203 and a panel area 201. In a feasible manner, as shown in FIG. Figure 2 As shown, the display motherboard may include a plurality of panel areas 201 . Figure 2 The area 202 outlined by the middle dashed line includes both the partially removed area 203 and part of the panel area 201. Figure 2a and Figure 2b Shows Figure 2 The dotted line framed area 202 is a partial cross-sectional view of the two film layer structures. Figure 2a and Figure 2b In the figure, the panel area 201 is framed by dotted lines, and the removal area 203 is not framed by dotted lines.

[0078] Alternatively, if Figure 3 and Figure 4 As shown, the substrate 10 of this embodiment includes a planarization layer 20, which is used to provide a planarized surface to reduce surface roughness, thereby facilitating subsequent formation of various film layers. In a feasible manner, the planarization layer 20 includes an organic material or an inorganic material.

[0079] Alternatively, if Figure 3 and Figure 4 As shown, the display motherboard of this embodiment also includes a pixel defining layer located on the side of the planarization layer 20 away from the substrate 10, and the pixel defining layer includes a plurality of pixel defining portions 31; in the removal area 203, the pixel defining portions 31 enclose a virtual pixel opening 311, and in the panel area 201, the pixel defining portions 31 enclose a display pixel opening 312. The virtual pixel opening 311 and the display pixel opening 312 are formed simultaneously, thereby reducing the change in the local etching rate due to the uneven feature size or pattern density of the surface of the etched pattern during the etching process, thereby reducing the phenomenon of uneven etching of the panel area 201, thereby improving the process performance of the display motherboard. In a feasible manner, the shape of the display pixel opening 312 is gradually increased in the direction away from the substrate 10, and is used to carry the display pixel 52.

[0080] Alternatively, if Figure 3 As shown, in the removal area 203, the display motherboard of this embodiment further includes a first isolation structure 41 and a plurality of virtual pixels 51 located on one side of the substrate 10. The first isolation structure 41 encloses and forms a plurality of first isolation openings 410, and the first isolation openings 410 are used to accommodate a plurality of virtual pixels 51, each virtual pixel 51 is at least partially located in the corresponding first isolation opening 410, and each virtual pixel 51 is separated by the first isolation structure 41. In a feasible manner, the first isolation structure 41 is a mesh structure, and the closed grid of the mesh structure of the first isolation structure 41 forms the first isolation opening 410, thereby, the virtual pixel 51 is enclosed and closed by the first isolation opening 410, thereby reducing the risk of peeling of each film layer in the virtual pixel 51, avoiding display defects and performance impairment caused by the peeling of the film layer during the preparation process of the display motherboard, and improving the yield rate of the display motherboard. In a feasible manner, the orthographic projection of the first isolation opening 410 on the substrate 10 covers the orthographic projection of the virtual pixel opening 311 on the substrate 10, and the first isolation structure 41 is located on the side of the pixel defining portion 31 away from the substrate 10.

[0081] Alternatively, if Figure 3As shown, in the removal area 203, the virtual pixel 51 includes a light-emitting functional layer 70 and a second electrode 80 which are stacked in sequence in a direction away from the substrate 10. Among them, the planarization layer 20 located on the side of the substrate 10 close to the first isolation structure 41 contacts the light-emitting functional layer 70 in the virtual pixel 51 through the virtual pixel opening 311. In a feasible manner, the light-emitting functional layer 70 includes an EL (Electro-Luminescence, electroluminescent material) material. Thus, the planarization layer 20 contacts the light-emitting functional layer 70, and both contain organic materials, so that the adhesion between the planarization layer 20 and the light-emitting functional layer 70 is stronger, reducing the risk of film peeling due to water vapor intrusion, etc., avoiding display defects and performance impairment caused by film peeling during the preparation of the display motherboard, and enhancing the reliability of the display motherboard.

[0082] Alternatively, if Figure 4 As shown, in the panel area 201, the display motherboard of this embodiment further includes a second isolation structure 42 and a plurality of display pixels 52 located on the same side of the substrate 10 as the first isolation structure 41 and the plurality of virtual pixels 51. The second isolation structure 42 encloses a plurality of second isolation openings 420, and the second isolation openings 420 are used to accommodate a plurality of display pixels 52, each display pixel 52 is at least partially located in the corresponding second isolation opening 420, and each display pixel 52 is separated by the second isolation structure 42. The orthographic projection of the second isolation opening 420 on the substrate 10 covers the orthographic projection of the display pixel opening 312 on the substrate 10. In a feasible manner, the second isolation structure 42 is located on the side of the pixel defining portion 31 away from the substrate 10.

[0083] Alternatively, if Figure 4 As shown, the display pixel 52 includes a first electrode 60, a light-emitting functional layer 70, and a second electrode 80 which are sequentially stacked in a direction away from the substrate 10. In the panel area 201, the planarization layer 20 is located on the side of the substrate 10 close to the second isolation structure 42, and the side of the first electrode 60 close to the substrate 10 is in contact with the planarization layer 20. The display pixel opening 312 exposes a portion of the first electrode 60, and the side of the first electrode 60 away from the substrate 10 is exposed through the display pixel opening 312. The portion is in contact with the light-emitting functional layer 70 in the display pixel 52, and is used to drive the light-emitting functional layer 70 to emit light in combination with the second electrode 80. Among them, the pixel defining portion 31 is located between the first electrode 60 and the second electrode 80.

[0084] In one feasible manner, the second isolation structure 42 includes a conductive material, and the second electrode 80 in the display pixel 52 is electrically connected to the second isolation structure 42, and an electrical signal is transmitted to the display pixel 52 through the second isolation structure 42. In one feasible manner, the second electrode 80 is implemented as a cathode, and the first electrode 60 is implemented as an anode. The first electrode 60 and the second electrode 80 cooperate to drive the light-emitting function layer 70 to realize the light-emitting function of the display pixel 52.

[0085] like Figure 4 As shown, in the panel area 201, the second isolation structure 42 includes a first sub-isolation structure 421 and a second sub-isolation structure 422 which are sequentially stacked in a direction close to the substrate 10. In one feasible manner, the orthographic projection of the second sub-isolation structure 422 on the substrate 10 is located inside the orthographic projection of the first sub-isolation structure 421 on the substrate 10, and at least a portion of the second isolation opening 420 is shielded and protected by the first sub-isolation structure 421. The materials of the first sub-isolation structure 421 and the second sub-isolation structure 422 are implemented to include metal materials. In one feasible manner, the material of the first sub-isolation structure 421 includes titanium (Ti), and / or the material of the second sub-isolation structure 422 includes aluminum (Al). Due to the hardness and chemical stability of Ti metal, at least a portion of the second isolation opening 420 is shielded and protected during the preparation of the display motherboard. The electrical signal is carried and transmitted by Al metal. In one feasible manner, as Figure 6 As shown, the second isolation structure 42 further includes a third sub-isolation structure 423, wherein the third sub-isolation structure 423 is disposed on a side of the second sub-isolation structure 422 close to the substrate 10, and the orthographic projection of the second sub-isolation structure 422 on the substrate 10 is located inside the orthographic projection of the third sub-isolation structure 423 on the substrate 10. In a feasible manner, the orthographic projection of the third sub-isolation structure 423 on the substrate 10 is located inside the orthographic projection of the first sub-isolation structure 421 on the substrate 10. In a feasible manner, the material of the third sub-isolation structure 423 includes molybdenum (Mo), which can improve the stability between the second sub-isolation structure 422 and the pixel defining portion 31, and prevent the elements in the second sub-isolation structure 422 from diffusing into the pixel defining portion 31, thereby extending the service life of the display motherboard.

[0086] Alternatively, if Figure 3 and Figure 4As shown, the display motherboard of this embodiment further includes a first encapsulation layer 100, and the first encapsulation layer 100 includes a plurality of encapsulation parts 101. In the removal area 203, the encapsulation part 101 is arranged on the side of the virtual pixel 51 away from the substrate 10, and extends to the side of the first isolation structure 41 away from the substrate 10, thereby, the encapsulation part 101 cooperates with the mesh structure of the first isolation structure 41 to enclose and seal the virtual pixel 51 in the first isolation opening 410, thereby preventing the invasion of water vapor, oxygen, etc., reducing the risk of peeling of each film layer in the virtual pixel 51, preventing the impact on each film layer in the panel area 201, and avoiding display defects and performance defects caused by the peeling of the film layer during the preparation process of the display motherboard. In the panel area 201, the encapsulation part 101 is arranged on the side of the display pixel 52 away from the substrate 10, and extends to the side of the second isolation structure 42 away from the substrate 10, and part of the structure of the encapsulation part 101 is located below the first sub-isolation structure 421 of the second isolation structure 42, thereby, the display pixel 52 is encapsulated in the second isolation opening 420 by the encapsulation part 101, which can prevent the invasion of water vapor, oxygen, etc., reduce the risk of peeling of each film layer in the display pixel 52, and improve the reliability of the display motherboard. Among them, the encapsulation part 101 in the removal area 203 is formed at the same time as the encapsulation part 101 in the panel area 201. In a feasible manner, the encapsulation part 101 extends to the side of the first sub-isolation structure 421 in the second isolation structure 42 away from the substrate 10. In a feasible manner, the material of the first encapsulation layer 100 includes an inorganic material.

[0087] In one possible approach, Figure 4 and Figure 6 As shown, in the panel area 201, the display motherboard of the embodiment of the present application further includes a second encapsulation layer 110 and a third encapsulation layer 120. The second encapsulation layer 110 is located on the side of the first encapsulation layer 100 away from the substrate 10; the third encapsulation layer 120 is located on the side of the second encapsulation layer 110 away from the substrate 10. In a feasible manner, the material of the second encapsulation layer 110 includes an organic material, and the material of the third encapsulation layer 120 includes an inorganic material.

[0088] In one possible approach, Figure 2a and Figure 2b As shown, in the removal area 203, the display motherboard of the embodiment of the present application further includes a second encapsulation layer 110 and a third encapsulation layer 120. The second encapsulation layer 110 is located on the side of the first encapsulation layer 100 away from the substrate 10; the third encapsulation layer 120 is located on the side of the second encapsulation layer 110 away from the substrate 10. In a feasible manner, the material of the second encapsulation layer 110 includes an organic material, and the material of the third encapsulation layer 120 includes an inorganic material. Through the second encapsulation layer 110 and the third encapsulation layer 120, the encapsulation performance of the display motherboard is enhanced, and the reliability of the display motherboard is improved.

[0089] In the display motherboard of this embodiment, the shape of the virtual pixel opening 311 can be the same as the shape of the display pixel opening 312, or can be designed to be different from the shape of the display pixel opening 312. Figure 3 and Figure 4 As shown, in a feasible manner, the shape of the virtual pixel opening 311 is the same as the shape of the display pixel opening 312. Thus, during the etching process, the change in local etching rate due to uneven feature size or pattern density on the surface of the etched pattern is reduced, thereby reducing the uneven etching of the panel area 201, thereby improving the process performance of the display motherboard.

[0090] In the display motherboard of this embodiment, the structure of the first isolation structure 41 may be the same as that of the second isolation structure 42, that is, the first isolation structure 41 may include a first sub-isolation structure 421 and a second sub-isolation structure 422. Alternatively, the structure of the first isolation structure 41 may be different from the structural design of the second isolation structure 42. In one feasible manner, in the removal area 203, the encapsulation portion 101 is disposed on a side of the virtual pixel 51 away from the substrate 10, and extends to a side of the first isolation structure 41 away from the substrate 10, and a portion of the structure of the encapsulation portion 101 is located below the first sub-isolation structure 421 of the first isolation structure 41. Figure 3 and Figure 4 As shown, in a feasible manner, the structure of the first isolation structure 41 is the same as the structure of the second isolation structure 42, such as Figure 5 As shown, in a feasible manner, the structure of the first isolation structure 41 includes a third sub-isolation structure 423. Thus, during the etching process, the phenomenon of uneven etching of the panel area 201 caused by changes in the local etching rate due to uneven feature size or pattern density on the surface of the etched pattern is reduced, thereby improving the process performance of the display motherboard.

[0091] In the display motherboard of the present embodiment, the corresponding film layers of the removal area 203 and the panel area 201 are formed by patterning. When the film layers of the display motherboard are patterned, for the film layer with the smallest area, the area of ​​the etched and removed portion occupies less than 25% of the area of ​​the substrate 10. In this case, the proportion of the pattern to be etched to the area of ​​the substrate 10 increases, achieving the effect of reducing etching loading and improving etching uniformity. In the actual production process, the film layer with the smallest area selected may be different according to different designs.

[0092] Therefore, in the display motherboard of the present embodiment, while each film layer in the panel area 201 is patterned accordingly, the corresponding film layer in the removal area 203 is also patterned. During the etching process, the uneven etching of the panel area 201 caused by changes in the local etching rate due to the uneven feature size or pattern density on the surface of the etched pattern is reduced, thereby improving the process performance of the display motherboard. At the same time, the display pixels 52 in the removal area 203 are in direct contact with the planarization layer 20, and the organic materials contained in the two make the display pixels 52 more adhesive to the planarization layer 20, reducing the risk of film peeling; and the mesh structure of the first isolation structure 41 encloses the virtual pixels 51 in the first isolation opening 410, and combines with the packaging part 101 to enclose and seal the virtual pixels 51, thereby preventing the invasion of water vapor, oxygen, etc., reducing the risk of peeling of each film layer in the virtual pixel 51, preventing the impact on each film layer in the panel area 201, avoiding display defects, performance damage and other problems caused by film peeling during the preparation process of the display motherboard, and improving the reliability of the display motherboard.

[0093] See also Figure 7 As shown, further optionally, a second aspect of the embodiment of the present application further provides a method for preparing a display panel, comprising the following steps:

[0094] S102. Provide a substrate, the substrate comprising a removal area and a panel area. S104. Form a first electrode in the panel area.

[0095] The local cross-sectional view of the formed film structure is shown in Figure 8 As shown in (a), the dotted line frame is the panel area, and the area not framed by the dotted line is the removal area.

[0096] S106. After forming the first electrode, forming a first isolation structure on the substrate in the removal area, and forming a second isolation structure on the substrate in the panel area;

[0097] The first isolation structure and the second isolation structure are located on the same side of the substrate, the first isolation structure encloses a first isolation opening, and the second isolation structure encloses a second isolation opening.

[0098] S108. In the first isolation opening and the second isolation opening, a light-emitting functional layer and a second electrode are sequentially formed in a direction away from the substrate; a partial cross-sectional view of the formed film structure is as follows Figure 8 (c)

[0099] The display pixel is at least partially located in the corresponding second isolation opening, and the display pixel includes a first electrode, a light-emitting functional layer and a second electrode; the virtual pixel is at least partially located in the corresponding first isolation opening, and the virtual pixel includes a light-emitting functional layer and a second electrode.

[0100] S110. Cut and remove the removal area structure.

[0101] In one feasible embodiment, in the removal area, the first isolation structure is a mesh structure, and the closed grid of the mesh structure forms a first isolation opening, whereby the virtual pixel is enclosed and closed by the first isolation opening, thereby reducing the risk of peeling of each film layer in the virtual pixel, avoiding display defects, performance damage and other problems caused by peeling of the film layer during the preparation of the display panel, and improving the yield rate of the display panel.

[0102] In one feasible manner, the substrate of the embodiment of the present application further includes: a planarization layer;

[0103] The planarization layer is located on a side of the first electrode close to the substrate, and is used to provide a planarized surface and reduce surface roughness, thereby facilitating the subsequent formation of various film layers.

[0104] In the removal area, the planarization layer contacts the light-emitting functional layer in the virtual pixel, and both contain organic materials. Therefore, the adhesion between the planarization layer and the light-emitting functional layer is stronger, reducing the risk of film peeling due to water vapor intrusion, etc., avoiding display defects, performance damage and other problems caused by film peeling during the preparation of the display panel, and enhancing the reliability of the display panel; in the panel area, the planarization layer contacts the first electrode in the display pixel.

[0105] In one feasible manner, before step S106, the method for preparing a display panel according to an embodiment of the present application further includes:

[0106] forming a pixel defining layer on a side of the planarization layer away from the substrate;

[0107] Wherein, the pixel defining layer includes a plurality of pixel defining portions;

[0108] In the removal area, the pixel defining portion encloses a virtual pixel opening, an orthographic projection of the virtual pixel opening on the substrate is located within an orthographic projection of the first isolation opening on the substrate, and the planarization layer contacts the light-emitting function layer in the virtual pixel through the virtual pixel opening;

[0109] In the panel area, the pixel defining portion is located between the first electrode and the second electrode, and the pixel defining portion encloses a display pixel opening. The orthographic projection of the display pixel opening on the substrate is located within the orthographic projection of the second isolation opening on the substrate. The display pixel opening exposes a portion of the first electrode. The first electrode in the display pixel contacts the light-emitting functional layer through the display pixel opening, and is used to combine with the second electrode to drive the light-emitting functional layer to emit light. The display pixel opening in the panel area and the virtual pixel opening in the removal area are formed simultaneously. The partial cross-sectional view of the film layer structure during the formation is shown in FIG. Figure 8 (b) as shown.

[0110] In one feasible manner, the shape of the display pixel opening is gradually increased in a direction away from the substrate, and is used to carry the display pixel;

[0111] Preferably, the shape of the virtual pixel opening is the same as the shape of the display pixel opening; thereby, the density of the graphics to be etched is increased, the distribution of the graphics to be etched is made more uniform, the uneven etching phenomenon is reduced, the etching uniformity is improved, and the process performance of the display panel is improved.

[0112] The first isolation structure and the second isolation structure are arranged on a side of the pixel defining portion away from the substrate.

[0113] In one feasible manner, the second isolation structure includes a conductive material, the second electrode in the display pixel is electrically connected to the second isolation structure, and an electrical signal is transmitted to the second electrode through the second isolation structure, so that the second electrode and the first electrode jointly drive the light-emitting functional layer to emit light;

[0114] Preferably, the first isolation structure has the same structure as the second isolation structure, thereby increasing the density of the graphics to be etched, making the distribution of the graphics to be etched more uniform, reducing the uneven etching phenomenon, improving the etching uniformity, and thus improving the process performance of the display panel.

[0115] In one feasible manner, the method for preparing the display panel of the embodiment of the present application further includes:

[0116] A first encapsulation layer is formed in the removal area and the panel area. The first encapsulation layer includes a plurality of encapsulation parts. A partial cross-sectional view of the formed film layer structure is shown in FIG. Figure 8 (d)

[0117] In the removal area, the encapsulation part is arranged on the side of the virtual pixel away from the substrate, and cooperates with the mesh structure of the first isolation structure to enclose the virtual pixel in the first isolation opening, thereby preventing the invasion of water vapor, oxygen, etc., reducing the peeling risk of each film layer in the virtual pixel, preventing the impact on each film layer in the panel area, avoiding display defects and performance damage caused by the peeling of the film layer during the preparation process of the display panel, and improving the reliability of the display panel;

[0118] In the panel area, the encapsulation part is arranged on the side of the display pixel away from the substrate, which can prevent the invasion of water vapor, oxygen, etc., and improve the reliability of the display panel. The encapsulation part in the panel area and the encapsulation part in the removal area are formed at the same time.

[0119] Preferably, the material of the first encapsulation layer includes an inorganic material.

[0120] By using the method for preparing the display panel of the embodiment of the present application, the etching loading in the preparation process is reduced; at the same time, the risk of peeling of each film layer in the preparation process is reduced, and the display panel obtained has a higher yield and stronger reliability.

[0121] Further optionally, the third aspect of the embodiment of the present application also provides a display device, which includes a display panel prepared by the display motherboard as described above or prepared by the display panel preparation method. Exemplarily, the above-mentioned display device can be implemented in the form of various electronic devices such as including but not limited to mobile phones, tablet computers, PDAs, PADs, etc.

[0122] The above implementation methods are only used to illustrate the embodiments of the present application, and are not limitations on the embodiments of the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, all equivalent technical solutions also belong to the scope of the embodiments of the present application. The scope of patent protection of the embodiments of the present application should be limited by the claims.

Claims

1. A display motherboard, comprising a removal area and a panel area; characterized in that: include: substrate; In the removal area, the display motherboard further includes a first isolation structure and a plurality of virtual pixels located on one side of the substrate, wherein the first isolation structure encloses a plurality of first isolation openings, the plurality of virtual pixels are respectively at least partially located in the corresponding first isolation openings, and the virtual pixels include a light-emitting functional layer and a second electrode sequentially stacked in a direction away from the substrate; In the panel area, the display motherboard also includes a second isolation structure and a plurality of display pixels located on the same side of the substrate as the first isolation structure and the plurality of virtual pixels, wherein the second isolation structure encloses a plurality of second isolation openings, and the plurality of display pixels are respectively at least partially located in the corresponding second isolation openings, and the display pixels include a first electrode, a light-emitting functional layer, and a second electrode which are sequentially stacked in a direction away from the substrate.

2. The display motherboard according to claim 1, characterized in that: In the removal area, the first isolation structure is a mesh structure, and the closed grids of the mesh structure form the first isolation openings.

3. The display motherboard according to claim 1, characterized in that: In the removal area and the panel area, the substrate further includes: a planarization layer; In the removal area, the planarization layer is located on a side of the substrate close to the first isolation structure, and the planarization layer is in contact with the light-emitting function layer in the virtual pixel; In the panel region, the planarization layer contacts the first electrode in the display pixel.

4. The display motherboard according to claim 3, characterized in that: The removal area and the panel area further include: a pixel defining layer, the pixel defining layer is located on a side of the planarization layer away from the substrate, the pixel defining layer includes a plurality of pixel defining portions; In the removal area, the pixel defining portion encloses a virtual pixel opening, the orthographic projection of the virtual pixel opening on the substrate is located within the orthographic projection of the first isolation opening on the substrate, and the planarization layer contacts the light-emitting function layer in the virtual pixel through the virtual pixel opening; In the panel area, the pixel defining portion is located between the first electrode and the second electrode, the pixel defining portion encloses a display pixel opening, the orthographic projection of the display pixel opening on the substrate is located within the orthographic projection of the second isolation opening on the substrate, the display pixel opening exposes a portion of the first electrode, and the first electrode in the display pixel contacts the light-emitting function layer through the display pixel opening; The first isolation structure and the second isolation structure are disposed on a side of the pixel defining portion away from the substrate.

5. The display motherboard according to claim 4, characterized in that: The shape of the display pixel opening is gradually increased in a direction away from the substrate; Preferably, the shape of the virtual pixel opening is the same as the shape of the display pixel opening.

6. The display motherboard according to claim 1, characterized in that: In the panel area, the second isolation structure includes a first sub-isolation structure and a second sub-isolation structure which are sequentially stacked in a direction close to the substrate; The orthographic projection of the second sub-isolation structure on the substrate is inside the orthographic projection of the first sub-isolation structure on the substrate.

7. The display motherboard according to claim 6, characterized in that: The material of the first sub-isolation structure includes titanium, and / or the material of the second sub-isolation structure includes aluminum.

8. The display motherboard according to claim 6, characterized in that: The second isolation structure also includes a third sub-isolation structure; The third sub-isolation structure is disposed on a side of the second sub-isolation structure close to the substrate; The orthographic projection of the second sub-isolation structure on the substrate is inside the orthographic projection of the third sub-isolation structure on the substrate; Preferably, the orthographic projection of the third sub-isolation structure on the substrate is inside the orthographic projection of the first sub-isolation structure on the substrate; Preferably, the material of the third sub-isolation structure includes molybdenum.

9. The display motherboard according to claim 8, characterized in that: The second isolation structure comprises a conductive material, and the second electrode in the display pixel is electrically connected to the second isolation structure; Preferably, the first isolation structure has the same structure as the second isolation structure.

10. The display motherboard according to claim 9, characterized in that: In the removal area and the panel area, the display motherboard further includes a first encapsulation layer, the first encapsulation layer includes a plurality of encapsulation parts; In the removal area, the encapsulation portion is disposed on a side of the dummy pixel away from the substrate; In the panel area, the packaging portion is disposed on a side of the display pixel away from the substrate; Preferably, the material of the first encapsulation layer includes an inorganic material.

11. The display motherboard according to claim 10, characterized in that , In the removal area, the encapsulation part extends to a side of the first isolation structure away from the substrate, and a partial structure of the encapsulation part is located below the first sub-isolation structure of the first isolation structure; the virtual pixel is encapsulated in the first isolation opening by the encapsulation part; In the panel area, the encapsulation part extends to a side of the second isolation structure away from the substrate, and a partial structure of the encapsulation part is located below the first sub-isolation structure of the second isolation structure; the display pixel is encapsulated in the second isolation opening by the encapsulation part.

12. The display motherboard according to claim 10, characterized in that , In the panel area, the display motherboard further includes a second encapsulation layer and a third encapsulation layer; The second encapsulation layer is located on a side of the first encapsulation layer away from the substrate; The third encapsulation layer is located on a side of the second encapsulation layer away from the substrate; Preferably, the material of the second encapsulation layer includes an organic material, and the material of the third encapsulation layer includes an inorganic material.

13. A method for preparing a display panel, characterized in that: include: Providing a substrate, the substrate comprising a removal area and a panel area; forming a first electrode in the panel region; After forming the first electrode, a first isolation structure is formed on the substrate in the removal area, and a second isolation structure is formed on the substrate in the panel area; wherein the first isolation structure encloses a first isolation opening, and the second isolation structure encloses a second isolation opening, In the first isolation opening and the second isolation opening, a light-emitting functional layer and a second electrode are sequentially formed in a direction away from the substrate; the display pixel is at least partially located in the corresponding second isolation opening, and the display pixel includes the first electrode, the light-emitting functional layer and the second electrode; the virtual pixel is at least partially located in the corresponding first isolation opening, and the virtual pixel includes the light-emitting functional layer and the second electrode; The removal area structure is removed by cutting.

14. The method according to claim 13, characterized in that The substrate comprises a planarization layer; the planarization layer is located on a side of the first electrode close to the substrate; In the removal area, the planarization layer contacts the light-emitting function layer in the dummy pixel; In the panel region, the planarization layer contacts the first electrode in the display pixel.

15. The method according to claim 14, characterized in that Before forming the first isolation structure on the substrate in the removal area and forming the second isolation structure on the substrate in the panel area, the method further includes: forming a pixel defining layer on a side of the planarization layer away from the substrate, wherein the pixel defining layer includes a plurality of pixel defining portions; In the removal area, the pixel defining portion encloses a virtual pixel opening, and in the panel area, the pixel defining portion is located between the first electrode and the second electrode, the pixel defining portion encloses a display pixel opening, and the virtual pixel opening is formed simultaneously with the display pixel opening.

16. The method according to claim 13, characterized in that The method further includes: forming a first encapsulation layer in the removal area and the panel area, the first encapsulation layer including a plurality of encapsulation parts; In the removal area, the encapsulation part is arranged on a side of the virtual pixel away from the substrate; in the panel area, the encapsulation part is arranged on a side of the display pixel away from the substrate; the encapsulation part in the removal area and the encapsulation part in the panel area are formed simultaneously; Preferably, the material of the first encapsulation layer includes an inorganic material.

17. The method according to claim 13, characterized in that The shape of the display pixel opening is gradually increased in a direction away from the substrate; Preferably, the shape of the virtual pixel opening is the same as the shape of the display pixel opening.

18. A display device, characterized in that: include: A display panel prepared using the display motherboard according to any one of claims 1 to 12 or prepared using the method according to claims 13 to 17.

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