Display panel, test method and preparation method of display panel and electronic equipment

Abstract

The embodiment of the invention provides a display panel, a test method of the display panel, a preparation method of the display panel and electronic equipment, and relates to the technical field of display. In the display panel, an isolation structure layer forms a test element group, the test element group comprises a first test isolation structure and a second test isolation structure which are oppositely arranged, and the orthographic projection of the first test isolation structure on a substrate has a first edge facing the second test isolation structure. The orthographic projection of the second test isolation structure on the substrate is provided with a second edge facing the first test isolation structure, the first edge is parallel to the second edge, and the length of the first edge is the same as that of the second edge. In the above design, by adjusting the moving directions of the first edge, the second edge and the evaporation source, the overlap resistance of the unit length of the test isolation structure under different evaporation angles can be directly and effectively obtained, so that the overlap resistance of light-emitting devices in different shapes can be calculated based on the overlap resistance of the unit length of the test isolation structure; and the subsequent design or adjustment of the isolation opening is facilitated.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel, a testing method and a preparation method of a display panel, and an electronic device. Background Art

[0002] Organic Light Emitting Diode (OLED) is considered to be the next generation of flat panel display technology after liquid crystal. It is widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to its excellent color and picture quality, becoming the mainstream in display panels.

[0003] However, the process performance of current OLED display products needs to be further improved. Summary of the invention

[0004] In order to overcome the technical problems mentioned in the above technical background, the present application provides a display panel, a testing method and a preparation method of the display panel, and an electronic device.

[0005] In a first aspect of the present application, a display panel is provided, the display panel comprising:

[0006] substrate;

[0007] an isolation structure layer, the isolation structure layer being located on one side of the substrate, the isolation structure layer comprising at least one test element group, the test element group comprising a first test isolation structure and a second test isolation structure, the first test isolation structure being arranged opposite to the second test isolation structure;

[0008] The orthographic projection of the first test isolation structure on the substrate has a first edge facing the second test isolation structure, and the orthographic projection of the second test isolation structure on the substrate has a second edge facing the first test isolation structure; the first edge and the second edge are parallel, and the first edge and the second edge have the same length.

[0009] In a possible implementation of the present application, the test element group further includes an isolation protection structure;

[0010] The isolation protection structure encloses a test opening on the substrate, and the first test isolation structure and the second test isolation structure are located in the test opening;

[0011] Preferably, the orthographic projections of the first test isolation structure and the second test isolation structure on the substrate do not overlap with the orthographic projection of the isolation protection structure on the substrate.

[0012] In a possible implementation of the present application, the orthographic projection shape of the isolation protection structure on the substrate is a ring;

[0013] Preferably, the orthographic projection shape of the isolation protection structure on the substrate is a rectangular ring;

[0014] Preferably, the first test isolation structure and the second test isolation structure have the same orthographic projection shape on the substrate;

[0015] Preferably, the orthographic projection shapes of the first test isolation structure and the second test isolation structure on the substrate are rectangular;

[0016] Preferably, the first edge corresponds to a long side of an orthographic projection of the first test isolation structure on the substrate, and the second edge corresponds to a long side of an orthographic projection of the second test isolation structure on the substrate.

[0017] In a possible implementation of the present application, the display panel further includes a bonding electrode;

[0018] The overlapping electrode at least overlaps the side walls of the first test isolation structure and the second test isolation structure that are opposite to each other, and electrically connects the first test isolation structure and the second test isolation structure;

[0019] Preferably, the bridging electrode is insulated from the isolation protection structure;

[0020] Preferably, the orthographic projection shape of the bonding electrode connecting the first test isolation structure and the second test isolation structure on the substrate is a rectangle or a parallelogram;

[0021] Preferably, a overlapping length between the overlapping electrode and the first test isolation structure is equal to a overlapping length between the overlapping electrode and the second test isolation structure.

[0022] In a possible implementation of the present application, the extension direction of the first edge intersects or is parallel to the moving direction of the evaporation source when the bridging electrode is formed by evaporation;

[0023] Preferably, the angle between the extension direction of the first edge and the moving direction of the evaporation source when the lap electrode is formed by evaporation includes 0 degrees, 45 degrees, 90 degrees and 135 degrees;

[0024] Preferably, the display panel comprises a plurality of test element groups having different included angles between an extension direction of the first edge and a moving direction of a vapor deposition source when the overlapping electrode is formed by vapor deposition.

[0025] In a possible implementation of the present application, the display panel further includes a light-emitting material layer;

[0026] In the test element group, the light emitting material layer is located on a side of the bonding electrode facing the substrate, wherein the light emitting color of the light emitting material layer in the same test element group is the same;

[0027] Preferably, the display panel comprises a plurality of test element groups whose luminescent material layers emit light of different colors.

[0028] In a possible implementation of the present application, the display panel further includes a conductive trace;

[0029] The conductive trace is located on a side of the isolation structure layer facing the substrate, the conductive trace includes a first conductive trace and a second conductive trace insulated from each other, and the display panel also includes a first test contact, a second test contact, a third test contact and a fourth test contact;

[0030] The first conductive trace connects the first test isolation structure with the first test contact and the second test contact, and the second conductive trace connects the second test isolation structure with the third test contact and the fourth test contact.

[0031] In a possible implementation of the present application, the display panel further includes an insulating layer, and the insulating layer is located on a side of the isolation structure layer facing the conductive trace;

[0032] The insulating layer comprises a first insulating layer through hole and a second insulating layer through hole, the first test isolation structure is connected to the first conductive trace through the first insulating layer through hole, and the second test isolation structure is connected to the second conductive trace through the second insulating layer through hole;

[0033] Preferably, the orthographic projection of the first insulating layer through hole on the substrate is located within the orthographic projection of the first test isolation structure on the substrate, and the orthographic projection of the second insulating layer through hole on the substrate is located within the orthographic projection of the second test isolation structure on the substrate.

[0034] In a possible implementation of the present application, the insulating layer includes a pixel defining layer;

[0035] The pixel definition layer includes a first definition layer through hole, a second definition layer through hole and a third definition layer through hole;

[0036] The first test isolation structure is connected to the first conductive trace through the first defining layer through-hole, and the second test isolation structure is connected to the second conductive trace through the second defining layer through-hole;

[0037] The orthographic projection of the third defining layer through hole on the substrate surrounds the orthographic projections of the first test isolation structure and the second test isolation structure on the substrate;

[0038] Preferably, the orthographic projection shape of the through hole of the third defining layer on the substrate is annular;

[0039] Preferably, the orthographic projections of the first test isolation structure, the second test isolation structure and the isolation protection structure on the substrate partially overlap with the orthographic projections of the third defining layer through hole on the substrate;

[0040] Preferably, the first test isolation structure and the second test isolation structure extend relative to the pixel definition layer on a side facing the isolation protection structure, and the isolation protection structure extends relative to the pixel definition layer on a side facing the center of the test opening;

[0041] Preferably, the electrode layer manufactured on the same layer as the bridging electrode covers the first test isolation structure and the second test isolation structure, and is located in the through hole of the third defining layer;

[0042] Preferably, the electrode layer is disconnected at the position of the through hole of the third defining layer;

[0043] Preferably, the electrode layer covering the first test isolation structure and the second test isolation structure is disconnected from the bonding electrode.

[0044] In a possible implementation of the present application, the insulating layer includes a planarization layer;

[0045] The planarization layer is located on a side of the pixel definition layer facing the conductive trace;

[0046] The planarization layer includes a first planarization layer through hole and a second planarization layer through hole, the first test isolation structure is connected to the first conductive trace through the first definition layer through hole and the first planarization layer through hole, and the second test isolation structure is connected to the second conductive trace through the second definition layer through hole and the second planarization layer through hole;

[0047] Preferably, the orthographic projection of the first defining layer through hole on the substrate is located within the orthographic projection of the first planarization layer through hole on the substrate, and the orthographic projection of the second defining layer through hole on the substrate is located within the orthographic projection of the second planarization layer through hole on the substrate.

[0048] In a possible implementation of the present application, the isolation structure layer includes a first isolation layer and a second isolation layer stacked in sequence in a direction away from the substrate, and the orthographic projection of the first isolation layer on the substrate is located within the orthographic projection of the second isolation layer on the substrate;

[0049] Preferably, the orthographic projection area of ​​the first isolation layer on the substrate is smaller than the orthographic projection area of ​​the second isolation layer on the substrate;

[0050] Preferably, in the first test isolation structure and on a side facing the second test isolation structure, the second isolation layer protrudes relative to the first isolation layer; in the second test isolation structure and on a side facing the first test isolation structure, the second isolation layer protrudes relative to the first isolation layer;

[0051] Preferably, in the isolation protection structure and on a side facing the first test isolation structure and the second test isolation structure, the second isolation layer covers the first isolation layer;

[0052] Preferably, in the first test isolation structure and on a side facing the isolation protection structure, the second isolation layer covers the first isolation layer; in the second test isolation structure and on a side facing the isolation protection structure, the second isolation layer covers the first isolation layer;

[0053] Preferably, the material of the first isolation layer includes aluminum, and / or the material of the second isolation layer includes titanium.

[0054] In a possible implementation of the present application, the isolation structure layer further includes a third isolation layer;

[0055] The orthographic projection of the third isolation layer on the substrate is located within the orthographic projection of the second isolation layer on the substrate;

[0056] Preferably, the orthographic projection area of ​​the third isolation layer on the substrate is smaller than the orthographic projection area of ​​the second isolation layer on the substrate;

[0057] Preferably, the material of the third isolation layer includes molybdenum.

[0058] In a possible implementation of the present application, the display panel includes a display area and a test area, and the test element group is located in the test area;

[0059] The isolation structure layer further comprises an isolation structure located in the display area, and the isolation structure encloses an isolation opening on the substrate;

[0060] The display panel further includes a light emitting device, at least a portion of which is located in the isolation opening, and the light emitting device includes a first electrode, a light emitting material layer, and a second electrode which are sequentially stacked in a direction away from the substrate;

[0061] Preferably, at least a portion of the second electrode extends from within the isolation opening to be electrically connected to a side wall of the isolation structure facing the isolation opening.

[0062] In a possible implementation of the present application, the display panel further includes a first encapsulation layer, the first encapsulation layer includes a plurality of first encapsulation units, different first encapsulation units are used to encapsulate light-emitting devices in different isolation openings, and two adjacent first encapsulation units are disconnected on a side of the isolation structure away from the substrate;

[0063] Preferably, on a side of the isolation structure away from the substrate, there is a gap between the first packaging unit and the isolation structure;

[0064] Preferably, the first packaging layer further comprises a second packaging unit, and the second packaging unit is located at a side of the test element group away from the substrate;

[0065] Preferably, there is a gap between the second packaging unit and the isolation protection structure;

[0066] Preferably, the first encapsulation layer is an inorganic encapsulation layer;

[0067] Preferably, the display panel further comprises a second encapsulation layer;

[0068] The second encapsulation layer is located on a side of the first encapsulation layer away from the substrate, and the second encapsulation layer at least covers the first encapsulation layer;

[0069] Preferably, the second encapsulation layer fills the gap between the first encapsulation unit and the isolation structure, and the gap between the second encapsulation unit and the isolation protection structure;

[0070] Preferably, the second encapsulation layer has a flat surface on a side away from the substrate;

[0071] Preferably, the display panel further comprises a third encapsulation layer, and the third encapsulation layer is located on a side of the second encapsulation layer away from the substrate;

[0072] Preferably, the third encapsulation layer is an inorganic encapsulation layer, and the second encapsulation layer is an organic encapsulation layer.

[0073] A second method of the present application further provides a method for testing a display panel, which is applied to the display panel described in the first aspect, and includes:

[0074] Acquire the overlap resistance of the first test isolation structure and the second test isolation structure by a test device;

[0075] Based on the overlap resistance, the overlap resistance per unit length of the first test isolation structure or the second test isolation structure is obtained.

[0076] In a possible implementation of the present application, the step of obtaining the connection resistance of the first test isolation structure and the second test structure by a test device includes:

[0077] Acquire the total resistance between the first test isolation structure and the second test isolation structure by the test device;

[0078] Acquire, by the test device, a first connection resistance between the first conductive trace and the first test isolation structure, and a second connection resistance between the second conductive trace and the second test isolation structure;

[0079] Acquire, by the test device, a third resistance of a bonding electrode between the first test isolation structure and the second test isolation structure;

[0080] Subtract the first connection resistance, the second connection resistance and the third resistance from the total resistance to obtain a lap resistance between the first test isolation structure and the second test structure;

[0081] The step of obtaining the lap resistance per unit length of the first test isolation structure or the second test isolation structure based on the lap resistance includes:

[0082] The quotient obtained by dividing the overlap resistance by 2 is divided by the length of the first edge or the second edge to obtain the overlap resistance per unit length of the first test isolation structure or the second test isolation structure.

[0083] In a third aspect of the present application, a method for preparing a display panel is further provided, the method comprising:

[0084] providing a substrate;

[0085] An isolation structure layer is formed on one side of the substrate, the isolation structure layer includes at least one test element group, the test element group includes a first test isolation structure and a second test isolation structure, the first test isolation structure is arranged opposite to the second test isolation structure; the orthographic projection of the first test isolation structure on the substrate has a first edge facing the second test isolation structure, and the orthographic projection of the second test isolation structure on the substrate has a second edge facing the first test isolation structure; the first edge is parallel to the second edge, and the lengths of the first edge and the second edge are the same.

[0086] In a possible implementation of the present application, the method further includes:

[0087] forming an isolation protection structure by the isolation structure layer;

[0088] The isolation protection structure encloses a test opening on the substrate, and the first test isolation structure and the second test isolation structure are located in the test opening;

[0089] Preferably, the orthographic projections of the first test isolation structure and the second test isolation structure on the substrate do not overlap with the orthographic projection of the isolation protection structure on the substrate.

[0090] In a possible implementation of the present application, the method further includes:

[0091] A overlapping electrode is formed on a side of the substrate where the isolation structure layer is provided, wherein the overlapping electrode at least overlaps the side walls of the first test isolation structure and the second test isolation structure that are opposite to each other, and electrically connects the first test isolation structure and the second test isolation structure, and the overlapping electrode is insulated from the isolation protection structure.

[0092] In a fourth aspect of the present application, an electronic device is further provided, comprising a display panel in any possible implementation manner in the first aspect or a display panel prepared in any possible implementation manner in the third aspect.

[0093] The embodiments of the present application provide a display panel, a test method for a display panel, a preparation method, and an electronic device. In the display panel, a test element group is formed by an isolation structure layer, and the test element group includes a first test isolation structure and a second test isolation structure arranged relatively to each other, and the orthographic projection of the first test isolation structure on the substrate has a first edge facing the second test isolation structure, and the orthographic projection of the second test isolation structure on the substrate has a second edge facing the first test isolation structure, and the first edge and the second edge are parallel, and the lengths of the first edge and the second edge are the same. In the above design, by adjusting the moving direction of the first edge and the second edge and the evaporation source, the lap resistance per unit length of the test isolation structure under different evaporation angles can be directly and effectively obtained, so as to calculate the lap resistance of light-emitting devices of different shapes based on the lap resistance per unit length of the test isolation structure, which is beneficial to the design or adjustment of the subsequent isolation opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0094] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0095] Figure 1 One of the structural schematic diagrams of the test element group in the display panel provided by this embodiment is illustrated;

[0096] Figure 2 Example Figure 1 A schematic cross-sectional view of the test element group in the AA direction;

[0097] Figure 3 The second structural schematic diagram of the test element group in the display panel provided by this embodiment is illustrated;

[0098] Figure 4 Example Figure 3 One of the cross-sectional schematic diagrams of the test element group in the AA direction;

[0099] Figure 5 Example Figure 3 The second schematic cross-sectional view of the test element group in the AA direction;

[0100] Figure 6 Example Figure 3 The third schematic cross-sectional view of the test element group in the AA direction;

[0101] Figure 7 One of the schematic diagrams of the test element group with different angles with the moving direction of the evaporation source is illustrated;

[0102] Figure 8 Example Figure 3 The fourth schematic cross-sectional view of the test element group in the AA direction;

[0103] Fig. 9 Example Figure 3 The fifth schematic cross-sectional view of the test element group in the AA direction;

[0104] Fig.10 A second schematic diagram illustrating a test element group having different angles with respect to the moving direction of the evaporation source;

[0105] Fig.11 A third schematic diagram illustrating a test element group having different angles with respect to the moving direction of the evaporation source;

[0106] Fig.12 A fourth schematic diagram of a test element group illustrating different angles between the test element group and the moving direction of the evaporation source;

[0107] Fig.13 Example Figure 3 The sixth schematic cross-sectional view of the test element group in the AA direction;

[0108] Fig.14 A schematic diagram illustrating the regional distribution of the display panel provided in this embodiment;

[0109] Fig.15 A schematic diagram of the film layer structure of the display panel corresponding to the display area is illustrated;

[0110] Fig.16 One of the schematic diagrams of the membrane layer structure of the isolation structure layer is illustrated;

[0111] Fig.17 Example Figure 3 The seventh schematic cross-sectional view of the test element group in the AA direction;

[0112] Fig.18 The second schematic diagram of the membrane structure of the isolation structure layer is illustrated;

[0113] Fig.19 Example Figure 3 The seventh schematic cross-sectional view of the test element group in the AA direction;

[0114] Fig. 20 Example Figure 3 A schematic cross-sectional view of the test element group in the BB direction;

[0115] Fig.21 A schematic diagram illustrating a flow chart of a method for testing a display panel provided in this embodiment;

[0116] Fig. 22 The schematic diagram illustrates a process flow of a method for manufacturing a display panel provided in this embodiment.

[0117] Icons: 1-display panel; 110-substrate; 12-isolation structure layer; 121-test element group; 1211-first test isolation structure; 1212-second test isolation structure; 1213-isolation protection structure; 1201-first edge; 1202-second edge; 1203-test opening; 1221-first isolation layer; 1222-second isolation layer; 1223-third isolation layer; 124-isolation structure; 1241-isolation opening; 13-bridging electrode; 14-conductive trace; 141-first conductive trace; 142-second conductive trace; 1401-first test contact; 1402-second test contact; 1403-third test Contact; 1404-the fourth test contact; 15-insulating layer; 1501-the first insulating layer through hole; 1502-the second insulating layer through hole; 151-pixel defining layer; 15101-the first defining layer through hole; 15102-the second defining layer through hole; 15103-the third defining layer through hole; 152-planarizing layer; 15201-the first planarizing layer through hole; 15202-the second planarizing layer through hole; 16-light-emitting device; 161-the first electrode; 162-the light-emitting material layer; 163-the second electrode; 171-the first encapsulation layer; 1711-the first encapsulation unit; 1712-the second encapsulation unit; 172-the second encapsulation layer; 173-the third encapsulation layer. DETAILED DESCRIPTION

[0118] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0119] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0120] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0121] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0122] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.

[0123] Improving the density of light-emitting devices in a display panel (i.e., pixel density) is an important way to improve the display effect. However, the display panels currently made using the fine metal evaporation mask (FMM) technology cannot further increase the density of light-emitting devices due to technical limitations. After long-term research, the inventors found that in order to solve the technical problem that the density of light-emitting devices cannot be further increased, an isolation structure is set in some display panels. When the light-emitting material layer and the cathode are evaporated in the entire layer, the light-emitting material layer and the cathode can be disconnected at the isolation structure position. Through multiple evaporation and multiple etching processes, light-emitting devices of different colors can be formed in different isolation openings, that is, light-emitting device patterning.

[0124] Patent PCT / CN2023 / 134518, patent 202310759370.2, patent 202310740412.8, patent 202310707209.0, patent 202311499823.9, patent 202310692671.8, patent 202311091555.7 and patent 202311346196.5 record relevant technical solutions of isolation structure and encapsulation layer, and their contents are incorporated into this application by reference for reference.

[0125] In the above-mentioned display panel, it is usually necessary to overlap the cathode formed by evaporation with the side wall of the isolation structure to achieve the transmission of a common voltage (e.g., ELVSS voltage) to the cathode through the isolation structure. However, since the transparent conductive material used for the cathode is different from the material used for the isolation structure, a relatively large overlap resistance will be generated at the overlap position. Factors such as the shape of the isolation opening formed by the isolation structure and the evaporation direction of the cathode will affect the overlap length and thus the overlap effect. How to determine the overlap resistance per unit length in different directions is crucial to the subsequent design of the appearance of the light-emitting device.

[0126] In order to solve the above-mentioned technical problems, the inventor innovatively designed the following technical solutions, and the specific implementation solutions of the present application will be described in detail below in conjunction with the accompanying drawings. It should be noted that the defects existing in the solutions in the above-mentioned prior art are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above-mentioned technical problems and the solutions proposed in this embodiment below for the above-mentioned problems should all be the contributions made by the inventor to the present application in the process of invention and creation, and should not be understood as the technical content known to those skilled in the art.

[0127] Please refer to Figure 1 and Figure 2 , Figure 1 The schematic diagram of the structure of the display panel provided by this embodiment is illustrated. Figure 2 Example Figure 1 In this embodiment, the display panel 1 includes a substrate 110 and an isolation structure layer.

[0128] The substrate 110 may include a flexible substrate or a rigid substrate. An array film layer structure 111 may be provided on one side of the substrate 110. The array film layer structure 111 may include a buffer layer, an active layer, multiple metal layers, multiple insulating layers, a planarization layer, and other multiple film layer structures. The multiple film layer structures may form multiple thin film transistors (TFTs) at different positions of the array film layer structure 111, and the thin film transistors may cooperate with each other to form multiple pixel driving units.

[0129] The isolation structure layer is located on one side of the substrate 11. Exemplarily, the isolation structure layer is located on the side of the array film layer structure 111 away from the substrate 110. The isolation structure layer is a single film layer or a multi-film layer structure. The isolation structure layer is a conductive isolation structure layer. The isolation structure layer includes at least one test element group (TEG) 121. The test element group 121 includes a first test isolation structure 1211 and a second test isolation structure 1212. The first test isolation structure 1211 and the second test isolation structure 1212 are arranged opposite to each other.

[0130] The orthographic projection of the first test isolation structure 1211 on the substrate 11 has a first edge 1201 facing the second test isolation structure 1212, and the orthographic projection of the second test isolation structure 1212 on the substrate 11 has a second edge 1202 facing the first test isolation structure 1211. The first edge 1201 and the second edge 1202 are parallel, and the first edge 1201 and the second edge 1202 have the same length.

[0131] In this embodiment, it is only necessary that the orthographic projections of the first test isolation structure 1211 and the second test isolation structure 1212 on the substrate 110 are parallel to each other and have the same length. The orthographic projections of the first test isolation structure 1211 and the second test isolation structure 1212 on the substrate 110 may be regular or irregular, which is not limited here. In addition, the orthographic projections of the first test isolation structure 1211 and the second test isolation structure 1212 on the substrate 110 may be the same or different.

[0132] In the above structure, by adjusting the moving direction of the first edge 1201 and the second edge 1202 and the evaporation source, the lap resistance per unit length of the test isolation structure under different evaporation angles can be directly and effectively obtained, so as to calculate the lap resistance of light-emitting devices of different shapes based on the lap resistance per unit length of the test isolation structure, which is beneficial to the subsequent design or adjustment of the isolation opening.

[0133] Furthermore, the inventors have found that in order to protect the first test isolation structure 1211 and the second test isolation structure 1212 from being etched by the etching solution, in this embodiment, please refer to Figure 3 and Figure 4The test element group 121 also includes an isolation protection structure 1213. The isolation protection structure 1213 encloses a test opening 1203 on the substrate 110. The first test isolation structure 1211 and the second test isolation structure 1212 are located in the test opening 1203. The isolation protection structure 1213 can form a dam structure around the first test isolation structure 1211 and the second test isolation structure 1212 to block the entry of etching liquid, so as to ensure that in the subsequent process technology, the first test isolation structure 1211 and the second test isolation structure 1212 will not be etched by the etching liquid, resulting in the first edge 1201 and the second edge 1202 failing to meet the parallel and equal requirements. In this embodiment, the orthographic projections of the first test isolation structure 1211 and the second test isolation structure 1212 on the substrate 110 do not overlap with the orthographic projections of the isolation protection structure 1213 on the substrate 110. Such a design allows the entire surface of the evaporated film to be disconnected between the isolation protection structure 1213 and the test isolation structure in the test opening 1203 during subsequent vapor deposition, thereby isolating the isolation protection structure 1213 and the test isolation structure in the test opening 1203.

[0134] In this embodiment, the orthographic projection shape of the isolation protection structure 1213 on the substrate 110 is a ring. It can be understood that the isolation protection structure 1213 only needs to form a dam structure surrounding the first test isolation structure 1211 and the second test isolation structure 1212. The orthographic projection shape of the isolation protection structure 1213 on the substrate 110 can be a regular ring or an irregular ring.

[0135] In a possible implementation, the orthographic projection shape of the isolation protection structure 1213 on the substrate 110 is a rectangular ring. The orthographic projection shapes of the first test isolation structure 1211 and the second test isolation structure 1212 on the substrate 110 are the same. Preferably, the orthographic projection shapes of the first test isolation structure 1211 and the second test isolation structure 1212 on the substrate 110 are rectangular. In this embodiment, the edges of the first test isolation structure 1211 and the second test isolation structure 1212 may be parallel to the corresponding edges of the isolation protection structure 1213. Exemplarily, the first edge 1201 corresponds to the long side of the orthographic projection of the first test isolation structure 1211 on the substrate 110, and the second edge 1202 corresponds to the long side of the orthographic projection of the second test isolation structure 1212 on the substrate 110. Using a longer edge as the overlap edge can increase the overlap length, thereby improving the calculation accuracy of the overlap resistance per unit length.

[0136] For further information, please refer to Figure 5The display panel 1 further includes a bridging electrode 13, which at least bridgingly connects the sidewalls of the first test isolation structure 1211 and the second test isolation structure 1212 that face each other, and electrically connects the first test isolation structure 1211 and the second test isolation structure 1212. The bridging electrode 13 may be insulated from the isolation protection structure 1213.

[0137] In a possible implementation, the first test isolation structure 1211 and the second test isolation structure 1212 may be arranged opposite to each other or diagonally. When the first test isolation structure 1211 and the second test isolation structure 1212 are arranged opposite to each other, the positive projection shape of the overlapping electrode 13 connecting the first test isolation structure 1211 and the second test isolation structure 1212 on the substrate 110 is a rectangle. When the first test isolation structure 1211 and the second test isolation structure 1212 are arranged diagonally, the positive projection shape of the overlapping electrode 13 connecting the first test isolation structure 1211 and the second test isolation structure 1212 on the substrate 110 is a parallelogram. Among them, the overlapping length of the overlapping electrode 13 and the first test isolation structure 1211 is equal to the overlapping length of the overlapping electrode 13 and the second test isolation structure 1212.

[0138] For further information, please refer to Figure 6 and Figure 7 The display panel 1 also includes a conductive trace 14, which is located on the side of the isolation structure layer 12 facing the substrate 110. The conductive trace 14 can be located in the array film layer structure 111. The conductive trace 14 includes a first conductive trace 141 and a second conductive trace 142 that are insulated from each other. The display panel 1 also includes a first test contact 1401, a second test contact 1402, a third test contact 1403 and a fourth test contact 1404.

[0139] The first conductive trace 141 connects the first test isolation structure 1211 with the first test contact 1401 and the second test contact 1402, and the second conductive trace 142 connects the second test isolation structure 1212 with the third test contact 1403 and the fourth test contact 1404. Exemplarily, the first test isolation structure 1211 is connected to the first test contact 1401 and the second test contact 1402 through two first conductive traces 141, respectively, wherein the two first conductive traces 141 can be partially shared. One of the first test contact 201 and the second test contact 202 can be in contact with a current supply probe (e.g., a positive electrode of a constant current source) of a test device, and the other can be in contact with a voltage collection probe. The second test isolation structure 1212 is connected to the third test contact 1403 and the fourth test contact 1404 through two second connecting traces 142, respectively, and the two second conductive traces 142 can be partially shared. One of the third test contact 1403 and the fourth test contact 1404 can be in contact with a current supply probe (e.g., the negative pole of a constant current source) of a test device, and the other can be in contact with a voltage collection probe. The total resistance R between the first test isolation structure 1211 and the second test isolation structure 1212 can be tested by using a four-probe test method. 总 The conductive trace 14 is generally made of a titanium-aluminum-titanium three-layer structure, and its trace resistance is small and can be ignored. In this embodiment, the total resistance R 总 The first conductive trace 141 is mainly composed of a first connection resistor R1 between the first conductive trace 141 and the first test isolation structure 1211, a second connection resistor R2 between the second conductive trace 142 and the second test isolation structure 1212, a third resistor R3 of the bridging electrode 13 between the first test isolation structure 1211 and the second test isolation structure 1212, and a bridging resistor R1 between the bridging electrode 13 and the first test isolation structure 1211 and the second test isolation structure 1212. t Composition. Lap resistor R t It can be expressed as R t =R 总 -R1-R2-R3, the lap resistance per unit length R d =R t / (2*L), where L is the length of the first edge or the second edge. The first connection resistor R1 and the second connection resistor R2 can be measured by a set reference test element group, and the third resistor R3 can also be directly measured by a test device.

[0140] In this embodiment, please refer to Figure 8The display panel 1 further includes an insulating layer 15, which is located on the side of the isolation structure layer 12 facing the conductive trace 13. The insulating layer 15 includes a first insulating layer through hole 1501 and a second insulating layer through hole 1502, the first test isolation structure 1211 is connected to the first conductive trace 141 through the first insulating layer through hole 1501, and the second test isolation structure 1212 is connected to the second conductive trace 142 through the second insulating layer through hole 1502.

[0141] Optionally, the orthographic projection of the first insulating layer through hole 1501 on the substrate 110 is located within the orthographic projection of the first test isolation structure 1211 on the substrate 110 , and the orthographic projection of the second insulating layer through hole 1502 on the substrate 110 is located within the orthographic projection of the second test isolation structure 1212 on the substrate 110 .

[0142] Further, please refer again to Figure 8 The insulating layer 15 may include a pixel defining layer 151, and the pixel defining layer 151 includes a first defining layer through hole 15101, a second defining layer through hole 15102, and a third defining layer through hole 15103. The first test isolation structure 1211 is connected to the first conductive trace 141 through the first defining layer through hole 15101, and the second test isolation structure 1212 is connected to the second conductive trace 142 through the second defining layer through hole 15102.

[0143] The orthographic projection of the third defining layer through hole 15103 on the substrate 110 surrounds the orthographic projections of the first test isolation structure 1211 and the second test isolation structure 1212 on the substrate 110 . Exemplarily, the orthographic projection of the third defining layer through hole 15103 on the substrate 110 is in the shape of a ring.

[0144] The orthographic projections of the first test isolation structure 1121, the second test isolation structure 1122, and the isolation protection structure 1123 on the substrate 110 partially overlap with the orthographic projection of the third definition layer through hole 15103 on the substrate 110. Exemplarily, the first test isolation structure 1121 and the second test isolation structure 1122 extend relative to the pixel definition layer 151 toward one side of the isolation protection structure 1123, and the side of the isolation protection structure 1123 toward the center of the test opening 1203 extends relative to the pixel definition layer 151.

[0145] For further information, please refer to Fig. 9 The electrode layer made in the same layer as the bonding electrode 13 covers the first test isolation structure 1211 and the second test isolation structure 1212, and the electrode layer made in the same layer as the bonding electrode 13 is also located in the third defining layer through hole 15103. The electrode layer made in the same layer as the bonding electrode 13 can also cover the isolation protection structure 1213. In the subsequent process technology, the electrode layer covering the isolation protection structure 1213 can be etched away by the etching solution.

[0146] Optionally, the electrode layer is disconnected at the location of the third defining layer through hole 15103 so that the first test isolation structure 1211 and the second test isolation structure 1212 are not electrically connected to the isolation protection structure 1213 .

[0147] Optionally, the electrode layer covering the first test isolation structure 1211 and the second test isolation structure 1212 is disconnected from the bonding electrode 13 .

[0148] Further, please refer again to Fig. 9 The insulating layer 15 further includes a planarization layer 152, which is located on the side of the pixel definition layer 151 facing the conductive trace 14. The planarization layer 152 includes a first planarization layer through hole 15201 and a second planarization layer through hole 15202. The first test isolation structure 1121 is connected to the first conductive trace 141 through the first definition layer through hole 15101 and the first planarization layer through hole 15201, and the second test isolation structure 1122 is connected to the second conductive trace 142 through the second definition layer through hole 15102 and the second planarization layer through hole 15202.

[0149] Exemplarily, the orthographic projection of the first defining layer through hole 15101 on the substrate 110 is located within the orthographic projection of the first planarization layer through hole 15201 on the substrate 110, and the orthographic projection of the second defining layer through hole 15102 on the substrate 110 is located within the orthographic projection of the second planarization layer through hole 15202 on the substrate 110. That is, the orthographic projection area of ​​the first defining layer through hole 15101 on the substrate 110 is smaller than the orthographic projection area of ​​the first planarization layer through hole 15201 on the substrate 110, and the orthographic projection area of ​​the second defining layer through hole 15102 on the substrate 110 is smaller than the orthographic projection area of ​​the second planarization layer through hole 15202 on the substrate 110.

[0150] In this embodiment, please refer to Figure 7 , Figure 10-12 , the extension direction of the first edge 1201 intersects or is parallel to the moving direction of the evaporation source when the lap electrode 13 is formed by evaporation (the X direction in the figure), that is, the angle between the extension direction of the first edge 1201 and the moving direction of the evaporation source when the lap electrode 13 is formed by evaporation is between 0 degrees and 180 degrees. Exemplarily, the angle between the extension direction of the first edge 1201 and the moving direction of the evaporation source when the lap electrode 13 is formed by evaporation includes 0 degrees, 10 degrees, 15 degrees, 25 degrees, 35 degrees, 45 degrees, 50 degrees, 65 degrees, 85 degrees, 90 degrees, 105 degrees, 120 degrees, 135 degrees, 145 degrees, 165 degrees, 175 degrees and 180 degrees, etc. Preferably, as Figure 7 , Figure 10-12 As shown, the included angles between the extension direction of the first edge and the moving direction of the evaporation source 13 when the overlapping electrode is formed by evaporation are 0 degrees, 45 degrees, 90 degrees and 135 degrees.

[0151] In order to directly and effectively obtain the lap resistance per unit length of the test isolation structure at different evaporation angles, the display panel 1 includes multiple test element groups 121 with different angles between the extension direction of the first edge and the moving direction of the evaporation source when evaporating to form the lap electrode 13.

[0152] In this embodiment, please refer to Fig.13 The display panel 1 further includes a light-emitting material layer 162 . In the test element group 121 , the light-emitting material layer 162 is located on the side of the bonding electrode 13 facing the substrate 110 . The light-emitting color of the light-emitting material layer 162 in the same test element group 121 is the same.

[0153] In order to directly and effectively obtain the bridging resistance of light-emitting devices of different colors after patterning, the display panel 1 includes a plurality of test element groups with different luminescent colors of the luminescent material layer 162. The same luminescent color can also correspond to a plurality of test element groups 121 with different angles with the moving direction of the evaporation source when the bridging electrode 13 is formed by evaporation.

[0154] For further information, please refer to Fig.14 The display panel 1 includes a display area AA and a test area NA1, and the test element group is located in the test area NA1. The test area NA1 may be located in a non-display area. The test area NA1 may be a to-be-cut area.

[0155] See also Fig.15 The isolation structure layer 12 further includes an isolation structure 124 located in the display area AA, and the isolation structure 124 encloses an isolation opening 1241. That is, the isolation structure 124, the first test isolation structure 1211, the second test isolation structure 1212 and the isolation protection structure 1213 are arranged in the same layer and are made by the same process.

[0156] The display panel 1 further includes a light emitting device 16 at least partially located in the isolation opening 1241, and the light emitting device 16 includes a first electrode 161, a light emitting material layer 162 and a second electrode 163 which are sequentially stacked in a direction away from the substrate 110. The second electrode 163 and the bonding electrode 13 are arranged in the same layer and are manufactured by the same process.

[0157] At least a portion of the second electrode 163 extends from the isolation opening 1241 to be electrically connected to a sidewall of the isolation structure 124 facing the isolation opening 1241 .

[0158] The isolation structure 124 can enclose a plurality of isolation openings 1241. The setting of the isolation structure 124 can form film layers of light-emitting devices of different colors in different isolation openings 1241 without the need for a fine metal mask, thereby reducing the manufacturing cost of the display panel. The isolation structure 124 can isolate the light-emitting material layer and the second electrode in the light-emitting device, so that different light-emitting devices are independent of each other, so as to improve the crosstalk between adjacent light-emitting devices 16 and enhance the display effect. Adjacent light-emitting devices 16 can be independently packaged to improve the packaging yield. At the same time, due to the existence of the isolation structure 124, the light-emitting material layer 162 and the second electrode 163 in the light-emitting device 16 of each color in the display panel can be first prepared on the entire surface and then patterned, thereby eliminating the fine metal mask to save the manufacturing cost of the display panel.

[0159] For some possible implementations, see Fig.16 The isolation structure layer 12 includes a first isolation layer 1221 and a second isolation layer 1222 stacked in a direction away from the substrate 110, the orthographic projection of the first isolation layer 1221 on the substrate 110 is located within the orthographic projection of the second isolation layer 1222 on the substrate 110, and the orthographic projection area of ​​the first isolation layer 1221 on the substrate 110 is smaller than the orthographic projection area of ​​the second isolation layer 1222 on the substrate 110. The cross-sections of the first test isolation structure 1211, the second test isolation structure 1212, the isolation protection structure 1213, and the isolation structure 124 may be T-shaped.

[0160] Please refer to Fig.17 , in the first test isolation structure 1211 and on a side facing the second test isolation structure 1212, the second isolation layer 1222 extends relative to the first isolation layer 1221; in the second test isolation structure 1212 and on a side facing the first test isolation structure 1211, the second isolation layer 1222 extends relative to the first isolation layer 1221.

[0161] Optionally, in the isolation protection structure 1213 and on a side facing the first test isolation structure 1211 and the second test isolation structure 1212 , the second isolation layer 1222 covers the first isolation layer 1221 .

[0162] Optionally, in the first test isolation structure 1211 and on a side facing the isolation protection structure 1213, the second isolation layer 1222 covers the first isolation layer 1221. Similarly, in the second test isolation structure 1212 and on a side facing the isolation protection structure 1213, the second isolation layer 1222 covers the first isolation layer 1221.

[0163] Optionally, the material of the first isolation layer 1221 includes aluminum, and / or the material of the second isolation layer 1222 includes titanium.

[0164] Optionally, see Fig.18 The isolation structure layer 12 further includes a third isolation layer 1223 located between the first isolation layer 1221 and the substrate 110 .

[0165] Optionally, the orthographic projection of the third isolation layer 1223 on the substrate 110 is located within the orthographic projection of the second isolation layer 1222 on the substrate 110, and the orthographic projection area of ​​the third isolation layer 1223 on the substrate 110 is smaller than the orthographic projection area of ​​the second isolation layer 1222 on the substrate 110. The cross-sections of the first test isolation structure 1211, the second test isolation structure 1212, the isolation protection structure 1213, and the isolation structure 124 may be I-shaped.

[0166] Optionally, the material of the third isolation layer 1223 includes molybdenum.

[0167] For some possible implementations, see again Fig.15 The display panel also includes a first encapsulation layer 171, which includes a first encapsulation unit 1711 located on the side of the second electrode 163 away from the substrate 110, and at least a portion of the first encapsulation unit 1711 extends from the isolation opening 1241 to the side of the isolation structure 124 away from the substrate 110.

[0168] Optionally, on a side of the isolation structure 124 away from the substrate 110 , there is a gap between the first encapsulation unit 1711 and the isolation structure 124 .

[0169] Optionally, see Fig.19 and Fig. 20 The first packaging layer 171 also includes a second packaging unit 1712 , which is located on a side of the test element group 121 away from the substrate 110 , and the second packaging unit 1712 at least covers the first test isolation structure 1211 , the second test isolation structure 1212 and the isolation protection structure 1213 .

[0170] Optionally, there is a gap between the second packaging unit 1712 and the isolation protection structure 1213 .

[0171] Optionally, the display panel 1 further includes a second encapsulation layer 172 and a third encapsulation layer 173 which are located on a side of the first encapsulation layer 171 away from the substrate 110 and are sequentially stacked in a direction away from the substrate 110. The second encapsulation layer 172 at least covers the first encapsulation layer 171, and the second encapsulation layer 172 has a flat surface on a side away from the substrate 110. The second encapsulation layer 172 can also fill the gap between the first encapsulation unit 1711 and the isolation structure 124, and the gap between the second encapsulation unit 1712 and the isolation protection structure 1213.

[0172] Optionally, the materials of the first encapsulation layer 171 and the third encapsulation layer 173 include inorganic materials, and the material of the second encapsulation layer 172 includes organic materials. For example, the first encapsulation layer 171 and the third encapsulation layer 173 can be formed by chemical vapor deposition (CVD), and the second encapsulation layer 172 can be formed by inkjet printing (IJP).

[0173] Based on the same inventive concept, this embodiment also provides a display panel testing method for testing the display panel provided by the above embodiment. Fig.21 , the method may include the following steps.

[0174] Step S110: obtaining the overlap resistance of the first test isolation structure and the second test isolation structure through a test device.

[0175] Step S120: obtaining the overlap resistance per unit length of the first test isolation structure or the second test isolation structure based on the overlap resistance.

[0176] Specifically, the lap resistance R per unit length of the first test isolation structure or the second test isolation structure can be calculated by the following formula: d :

[0177] R d =R t / (2*L)

[0178] Among them, R t is the bonding resistance between the bonding electrode and the first test isolation structure and the second test isolation structure, and L is the length of the first edge or the second edge.

[0179] In some possible implementations, step S110 may be implemented in the following manner.

[0180] First, the total resistance R between the first test isolation structure and the second test isolation structure is obtained by a test device. 总 .

[0181] The total resistance R between the first test isolation structure 1211 and the second test isolation structure 1212 can be tested by using a four-probe test method. 总 .

[0182] Next, a first connection resistance R1 between the first conductive trace and the first test isolation structure, and a second connection resistance R2 between the second conductive trace and the second test isolation structure are obtained through a test device.

[0183] The first connection resistor R1 and the second connection resistor R2 can be obtained by measuring the connection resistance of the test isolation structure and the conductive trace in a separately set reference test element group, wherein the test isolation structure and the conductive trace can have the same design in the reference test element group and the test element group.

[0184] Then, a third resistance of the bonding electrode between the first test isolation structure and the second test isolation structure is obtained by using a test device.

[0185] Finally, the first connection resistor R1, the second connection resistor R2 and the third resistor R3 are subtracted from the total resistance to obtain the overlapping resistance R of the first test isolation structure and the second test structure. t .

[0186] Lap resistor R t It can be expressed as follows:

[0187] R t =R 总 -R1-R2-R3

[0188] Based on the same inventive concept, this embodiment also provides a method for preparing a display panel, which can be used to prepare the display panel described above. Fig. 22 , the method may include the following steps.

[0189] Step S210, providing a substrate.

[0190] The substrate may include a flexible substrate or a rigid substrate.

[0191] Step S220: forming an isolation structure layer on one side of the substrate, wherein the isolation structure layer includes at least one test element group.

[0192] The test element group includes a first test isolation structure and a second test isolation structure, wherein the first test isolation structure is arranged opposite to the second test isolation structure. The orthographic projection of the first test isolation structure on the substrate has a first edge facing the second test isolation structure, and the orthographic projection of the second test isolation structure on the substrate has a second edge facing the first test isolation structure. The first edge and the second edge are parallel, and the lengths of the first edge and the second edge are the same.

[0193] In a possible implementation manner, the isolation structure layer also forms an isolation protection structure;

[0194] The isolation protection structure encloses a test opening on the substrate, and the first test isolation structure and the second test isolation structure are located in the test opening.

[0195] Optionally, the orthographic projections of the first test isolation structure and the second test isolation structure on the substrate do not overlap with the orthographic projection of the isolation protection structure on the substrate.

[0196] In a possible implementation, a overlapping electrode is formed on a side of the substrate where the isolation structure layer is provided, wherein the overlapping electrode at least overlaps the side walls of the first test isolation structure and the second test isolation structure that are opposite to each other, and electrically connects the first test isolation structure and the second test isolation structure, and the overlapping electrode is insulated from the isolation protection structure.

[0197] Based on the same inventive concept, an embodiment of the present application also provides an electronic device, which includes the display panel provided in the present application, or includes a display panel prepared by the display panel manufacturing method provided in the present embodiment. The electronic device may include a mobile phone, a tablet computer, a smart wearable device, a television, a laptop computer, a monitor, and other devices with a display function.

[0198] The embodiments of the present application provide a display panel, a test method for display panel, a preparation method and an electronic device. In the display panel, a test element group is formed by an isolation structure layer, and the test element group includes a first test isolation structure and a second test isolation structure arranged relatively to each other, and the orthographic projection of the first test isolation structure on the substrate has a first edge facing the second test isolation structure, and the orthographic projection of the second test isolation structure on the substrate has a second edge facing the first test isolation structure, and the first edge and the second edge are parallel, and the lengths of the first edge and the second edge are the same. In the above design, by adjusting the moving direction of the first edge and the second edge and the evaporation source, the lap resistance per unit length of the test isolation structure under different evaporation angles can be directly and effectively obtained, so as to calculate the lap resistance of light-emitting devices of different shapes based on the lap resistance per unit length of the test isolation structure, which is beneficial to the design or adjustment of the subsequent isolation opening.

[0199] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises: substrate; an isolation structure layer, the isolation structure layer being located on one side of the substrate, the isolation structure layer comprising at least one test element group, the test element group comprising a first test isolation structure and a second test isolation structure, the first test isolation structure being arranged opposite to the second test isolation structure; The orthographic projection of the first test isolation structure on the substrate has a first edge facing the second test isolation structure, and the orthographic projection of the second test isolation structure on the substrate has a second edge facing the first test isolation structure; the first edge and the second edge are parallel, and the first edge and the second edge have the same length.

2. The display panel according to claim 1, wherein: The test element group also includes an isolation protection structure; The isolation protection structure encloses a test opening on the substrate, and the first test isolation structure and the second test isolation structure are located in the test opening; Preferably, the orthographic projections of the first test isolation structure and the second test isolation structure on the substrate do not overlap with the orthographic projection of the isolation protection structure on the substrate.

3. The display panel according to claim 2, wherein: The orthographic projection shape of the isolation protection structure on the substrate is a ring; Preferably, the orthographic projection shape of the isolation protection structure on the substrate is a rectangular ring; Preferably, the first test isolation structure and the second test isolation structure have the same orthographic projection shape on the substrate; Preferably, the orthographic projection shapes of the first test isolation structure and the second test isolation structure on the substrate are rectangular; Preferably, the first edge corresponds to a long side of an orthographic projection of the first test isolation structure on the substrate, and the second edge corresponds to a long side of an orthographic projection of the second test isolation structure on the substrate.

4. The display panel according to claim 2, wherein: The display panel further includes a lap electrode; The overlapping electrode at least overlaps the side walls of the first test isolation structure and the second test isolation structure that are opposite to each other, and electrically connects the first test isolation structure and the second test isolation structure; Preferably, the bridging electrode is insulated from the isolation protection structure; Preferably, the orthographic projection shape of the bonding electrode connecting the first test isolation structure and the second test isolation structure on the substrate is a rectangle or a parallelogram; Preferably, a overlapping length between the overlapping electrode and the first test isolation structure is equal to a overlapping length between the overlapping electrode and the second test isolation structure.

5. The display panel according to claim 4, wherein: The extension direction of the first edge intersects or is parallel to the moving direction of the evaporation source when the bridging electrode is formed by evaporation; Preferably, the angle between the extension direction of the first edge and the moving direction of the evaporation source when the lap electrode is formed by evaporation includes 0 degrees, 45 degrees, 90 degrees and 135 degrees; Preferably, the display panel comprises a plurality of test element groups having different included angles between an extension direction of the first edge and a moving direction of a vapor deposition source when the overlapping electrode is formed by vapor deposition.

6. The display panel according to claim 4, wherein: The display panel further comprises a light emitting material layer; In the test element group, the light emitting material layer is located on a side of the bonding electrode facing the substrate, wherein the light emitting color of the light emitting material layer in the same test element group is the same; Preferably, the display panel comprises a plurality of test element groups whose luminescent material layers emit light of different colors.

7. The display panel according to claim 4, wherein: The display panel also includes conductive traces; The conductive trace is located on a side of the isolation structure layer facing the substrate, the conductive trace includes a first conductive trace and a second conductive trace insulated from each other, and the display panel also includes a first test contact, a second test contact, a third test contact and a fourth test contact; The first conductive trace connects the first test isolation structure with the first test contact and the second test contact, and the second conductive trace connects the second test isolation structure with the third test contact and the fourth test contact.

8. The display panel according to claim 7, wherein: The display panel further comprises an insulating layer, wherein the insulating layer is located on a side of the isolation structure layer facing the conductive trace; The insulating layer comprises a first insulating layer through hole and a second insulating layer through hole, the first test isolation structure is connected to the first conductive trace through the first insulating layer through hole, and the second test isolation structure is connected to the second conductive trace through the second insulating layer through hole; Preferably, the orthographic projection of the first insulating layer through hole on the substrate is located within the orthographic projection of the first test isolation structure on the substrate, and the orthographic projection of the second insulating layer through hole on the substrate is located within the orthographic projection of the second test isolation structure on the substrate.

9. The display panel according to claim 8, wherein: The insulating layer includes a pixel defining layer; The pixel definition layer includes a first definition layer through hole, a second definition layer through hole and a third definition layer through hole; The first test isolation structure is connected to the first conductive trace through the first defining layer through-hole, and the second test isolation structure is connected to the second conductive trace through the second defining layer through-hole; The orthographic projection of the third defining layer through hole on the substrate surrounds the orthographic projections of the first test isolation structure and the second test isolation structure on the substrate; Preferably, the orthographic projection shape of the through hole of the third defining layer on the substrate is annular; Preferably, the orthographic projections of the first test isolation structure, the second test isolation structure and the isolation protection structure on the substrate partially overlap with the orthographic projections of the third defining layer through hole on the substrate; Preferably, the first test isolation structure and the second test isolation structure extend relative to the pixel definition layer on a side facing the isolation protection structure, and the isolation protection structure extends relative to the pixel definition layer on a side facing the center of the test opening; Preferably, the electrode layer manufactured on the same layer as the bridging electrode covers the first test isolation structure and the second test isolation structure, and is located in the through hole of the third defining layer; Preferably, the electrode layer is disconnected at the position of the through hole of the third defining layer; Preferably, the electrode layer covering the first test isolation structure and the second test isolation structure is disconnected from the bonding electrode.

10. The display panel according to claim 9, wherein: The insulating layer includes a planarization layer; The planarization layer is located on a side of the pixel definition layer facing the conductive trace; The planarization layer includes a first planarization layer through hole and a second planarization layer through hole, the first test isolation structure is connected to the first conductive trace through the first definition layer through hole and the first planarization layer through hole, and the second test isolation structure is connected to the second conductive trace through the second definition layer through hole and the second planarization layer through hole; Preferably, the orthographic projection of the first defining layer through hole on the substrate is located within the orthographic projection of the first planarization layer through hole on the substrate, and the orthographic projection of the second defining layer through hole on the substrate is located within the orthographic projection of the second planarization layer through hole on the substrate.

11. The display panel according to claim 2, wherein: The isolation structure layer comprises a first isolation layer and a second isolation layer which are sequentially stacked in a direction away from the substrate, wherein the orthographic projection of the first isolation layer on the substrate is located within the orthographic projection of the second isolation layer on the substrate; Preferably, the orthographic projection area of ​​the first isolation layer on the substrate is smaller than the orthographic projection area of ​​the second isolation layer on the substrate; Preferably, in the first test isolation structure and on a side facing the second test isolation structure, the second isolation layer protrudes relative to the first isolation layer; in the second test isolation structure and on a side facing the first test isolation structure, the second isolation layer protrudes relative to the first isolation layer; Preferably, in the isolation protection structure and on a side facing the first test isolation structure and the second test isolation structure, the second isolation layer covers the first isolation layer; Preferably, in the first test isolation structure and on a side facing the isolation protection structure, the second isolation layer covers the first isolation layer; in the second test isolation structure and on a side facing the isolation protection structure, the second isolation layer covers the first isolation layer; Preferably, the material of the first isolation layer includes aluminum, and / or the material of the second isolation layer includes titanium.

12. The display panel according to claim 11, wherein: The isolation structure layer also includes a third isolation layer; The orthographic projection of the third isolation layer on the substrate is located within the orthographic projection of the second isolation layer on the substrate; Preferably, the orthographic projection area of ​​the third isolation layer on the substrate is smaller than the orthographic projection area of ​​the second isolation layer on the substrate; Preferably, the material of the third isolation layer includes molybdenum.

13. The display panel according to claim 2, wherein: The display panel includes a display area and a test area, and the test element group is located in the test area; The isolation structure layer further comprises an isolation structure located in the display area, and the isolation structure encloses an isolation opening on the substrate; The display panel further includes a light emitting device, at least a portion of which is located in the isolation opening, and the light emitting device includes a first electrode, a light emitting material layer, and a second electrode which are sequentially stacked in a direction away from the substrate; Preferably, at least a portion of the second electrode extends from within the isolation opening to be electrically connected to a side wall of the isolation structure facing the isolation opening.

14. The display panel according to claim 13, wherein: The display panel further includes a first encapsulation layer, the first encapsulation layer includes a plurality of first encapsulation units, different first encapsulation units are used to encapsulate light-emitting devices in different isolation openings, and two adjacent first encapsulation units are disconnected at a side of the isolation structure away from the substrate; Preferably, on a side of the isolation structure away from the substrate, there is a gap between the first packaging unit and the isolation structure; Preferably, the first packaging layer further comprises a second packaging unit, and the second packaging unit is located at a side of the test element group away from the substrate; Preferably, there is a gap between the second packaging unit and the isolation protection structure; Preferably, the first encapsulation layer is an inorganic encapsulation layer; Preferably, the display panel further comprises a second encapsulation layer; The second encapsulation layer is located on a side of the first encapsulation layer away from the substrate, and the second encapsulation layer at least covers the first encapsulation layer; Preferably, the second encapsulation layer fills the gap between the first encapsulation unit and the isolation structure, and the gap between the second encapsulation unit and the isolation protection structure; Preferably, the second encapsulation layer has a flat surface on a side away from the substrate; Preferably, the display panel further comprises a third encapsulation layer, and the third encapsulation layer is located on a side of the second encapsulation layer away from the substrate; Preferably, the third encapsulation layer is an inorganic encapsulation layer, and the second encapsulation layer is an organic encapsulation layer.

15. A method for testing a display panel, characterized in that: The method is applied to the display panel according to any one of claims 1 to 14, and the method comprises: Acquire the overlap resistance of the first test isolation structure and the second test isolation structure by a test device; Based on the overlap resistance, the overlap resistance per unit length of the first test isolation structure or the second test isolation structure is obtained.

16. The display panel testing method according to claim 15, wherein: The step of obtaining the overlap resistance of the first test isolation structure and the second test structure by a test device includes: Acquire the total resistance between the first test isolation structure and the second test isolation structure by the test device; Acquire, by the test device, a first connection resistance between the first conductive trace and the first test isolation structure, and a second connection resistance between the second conductive trace and the second test isolation structure; Acquire, by the test device, a third resistance of a bonding electrode between the first test isolation structure and the second test isolation structure; Subtract the first connection resistance, the second connection resistance and the third resistance from the total resistance to obtain a lap resistance between the first test isolation structure and the second test structure; The step of obtaining the lap resistance per unit length of the first test isolation structure or the second test isolation structure based on the lap resistance includes: The quotient obtained by dividing the overlap resistance by 2 is divided by the length of the first edge or the second edge to obtain the overlap resistance per unit length of the first test isolation structure or the second test isolation structure.

17. A method for preparing a display panel, characterized in that: The method comprises: providing a substrate; An isolation structure layer is formed on one side of the substrate, the isolation structure layer includes at least one test element group, the test element group includes a first test isolation structure and a second test isolation structure, the first test isolation structure is arranged opposite to the second test isolation structure; the orthographic projection of the first test isolation structure on the substrate has a first edge facing the second test isolation structure, and the orthographic projection of the second test isolation structure on the substrate has a second edge facing the first test isolation structure; the first edge is parallel to the second edge, and the lengths of the first edge and the second edge are the same.

18. The preparation method according to claim 17, characterized in that: The method further comprises: forming an isolation protection structure by the isolation structure layer; The isolation protection structure encloses a test opening on the substrate, and the first test isolation structure and the second test isolation structure are located in the test opening; Preferably, the orthographic projections of the first test isolation structure and the second test isolation structure on the substrate do not overlap with the orthographic projection of the isolation protection structure on the substrate.

19. The preparation method according to claim 18, characterized in that: The method further comprises: A overlapping electrode is formed on a side of the substrate where the isolation structure layer is provided, wherein the overlapping electrode at least overlaps the side walls of the first test isolation structure and the second test isolation structure that are opposite to each other, and electrically connects the first test isolation structure and the second test isolation structure, and the overlapping electrode is insulated from the isolation protection structure.

20. An electronic device, characterized in that: A display panel comprising any one of claims 1-14, or a display panel prepared by the method for preparing a display panel according to any one of claims 17-19.

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