Display panel mother board, manufacturing method of display panel mother board and display device

Abstract

The invention provides a display panel mother board, a manufacturing method of the display panel mother board and a display device. The display device comprises a substrate; the at least one test assembly is arranged on one side of the substrate and comprises a lap joint electrode and a test element group electrically connected with the lap joint electrode; the test element group comprises a first test isolation structure and a second test isolation structure which are separated from each other, and the first test isolation structure and the second test isolation structure are arranged on the two opposite sides of the lap joint electrode; and the second test isolation structure is electrically connected with the lap joint electrode. The first test isolation structure and the second test isolation structure in the test element group are arranged to be located on the two sides of the lap joint electrode respectively, it is guaranteed that the second test isolation structure is in lap joint with the lap joint electrode, and therefore the test element group can be tested under the condition that lap joint of the lap joint electrode is poor due to the evaporation problem. And the evaporation chamber with problems in the evaporation source can be determined more accurately.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel motherboard, a method for manufacturing a display panel motherboard, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat-panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream of display devices.

[0003] However, the process performance of current OLED display products needs to be improved. Summary of the invention

[0004] In order to overcome the above-mentioned deficiencies in the prior art, the object of the present application is to provide a display panel motherboard, the display panel motherboard comprising: substrate; At least one test assembly disposed on one side of the substrate, the test assembly comprising a bonding electrode and a test element group electrically connected to the bonding electrode; The test element group includes a first test isolation structure and a second test isolation structure which are separate from each other, wherein the first test isolation structure and the second test isolation structure are arranged on two opposite sides of the bonding electrode; The second test isolation structure is electrically connected to the bonding electrode.

[0005] In some possible implementations, in at least one of the test components, the first test isolation structure is arranged on one side of the bonding electrode in a first direction, and the second test isolation structure is located on the other side of the bonding electrode; the first direction is the same as or opposite to an extension direction of a preset signal line in the display panel motherboard; Preferably, in at least one other test assembly, the first test isolation structure is arranged on one side of the bonding electrode in a second direction, and the second test isolation structure is located on the other side of the bonding electrode; the second direction is opposite to the first direction; Preferably, in at least one other test component, the first test isolation structure is arranged on one side of the overlapping electrode in a third direction, and the second test isolation structure is located on the other side of the overlapping electrode; the third direction intersects with the extension direction of some signal lines in the display panel motherboard.

[0006] In some possible implementations, the bonding electrode has a first opening, the second test isolation structure is located in the first opening, and the bonding electrode is connected to at least one side surface of the second test isolation structure; Preferably, the bonding electrode is connected to at least one side surface of the second test isolation structure facing the first direction or opposite to the first direction.

[0007] In some possible implementations, in a direction parallel to the substrate and intersecting the first direction, a length of the first test isolation structure is greater than a length of the second test isolation structure.

[0008] In some possible implementations, the extension direction of the first test isolation structure is perpendicular to the first direction; Preferably, a surface of the first test isolation structure facing the second test isolation structure is perpendicular to the first direction.

[0009] In some possible implementations, the display panel further includes a wiring layer located on one side of the substrate and an insulating layer located on a side of the wiring layer away from the substrate, and the test element group is arranged on a side of the insulating layer away from the substrate; the first test isolation structure and the second test isolation structure are respectively electrically connected to connecting wirings located in the wiring layer through through holes penetrating the insulating layer, and the connecting wirings respectively connect the first test isolation structure and the second test isolation structure to test contacts; Preferably, the insulating layer comprises at least one planarization layer and / or a pixel defining layer.

[0010] In some possible implementations, the insulating layer includes a first thickness region and a second thickness region, the thickness of the second thickness region is greater than the thickness of the first thickness region, and the test element group is located in the second thickness region.

[0011] In some possible implementations, the display panel motherboard includes a display panel and a test area; the test element group is located in the test area; The display panel includes a pixel isolation structure located at one side of the substrate, the first test isolation structure and the second test isolation structure are arranged in the same layer as the pixel isolation structure, and the pixel isolation structure includes isolation openings arranged at intervals; The display panel further comprises a first pixel electrode, a pixel light emitting unit and a second pixel electrode which are at least partially located in the isolation opening and are stacked in a direction away from the substrate; the second pixel electrode is arranged in the same layer as the bridging electrode; The second pixel electrode extends from the isolation opening to a side of the pixel isolation structure facing the isolation opening and is electrically connected to the pixel isolation structure.

[0012] In some possible implementations, the display panel motherboard further includes a test light emitting unit located on a side of the bonding electrode close to the substrate; the test light emitting unit and the pixel light emitting unit are arranged on the same layer; Preferably, the pixel light-emitting unit includes a first light-emitting unit and a second light-emitting unit, the display panel motherboard includes at least two test element groups, at least two test element groups are respectively arranged corresponding to the first light-emitting unit and the second light-emitting unit, the test element group arranged corresponding to the first light-emitting unit has the same material as the first light-emitting unit, and the test element group arranged corresponding to the first light-emitting unit has the same material as the first light-emitting unit. Preferably, in at least two of the test element groups having the same luminous color of the test luminous unit, along the first direction, the first test isolation structure and the second test isolation structure in at least one of the test element groups are arranged in sequence, and the second test isolation structure and the first test isolation structure in another of the test element groups are arranged in sequence; Preferably, in at least two of the test element groups having the same luminous color of the test luminous unit, two adjacent test element groups share the first test isolation structure, wherein the second test isolation structure of one of the test element groups is arranged on one side of the first test isolation structure in the extension direction of the preset signal line in the display panel motherboard, and the second test isolation structure of the other test element group is arranged on one side of the first test isolation structure away from the extension direction of the preset signal line in the display panel motherboard; Preferably, among at least two of the test element groups having the same luminous color of the test light-emitting unit, two adjacent test element groups share the second test isolation structure, wherein the first test isolation structure of one of the test element groups is arranged on the side of the second test isolation structure in the extension direction of the preset signal line in the display panel motherboard, and the first test isolation structure of the other test element group is arranged on the side of the second test isolation structure away from the extension direction of the preset signal line in the display panel motherboard.

[0013] In some possible implementations, the first test isolation structure, the second test isolation structure, and the pixel isolation structure include a first sublayer and a second sublayer stacked in a direction away from the substrate, and an orthographic projection of the first sublayer on the substrate is located within an orthographic projection of the second sublayer on the substrate; Preferably, the material of the first sublayer includes aluminum, and / or the material of the second sublayer includes titanium; Preferably, the first test isolation structure, the second test isolation structure and the pixel isolation structure further include a third sublayer located between the first sublayer and the substrate; Preferably, the orthographic projection of the third sub-layer on the substrate is located within the orthographic projection of the second sub-layer on the substrate; Preferably, the material of the third sublayer includes molybdenum.

[0014] In some possible implementations, the display panel motherboard further includes a test packaging unit, wherein the test packaging unit is located at a side of the bonding electrode away from the substrate and covers the bonding electrode; Preferably, at least a portion of the test package unit extends from between the first test isolation structure and the second test isolation structure to a side of the first test isolation structure and the second test isolation structure away from the substrate; Preferably, the display panel motherboard further comprises a pixel encapsulation unit located at a side of the second pixel electrode away from the substrate, at least a portion of the pixel encapsulation unit extends from the isolation opening to a side of the pixel isolation structure away from the substrate; the pixel encapsulation unit is disposed in the same layer as the test encapsulation unit; Preferably, the display panel motherboard further comprises a second encapsulation layer and a third encapsulation layer which are located on a side of the pixel encapsulation unit and the test encapsulation unit away from the substrate and are stacked in a direction away from the substrate; Preferably, the materials of the pixel encapsulation unit, the test encapsulation unit and the third encapsulation layer include inorganic materials, and the material of the second encapsulation layer includes organic materials.

[0015] Another object of the present application is to provide a method for manufacturing a display panel motherboard, the method comprising: providing a substrate; At least one test assembly is formed on one side of the substrate, the test assembly comprising a bonding electrode and a test element group electrically connected to the bonding electrode; The test element group includes a first test isolation structure and a second test isolation structure which are separate from each other, and the first test isolation structure and the second test isolation structure are arranged on two opposite sides of the bonding electrode; The second test isolation structure is electrically connected to the bonding electrode.

[0016] In some possible implementations, the display panel motherboard includes a display panel and a test area, and the test component is disposed in the test area; The display panel further includes a pixel isolation structure located on one side of the substrate, and the pixel isolation structure is disposed on the same layer as the first test isolation structure and the second test isolation structure; the step of forming at least one test component on one side of the substrate includes: forming the first test isolation structure and the second test isolation structure in the test area, and forming a pixel isolation structure in the display panel, wherein the pixel isolation structure includes isolation openings arranged at intervals; A lap electrode is provided between the first test isolation structure and the second test isolation structure, and a second pixel electrode is formed on the display panel, at least part of which is located in the isolation opening, and the second pixel electrode extends from the isolation opening to the side of the pixel isolation structure facing the isolation opening and contacts the pixel isolation structure; Preferably, the method further comprises: For the test element group, determining the overlapping effect of the second pixel electrode and the pixel isolation structure; After the test is completed, the test area is cut.

[0017] In some possible implementations, the evaporation directions of the second pixel electrode and the strapping electrode include a first direction and a second direction that are relatively arranged; the test assembly includes at least one of the first test isolation structure, the strapping electrode, and the second test isolation structure distributed along the first direction; the test assembly also includes at least one of the second test isolation structure, the strapping electrode, and the first test isolation structure distributed along the second direction; The step of determining the overlapping effect between the second pixel electrode and the pixel isolation structure for the test element group further includes: Acquire a first lap resistance between the first test isolation structure and the second test isolation structure distributed along a first direction by means of a detection device; acquire a second lap resistance between the first test isolation structure and the second test isolation structure distributed along a second direction by means of a detection device; The overlapping effect of the second pixel electrode when overlapping with the pixel isolation structure along the second direction is determined according to the first overlapping resistance; the overlapping effect of the second pixel electrode when overlapping with the pixel isolation structure along the first direction is determined according to the second overlapping resistance.

[0018] Another object of the present application is to provide a display device, which includes a display panel manufactured by the method for manufacturing the display panel motherboard provided in the present application.

[0019] Compared with the prior art, this application has the following beneficial effects: The present application provides a display panel motherboard, a method for manufacturing a display panel motherboard, and a display device. By setting a first test isolation structure and a second test isolation structure in a test element group to be located on both sides of a overlapping electrode, respectively, and ensuring that the second test isolation structure is overlapped with the overlapping electrode, when the overlapping electrode has poor overlap due to an evaporation problem, the evaporation chamber with a problem in the evaporation source can be more accurately determined. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 is a perspective view of an existing test element group; Figure 2 is a cross-sectional schematic diagram of an existing test element group; Figure 3 One of the cross-sectional schematic diagrams of the display panel motherboard provided in this embodiment; Figure 4 The second cross-sectional schematic diagram of the display panel motherboard provided in this embodiment; Figure 5 One of the perspective schematic diagrams of the display panel motherboard provided in this embodiment; Figure 6 The second perspective schematic diagram of the display panel motherboard provided in this embodiment; Figure 7 The third perspective schematic diagram of the display panel motherboard provided in this embodiment; Figure 8 A fourth perspective schematic diagram of a display panel motherboard provided in this embodiment; Fig. 9 A fifth perspective schematic diagram of a display panel motherboard provided in this embodiment; Fig.10 A sixth perspective schematic diagram of a display panel motherboard provided in this embodiment; Fig.11 The third cross-sectional schematic diagram of the display panel motherboard provided in this embodiment; Fig.12 A fourth cross-sectional schematic diagram of the display panel motherboard provided in this embodiment; Fig.13 A schematic diagram of the region of the display panel motherboard provided in this embodiment; Fig.14 The seventh cross-sectional schematic diagram of the display panel motherboard provided in this embodiment; Fig.15 A seventh perspective schematic diagram of a display panel motherboard provided in this embodiment; Fig.16 An eighth perspective schematic diagram of a display panel motherboard provided in this embodiment; Fig.17 A schematic diagram of the isolation structure layer provided in this embodiment; Fig.18 The eighth cross-sectional schematic diagram of the display panel motherboard provided in this embodiment; Fig.19 A ninth cross-sectional schematic diagram of a display panel motherboard provided in this embodiment; Fig. 20 This is a flow chart of a method for manufacturing a display panel provided in this embodiment.

[0022] Icons: 110-substrate; 111-array film structure; 112-other film layers; 113-connection wiring; 114-planarization layer; 115-pixel definition layer; 123-first pixel electrode; 141, 141A, 141B-first test isolation structure; 142, 142A, 142B-second test isolation structure; 145-pixel isolation structure; 151, 151A, 151B-test light-emitting unit; 153-pixel light-emitting unit; 161, 1 61A, 161B-bridging electrodes; 163-second pixel electrode; 171, 171A, 171B-test packaging unit; 173-pixel packaging unit; 180-second packaging layer; 190-third packaging layer; 200-test contact; 1401-first sublayer; 1402-second sublayer; 1403-third sublayer; AA-display panel; NA1-test area; NA2-bonding area; D1-first direction; D2-second direction; D3-third direction. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0024] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0025] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0026] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0027] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.

[0028] In some display panels, an isolation structure is provided in the display panel, so that different color light-emitting units and cathodes can be formed in different pixel openings by etching after the entire layer is evaporated. Among them, patent applications PCT / CN2023 / 134518, 202310759370.2, 202310740412.8, 202310707209.0, and 202311346196.5 record relevant technical solutions of the isolation structure, and their contents are incorporated into this application by reference for reference.

[0029] In such display panels, it is usually necessary to overlap the cathode formed by evaporation with the side wall of the isolation structure to achieve the transmission of common voltage to the cathode through the isolation structure. In order to determine the evaporation effect of the cathode, a test area is set outside the display panel during the manufacturing process of some display panel motherboards. The test area includes a test element group (TEG). By detecting the overlap resistance between the isolation structure and the cathode in the test element group, the overlap effect of each isolation structure and the cathode in the display area is determined.

[0030] Specifically, see Figure 1 , Figure 1 It is a partial perspective view of an existing test element group, wherein the test element group includes a first test isolation structure 141' arranged in the same layer as the pixel isolation structure of the display panel AA, the first test isolation structure 141' encloses a test opening, and the test opening is similar in shape to the isolation opening of the pixel isolation structure of the display panel AA. A second test isolation structure 142' is also arranged in the test opening.

[0031] See also Figure 2 , Figure 2 for Figure 1 In the cross-sectional schematic diagram at the AA position, the existing display panel may include a substrate 110', a connecting wire 113' located on one side of the substrate 110', and an insulating layer 130' located on a side of the connecting wire 113' away from the substrate 110', wherein the first test isolation structure 141' and the second test isolation structure 142' are located on a side of the insulating layer 130' away from the substrate 110'.

[0032] While forming the pixel light-emitting unit and the pixel cathode on the display panel AA by the whole-layer evaporation method, the test light-emitting unit 150' and the test cathode 160' are also formed in the test opening. In this way, the overlapping effect of the first test isolation structure 141' and the test cathode 150' can reflect the overlapping effect of the pixel isolation structure and the pixel cathode in the display panel AA. Among them, in the scenario of using a linear evaporation source for mobile evaporation, if the moving direction of the evaporation source is the first direction D1 or the second direction D2 (the first direction D1 is opposite to the second direction D2), the test cathode 'formed by evaporation mainly overlaps with the first test isolation structure 141' and the second test isolation structure 142' in the first direction D1 and the second direction D2.

[0033] On this basis, the method of testing the overlapping effect of the first test isolation structure 141' and the test cathode 160' is to respectively connect the first test isolation structure 141' and the second test isolation structure 142' to the test contacts through the connecting line 113', and determine the overlapping effect of the first test isolation structure 141' and / or the second test isolation structure 142' and the test cathode 150' by detecting the resistance between the first test isolation structure 141' and the second test isolation structure 142'.

[0034] However, in the above structure, since the first test isolation structure 141' is an annular structure and the second test isolation structure 142' is located inside the first test isolation structure 141', the second test isolation structure 142' will be covered in both moving directions of the evaporation source, and the first test isolation structure 141' on any side is overlapped with the test cathode 150', and the test results can be obtained. When the overlap problem is found according to the test results, it can only be determined that there is a problem with the evaporation source, but it is impossible to directly determine in which direction the evaporation source is facing the evaporation chamber that has the problem, and further test analysis needs to be performed, which increases the test difficulty and test cost.

[0035] In view of this, the present embodiment provides a solution for more accurately determining a evaporation chamber having problems in an evaporation source. The solution provided by the present embodiment is described in detail below.

[0036] See also Figure 3 and Figure 4 , Figure 3 and Figure 4 This is a schematic diagram of a display panel motherboard provided in this embodiment. The display panel motherboard may include a substrate 110 and at least one test component disposed on one side of the substrate 110 .

[0037] The substrate 110 may include a flexible substrate or a rigid substrate. An array film layer structure 111 may be provided on one side of the substrate 110, and the array film layer structure 111 may include a buffer layer, an active layer, multiple metal layers, multiple insulating layers, and a planarization layer 114 and other multiple film layer structures. The multiple film layer structures may form multiple thin film transistors (TFTs) at different positions of the array film layer structure 111, and the thin film transistors may cooperate with each other to form multiple pixel driving units.

[0038] The test assembly may include a bonding electrode 161 and a test element group electrically connected to the bonding electrode 161 .

[0039] The test element group includes a first test isolation structure 141 and a second test isolation structure 142 which are separate from each other. The first test isolation structure 141 and the second test isolation structure 142 are disposed on two opposite sides of the bonding electrode 161 .

[0040] The second test isolation structure 142 is electrically connected to the bonding electrode 161. The first test isolation structure 142 may at least partially bond to or not bond to the bonding electrode 161 depending on the evaporation formation of the bonding electrode 161.

[0041] Based on the above design, in this embodiment, by setting the first test isolation structure 141 and the second test isolation structure 142 in the test element group to be located on both sides of the overlapping electrode 161 respectively, and ensuring that the second test isolation structure 142 is overlapped with the overlapping electrode 161, when the overlapping electrode 161 has poor overlap due to evaporation problems, the evaporation chamber with problems in the evaporation source can be more accurately determined according to the relative position of the first test isolation structure 141.

[0042] Optionally, in some possible implementations, in at least one test assembly, the first test isolation structure 141 is disposed on one side of the bonding electrode 161 in the first direction D1, and the second test isolation structure 142 is located on the other side of the bonding electrode 161. The first direction D1 is the extension direction of the preset signal line in the display panel motherboard.

[0043] Optionally, when evaporating to form the overlapping electrode 161, the linear evaporation source usually moves along the extension direction of the preset signal line. Therefore, in this embodiment, the first direction D1 is the same as or opposite to the evaporation direction of the overlapping electrode 161. The evaporation direction is the moving direction of the evaporation source when evaporating to form the overlapping electrode 161. The preset signal line can be a scanning signal line, a data signal line or a power signal line used for the normal operation of the pixel circuit in the display panel, which is usually a scanning signal line.

[0044] For example, see again Figure 3 In a direction parallel to the substrate 110 , the test element group includes a first test isolation structure 141 and a second test isolation structure 142 arranged along an interval, and the bonding electrode 161 is located between the first test isolation structure 141 and the second test isolation structure 142 .

[0045] Further, please see again Figure 4 In some possible implementations, the bonding electrode 161 has a first opening, the second test isolation structure 142 is located in the first opening, and the bonding electrode 161 is connected to at least one side of the second test isolation structure 142. For example, the bonding electrode 161 is connected to at least one side of the second test isolation structure 142 facing the first direction D1 or opposite to the first direction D1, that is, the bonding electrode 161 is connected to at least one side of the second test isolation structure 142 facing the evaporation direction or opposite to the evaporation direction.

[0046] That is, in this embodiment, the orthographic projection of the strapping electrode 161 on the substrate 110 surrounds the orthographic projection of the second test isolation structure 142 on the substrate 110. In this way, it can be ensured that the strapping electrode 161 is connected to at least one side of the second test isolation structure 142, thereby eliminating the influence of the second test isolation structure 142 on the test results.

[0047] In this case, at most only one side (the side facing the second test isolation structure 142) of the first test isolation structure 141 can be overlapped with the overlapping electrode 161. By testing the resistance between the first test isolation structure 141 and the second test isolation structure 142, it can be determined whether the overlapping electrode 161 is well overlapped with the first test isolation structure 141, thereby determining the evaporation effect of the overlapping electrode 161.

[0048] For example, in the case where the evaporation of the overlapping electrode 161 is preferably performed, the overlapping electrode 161 overlaps with the side of the first test isolation structure 141 facing the second test isolation structure 142, and the overlapping electrode 161 also overlaps with the side of the second test isolation structure 142 facing the first test isolation structure 141 and the side away from the first test isolation structure 141. That is, only the side of the first test isolation structure 141 facing the second test isolation structure 142 overlaps with the overlapping electrode 161, while both sides of the second test isolation structure 142 overlap with the overlapping electrode 161. In this way, it can be detected that the resistance between the first test isolation structure 141 and the second test isolation structure 142 in the test assembly is normal, thereby determining that there is no problem with the evaporation chamber in the corresponding direction.

[0049] For another example, if the evaporation condition of the bridge electrode 161 is not good along the second direction D2, the bridge electrode 161 does not contact the first test isolation structure 141, and the bridge electrode 161 is only overlapped with the side of the second test isolation structure 142 away from the first test isolation structure 141. In this way, it can be detected that the resistance between the first test isolation structure 141 and the second test isolation structure 142 in the test assembly is abnormal, thereby determining that there is a problem in the evaporation chamber in the corresponding direction.

[0050] Optionally, the bonding electrode 161 is connected to at least one side of the second test isolation structure 142 facing the first direction D1 or opposite to the first direction D1, for example, the bonding electrode 161 is connected to at least one side of the second test isolation structure 142 facing the evaporation direction or opposite to the evaporation direction. In this way, it can be determined by the test assembly whether there is a problem in the evaporation chamber with the evaporation source facing one direction.

[0051] For some possible implementations, see again Figure 3 and Figure 4 In at least one test assembly, the first test isolation structure 141A is disposed on one side of the bonding electrode 161A along the first direction D1, and the second test isolation structure 142A is located on the other side of the bonding electrode 161A.

[0052] That is, in a direction parallel to the substrate 110 , the test assembly includes a first test isolation structure 141A and a second test isolation structure 142A sequentially arranged along a first direction D1 , and the strapping electrode 161A is located between the first test isolation structure 141A and the second test isolation structure 142A.

[0053] The evaporation source may include an evaporation chamber whose evaporation direction moves in a first direction D1 and another evaporation chamber whose evaporation direction moves in a second direction D2, wherein the first direction D1 is opposite to the second direction D2. Thus, the test assembly may be used to determine whether there is a problem in the evaporation chamber that moves in the second direction D2 in the evaporation source.

[0054] Optionally, see some possible implementations. Figure 5 and Figure 6 In at least one other test assembly, the first test isolation structure 141B is disposed on one side of the bonding electrode 161B according to the second direction D2, and the second test isolation structure 142B is located on the other side of the bonding electrode 161B.

[0055] That is, in a direction parallel to the substrate 110 , the test assembly includes a first test isolation structure 141B and a second test isolation structure 142B sequentially arranged along the second direction D2 , and the strapping electrode 161B is located between the first test isolation structure 141B and the second test isolation structure 142B.

[0056] In this way, the test assembly can be used to determine whether there is a problem in the evaporation chamber facing the first direction D1 in the evaporation source.

[0057] The above two test components cooperate to determine which evaporation chamber in the evaporation source moving direction has a problem.

[0058] Specifically, when there is a problem with the evaporation of the overlapping electrode layer, if the resistance between the first test isolation structure 141A and the second test isolation structure 141B is abnormal, while the resistance between the first test isolation structure 141AB and the second test isolation structure 141BB is normal, it can be determined that there is a problem with the evaporation chamber in the evaporation source facing the second direction D2; if the resistance between the first test isolation structure 141A and the second test isolation structure 141B is normal, while the resistance between the first test isolation structure 141AB and the second test isolation structure 141BB is abnormal, it can be determined that there is a problem with the evaporation chamber in the evaporation source facing the first direction D1.

[0059] Alternatively, in other implementations, see Figure 7 In at least one other test assembly, the first test isolation structure 141C is disposed on one side of the bonding electrode 161C in a third direction D3, and the second test isolation structure 142C is located on the other side of the bonding electrode 161C. The third direction D3 intersects with the first direction D1, for example, the third direction D3 intersects with the evaporation direction of the bonding electrode 163C.

[0060] In this way, the test assembly can be used to determine the overlapping effect of the overlapping electrode 161C and the first test isolation structure 141C in the non-evaporation direction.

[0061] For some possible implementations, see Figure 8, in a direction parallel to the substrate 110 and intersecting with the evaporation direction, the length D1 of the first test isolation structure 141 is greater than the length D2 of the second test isolation structure 141. For example, the length D1 of the first test isolation structure 141 is greater than the length D3 of the bonding electrode 161, and the length D2 of the second test isolation structure 141 is less than the length D3 of the bonding electrode 161. The bonding electrode 161 can be formed by evaporating a conductive material in a whole layer and then performing patterned etching. In this process, the length of the bonding electrode 161 retained after etching can be controlled by controlling the distribution of the etching barrier material (such as photoresist).

[0062] In this way, it can be ensured that the bridging electrode 161 is only bridging one side of the first test isolation structure 141A at most. Moreover, the bridging electrode 161 can cover and surround the second test isolation structure 141B, ensuring that the bridging electrode 161 is bridging at least one side of the second test isolation structure 141B, thereby eliminating the interference of the second test isolation structure 141B on the test results.

[0063] In some possible implementations, a surface of the first test isolation structure 141 facing the second test isolation structure 142 is perpendicular to the evaporation direction.

[0064] That is, the side of the first test isolation structure 141 facing the second test isolation structure 142 is perpendicular to the moving direction of the evaporation source. In this way, the overlapping effect between the first test isolation structure 141 and the overlapping electrode 161 and the overlapping effect between the overlapping electrode 162B can more accurately reflect the evaporation effect of the evaporation chamber with the evaporation source facing different directions.

[0065] In some possible implementations, the first test isolation structure 141 and the second test isolation structure 142 are respectively connected to the test contact 200 through the connection traces 113 in the array film layer structure 111 .

[0066] For example, see again Figure 3 and Figure 5 The array film layer structure 111 includes other film layers 112 located on one side of the substrate 110, a wiring layer located on the side of the other film layers 112 away from the substrate 110, and an insulating layer located on the side of the wiring layer away from the substrate 110, and the test element group is arranged on the side of the insulating layer away from the substrate 110. Among them, the insulating layer includes at least one planarization layer 114 and / or a pixel definition layer 115, and the other film layers 112 include but are not limited to device layers, dielectric layers, wiring layers, etc. located on the substrate 110.

[0067] The first test isolation structure 141 and the second test isolation structure 142 are electrically connected to the connection traces 113 located in the trace layer through vias penetrating the insulating layer.

[0068] See also Fig. 9and Fig.10 The connecting wires 113 connect the first test isolation structure 141 and the second test isolation structure 142 to the test contact 200 respectively.

[0069] In this way, the test equipment can detect the resistance between the first test isolation structure 141 and the second test isolation structure 142 connected through the bonding electrode 161 through the test contact 200 .

[0070] Optionally, the first test isolation structure 141 and the second test isolation structure 142 may both be connected to two test contacts 200 via the connecting wires 113 , and the two test contacts 200 may be used to be connected to current collection and voltage collection terminals of the test equipment, respectively.

[0071] In some possible implementations, the insulating layer includes a first thickness area WA1 and a second thickness area WA2 , a thickness H2 of the second thickness area WA2 is greater than a thickness H1 of the first thickness area WA1 , and the test element group is located in the second thickness area WA2 .

[0072] In this way, the first test isolation structure 141 and the second test isolation structure 142 are located on the boss structure formed by the insulating layer, thereby preventing the etching solution from accumulating between the test isolation structures during the wet etching process and causing damage to the overlapping electrode 161, thereby ensuring the accuracy of subsequent test results.

[0073] Optionally, in some possible implementations, please refer again to Fig.11 and Fig.12 At the point where the first test isolation structure 141 and the second test isolation structure 142 are connected to the connection wiring 113 through the through hole penetrating the insulating layer, the pixel defining layer 115 may cover the side wall of the planarization layer 114 facing the through hole. The material of the pixel defining layer 115 may include an inorganic material. In this way, the pixel defining layer 115 protects the planarization layer 114 at the through hole from being exposed, thereby reducing the risk of water vapor invading the planarization layer 114.

[0074] For some possible implementations, see Fig.13 The display panel motherboard includes a display panel AA and a test area NA1, and the test element group is located in the test area NA1.

[0075] For example, in one example, a bonding area NA2 for connecting with a driving chip or other circuit boards may be provided on one side of the display panel AA, and the test area NA1 may be located on a side of the bonding area NA2 away from the display panel AA.

[0076] In other examples, the test area NA1 may also be located at other positions that do not overlap with the display panel AA, which is not specifically limited in this embodiment.

[0077] In this example, see Fig.14 The isolation structure layer also includes a pixel isolation structure 145 located on the display panel AA, that is, the first test isolation structure 141 and the second test isolation structure 142 are arranged on the same layer as the pixel isolation structure 145 of the display panel AA, and have similar or identical cross-sectional morphology structures. The display panel also includes an insulating layer, and the pixel isolation structure 145 is arranged on a side of the insulating layer away from the substrate 110, and the pixel isolation structure 145 is located in the first thickness area WA1 of the insulating layer.

[0078] The pixel isolation structure 145 encloses and forms an isolation opening arranged at intervals, and the display panel further includes a first pixel electrode 123, a pixel light emitting unit 153, and a second pixel electrode 163 which are at least partially located in the isolation opening and are stacked in a direction away from the substrate 110. The second pixel electrode 163 is arranged in the same layer as the lap electrode 161. The second pixel electrode 163 extends from the isolation opening to the side of the pixel isolation structure 145 facing the isolation opening and is electrically connected to the pixel isolation structure 145.

[0079] For example, in the display panel AA, the array film layer structure 111 may further include a first pixel electrode 123 located on a side of the planarization layer 114 away from the substrate 110. The pixel defining layer 115 is located on a side of the first pixel electrode 123 away from the substrate 110, and the pixel defining layer 115 includes a pixel opening that exposes at least a portion of the first pixel electrode 123. The pixel isolation structure 145 is located on a side of the pixel defining layer 115 away from the substrate 110, and the orthographic projection of the pixel opening on the substrate 110 is located within the orthographic projection of the isolation opening on the substrate 110, that is, the isolation opening is connected with the pixel opening to expose at least a portion of the first pixel electrode 123.

[0080] At least a portion of the pixel light emitting unit 153 is located in the pixel opening and / or the isolation opening, and is located on a side of the first pixel electrode 123 away from the substrate 110. At least a portion of the second pixel electrode 163 is located in the pixel opening and / or the isolation opening, and is located on a side of the pixel light emitting unit 153 away from the substrate 110. The second pixel electrode 163 extends from the isolation opening and / or the pixel opening to a side of the pixel isolation structure 145 facing the isolation opening, and contacts the pixel isolation structure 145.

[0081] Thus, in this embodiment, the manufacturing process of the first test isolation structure 141 and the second test isolation structure 142 is the same as that of the pixel isolation structure 145 located in the display panel AA, and the manufacturing process of the second pixel electrode 163 is the same as that of the overlapping electrode 161A and the overlapping electrode 161B. Therefore, the overlapping effect of the first test isolation structure 141 and the overlapping electrode 161 can directly reflect the overlapping effect of the pixel isolation structure 145 and the second pixel electrode 163 in the display panel AA.

[0082] In some possible implementations, when only one side of the second pixel electrode 163 extends to connect with the pixel isolation structure 145, that is, there is only one evaporation direction to prepare the second pixel electrode 163 to connect with the pixel isolation structure 145 on one side, only at least one test element group can be set, and the first test isolation structure 141 and the second test isolation structure 142 in at least one test element group are arranged in the same direction, which is the side where the second pixel electrode 163 overlaps with the pixel isolation structure 145. For example, if the side of the second pixel electrode 163 facing the first direction D1 overlaps with the pixel isolation structure 145, the first test isolation structure 141 is set on the side of the overlapping electrode 161 in the first direction D1.

[0083] In some possible implementations, when the second pixel electrode 163 has two sides extending to connect with the pixel isolation structure 145, there will be two oppositely arranged evaporation directions to prepare the second pixel electrode 163 connected to the pixel isolation structure 145 located on the opposite sides, and at least two test element groups need to be set, in which the first test isolation structure 141 and the second test isolation structure 142 in one test element group are arranged in one evaporation direction, and the first test isolation structure 141 and the second test isolation structure 142 in the other test element group are arranged in the other evaporation direction. For example, if one of the evaporation directions is a first direction, the first test isolation structure 141 is arranged on one side of the overlapping electrode 161 in the first direction. If the other evaporation direction is a second direction opposite to the first direction, the first test isolation structure 141 is located on the side of the overlapping electrode 161 opposite to the first direction.

[0084] For some possible implementations, please refer again to Figure 3 and Figure 5 The display panel motherboard further includes a test light emitting unit 151 located on the side of the bonding electrode 161 close to the substrate 110. The test light emitting unit 151 and the pixel light emitting unit 153 are arranged on the same layer. That is, the test light emitting unit 151 is formed in the test area NA1 while the pixel light emitting unit 153 is formed in the display panel AA.

[0085] It should be noted that in this embodiment, it is not necessary to set a test electrode corresponding to the first pixel electrode 123 at the position corresponding to the test element group, and a test electrode corresponding to the first pixel electrode 123 may be set in the test element group and the corresponding position, which is not specifically limited in this embodiment.

[0086] In this embodiment, the pixel light-emitting unit 153 includes a first light-emitting unit and a second light-emitting unit, and the display panel motherboard includes at least two test element groups, which are respectively arranged corresponding to the first light-emitting unit and the second light-emitting unit, and the test element group arranged corresponding to the first light-emitting unit has the same material as the first light-emitting unit, and the test element group arranged corresponding to the first light-emitting unit has the same material as the first light-emitting unit.

[0087] For example, in the case where the display panel includes at least two sub-pixels of luminous colors, the display panel motherboard includes at least two test element groups, and the luminous colors of the test luminous units 151 corresponding to the at least two test element groups are different. If one side of the second pixel electrode 163 overlaps with the pixel isolation structure 145, at least one test element group is set to test the overlap of the second pixel electrode 163 corresponding to the first luminous unit, and at least one test element group is also set to test the overlap of the second pixel electrode 163 corresponding to the second luminous unit. If both sides of the second pixel electrode 163 overlap with the pixel isolation structure 145, at least two test element groups with different arrangement directions of the first test isolation structures 141 are required to test the overlap of the second pixel electrode corresponding to the first luminous unit, and at least two test element groups with different arrangement directions of the first test isolation structures 141 are also required to test the overlap of the second pixel electrode corresponding to the second luminous unit.

[0088] It should be noted that, in the present embodiment, the test light emitting unit 151 does not actually emit light, and the light emitting color of the test light emitting unit 151 refers to the light emitting color that the material used by the test light emitting unit 151 can generate when powered on.

[0089] That is, in this embodiment, since the pixel light-emitting unit 153 and the second pixel electrode 163 corresponding to sub-pixels of different colors are formed in different evaporation processes and have certain differences, at least one test element group can be set for sub-pixels of different colors respectively to test the overlapping effect of the second pixel electrode 163 and the pixel isolation structure 145 of sub-pixels of different colors.

[0090] In some possible implementations, in at least two test element groups having the same luminous color of the test light-emitting unit 151, along the first direction D1, the first test isolation structure 141 and the second test isolation structure 142 are arranged in sequence in at least one test element group, and the second test isolation structure 142 and the first test isolation structure 141 are arranged in sequence in another test element group.

[0091] That is, in at least two test element groups whose test light emitting units 151 emit the same light color, the arrangement directions of the first test isolation structures 141 and the second test isolation structures 142 are different.

[0092] That is, for each sub-pixel of a light-emitting color, at least two test element groups may be set. Figure 4 and Figure 6 The test element groups of the two arrangements shown, or other test element groups of more arrangements can also be set. The arrangement is that the arrangement direction of the first test isolation structure 141 and the second test isolation structure 142 has a preset angle with the first direction, such as 30 degrees, 45 degrees, 60 degrees, 90 degrees, etc.

[0093] For some possible implementations, see Fig.15 In at least two test element groups with the same luminous color of the test light-emitting unit 151, two adjacent test element groups share a first test isolation structure 141, wherein the second test isolation structure 142 of one test element group is arranged on the side of the first test isolation structure 141 in the extension direction of the preset signal line in the display panel motherboard, and the second test isolation structure 142 of the other test element group is arranged on the side of the first test isolation structure 141 away from the extension direction of the preset signal line in the display panel motherboard.

[0094] For example, along the first direction D1, the second test isolation structure 142A and the second test isolation structure 142B are respectively located on both sides of the first test isolation structure 141, the strapping electrode 161A is located between the second test isolation structure 142A and the first test isolation structure 141, and the strapping electrode 161B is located between the second test isolation structure 142B and the first test isolation structure 141.

[0095] For other possible implementations, see Fig.16 In at least two test element groups with the same luminous color of the test luminous unit, two adjacent test element groups share a second test isolation structure 142, wherein the first test isolation structure 141 of one test element group is arranged on the side of the second test isolation structure in the extension direction of the preset signal line in the display panel motherboard, and the first test isolation structure 141 of the other test element group is arranged on the side of the second test isolation structure 142 away from the extension direction of the preset signal line in the display panel motherboard.

[0096] For example, along the first direction D1, the first test isolation structure 141A and the first test isolation structure 141B are respectively located on both sides of the second test isolation structure 142, and the strapping electrode 161 and the second test isolation structure 142 are located between the first test isolation structure 141A and the first test isolation structure 141B.

[0097] For some possible implementations, see Fig.17The first test isolation structure 141, the second test isolation structure 142 and the pixel isolation structure 145 include a first sublayer 1401 and a second sublayer 1402 stacked in a direction away from the substrate 110, and the orthographic projection of the first sublayer 1401 on the substrate 110 is located within the orthographic projection of the second sublayer 1402 on the substrate 110. That is, the first sublayer 1401 is retracted compared to the second sublayer 1402, forming an undercut structure.

[0098] Optionally, the material of the first sub-layer 1401 includes aluminum, and / or the material of the second sub-layer 1402 includes titanium.

[0099] Optionally, the first test isolation structure 141 , the second test isolation structure 142 , and the pixel isolation structure 145 may further include a third sublayer 1403 located between the first sublayer 1401 and the substrate 110 .

[0100] Optionally, the orthographic projection of the third sublayer 1403 on the substrate 110 is located within the orthographic projection of the second sublayer 1402 on the substrate 110. Optionally, the orthographic projection of the first sublayer 1401 on the substrate 110 is located within the orthographic projection of the third sublayer 1403 on the substrate 110.

[0101] Optionally, the material of the third sublayer 1403 includes molybdenum.

[0102] In some possible implementations, the display panel motherboard further includes a first packaging layer, see Fig.18 and Fig.19 The first packaging layer includes a test packaging unit 171 . The first test packaging unit 171 is located on a side of the bonding electrode 161 away from the substrate 110 and covers the bonding electrode 161 .

[0103] Optionally, at least a portion of the first test package unit 171 extends from between the first test isolation structure 141 and the second test isolation structure 142 to a side of the first test isolation structure 141 and the second test isolation structure 142 away from the substrate 110 .

[0104] Accordingly, please refer again to Fig.14 The first encapsulation layer further includes a pixel encapsulation unit 173 located on a side of the second pixel electrode 163 away from the substrate 110 , and at least a portion of the pixel encapsulation unit 173 extends from the isolation opening to a side of the pixel isolation structure 145 away from the substrate 110 .

[0105] Optionally, the display panel motherboard further includes a second encapsulation layer 180 and a third encapsulation layer 190 which are located on a side of the first encapsulation layer away from the substrate 110 and are stacked in a direction away from the substrate 110 .

[0106] Optionally, the materials of the first encapsulation layer and the third encapsulation layer 190 include inorganic materials, and the material of the second encapsulation layer 180 includes organic materials. For example, the first encapsulation layer and the third encapsulation layer 190 can be formed by chemical vapor deposition (CVD), and the second encapsulation layer 180 can be formed by inkjet printing (IJP).

[0107] This application also provides a method for manufacturing a display panel motherboard, see Fig. 20 , the method may include the following steps.

[0108] In step S210 , a substrate 110 is provided.

[0109] Step S220 , forming at least one test component on one side of the substrate 110 , the test component may include a bonding electrode 161 and a test element group electrically connected to the bonding electrode 161 .

[0110] The test element group includes a first test isolation structure 141 and a second test isolation structure 142 which are separate from each other. The first test isolation structure 141 and the second test isolation structure 142 are disposed on two opposite sides of the bonding electrode 161 .

[0111] The second test isolation structure 142 is electrically connected to the bonding electrode 161. The first test isolation structure 142 may at least partially bond to or not bond to the bonding electrode 161 depending on the evaporation formation of the bonding electrode 161.

[0112] In some possible implementations, the display panel motherboard includes a display panel AA and a test area NA1 , and the isolation structure layer further includes a pixel isolation structure 145 located on the display panel AA.

[0113] In step S220 , a first test isolation structure 141 and a second test isolation structure 142 may be formed in the test area NA1 , and a pixel isolation structure 145 may be formed in the display panel AA. The pixel isolation structure 145 surrounds an isolation opening.

[0114] A lap electrode 161 is arranged between the first test isolation structure 141 and the second test isolation structure 142, and a second pixel electrode 163 at least partially located in the isolation opening is formed on the display panel AA. The second pixel electrode 163 extends from the isolation opening to the pixel isolation structure 145 and contacts the pixel isolation structure 145 on one side facing the isolation opening.

[0115] Optionally, the method for manufacturing the display panel provided in this embodiment may further include the following steps.

[0116] Step S310 , testing the test element group to determine the overlapping effect between the second pixel electrode 163 and the pixel isolation structure 145 .

[0117] Step S320, after the test is completed, cutting the test area NA1.

[0118] That is, in this embodiment, the area where the test element group is located can be removed after the test is completed.

[0119] In some possible implementations, the evaporation directions of the second pixel electrode 163 and the strapping electrode 161 include a first direction and a second direction that are arranged opposite to each other. The test assembly includes at least one first test isolation structure 141A, a strapping electrode 161A, and a second test isolation structure 142A distributed along the first direction; the test assembly also includes at least one second test isolation structure 142B, a strapping electrode 161B, and a first test isolation structure 141B distributed along the second direction, such as Fig.10 shown.

[0120] Step S310 may include the following sub-steps.

[0121] Step S311, obtaining a first lap resistance between the first test isolation structure 141A and the second test isolation structure 142A distributed along the first direction D1 through a detection device; obtaining a second lap resistance between the first test isolation structure 141B and the second test isolation structure 142B distributed along the second direction D2 through a detection device.

[0122] Step S312, determining the overlapping effect of the second pixel electrode 163 overlapping the pixel isolation structure 145 along the second direction D2 according to the first overlapping resistance; determining the overlapping effect of the second pixel electrode 163 overlapping the pixel isolation structure 145 along the first direction D1 according to the second overlapping resistance.

[0123] In this embodiment, in this embodiment, the manufacturing process of the first test isolation structure 141 and the second test isolation structure 142 is the same as that of the pixel isolation structure 145 of the display panel AA, and the manufacturing process of the second pixel electrode 163 is the same as that of the overlapping electrode 161. The overlapping effect of the first test isolation structure 141 and the overlapping electrode 161 can directly reflect the overlapping effect of the pixel isolation structure 145 and the second pixel electrode 163.

[0124] Furthermore, the first test isolation structure 141 in the test element group is overlapped with the overlap electrode 161 on at most one side, so that when the overlap electrode has poor overlap due to evaporation problems, the evaporation chamber with problems in the evaporation source can be more accurately determined.

[0125] In some other possible implementations, in step S310, the second pixel electrode 163 and the pixel isolation structure 145 that are overlapped on one side may be overlapped in the direction of the overlapped second pixel electrode 163 facing the first direction D1. Fig. 9 As shown, the method may include the following steps.

[0126] Step S313, obtaining a first lap resistance between the first test isolation structure 141 and the second test isolation structure 142 distributed along the first direction D1 by a detection device; Step S314 , determining the overlapping effect of the second pixel electrode 163 overlapping the pixel isolation structure 145 along the first direction D1 according to the first overlapping resistance.

[0127] The present application also provides an electronic device, which includes the display panel provided in the present application, or includes a display panel prepared by the display panel motherboard manufacturing method provided in this embodiment. The electronic device may include a mobile phone, a tablet computer, a smart wearable device, a television, a laptop computer, a monitor, and other devices with a display function.

[0128] In summary, the present application provides a display panel motherboard, a manufacturing method for a display panel motherboard, and an electronic device, by setting a test isolation structure in a test element group to overlap with a overlapping electrode on only one side, and setting two test element groups for testing the effects of the test isolation structure and the overlapping electrode in two relative directions, thereby being able to more accurately determine the evaporation chamber with problems in the evaporation source when the overlapping electrode has poor overlap due to evaporation problems.

[0129] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0130] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A display panel motherboard, characterized in that: The display panel motherboard comprises: substrate; At least one test assembly disposed on one side of the substrate, the test assembly comprising a bonding electrode and a test element group electrically connected to the bonding electrode; The test element group includes a first test isolation structure and a second test isolation structure which are separate from each other, wherein the first test isolation structure and the second test isolation structure are arranged on two opposite sides of the bonding electrode; The second test isolation structure is electrically connected to the bonding electrode.

2. The display panel motherboard according to claim 1, characterized in that: In at least one of the test components, the first test isolation structure is arranged on one side of the bonding electrode in a first direction, and the second test isolation structure is located on the other side of the bonding electrode; the first direction is the same as or opposite to the extension direction of the preset signal line in the display panel motherboard; Preferably, in at least one other test assembly, the first test isolation structure is arranged on one side of the bonding electrode in a second direction, and the second test isolation structure is located on the other side of the bonding electrode; the second direction is opposite to the first direction; Preferably, in at least one other test component, the first test isolation structure is arranged on one side of the overlapping electrode in a third direction, and the second test isolation structure is located on the other side of the overlapping electrode; the third direction intersects with the extension direction of some signal lines in the display panel motherboard.

3. The display panel motherboard according to claim 2, characterized in that: The bonding electrode has a first opening, the second test isolation structure is located in the first opening, and the bonding electrode is connected to at least one side surface of the second test isolation structure; Preferably, the strapping electrode is connected to at least one side surface of the second test isolation structure facing the first direction or opposite to the first direction.

4. The display panel motherboard according to claim 2, characterized in that: In a direction parallel to the substrate and intersecting the first direction, a length of the first test isolation structure is greater than a length of the second test isolation structure.

5. The display panel motherboard according to claim 4, characterized in that: The extension direction of the first test isolation structure is arranged perpendicular to the first direction; Preferably, a surface of the first test isolation structure facing the second test isolation structure is perpendicular to the first direction.

6. The display panel motherboard according to claim 1, characterized in that: The display panel further comprises a wiring layer located at one side of the substrate and an insulating layer located at a side of the wiring layer away from the substrate, the test element group is arranged at a side of the insulating layer away from the substrate; the first test isolation structure and the second test isolation structure are respectively electrically connected to a connecting wiring located in the wiring layer through a through hole penetrating the insulating layer, and the connecting wiring respectively connects the first test isolation structure and the second test isolation structure to a test contact; Preferably, the insulating layer comprises at least one planarization layer and / or a pixel defining layer.

7. The display panel motherboard according to claim 6, characterized in that: The insulating layer includes a first thickness region and a second thickness region, the thickness of the second thickness region is greater than the thickness of the first thickness region, and the test element group is located in the second thickness region.

8. The display panel motherboard according to claim 1, characterized in that: The display panel motherboard includes a display panel and a test area; the test element group is located in the test area; The display panel includes a pixel isolation structure located at one side of the substrate, the first test isolation structure and the second test isolation structure are arranged in the same layer as the pixel isolation structure, and the pixel isolation structure includes isolation openings arranged at intervals; The display panel further includes a first pixel electrode, a pixel light emitting unit and a second pixel electrode which are at least partially located in the isolation opening and are stacked in a direction away from the substrate; The second pixel electrode is arranged in the same layer as the bridging electrode; The second pixel electrode extends from the isolation opening to a side of the pixel isolation structure facing the isolation opening and is electrically connected to the pixel isolation structure.

9. The display panel motherboard according to claim 8, characterized in that: The display panel motherboard further comprises a test light emitting unit located on a side of the bonding electrode close to the substrate; the test light emitting unit and the pixel light emitting unit are arranged on the same layer; Preferably, the pixel light-emitting unit includes a first light-emitting unit and a second light-emitting unit, the display panel motherboard includes at least two test element groups, at least two test element groups are respectively arranged corresponding to the first light-emitting unit and the second light-emitting unit, the test element group arranged corresponding to the first light-emitting unit has the same material as the first light-emitting unit, and the test element group arranged corresponding to the first light-emitting unit has the same material as the first light-emitting unit. Preferably, in at least two of the test element groups having the same luminous color of the test luminous unit, along the first direction, the first test isolation structure and the second test isolation structure in at least one of the test element groups are arranged in sequence, and the second test isolation structure and the first test isolation structure in another of the test element groups are arranged in sequence; Preferably, in at least two of the test element groups having the same luminous color of the test luminous unit, two adjacent test element groups share the first test isolation structure, wherein the second test isolation structure of one of the test element groups is arranged on one side of the first test isolation structure in the extension direction of the preset signal line in the display panel motherboard, and the second test isolation structure of the other test element group is arranged on one side of the first test isolation structure away from the extension direction of the preset signal line in the display panel motherboard; Preferably, among at least two of the test element groups having the same luminous color of the test light-emitting unit, two adjacent test element groups share the second test isolation structure, wherein the first test isolation structure of one of the test element groups is arranged on the side of the second test isolation structure in the extension direction of the preset signal line in the display panel motherboard, and the first test isolation structure of the other test element group is arranged on the side of the second test isolation structure away from the extension direction of the preset signal line in the display panel motherboard.

10. The display panel motherboard according to claim 8, characterized in that: The first test isolation structure, the second test isolation structure and the pixel isolation structure include a first sublayer and a second sublayer stacked in a direction away from the substrate, and an orthographic projection of the first sublayer on the substrate is located within an orthographic projection of the second sublayer on the substrate; Preferably, the material of the first sublayer includes aluminum, and / or the material of the second sublayer includes titanium; Preferably, the first test isolation structure, the second test isolation structure and the pixel isolation structure further include a third sublayer located between the first sublayer and the substrate; Preferably, the orthographic projection of the third sub-layer on the substrate is located within the orthographic projection of the second sub-layer on the substrate; Preferably, the material of the third sublayer includes molybdenum.

11. The display panel motherboard according to claim 8, characterized in that: The display panel motherboard further comprises a test packaging unit, wherein the test packaging unit is located at a side of the bonding electrode away from the substrate and covers the bonding electrode; Preferably, at least a portion of the test package unit extends from between the first test isolation structure and the second test isolation structure to a side of the first test isolation structure and the second test isolation structure away from the substrate; Preferably, the display panel motherboard further comprises a pixel encapsulation unit located at a side of the second pixel electrode away from the substrate, at least a portion of the pixel encapsulation unit extends from the isolation opening to a side of the pixel isolation structure away from the substrate; the pixel encapsulation unit is disposed in the same layer as the test encapsulation unit; Preferably, the display panel motherboard further comprises a second encapsulation layer and a third encapsulation layer which are located on a side of the pixel encapsulation unit and the test encapsulation unit away from the substrate and are stacked in a direction away from the substrate; Preferably, the materials of the pixel encapsulation unit, the test encapsulation unit and the third encapsulation layer include inorganic materials, and the material of the second encapsulation layer includes organic materials.

12. A method for manufacturing a display panel motherboard, characterized in that: The method comprises: providing a substrate; At least one test assembly is formed on one side of the substrate, the test assembly comprising a bonding electrode and a test element group electrically connected to the bonding electrode; The test element group includes a first test isolation structure and a second test isolation structure which are separate from each other, and the first test isolation structure and the second test isolation structure are arranged on two opposite sides of the bonding electrode; The second test isolation structure is electrically connected to the bonding electrode.

13. The method for manufacturing a display panel according to claim 12, characterized in that: The display panel motherboard includes a display panel and a test area, and the test component is arranged in the test area; The display panel further comprises a pixel isolation structure located at one side of the substrate, wherein the pixel isolation structure is arranged at the same layer as the first test isolation structure and the second test isolation structure; The step of forming at least one test component on one side of the substrate comprises: forming the first test isolation structure and the second test isolation structure in the test area, and forming a pixel isolation structure in the display panel, wherein the pixel isolation structure includes isolation openings arranged at intervals; A lap electrode is provided between the first test isolation structure and the second test isolation structure, and a second pixel electrode is formed on the display panel, at least part of which is located in the isolation opening, and the second pixel electrode extends from the isolation opening to the side of the pixel isolation structure facing the isolation opening and contacts the pixel isolation structure; Preferably, the method further comprises: For the test element group, determining the overlapping effect of the second pixel electrode and the pixel isolation structure; After the test is completed, the test area is cut.

14. The method for manufacturing a display panel according to claim 13, wherein: The evaporation directions of the second pixel electrode and the strapping electrode include a first direction and a second direction that are arranged opposite to each other; the test assembly includes at least one of the first test isolation structure, the strapping electrode and the second test isolation structure distributed along the first direction; the test assembly also includes at least one of the second test isolation structure, the strapping electrode and the first test isolation structure distributed along the second direction; The step of determining the overlapping effect between the second pixel electrode and the pixel isolation structure for the test element group further includes: Acquire a first lap resistance between the first test isolation structure and the second test isolation structure distributed along a first direction by means of a detection device; acquire a second lap resistance between the first test isolation structure and the second test isolation structure distributed along a second direction by means of a detection device; The overlapping effect of the second pixel electrode when overlapping with the pixel isolation structure along the second direction is determined according to the first overlapping resistance; the overlapping effect of the second pixel electrode when overlapping with the pixel isolation structure along the first direction is determined according to the second overlapping resistance.

15. A display device, characterized in that: The display device comprises a display panel manufactured by the method for manufacturing a display panel motherboard as claimed in claim 14.

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