Array substrate, display panel and display device

Abstract

An array substrate, a display panel and a display device. The array substrate comprises: a substrate (1); a plurality of gate lines (2) located on one side of the substrate (1) and extending along a first direction (X); a plurality of data lines (3) extending along a second direction (Y); a plurality of pixel electrodes (4), the pixel electrode comprising: a first pixel electrode (41) located on one side of the gate line (2), and a second pixel electrode (42) located on the other side of the gate line (2); the first pixel electrode (41) comprises: a first sub-pixel electrode (411) distributed along the first direction (X), and a second sub-pixel electrode (412); the second pixel electrode (42) comprises: a third sub-pixel electrode (421) distributed along the first direction (X), and a fourth sub-pixel electrode (422); one of the first sub-pixel electrode (411) and the second sub-pixel electrode (412) is electrically connected to one of the third sub-pixel electrode (421) and the fourth sub-pixel electrode (422).

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to the international application filed on August 29, 2023, with the State Intellectual Property Office of the People's Republic of China, application number PCT / CN2023 / 115605, and application name "Array substrate, display panel and display device", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the field of semiconductor technology, in particular to an array substrate, a display panel and a display device. BACKGROUND

[0004] The name of UV2A comes from the multiplication of ultraviolet (UV) and the VA mode of liquid crystal panel. This technology can precisely control the alignment of liquid crystal molecules through ultraviolet light, greatly improving the light transmittance.

[0005] The key of UV2A is to use a special polymer material as an alignment film to control the tilt of liquid crystal molecules along the direction of ultraviolet light with high precision. The precision unit is picometer (one millionth of a meter). The advantage of UV2A is that the liquid crystal panel is a simple structure without protrusions and slits. This "dream of liquid crystal technicians" has been explored for more than 30 years. Today, with the three conditions of new materials, production equipment and perfect processing process, this dream has come true. The simple structure of the liquid crystal panel not only improves the production efficiency, but also has many advantages in picture quality. SUMMARY

[0006] The present disclosure provides an array substrate, a display panel and a display device. The array substrate comprises:

[0007] a substrate;

[0008] a plurality of gate lines located on one side of the substrate and extending along a first direction;

[0009] a plurality of data lines extending along a second direction;

[0010] a plurality of pixel electrodes, the pixel electrodes comprising: a first pixel electrode located on one side of the gate line, and a second pixel electrode located on the other side of the gate line; the first pixel electrode comprising: a first sub-pixel electrode distributed along the first direction, and a second sub-pixel electrode; the second pixel electrode comprising: a third sub-pixel electrode distributed along the first direction, and a fourth sub-pixel electrode;

[0011] One of the first sub-pixel electrode and the second sub-pixel electrode is electrically connected to one of the third sub-pixel electrode and the fourth sub-pixel electrode.

[0012] In a possible implementation, the array substrate further comprises: a plurality of transistors; the plurality of transistors are electrically connected to the same pixel electrode, and are electrically connected to the same data line and the same gate line;

[0013] The second sub-pixel electrode is located on a side of the first sub-pixel electrode away from the electrically connected data line, and the fourth sub-pixel electrode is located on a side of the third sub-pixel electrode away from the electrically connected data line; the first sub-pixel electrode is electrically connected to the fourth sub-pixel electrode.

[0014] In a possible implementation, the array substrate further comprises: a first signal line extending along the second direction; the plurality of transistors comprise: a first transistor, a second transistor, and a third transistor;

[0015] The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode;

[0016] The control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second sub-pixel electrode and the third sub-pixel electrode;

[0017] The control electrode of the third transistor is electrically connected to the gate line, the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is multiplexed with the first signal line.

[0018] In a possible implementation, the pixel electrode further comprises: a first sub-pixel electrode protrusion connected to a side of the first sub-pixel electrode facing the third sub-pixel electrode; and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode through the first sub-pixel electrode protrusion.

[0019] In a possible implementation, the pixel electrode further comprises: a connecting portion connecting the first sub-pixel electrode and the fourth sub-pixel electrode; the connecting portion comprises: a first connecting portion extending along the second direction, and a second connecting portion extending along a third direction; the third direction intersects the first direction and the second direction;

[0020] One end of the first connecting portion is electrically connected to one end of the first sub-pixel electrode on a side facing the third sub-pixel electrode, and the other end of the first connecting portion is electrically connected to the second connecting portion; and the other end of the second connecting portion is electrically connected to one end of the fourth sub-pixel electrode on a side facing the second sub-pixel electrode.

[0021] In a possible implementation, the pixel electrode further includes: a third sub-pixel electrode protrusion connected to the third sub-pixel electrode towards the first sub-pixel electrode side.

[0022] The second electrode of the second transistor is electrically connected to the third sub-pixel electrode through the third sub-pixel electrode protrusion.

[0023] In a possible implementation, the pixel electrode further includes: a second sub-pixel electrode protrusion and a second sub-pixel electrode extension extending along the second direction; one end of the second sub-pixel electrode extension is electrically connected to one end of the second sub-pixel electrode towards the fourth sub-pixel electrode side, and the other end is electrically connected to the second sub-pixel electrode protrusion.

[0024] The second electrode of the second transistor is electrically connected to the second sub-pixel electrode through the second sub-pixel electrode protrusion.

[0025] In a possible implementation, the extension direction of the second sub-pixel electrode extension is parallel to the extension direction of the first connection part.

[0026] In a possible implementation, the second sub-pixel electrode protrusion has a second sub-pixel electrode protrusion outer edge extending away from the second sub-pixel electrode side and along the first direction; and the third sub-pixel electrode protrusion has a third sub-pixel electrode protrusion outer edge extending away from the third sub-pixel electrode side and along the first direction.

[0027] The extension line of the second sub-pixel electrode protrusion outer edge coincides with the extension line of the third sub-pixel electrode protrusion outer edge; or the extension line of the second sub-pixel electrode protrusion outer edge at least partially overlaps the third sub-pixel electrode protrusion; or the extension line of the third sub-pixel electrode protrusion outer edge at least partially overlaps the second sub-pixel electrode protrusion.

[0028] In a possible implementation, the center of the third sub-pixel electrode protrusion is parallel to the connection line of the center of the first sub-pixel electrode protrusion along the second direction.

[0029] In a possible implementation, the second electrode of the first transistor includes: a first transistor first part extending along the first direction.

[0030] The first transistor first part has an overlapping area with the first sub-pixel electrode protrusion in the orthographic projection of the substrate.

[0031] In a possible implementation, the second electrode of the second transistor comprises: a first part of the second transistor extending along the first direction, and a second part of the second transistor extending along the second direction and electrically connected to one end of the first part of the second transistor.

[0032] The first part of the second transistor has an overlapping area with the projection of the third sub-pixel electrode on the substrate, and the second part of the second transistor has an overlapping area with the projection of the second sub-pixel electrode on the substrate.

[0033] In a possible implementation, at least part of the projection of the second part of the second transistor on the substrate overlaps at least part of the projection of the second sub-pixel electrode extension on the substrate.

[0034] In a possible implementation, the first signal line has a recessed part; at least part of the projection of the second part of the second transistor on the substrate is located in an area surrounded by the projection of the recessed part on the substrate.

[0035] In a possible implementation, the first signal line comprises: a first signal part, a second signal part, and a third signal part distributed along the second direction in sequence, a fourth signal part extending along the first direction and connecting the second signal part and the first signal part, and a fifth signal part extending along the first direction and connecting the second signal part and the third signal part.

[0036] An extension line of the first signal part coincides with an extension line of the third signal part; an extension line of the second signal part does not coincide with the extension line of the first signal part; the second signal part, the fourth signal part, and the fifth signal part constitute the recessed part, and the fourth signal part and / or the fifth signal part at least partially overlaps with the pixel electrode.

[0037] In a possible implementation, the array substrate further comprises: a first common wire extending along the first direction on one side of the gate line; and the plurality of transistors comprises: a first transistor, a second transistor, and a third transistor electrically connected to the data line.

[0038] The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode.

[0039] The control electrode of the second transistor is electrically connected with the gate line, the first electrode of the second transistor is electrically connected with the data line, and the second electrode of the second transistor is electrically connected with the second sub-pixel electrode and the third sub-pixel electrode.

[0040] The control electrode of the third transistor is electrically connected with the gate line, the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is electrically connected with the first common wire.

[0041] In a possible implementation, the first sub-pixel electrode is electrically connected with the fourth sub-pixel electrode; the array substrate further includes: a plurality of transistors, a third common wire located on one side of the gate line and extending along the first direction, and an auxiliary gate line located between the gate line and the third common wire and extending along the first direction; the plurality of transistors include: a first transistor, a second transistor, and a third transistor.

[0042] The control electrode of the first transistor is electrically connected with the gate line, the first electrode of the first transistor is electrically connected with the data line, and the second electrode of the first transistor is electrically connected with the first sub-pixel electrode and the fourth sub-pixel electrode.

[0043] The control electrode of the second transistor is electrically connected with the gate line, the first electrode of the second transistor is electrically connected with the data line, and the second electrode of the second transistor is electrically connected with the second sub-pixel electrode and the third sub-pixel electrode.

[0044] The control electrode of the third transistor is electrically connected with the auxiliary gate line, the first electrode of the third transistor is multiplexed with the second electrode of the first transistor, and the second electrode of the third transistor has an overlapping area with the first common wire in the orthographic projection of the substrate.

[0045] In a possible implementation, the pixel electrode further includes: a connecting portion connecting the first sub-pixel electrode and the fourth sub-pixel electrode, and a first overlap portion connected to the connecting portion; the connecting portion includes: a third connecting portion extending along the first direction, a fourth connecting portion, and a fifth connecting portion extending along the second direction.

[0046] One end of the third connecting portion is connected with the first sub-pixel electrode, one end of the fourth connecting portion is connected with the fourth sub-pixel electrode, one end of the fifth connecting portion is connected with the other end of the third connecting portion, and the other end of the fifth connecting portion is connected with the other end of the fourth connecting portion; the first overlap portion is electrically connected to the third connecting portion and away from one side of the first sub-pixel electrode connected with the third connecting portion.

[0047] The second electrode of the first transistor is electrically connected with the first sub-pixel electrode and the fourth sub-pixel electrode through the first overlap part.

[0048] In a possible implementation, the control electrode of the third transistor is electrically connected with the gate line; the third transistor and the first transistor are located on different sides of the projection of the fifth connection part on the substrate.

[0049] In a possible implementation, the pixel electrode further includes a first transfer part extending along the first direction, a second transfer part extending along a second direction, and a second overlap part;

[0050] One end of the first transfer part is electrically connected with one end of the second sub-pixel electrode towards the fourth sub-pixel electrode, and the other end of the first transfer part is electrically connected with one end of the second transfer part; the other end of the second transfer part is electrically connected with the second overlap part.

[0051] The second electrode of the second transistor is electrically connected with the second sub-pixel electrode through the second overlap part.

[0052] In a possible implementation, the second transfer part is parallel to the extending direction of the fifth connection part.

[0053] In a possible implementation, the control electrode of the third transistor is electrically connected with the auxiliary gate line; the third transistor and the first transistor are located on the same side of the projection of the fifth connection part on the substrate.

[0054] In a possible implementation, the fifth connection part includes a first sub-connection part, a second sub-connection part, and a third sub-connection part.

[0055] The first sub-connection part extends along a fourth direction, one end of the first sub-connection part is electrically connected with the other end of the third connection part, and the other end of the first sub-connection part is electrically connected with the second sub-connection part; the fourth direction intersects with the first direction and intersects with the second direction.

[0056] The second sub-connection part extends along the second direction, and the other end of the second sub-connection part is electrically connected with one end of the third sub-connection part.

[0057] The third sub-connection part extends along the fourth direction, and the other end of the third sub-connection part is electrically connected with the other end of the fourth connection part.

[0058] In a possible implementation, the pixel electrode further includes: a first adapter extending along the third direction, and a second adapter extending along the second direction, and a second lap joint;

[0059] One end of the first adapter is electrically connected to one end of the second sub-pixel electrode toward the fourth sub-pixel electrode, and the other end of the first adapter is electrically connected to one end of the second adapter; the other end of the second adapter is electrically connected to the second lap joint.

[0060] The second electrode of the second transistor is electrically connected to the second sub-pixel electrode through the second lap joint.

[0061] In a possible implementation, the pixel electrode further includes: a third adapter extending along the first direction, and a third lap joint.

[0062] One end of the third adapter is electrically connected to one end of the third sub-pixel electrode toward the first sub-pixel electrode, and the other end of the third adapter is electrically connected to the third lap joint.

[0063] The second electrode of the second transistor is electrically connected to the third sub-pixel electrode through the third lap joint.

[0064] In a possible implementation, the third connection part and the first pixel electrode have a first gap therebetween; the fourth connection part and the second pixel electrode have a second gap therebetween.

[0065] The first adapter and the first pixel electrode have a third gap therebetween, and the third adapter and the second pixel electrode have a fourth gap therebetween.

[0066] In a possible implementation, the array substrate further includes: a fourth lap joint; the second electrode of the third transistor is electrically connected to the first common wire through the fourth lap joint.

[0067] In a possible implementation, the fourth lap joint has a fourth lap joint outer edge extending along the first direction, and the second lap joint has a second lap joint outer edge extending along the first direction; the first lap joint has a first lap joint outer edge extending along the second direction, and the third lap joint has a third lap joint outer edge extending along the second direction.

[0068] An extension line of the fourth lap joint outer edge coincides with an extension line of the second lap joint outer edge; and an extension line of the first lap joint outer edge coincides with an extension line of the third lap joint outer edge.

[0069] In a possible implementation, the second electrode of the first transistor comprises: a first transistor first part extending along the first direction;

[0070] The first transistor first part has an overlapping area with the first lap part in the orthographic projection of the substrate.

[0071] In a possible implementation, the second electrode of the second transistor comprises: a second transistor first part extending along the first direction, and a second transistor second part extending along the second direction and electrically connected to one end of the second transistor first part;

[0072] The second transistor first part has an overlapping area with the third lap part in the orthographic projection of the substrate; and the second transistor second part has an overlapping area with the second lap part in the orthographic projection of the substrate.

[0073] In a possible implementation, the array substrate further comprises: a plurality of transistors; the plurality of transistors are electrically connected to the same pixel electrode, and are electrically connected to the same data line and the same gate line;

[0074] The second sub-pixel electrode is located on a side of the first sub-pixel electrode away from the electrically connected data line, and the fourth sub-pixel electrode is located on a side of the third sub-pixel electrode away from the electrically connected data line; the first sub-pixel electrode is electrically connected to the third sub-pixel electrode, and the second sub-pixel electrode is electrically connected to the fourth sub-pixel electrode.

[0075] In a possible implementation, the array substrate further comprises: a first signal line extending along the second direction; and the plurality of transistors comprise: a first transistor, a second transistor, and a third transistor.

[0076] The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode;

[0077] The control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the fourth sub-pixel electrode;

[0078] The control electrode of the third transistor is electrically connected to the gate line, the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is multiplexed with the first signal line.

[0079] In a possible implementation, the pixel electrode further includes a connecting portion; the connecting portion extends along the second direction and connects the first sub-pixel electrode and the third sub-pixel electrode.

[0080] In a possible implementation, the pixel electrode further includes a connecting portion; the connecting portion extends along the second direction and connects the first sub-pixel electrode and the third sub-pixel electrode.

[0081] The first connecting portion extends along a third direction, one end of the first connecting portion is electrically connected to the second sub-pixel electrode, and the other end of the first connecting portion is electrically connected to one end of the second connecting portion;

[0082] The second connecting portion extends along the second direction, and the other end of the second connecting portion is electrically connected to one end of the third connecting portion.

[0083] The third connecting portion extends along a fourth direction, and the other end of the third connecting portion is electrically connected to the fourth sub-pixel electrode.

[0084] In a possible implementation, the first pixel electrode has a notch on a side facing the gate line; and the connecting portion is located in a projection of the notch on the substrate.

[0085] In a possible implementation, the pixel electrode further includes a first sub-pixel electrode protrusion connected to a side of the first sub-pixel electrode facing the third sub-pixel electrode; and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode through the first sub-pixel electrode protrusion.

[0086] The pixel electrode further includes a fourth sub-pixel electrode protrusion connected to a side of the fourth sub-pixel electrode facing the first sub-pixel electrode; and the second electrode of the second transistor is electrically connected to the fourth sub-pixel electrode through the third sub-pixel electrode protrusion.

[0087] In a possible implementation, the first sub-pixel electrode protrusion and the fourth sub-pixel electrode protrusion are both located between a projection of the connecting portion on the substrate and a projection of the connecting portion on the substrate.

[0088] In a possible implementation, the first sub-pixel electrode protrusion has a first sub-pixel electrode protrusion outer edge extending along the second direction; and an extension line of the first sub-pixel electrode protrusion outer edge at least partially overlaps the fourth sub-pixel electrode protrusion.

[0089] In a possible implementation, the array substrate further includes: a first common line extending along the first direction on one side of the gate line; the first common line is disconnected at a position crossing the data line.

[0090] In a possible implementation, the array substrate further includes: a second common line group electrically connected with the first common line and extending away from the side of the gate line, the second common line group includes: two second common lines;

[0091] The data line in the orthographic projection of the substrate has an overlapping area with the gap between the two second common lines of the same second common line group in the orthographic projection of the substrate.

[0092] In a possible implementation, the array substrate further includes: a third common line extending along the first direction on the other side of the gate line, and a fourth common line group connected with the third common line and extending away from the side of the gate line;

[0093] The third common line is disconnected at a position crossing the data line; the fourth common line group includes: two fourth common lines; the data line in the orthographic projection of the substrate has an overlapping area with the gap between the two fourth common lines of the same fourth common line group in the orthographic projection of the substrate.

[0094] In a possible implementation, the array substrate further includes: a fifth common line extending along the first direction and electrically connected with the second common line, the fifth common line passes through the second pixel electrode in the central area of the orthographic projection of the substrate in the orthographic projection of the substrate.

[0095] In a possible implementation, the array substrate further includes: a sixth common line extending along the first direction and electrically connected with the fourth common line, the sixth common line passes through the first pixel electrode in the central area of the orthographic projection of the substrate in the orthographic projection of the substrate.

[0096] In a possible implementation, the first sub-pixel electrode and the second sub-pixel electrode each include: a first sub-electrode part distributed along the second direction, and a second sub-electrode part; the third sub-pixel electrode and the fourth sub-pixel electrode each include: a third sub-electrode part distributed along the second direction, and a fourth sub-electrode part;

[0097] The first sub-electrode part, the second sub-electrode part, the third sub-electrode part and the fourth sub-electrode part each have a plurality of slits; and the extension direction of the slits of the first sub-electrode part is the same as the extension direction of the slits of the fourth sub-electrode part; the extension direction of the slits of the second sub-electrode part is the same as the extension direction of the slits of the third sub-electrode part.

[0098] In a possible implementation, the length of the slit in the direction perpendicular to the extension direction can be 2 μm to 4 μm.

[0099] In a possible implementation, the first sub-pixel electrode, the second sub-pixel electrode, the third sub-pixel electrode and the fourth sub-pixel electrode each have a rectangular shape in the orthographic projection on the substrate.

[0100] In a possible implementation, the first sub-electrode part, the second sub-electrode part, the third sub-electrode part and the fourth sub-electrode part each have a trapezoidal shape in the orthographic projection on the substrate.

[0101] In the first sub-pixel electrode and the fourth sub-pixel electrode, the first sub-electrode part and the second sub-electrode part are arranged opposite to each other at the top edge; and in the second sub-pixel electrode and the third sub-pixel electrode, the first sub-electrode part and the second sub-electrode part are arranged opposite to each other at the bottom edge.

[0102] In a possible implementation, the first sub-electrode part, the second sub-electrode part, the third sub-electrode part and the fourth sub-electrode part each have a trapezoidal shape in the orthographic projection on the substrate.

[0103] In the first sub-pixel electrode and the fourth sub-pixel electrode, the first sub-electrode part and the second sub-electrode part are arranged opposite to each other at the bottom edge; and in the second sub-pixel electrode and the third sub-pixel electrode, the first sub-electrode part and the second sub-electrode part are arranged opposite to each other at the top edge.

[0104] In a possible implementation, the first sub-pixel electrode comprises: a first main part, a second main part connected along the second direction and extending along the first direction, a first side part, a plurality of first branch parts extending along a fourth direction from the first main part and the first side part, and a plurality of second branch parts extending along a fifth direction from the second main part and the first side part; the second sub-pixel electrode comprises: a third main part, a fourth main part connected along the second direction and extending along the first direction, a fifth main part connected to one end of the third main part and extending along the first direction, a sixth main part connected to one end of the fourth main part and extending along the first direction, a plurality of third branch parts extending along the fourth direction from the third main part and the fifth main part, and a plurality of fourth branch parts extending along the fifth direction from the fourth main part and the sixth main part; the plurality of first branch parts and the plurality of third branch parts are in an interdigital distribution, and the plurality of second branch parts and the plurality of fourth branch parts are in an interdigital distribution;

[0105] The third sub-pixel electrode comprises: a seventh main part, an eighth main part connected along the second direction and extending along the first direction, a ninth main part connected to one end of the seventh main part and extending along the first direction, a tenth main part connected to one end of the eighth main part and extending along the first direction, a plurality of fifth branch parts extending along the fourth direction from the seventh main part and the ninth main part, and a plurality of sixth branch parts extending along the fifth direction from the eighth main part and the tenth main part; the fourth sub-pixel electrode comprises: an eleventh main part, a twelfth main part connected along the second direction and extending along the first direction, and a second side part extending along the first direction, a plurality of seventh branch parts extending along the fourth direction from the eleventh main part and the second side part, and a plurality of eighth branch parts extending along the fifth direction from the twelfth main part and the second side part; the plurality of fifth branch parts and the plurality of seventh branch parts are in an interdigital distribution, and the plurality of sixth branch parts and the plurality of eighth branch parts are in an interdigital distribution.

[0106] In a possible implementation, the array substrate further comprises: a first conductive layer on a side of the pixel electrode facing the substrate; the first conductive layer has a first hollow part, a second hollow part, a third hollow part, and a fourth hollow part;

[0107] The first hollow part overlaps at least part of a projection of the first sub-pixel electrode on the substrate, the second hollow part overlaps at least part of a projection of the second sub-pixel electrode on the substrate, the third hollow part overlaps at least part of a projection of the third sub-pixel electrode on the substrate, and the fourth hollow part overlaps at least part of a projection of the fourth sub-pixel electrode on the substrate.

[0108] The display panel provided by the embodiments of the present disclosure includes the array substrate provided by the embodiments of the present disclosure, and further includes a counter substrate arranged opposite to the array substrate, wherein the counter substrate is provided with a common electrode layer.

[0109] In a possible implementation, the display panel further includes a liquid crystal layer between the array substrate and the counter substrate.

[0110] The liquid crystal layer includes a plurality of liquid crystal portions, at least one of the plurality of liquid crystal portions includes a first sub-liquid crystal portion, a second sub-liquid crystal portion, a third sub-liquid crystal portion, and a fourth sub-liquid crystal portion; the liquid crystal portion in the orthographic projection of the substrate overlaps with the pixel electrode in the orthographic projection of the substrate; the first sub-liquid crystal portion in the orthographic projection of the substrate overlaps with the first sub-electrode portion in the orthographic projection of the substrate; the second sub-liquid crystal portion in the orthographic projection of the substrate overlaps with the second sub-electrode portion in the orthographic projection of the substrate; the third sub-liquid crystal portion in the orthographic projection of the substrate overlaps with the third sub-electrode portion in the orthographic projection of the substrate; and the fourth sub-liquid crystal portion in the orthographic projection of the substrate overlaps with the fourth sub-electrode portion in the orthographic projection of the substrate.

[0111] The initial alignment direction of the first sub-liquid crystal portion, the initial alignment direction of the second sub-liquid crystal portion, the initial alignment direction of the third sub-liquid crystal portion, and the initial alignment direction of the fourth sub-liquid crystal portion are different from each other.

[0112] In a possible implementation, the angle between the initial alignment direction of the first sub-liquid crystal portion and the first direction ranges from 210° to 240°; the angle between the initial alignment direction of the second sub-liquid crystal portion and the first direction ranges from 120° to 150°; the angle between the initial alignment direction of the third sub-liquid crystal portion and the first direction ranges from 300° to 330°; and the angle between the initial alignment direction of the fourth sub-liquid crystal portion and the first direction ranges from 30° to 60°.

[0113] In a possible implementation, the alignment direction of at least part of the liquid crystal at the junction of the first sub-liquid crystal portion and the second sub-liquid crystal portion is opposite to the alignment direction of at least part of the liquid crystal at the junction of the third sub-liquid crystal portion and the fourth sub-liquid crystal portion.

[0114] The display device provided by the embodiments of the present disclosure includes the display panel provided by the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0115] Figure 1A FIG. 1 is a top view of an array substrate provided by the embodiments of the present disclosure;

[0116] Figure 1B Fig. 2 is an enlarged schematic view of the dashed-line frame S1 in Fig. 1; Figure 1A Fig. 3 is a schematic view of a single film layer of the gate line layer in Fig. 2;

[0117] Figure 1C Fig. 4 is a schematic view of a single film layer of the active layer in Fig. 2; Figure 1A Fig. 5 is a schematic view of a single film layer of the data line in Fig. 2;

[0118] Figure 1D Fig. 6 is a schematic view of a single film layer of the first insulating layer in Fig. 2; Figure 1A Fig. 7 is a schematic view of a single film layer of the pixel electrode in Fig. 2;

[0119] Figure 1E Fig. 8 is a schematic view of a single film layer of the data line in Fig. 3; Figure 1A Fig. 9 is a schematic view of a single film layer of the first insulating layer in Fig. 3;

[0120] Figure 1F Fig. 10 is a schematic view of a single film layer of the pixel electrode in Fig. 3; Figure 1A Fig. 11 is a schematic view of a single film layer of the gate line layer in Fig. 4;

[0121] Figure 1G Fig. 12 is a schematic view of a single film layer of the active layer in Fig. 4; Figure 1A Fig. 13 is a schematic view of a single film layer of the pixel electrode in Fig. 4;

[0122] Figure 1H Fig. 14 is a schematic view of a single film layer of the data line in Fig. 5; Figure 1A Fig. 15 is a schematic view of a single film layer of the first insulating layer in Fig. 5;

[0123] Figure 2A Fig. 16 is a schematic view of a single film layer of the pixel electrode in Fig. 5;

[0124] Figure 2B Fig. 17 is an enlarged schematic view of the dashed-line frame S1 in Fig. 6; Figure 2A Fig. 18 is a schematic view of a single film layer of the gate line layer in Fig. 6;

[0125] Figure 2C Fig. 19 is a schematic view of a single film layer of the active layer in Fig. 6; Figure 2A Fig. 20 is a schematic view of a single film layer of the pixel electrode in Fig. 6;

[0126] Figure 2D Fig. 21 is a schematic view of a single film layer of the data line in Fig. 7; Figure 2A Fig. 22 is a schematic view of a single film layer of the first insulating layer in Fig. 7;

[0127] Figure 2E Fig. 23 is a schematic view of a single film layer of the pixel electrode in Fig. 7; Figure 2A

[0128] Fig. 24 is a schematic view of a single film layer of the gate line layer in Fig. 8; Figure 2F Figure 2A Fig. 25 is a schematic view of a single film layer of the active layer in Fig. 8;

[0129] Figure 2G Figure 2A Fig. 26 is a schematic view of a single film layer of the pixel electrode in Fig. 8;

[0130] Figure 2H Fig. 27 is a schematic view of a single film layer of the data line in Fig. 9; Figure 2A Fig. 28 is a schematic view of a single film layer of the first insulating layer in Fig. 9;

[0131] Figure 2I Fig. 29 is a schematic view of a single film layer of the pixel electrode in Fig. 9;​​Figure 2B Cross-sectional schematic view at dotted line EF;

[0132] Figure 3A Top view schematic diagram of array substrate provided by the embodiment of the present disclosure III;

[0133] Figure 3B For Figure 3A Enlarged schematic view of the dashed line frame S1;

[0134] Figure 3C For Figure 3A Single film layer schematic diagram of the gate line layer;

[0135] Figure 3D For Figure 3A Single film layer schematic diagram of the active layer;

[0136] Figure 3E For Figure 3A Single film layer schematic diagram of the data line;

[0137] Figure 3F For Figure 3A Single film layer schematic diagram of the first insulating layer;

[0138] Figure 3G For Figure 3A Single film layer schematic diagram of the pixel electrode;

[0139] Figure 3H For Figure 3A Corresponding light efficiency simulation schematic diagram;

[0140] Figure 4A Top view schematic diagram of array substrate provided by the embodiment of the present disclosure IV; Figure 4B For Figure 4A Enlarged schematic view of the dashed line frame S1;

[0141] Figure 4C For Figure 4A Single film layer schematic diagram of the gate line layer;

[0142] Figure 4D For Figure 4A Single film layer schematic diagram of the active layer;

[0143] Figure 4E For Figure 4A Single film layer schematic diagram of the data line;

[0144] Figure 4F For Figure 4A Single film layer schematic diagram of the first insulating layer;

[0145] Figure 4G For Figure 4A Single film layer schematic diagram of the pixel electrode;

[0146] Figure 4H For Figure 4A Corresponding light effect simulation schematic diagram;

[0147] Figure 5A For the fifth schematic diagram of the array substrate provided by the embodiment of the present disclosure; Figure 5B For Figure 5A Enlarged schematic diagram of the dashed line frame S1;

[0148] Figure 5C For Figure 5A Schematic diagram of a single film layer of the gate line layer;

[0149] Figure 5D For Figure 5A Schematic diagram of a single film layer of the active layer;

[0150] Figure 5E For Figure 5A Schematic diagram of a single film layer of the data line;

[0151] Figure 5F For Figure 5A Schematic diagram of a single film layer of the first insulating layer;

[0152] Figure 5G For Figure 5A Schematic diagram of a single film layer of the pixel electrode;

[0153] Figure 5H For Figure 5A Corresponding light effect simulation schematic diagram;

[0154] Figure 6A For the sixth schematic diagram of the array substrate provided by the embodiment of the present disclosure; Figure 6B For Figure 6A Enlarged schematic diagram of the dashed line frame S1;

[0155] Figure 6C For Figure 6A Schematic diagram of a single film layer of the gate line layer;

[0156] Figure 6D For Figure 6A Schematic diagram of a single film layer of the active layer;

[0157] Figure 6E For Figure 6A Schematic diagram of a single film layer of the data line;

[0158] Figure 6F For Figure 6A Schematic diagram of a single film layer of the first insulating layer;

[0159] Figure 6G For Figure 6A Schematic diagram of a single film layer of the first conductive layer;

[0160] Figure 6H ForFigure 6A A schematic view of a single film layer of the second insulating layer;

[0161] Figure 6I For Figure 6A A schematic view of a single film layer of the pixel electrode;

[0162] Figure 6J For Figure 6A A schematic view of the corresponding black matrix;

[0163] Figure 6K For Figure 6A A schematic view of the corresponding light efficiency simulation;

[0164] Figure 7 A schematic view of a dark line when the conventional 8-domain structure is taken;

[0165] Figure 8 A schematic view of a dark line of the array substrate provided by the embodiment of the present disclosure;

[0166] Figure 9 A schematic view of a sub-pixel equivalent circuit provided by the embodiment of the present disclosure;

[0167] Figure 10 A schematic view of a cross-section of the display panel provided by the embodiment of the present disclosure;

[0168] Figure 11A A schematic view of the array substrate provided by the embodiment of the present disclosure; Figure 11B For Figure 11A An enlarged schematic view of the dashed-line frame S1 in the embodiment;

[0169] Figure 11C For Figure 11A A schematic view of a single film layer of the gate line layer;

[0170] Figure 11D For Figure 11A A schematic view of a single film layer of the active layer;

[0171] Figure 11E For Figure 11A A schematic view of a single film layer of the data line;

[0172] Figure 11F For Figure 11A A schematic view of a single film layer of the first insulating layer;

[0173] Figure 11G For Figure 11A A schematic view of a single film layer of the pixel electrode;

[0174] Figure 11H For Figure 11A A schematic view of the corresponding black matrix;

[0175] Figure 11I For Figure 11ACorresponding light efficiency simulation schematic diagram;

[0176] Figure 12 For Figure 11A Corresponding equivalent circuit diagram;

[0177] Figure 13A For the array substrate top view schematic diagram provided by the embodiment of the present disclosure No. 8; Figure 13B For Figure 13A Single film layer schematic diagram of middle pixel electrode;

[0178] Figure 13C For Figure 13A Corresponding light efficiency simulation schematic diagram;

[0179] Figure 14A For the array substrate top view schematic diagram provided by the embodiment of the present disclosure No. 9;

[0180] Figure 14B For Figure 14A Single film layer schematic diagram of middle pixel electrode;

[0181] Figure 14C For Figure 14A Corresponding light efficiency simulation schematic diagram;

[0182] Figure 15A For the array substrate top view schematic diagram provided by the embodiment of the present disclosure No. 10; Figure 15B For Figure 15A Single film layer schematic diagram of middle pixel electrode;

[0183] Figure 15C For Figure 15A Corresponding light efficiency simulation schematic diagram;

[0184] Figure 16A For the array substrate top view schematic diagram provided by the embodiment of the present disclosure No. 11;

[0185] Figure 16B For Figure 16A Enlarged schematic diagram of dashed line frame S1 in the middle;

[0186] Figure 16C For Figure 16A Single film layer schematic diagram of gate line layer in the middle;

[0187] Figure 16D For Figure 16A Single film layer schematic diagram of active layer in the middle;

[0188] Figure 16E For Figure 16A Single film layer schematic diagram of data line in the middle;

[0189] Figure 16F For Figure 16A Single film layer schematic diagram of first insulating layer in the middle;

[0190] Figure 16G For Figure 16A Single film layer schematic diagram of middle pixel electrode;

[0191] Figure 16H For Figure 16A Corresponding black matrix schematic diagram;

[0192] Figure 16I For Figure 16A Corresponding light efficiency simulation schematic diagram;

[0193] Figure 17A Twelfth schematic diagram of top view of array substrate provided by the embodiment of the disclosure; Figure 17B For Figure 17A Single film layer schematic diagram of middle pixel electrode;

[0194] Figure 17C For Figure 17A Corresponding light efficiency simulation schematic diagram;

[0195] Figure 18A Thirteenth schematic diagram of top view of array substrate provided by the embodiment of the disclosure;

[0196] Figure 18B For Figure 18A Single film layer schematic diagram of middle pixel electrode;

[0197] Figure 18C For Figure 18A Corresponding light efficiency simulation schematic diagram;

[0198] Figure 19A Fourteenth schematic diagram of top view of array substrate provided by the embodiment of the disclosure; Figure 19B For Figure 19A Single film layer schematic diagram of middle pixel electrode;

[0199] Figure 19C For Figure 19A Corresponding light efficiency simulation schematic diagram;

[0200] Figure 20A Fifteenth schematic diagram of top view of array substrate provided by the embodiment of the disclosure;

[0201] Figure 20B For Figure 20A Enlarged schematic diagram of middle dotted line frame S1;

[0202] Figure 20C For Figure 20A Single film layer schematic diagram of gate line layer;

[0203] Figure 20D For Figure 20A Single film layer schematic diagram of active layer;

[0204] Figure 20E ForFigure 20A A single film layer schematic diagram of the middle data line;

[0205] Figure 20F For Figure 20A A single film layer schematic diagram of the first insulating layer;

[0206] Figure 20G For Figure 20A A single film layer schematic diagram of the pixel electrode;

[0207] Figure 20H For Figure 20A A single film layer schematic diagram of the second insulating layer;

[0208] Figure 20I For Figure 20A A single film layer schematic diagram of the first conductive layer;

[0209] Figure 20J A corresponding black matrix schematic diagram;

[0210] Figure 20K For Figure 20A A corresponding light efficiency simulation schematic diagram;

[0211] Figure 21A A sixteenth array substrate top view schematic diagram provided by the embodiments of the present disclosure;

[0212] Figure 21B For Figure 21A A single film layer schematic diagram of the pixel electrode;

[0213] Figure 21C For Figure 21A A corresponding light efficiency simulation schematic diagram;

[0214] Figure 22A A seventeenth array substrate top view schematic diagram provided by the embodiments of the present disclosure;

[0215] Figure 22B For Figure 22A A single film layer schematic diagram of the pixel electrode;

[0216] Figure 22C For Figure 22A A corresponding light efficiency simulation schematic diagram;

[0217] Figure 23A An eighteenth array substrate top view schematic diagram provided by the embodiments of the present disclosure;

[0218] Figure 23B For Figure 23A A single film layer schematic diagram of the pixel electrode;

[0219] Figure 23C For Figure 23A A corresponding light efficiency simulation schematic diagram. DETAILED DESCRIPTION

[0220] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure. The embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand that the manners and contents can be converted into one or more forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents of the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other in any manner without conflict.

[0221] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include" or "contain" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0222] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art to be considered equivalent in the context of measuring the particular quantity and the error associated with measuring the particular quantity (i.e., limitations of the measurement system). For example, "about" can mean a difference in one or more standard deviations from the stated value, or within a range of ± 30%, 20%, 10%, 5%. In the present specification, "about" can be a case where the exponential values differ within 10%.

[0223] In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an area illustrated or described as flat can typically have rough and / or nonlinear features. Moreover, sharp angles that are illustrated can be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.

[0224] In this specification, terms of "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or locational relationship are used to describe the positional relationship of constituent elements with reference to the drawings only for the convenience of describing this specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting on the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, it is not limited to the words described in the specification, and can be appropriately replaced according to the situation.

[0225] In this specification, unless explicitly stated and limited otherwise, the terms "mount", "connected", "connection" should be interpreted broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or communication inside two elements. The above terms in the present disclosure can be understood according to the situation by those skilled in the art.

[0226] In this specification, "electrically connected" includes the case where the constituent elements are connected together through an element having some electrical effect. The "element having some electrical effect" is not particularly limited as long as it can transmit electrical signals between the connected constituent elements. Examples of the "element having some electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having one or more functions, and the like.

[0227] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain) and the source electrode (source terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0228] Furthermore, the gate of a transistor can be referred to as the control electrode. In cases where transistors with opposite polarities are used, or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0229] In this specification, "parallel" refers to a state in which two straight lines form an angle of -10° or more and less than 10°, and therefore can include a state in which the angle is -5° or more and less than 5°. Similarly, "perpendicular" refers to a state in which two straight lines form an angle of 80° or more and less than 100°, and therefore can include a state in which the angle is 85° or more and less than 95°.

[0230] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0231] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0232] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0233] High-resolution products, such as 8K and 16K displays, are the main direction for future products. However, current 8K products using vertically aligned liquid crystal (VA) have problems with low transmittance and poor color shift.

[0234] In view of this, see Figure 1A- Figure 1G , Figure 2A- Figure 2G , Figure 3A- Figure 3G , Figure 4A- Figure 4G , Figure 5A- Figure 5G , Figure 6A- Figure 6G , Figure 11A- Figure 11I , Figure 13A- Figure 13C , Figure 14A- Figure 14C , Figure 15A- Figure 15C , Figure 16A- Figure 16I ,Figure 17A- Figure 17C 、 Figure 18A- Figure 18C 、 Figure 19A- Figure 19C 、 Figure 20A- Figure 20K 、 Figure 21A- Figure 21C 、 Figure 22A- Figure 22C 、 Figure 23A- Figure 23C As shown in FIG. 1, the array substrate provided by the embodiment of the present disclosure comprises:

[0235] a substrate 1;

[0236] a plurality of gate lines 2 located on one side of the substrate 1 and extending along a first direction X;

[0237] a plurality of data lines 3 extending along a second direction Y; specifically, the second direction Y can be perpendicular to the first direction X; specifically, the second direction Y can be the direction of the pixel electrode column, and the first direction X can be the direction of the pixel electrode row;

[0238] a plurality of pixel electrodes 4, the pixel electrode 4 comprising: a first pixel electrode 41 located on one side of the gate line 2, and a second pixel electrode 42 located on the other side of the gate line 2; the first pixel electrode 41 comprising: a first sub-pixel electrode 411 and a second sub-pixel electrode 412 distributed along the first direction X; the second pixel electrode 42 comprising: a third sub-pixel electrode 421 and a fourth sub-pixel electrode 422 distributed along the first direction X; specifically, for example, as shown in FIG. 2, the pixel electrode 4 comprises the first pixel electrode 41 located on the upper side of the gate line 2, and the second pixel electrode 42 located on the lower side of the gate line 2, wherein the first pixel electrode 41 comprises the first sub-pixel electrode 411 located on the left side, and the second sub-pixel electrode 412 located on the right side; the second pixel electrode 42 comprises the third sub-pixel electrode 421 located on the left side, and the fourth sub-pixel electrode 422 located on the right side; Figure 1G

[0239] One of the first sub-pixel electrode 411 and the second sub-pixel electrode 412 is electrically connected to one of the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422. The brightness of the two electrically connected ones is different from the brightness of the other two. Specifically, for example, the first sub-pixel electrode 411 can be electrically connected to the third sub-pixel electrode 421, and the second sub-pixel electrode 412 can be electrically connected to the fourth sub-pixel electrode 422; or, the first sub-pixel electrode 411 can be electrically connected to the fourth sub-pixel electrode 422, and the second sub-pixel electrode 412 can be electrically connected to the third sub-pixel electrode 421.

[0240] ​In the embodiments of the present disclosure, the pixel electrode 4 comprises: a first pixel electrode 41 located on one side of the gate line 2, and a second pixel electrode 42 located on the other side of the gate line 2; the first pixel electrode 41 comprises: a first sub-pixel electrode 411 distributed along the first direction X, and a second sub-pixel electrode 412; the second pixel electrode 42 comprises: a third sub-pixel electrode 421 distributed along the first direction X, and a fourth sub-pixel electrode 422; and one of the first sub-pixel electrode 411 and the second sub-pixel electrode 412 is electrically connected to one of the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422, that is, one pixel electrode 4 is divided into two parts, the upper half is divided into two parts, and the lower half is also divided into two parts, the brightness of the two parts electrically connected is different from the brightness of the other two parts, and 8 domains can be formed in one sub-pixel, and compared with the conventional 8-domain structure, the array substrate provided by the embodiments of the present disclosure has fewer dark lines, better transmittance, and can compensate the viewing angles of each other, thereby improving the left-right viewing angle deviation.

[0241] Specifically, as shown in Figure 7 and Figure 8 , Figure 7 the dark lines of the conventional 8-domain structure can be seen, and the dark line distribution is more, and the transmittance is greatly affected; Figure 8 the dark lines of the array substrate provided by the embodiments of the present disclosure can be obviously seen, and the number of dark lines is obviously reduced, and the 8-domain array substrate structure provided by the embodiments of the present disclosure has obvious advantages in improving the transmittance; and Figure 7 as shown in the 8-domain structure, the liquid crystal angles cannot be compensated for the left-right viewing angles, the transverse liquid crystals are all oriented to the right, and there is no transverse liquid crystal oriented to the left, but Figure 8 as shown in the array substrate provided by the embodiments of the present disclosure, the transverse liquid crystals in the left-right directions can be compensated for the viewing angles, thereby improving the left-right viewing angle deviation.

[0242] In combination with Figure 1A , Figure 1G and Figure 8 , in one pixel electrode 4, the first pixel electrode 41 is a く-shaped slit, and the second pixel electrode 42 is an inverted く-shaped slit; in combination with the extension direction of the slit F, the first pixel electrode 41 can be provided with two liquid crystal alignment directions, which can be 225° and 135° respectively; the second pixel electrode 42 can be provided with two liquid crystal alignment directions, which are 315° and 45° respectively; in combination with the light-dark areas divided into left and right, an 8-domain alignment mode in one sub-pixel can be formed when the SUVA technology is used.

[0243] It should be noted that in the embodiments of the present disclosure, one of the first sub-pixel electrode 411 and the second sub-pixel electrode 412 is electrically connected with one of the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422. The one of the first sub-pixel electrode 411 and the second sub-pixel electrode 412 can be electrically connected with the one of the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422 in the layer where the pixel electrode 4 is located. As for the other two, they can not be connected in the layer where the pixel electrode 4 is located, or can be electrically connected through other structures, for example, both are connected to the same transistor drain. Specifically, for example, the first sub-pixel electrode 411 is electrically connected with the third sub-pixel electrode 421 in the layer where the pixel electrode 4 is located, and both present one brightness; and the second sub-pixel electrode 412 is not electrically connected with the third sub-pixel electrode 421 in the layer where the pixel electrode 4 is located, but both can be connected to the same transistor drain (i.e., electrically connected through the drain layer), to realize another brightness. The brightness of the two connected in the layer where the pixel electrode 4 is located can be different from the brightness of the other two.

[0244] It can be understood that the brightness of the two electrically connected to the main body is different from the brightness of the other two, which refers to the brightness comparison in one sub-pixel when the display panel is powered on and lit up.

[0245] In a possible implementation, in combination with Figure 1A- Figure 1G , Figure 2A- Figure 2G , Figure 3A- Figure 3G , Figure 4A- Figure 4G , Figure 5A- Figure 5G , Figure 6A- Figure 6G As shown in the array substrate further comprises: a plurality of transistors T; a plurality of transistors electrically connected to the same pixel electrode 4, which are electrically connected to the same data line 3 and the same gate line 2, for example, as shown in Figure 1B , there are three transistors electrically connected to the same pixel electrode 4, which are the first transistor T1, the second transistor T2, and the third transistor T3. The three transistors are electrically connected to the same data line 3 and the same gate line 2; the second sub-pixel electrode 412 is located on the side of the first sub-pixel electrode 411 away from the electrically connected data line 3, and the fourth sub-pixel electrode 422 is located on the side of the third sub-pixel electrode 421 away from the electrically connected data line 3; the first sub-pixel electrode 411 is electrically connected with the fourth sub-pixel electrode 422. Specifically, the first sub-pixel electrode 411 is electrically connected with the fourth sub-pixel electrode 422 in the layer where the pixel electrode 4 is located, and the second sub-pixel electrode 412 and the third sub-pixel electrode 421 are both electrically connected to the second electrode TC of the second transistor T2. In the embodiments of the present disclosure, the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 are electrically connected in the pixel electrode 4, and the second sub-pixel electrode 412 and the third sub-pixel electrode 421 are electrically connected, that is, the four parts of the pixel electrode 4 are electrically connected in pairs, which is conducive to forming an 8-domain distribution in the same pixel electrode 4.

[0246] It should be noted that the plurality of transistors electrically connected to the same pixel electrode 4 can mean that the plurality of transistors are electrically connected to the same pixel electrode 4 directly or indirectly. For example, the first transistor T1 and the second transistor T2 can be directly electrically connected to the pixel electrode 4, and the third transistor T3 can be considered as being electrically connected to the pixel electrode 4 because it is electrically connected to the second transistor T2. Specifically, the plurality of transistors electrically connected to the same pixel electrode 4 can also mean that each transistor driving the same pixel electrode 4.

[0247] In a possible implementation, in combination with Figure 1A- Figure 1G As shown, the array substrate further includes: a first signal line 5 extending along the second direction Y; and the plurality of transistors T includes: a first transistor T1, a second transistor T2, and a third transistor T3.

[0248] The control electrode TA of the first transistor T1 is electrically connected to the gate line 2, the first electrode TB of the first transistor T1 is electrically connected to the data line 3, and the second electrode TC of the first transistor T1 is electrically connected to the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422. Specifically, the second electrode TC of the first transistor T1 can be electrically connected to the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 through the first via hole K1.

[0249] The control electrode TA of the second transistor T2 is electrically connected to the gate line 2, the first electrode TB of the second transistor T2 is electrically connected to the data line 3, and the second electrode TC of the second transistor T2 is electrically connected to the second sub-pixel electrode 412 and the third sub-pixel electrode 421. Specifically, the second electrode TC of the second transistor T2 can be electrically connected to the third sub-pixel electrode 421 through the second via hole K2, and the second electrode TC of the second transistor T2 can be electrically connected to the second sub-pixel electrode 412 through the third via hole K3.

[0250] The control electrode TA of the third transistor T3 is electrically connected to the gate line 2, the first electrode TB of the third transistor T3 is multiplexed with the second electrode TC of the second transistor T2, and the second electrode TC of the third transistor T3 is multiplexed with the first signal line 5.

[0251] Figure 9 It can be Figure 1BThe corresponding equivalent circuit diagram, wherein Sself is the data line on the left side of the pixel, that is, the signal line for transmitting the data signal of the current sub-pixel, Sother is the data line on the right side of the pixel, that is, the data line electrically connected to the current sub-pixel, the pixel circuit can comprise: a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor Cpd_light, a second capacitor Cgp_light, a third capacitor Cst_light, a fourth capacitor Clc_light, a fifth capacitor Cpp_light_dark, a sixth capacitor Cpd_other_light, a seventh capacitor Cpd_dark, an eighth capacitor Cgp_dark, a ninth capacitor Cst_dark, a tenth capacitor Clc_dark, an eleventh capacitor Cpd_other_dark, a twelfth capacitor CgD, and a thirteenth capacitor CcD; wherein the first pixel electrode 41 and the data line 3 form the first capacitor Cpd_light, the first pixel electrode 41 and the gate line 2 form the second capacitor Cgp_light, the overlapping area of the first pixel electrode 41 and the third common wire 23 can form the third capacitor Cst_light, the first pixel electrode 41 and the common electrode on the opposite substrate side can form the fourth capacitor Clc_light, the first pixel electrode 41 and the second pixel electrode 42 can form the fifth capacitor Cpp_light_dark, and the first pixel electrode 41 and the adjacent data line 3 can form the sixth capacitor Cpd_other_light; the second pixel electrode 42 and the data line 3 form the seventh capacitor Cpd_dark, the second pixel electrode 42 and the gate line 2 form the eighth capacitor Cgp_dark, the overlapping area of the second pixel electrode 42 and the first common wire 21 can form the ninth capacitor Cst_dark, the second pixel electrode 42 and the common electrode on the opposite substrate side can form the tenth capacitor Clc_dark, the second pixel electrode 42 and the adjacent data line 3 can form the eleventh capacitor Cpd_other_dark, and the overlapping area of the gate line 2 and the first signal line 5 can form the twelfth capacitor CgD, and the overlapping area of the first signal line 5 and the first common wire 21 can form the thirteenth capacitor CcD.

[0252] Specifically, in combination with the embodiments shown in Figure 1A and Figure 9 Since the third transistor T3 is connected to the second transistor T2, the voltage loaded on the second sub-pixel electrode 412 and the third sub-pixel electrode 421 will be partially divided to the twelfth capacitor CgD (and / or the thirteenth capacitor CcD, and / or the first signal line 5) through the third transistor T3, so that the voltage obtained by the second sub-pixel electrode 412 and the third sub-pixel electrode 421 is lower than the voltage obtained by the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, and further, the luminance of the second sub-pixel electrode 412 and the third sub-pixel electrode 421 is less than the luminance of the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, and further, in the sub-pixel, a display effect of different brightness is formed.

[0253] In a possible implementation, the voltage loaded on the first signal line 5 can be consistent with the voltage loaded on the common electrode layer of the opposite substrate, that is, a common voltage is loaded.

[0254] In a possible implementation, in combination with Figure 1A- Figure 1G As shown in the figure, the pixel electrode 4 further includes: a first sub-pixel electrode protrusion 41A connected to the first sub-pixel electrode 411 on the side facing the third sub-pixel electrode 421; and the second electrode TB of the first transistor T1 is electrically connected to the first sub-pixel electrode 411 through the first sub-pixel electrode protrusion 41A. In the embodiment of the present disclosure, the first sub-pixel electrode 411 on the side facing the third sub-pixel electrode 421 is further provided with the first sub-pixel electrode protrusion 41A, which is simple and regular in wiring mode when connected to the second electrode TB of the first transistor T1, is conducive to simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit failure when multiple pattern layouts are complex.

[0255] In a possible implementation, in combination with Figure 1A- Figure 1G As shown in the figure, the pixel electrode 4 further includes: a connection part 44 connecting the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422; the connection part 44 includes: a first connection part 441 extending along the second direction Y, and a second connection part 442 extending along the third direction Z; one end of the first connection part 441 is electrically connected to one end of the first sub-pixel electrode 411 on the side facing the third sub-pixel electrode 421, and the other end is electrically connected to the second connection part 442, and the other end of the second connection part 442 is electrically connected to one end of the fourth sub-pixel electrode 422 on the side facing the second sub-pixel electrode 412.

[0256] In the embodiment of the present disclosure, the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 are directly electrically connected through the connection part 44 on the layer where the pixel electrode 4 is located, and the connection part 44 includes: a first connection part 441 extending along the second direction Y, and a second connection part 442 extending along the third direction Z, and the wiring mode of the connection part 44 is simple and regular, which is conducive to simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit failure when multiple pattern layouts are complex.

[0257] In a possible implementation, the third direction Z intersects the first direction X and intersects the second direction Y; the third direction Z can form an angle of 0-90° with the second direction Y, specifically, the third direction Z can form an angle of 30°-60° with the second direction Y, specifically, the third direction Z can form an angle of 45° with the second direction Y.

[0258] In a possible implementation, in combination with Figure 1A- Figure 1GAs shown, the pixel electrode 4 further comprises: a third sub-pixel electrode protrusion 43A connected to the third sub-pixel electrode 421 towards the side of the first sub-pixel electrode 411; and the second electrode TC of the second transistor T2 is electrically connected to the third sub-pixel electrode 421 through the third sub-pixel electrode protrusion 43A. In the embodiment of the present disclosure, the third sub-pixel electrode 421 further comprises the third sub-pixel electrode protrusion 43A connected to the side of the first sub-pixel electrode 411, which is simple and regular in wiring mode when connected to the second electrode TC of the second transistor T2, and is conducive to simple wiring between the first pixel electrode 41 and the second pixel electrode 42, thereby avoiding the risk of short circuit failure during etching and patterning when the multiple patterns are complex.

[0259] In a possible implementation, in combination with Figure 1A- Figure 1G As shown, the pixel electrode 4 further comprises: a second sub-pixel electrode extension 42B extending along the second direction Y, and a second sub-pixel electrode protrusion 42A; one end of the second sub-pixel electrode extension 42B is electrically connected to one end of the second sub-pixel electrode 412 towards the side of the fourth sub-pixel electrode 422, and the other end is electrically connected to the second sub-pixel electrode protrusion 42A; and the second electrode TC of the second transistor T2 is electrically connected to the second sub-pixel electrode 412 through the second sub-pixel electrode protrusion 42A. In the embodiment of the present disclosure, the second sub-pixel electrode 412 further comprises the second sub-pixel electrode extension 42B extending along the second direction Y and the second sub-pixel electrode protrusion 42A towards the side of the fourth sub-pixel electrode 422, which is conducive to electrical connection of the second sub-pixel electrode 412 and the third sub-pixel electrode 421 to the second electrode TC of the second transistor T2, and the wiring mode is simple and regular when the second sub-pixel electrode 412 is connected to the second electrode TC of the second transistor T2, which is conducive to simple wiring between the first pixel electrode 41 and the second pixel electrode 42, thereby avoiding the risk of short circuit failure during etching and patterning when the multiple patterns are complex.

[0260] In a possible implementation, in combination with Figure 1A- Figure 1G As shown, the extension direction of the second sub-pixel electrode extension 42B is parallel to the extension direction of the first connecting portion 441, which is conducive to simple wiring between the first pixel electrode 41 and the second pixel electrode 42, thereby avoiding the risk of short circuit failure during etching and patterning when the multiple patterns are complex.

[0261] In a possible implementation, in combination with Figure 1A- Figure 1G As shown, the second sub-pixel electrode protrusion 42A has a second sub-pixel electrode protrusion outer edge f1 extending away from the side of the second sub-pixel electrode 412 along the first direction X; and the third sub-pixel electrode protrusion 43A has a third sub-pixel electrode protrusion outer edge f2 extending away from the side of the third sub-pixel electrode 421 along the first direction X.

[0262] The extension line of the outer edge f1 of the second sub-pixel electrode protruding portion coincides with the extension line of the outer edge f2 of the third sub-pixel electrode protruding portion, or the extension line of the outer edge f1 of the second sub-pixel electrode protruding portion at least partially overlaps the third sub-pixel electrode protruding portion 43A, or the extension line of the outer edge f2 of the third sub-pixel electrode protruding portion at least partially overlaps the second sub-pixel electrode protruding portion 42A. In this way, it is beneficial to electrically connect the second sub-pixel electrode 412 and the third sub-pixel electrode 421 to the second electrode TC of the second transistor T2, to simplify the wiring between the first pixel electrode 41 and the second pixel electrode 42 gap, and to avoid the risk of short circuit failure during etching and patterning when the layout of multiple patterns is complex.

[0263] In a possible implementation, in combination with Figure 1A- Figure 1G Figure 1A- Figure 1G As shown, the center of the third sub-pixel electrode protruding portion 43A is parallel to the second direction Y with the connection line e1 of the center of the first sub-pixel electrode protruding portion 41A. In this way, it is beneficial to simplify the pattern between the first pixel electrode 41 and the second pixel electrode 42 gap, and to avoid the risk of short circuit failure during etching and patterning when the layout of multiple patterns is complex.

[0264] In a possible implementation, in combination with Figures 1A-1G As shown, the array substrate includes a first axis f7 extending between the first pixel electrode 41 and the second pixel electrode 42 and along the first direction X, and the third sub-pixel electrode protruding portion 43A and the first sub-pixel electrode protruding portion 41A can be symmetrical about the first axis f7.

[0265] In a possible implementation, in combination with Figures 1A-1G As shown, the first sub-pixel electrode protruding portion 41A can have a trapezoidal shape in the orthographic projection on the substrate 1, and the third sub-pixel electrode protruding portion 43A can have a trapezoidal shape in the orthographic projection on the substrate 1; in a possible implementation, the first sub-pixel electrode protruding portion 41A can also have a rectangular, semicircular or semi-elliptical shape in the orthographic projection on the substrate 1; the third sub-pixel electrode protruding portion 43A can also have a rectangular, semicircular or semi-elliptical shape in the orthographic projection on the substrate 1.

[0266] In a possible implementation, in combination with Figures 1A-1G As shown, the second electrode TC of the first transistor T1 includes a first transistor first portion T1C1 extending along the first direction X; the orthographic projection of the first transistor first portion T1C1 on the substrate 1 has an overlapping area with the orthographic projection of the first sub-pixel electrode protruding portion 41A on the substrate 1. In this way, it is convenient for the first transistor first portion T1C1 and the first sub-pixel electrode protruding portion 41A to be electrically connected through the first via K1.

[0267] In a possible implementation, in combination with Figures 1A-1GAs shown, the second electrode TC of the first transistor T1 includes: a first transistor second part T1C2 extending along the second direction Y and electrically connected with the first transistor first part T1C1; in particular, the first transistor second part T1C2 in the orthographic projection of the substrate 1 can have an overlapping area with the active pattern 6 in the orthographic projection of the substrate 1.

[0268] In a possible implementation, in combination Figures 1A-1G As shown, the second electrode TC of the second transistor T2 includes: a second transistor first part T2C1 extending along the first direction X, and a second transistor second part T2C2 extending along the second direction Y and electrically connected with one end of the second transistor first part T2C1; the second transistor first part T2C1 in the orthographic projection of the substrate 1 has an overlapping area with the third sub-pixel electrode convex part 43A in the orthographic projection of the substrate 1, so as to realize that the second transistor first part T2C1 is electrically connected with the third sub-pixel electrode convex part 43A through the second via hole K2; the second transistor second part T2C2 in the orthographic projection of the substrate 1 has an overlapping area with the second sub-pixel electrode convex part 42A in the orthographic projection of the substrate 1, so as to realize that the second transistor second part T2C2 is electrically connected with the second sub-pixel electrode convex part 42A through the third via hole K3.

[0269] In a possible implementation, in combination Figures 1A-1G As shown, the second electrode TC of the second transistor T2 can further include: a second transistor third part T2C3 electrically connected with the other end of the second transistor first part T2C1 and extending along the second direction Y; in particular, the second transistor third part T2C3 in the orthographic projection of the substrate 1 can have an overlapping area with the active pattern 6 in the orthographic projection of the substrate 1.

[0270] In a possible implementation, in combination Figures 1A-1G As shown, at least part of the orthographic projection of the second transistor second part T2C2 on the substrate 1 overlaps at least part of the orthographic projection of the second sub-pixel electrode extension part 42B on the substrate 1. Since the second transistor second part T2C2 has an overlapping area with the gate line 2, the two form a coupling capacitor, and the second sub-pixel electrode extension part 42B covers part of the second transistor second part T2C2, which can shield the coupling capacitor between part of the second transistor second part T2C2 and the gate line 2; moreover, at least part of the orthographic projection of the second transistor second part T2C2 on the substrate 1 overlaps at least part of the orthographic projection of the second sub-pixel electrode extension part 42B on the substrate 1, which can make the array substrate wiring easy, reduce the wiring width and optimize the layout of the wiring.

[0271] In a possible implementation, the orthographic projection of the second transistor second part T2C2 on the substrate 1 can also not overlap with the orthographic projection of the second sub-pixel electrode extension part 42B on the substrate 1.

[0272] In a possible implementation, in combination with Figures 1A-1G As shown in FIG. 6, the first signal line 5 has a recess 50; the second transistor second part T2C2 is located in at least part of the orthographic projection of the substrate 1, in the area surrounded by the orthographic projection of the recess 50 on the substrate 1. In the embodiment of the present disclosure, the first signal line 5 has the recess 50, so that the second transistor second part T2C2 can be avoided while achieving the same layer setting of the first signal line 5 and the second pole TC of the second transistor T2, and the short circuit between the first signal line 5 and the second pole TC of the second transistor T2 is avoided.

[0273] In a possible implementation, in combination with Figures 1A-1G As shown in FIG. 6, the first signal line 5 includes: the first signal part 51, the second signal part 52, and the third signal part 53 distributed in the second direction Y in sequence, the fourth signal part 54 extending in the first direction X and connecting the second signal part 52 and the first signal part 51, and the fifth signal part 55 extending in the first direction X and connecting the second signal part 52 and the third signal part 53; the extension line of the first signal part 51 coincides with the extension line of the third signal part 53; the extension line of the second signal part 52 does not coincide with the extension line of the first signal part 51; the second signal part 52, the fourth signal part 54, and the fifth signal part 55 constitute the recess 50, and the fourth signal part 54 and / or the fifth signal part 55 at least partially overlap the pixel electrode 4.

[0274] Specifically, the third signal part 53 can serve as the second pole TC of the third transistor T3. In this way, the partial voltage of the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 is released to the first signal line 5 through the third transistor T3.

[0275] In a possible implementation, in combination with Figures 1A-1G As shown in FIG. 6, the first signal line 5 is in the same layer as the data line 3. In this way, the first signal line 5 is formed at the same time as the data line 3, so as to simplify the manufacturing process of the array substrate and reduce the manufacturing cost of the array substrate while achieving different display effects of light and shade in the same sub-pixel.

[0276] In a possible implementation, referring to Figures 2A-2G 、 Figures 3A-3G 、 Figures 4A-4G 、 Figures 5A-5G As shown in FIG. 6, the array substrate further includes: the first common wire 21 located on one side of the gate line 2 and extending in the first direction X; and the plurality of transistors T including: the first transistor T1 electrically connected with the data line 3, the second transistor T2, and the third transistor T3;

[0277] The control electrode TA of the first transistor T1 is electrically connected with the gate line 2, the first electrode TB of the first transistor T1 is electrically connected with the data line 3, and the second electrode TC of the first transistor T1 is electrically connected with the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422; specifically, the second electrode TC of the first transistor T1 can be electrically connected with the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 through the first via hole K1.

[0278] The control electrode TA of the second transistor T2 is electrically connected with the gate line 2, the first electrode TB of the second transistor T2 is electrically connected with the data line 3, and the second electrode TC of the second transistor T2 is electrically connected with the second sub-pixel electrode 412 and the third sub-pixel electrode 421; specifically, the second electrode TC of the second transistor T2 can be electrically connected with the third sub-pixel electrode 421 through the second via hole K2, and the second electrode TC of the second transistor T2 can be electrically connected with the second sub-pixel electrode 412 through the third via hole K3.

[0279] The control electrode TA of the third transistor T3 is electrically connected with the gate line 2, the first electrode TB of the third transistor T3 is multiplexed with the second electrode TC of the second transistor T2, and the second electrode TC of the third transistor T3 is electrically connected with the first common line 21.

[0280] In the embodiment of the present disclosure, since the third transistor T3 is connected with the second transistor T2, the voltage loaded on the second sub-pixel electrode 412 and the third sub-pixel electrode 421 is partially divided to the first common line 21 through the third transistor T3, so that the voltage obtained by the second sub-pixel electrode 412 and the third sub-pixel electrode 421 is lower than the voltage obtained by the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, and further, the luminance of the second sub-pixel electrode 412 and the third sub-pixel electrode 421 is less than the luminance of the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, and further, in the sub-pixel, a display effect with different brightness is formed.

[0281] In a possible implementation, as shown in FIGS. 1 to 5, Figures 11A-11I 、 Figures 13A-13C 、 Figures 14A-14C 、 Figures 15A-15C The first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 are electrically connected; the array substrate further comprises: a plurality of transistors, a third common line 23 located on one side of the gate line 2 and extending along the first direction X, and an auxiliary gate line 20 located between the gate line 2 and the third common line 23 and extending along the first direction X; the plurality of transistors T comprises: a first transistor T1, a second transistor T2, and a third transistor T3.

[0282] The control electrode TA of the first transistor T1 is electrically connected with the gate line 2, the first electrode TB of the first transistor T1 is electrically connected with the data line 3, and the second electrode TC of the first transistor T1 is electrically connected with the first sub-pixel electrode 411.

[0283] The control electrode TA of the second transistor T2 is electrically connected with the gate line 2, the first electrode TB of the second transistor T2 is electrically connected with the data line 3, and the second electrode TC of the second transistor T2 is electrically connected with the second sub-pixel electrode 412 and the third sub-pixel electrode 421; optionally, the first electrode TB of the second transistor T2 can be multiplexed with the first electrode TB of the first transistor T1 and connected to the data line 3.

[0284] The control electrode TA of the third transistor T3 is electrically connected with the auxiliary gate line 20, the first electrode TB of the third transistor T3 is multiplexed with the second electrode TC of the first transistor T1, and the second electrode TC of the third transistor T3 has an overlapping area with the second electrode TC of the first transistor T1 in the orthographic projection of the substrate 1.

[0285] Referring to Figure 12 As shown in the figure, wherein, Figure 12 As Figure 11A The corresponding equivalent circuit diagram, S is the data line on the left side of the pixel, that is, the signal line for transmitting the data signal of the current sub-pixel, that is, the data line to which the current sub-pixel is electrically connected. The pixel circuit can include: the first transistor T1, the second transistor T2, the third transistor T3, the third capacitor Cst_light, the fourth capacitor Clc_light, the ninth capacitor Cst_dark, the tenth capacitor Clc_dark, and the fourteenth capacitor Cd; wherein the overlapping area of the first pixel electrode 41 and the third common line 23 can form the third capacitor Cst_light, the first pixel electrode 41 and the common electrode on the opposite substrate side can form the fourth capacitor Clc_light, the overlapping area of the second pixel electrode 42 and the first common line 21 can form the ninth capacitor Cst_dark, the second pixel electrode 42 and the common electrode on the opposite substrate side can form the tenth capacitor Clc_dark, and the overlapping area of the second electrode TC of the third transistor T3 and the third common line 23 can form the fourteenth capacitor Cd.

[0286] Specifically, the array substrate can further include a plurality of cascaded gate driving units, the nth gate line 2 can be electrically connected with the nth gate driving unit to transmit the gate signal output by the nth gate driving unit, and the auxiliary gate line 22 can be electrically connected with the n+mth gate driving unit, that is, the n+mth gate driving unit is electrically connected with the n+mth main gate line 2 and the n-th auxiliary gate line 20 to provide the gate signal to the n+mth gate line 2 and the n-th auxiliary gate line 20 to open the third transistor T3 of the n-th row when the first transistor T1 and the second transistor T2 of the n+mth row are opened, so that the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 of the n-th row are connected through the third transistor T3 and the fourteenth capacitor Cd, and the voltages of the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 are lower than the voltages of the second sub-pixel electrode 412 and the third sub-pixel electrode 421. Therefore, the luminance of the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 is lower than the luminance of the second sub-pixel electrode 412 and the third sub-pixel electrode 421, and more luminance steps can improve the color deviation problem of the liquid crystal display panel.

[0287] Specifically, m≥1; specifically, m=6; for example, when n=1 and m=6, that is, the 7th gate driving unit is electrically connected with the 7th main gate line 21 and the 1st auxiliary gate line 22 to provide the gate signal to the 7th main gate line 21 and the 1st auxiliary gate line 22 to open the second transistor T2 of the 1st row when the first transistor T1 of the 7th row is opened, so that the luminance of the 1st pixel electrode 4200 is reduced.

[0288] In one possible implementation, as shown in Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G The pixel electrode 4 further includes a connecting portion 44 connecting the first sub-pixel electrode 412 and the fourth sub-pixel electrode 422, and a first overlap portion PD1 connected to the connecting portion 44; the connecting portion 44 includes a third connecting portion 443 extending along the first direction X, a fourth connecting portion 444, and a fifth connecting portion 445 extending along the second direction Y;

[0289] One end of the third connecting portion 443 is connected with the first sub-pixel electrode 411, one end of the fourth connecting portion 444 is connected with the fourth sub-pixel electrode 422, one end of the fifth connecting portion 445 is connected with the other end of the third connecting portion 443, and the other end of the fifth connecting portion 445 is connected with the other end of the fourth connecting portion 444; the first overlap portion PD1 is electrically connected to the first connecting portion 441 and away from the side of the first sub-pixel electrode 411 connected to the first connecting portion 441;

[0290] The second electrode TC of the first transistor T1 is electrically connected with the first sub-pixel electrode 411 and the fourth sub-pixel electrode 421 through the first bonding portion PD1.

[0291] In the embodiments of the present disclosure, the connecting portion 44 includes a third connecting portion 443 extending along the first direction X, a fourth connecting portion 444, and a fifth connecting portion 445 extending along the second direction Y. The wiring of the connecting portion 44 is regular, which is conducive to simple wiring between the first pixel electrode 41 and the second pixel electrode 42. In addition, the connecting portion 44 is also connected with the first bonding portion PD1. In this way, the first bonding portion PD1 and the second electrode TC of the first transistor T1 are electrically connected through the first via K1.

[0292] In a possible implementation, as shown in Figure 2B , the control electrode TA of the third transistor T3 is electrically connected with the gate line 2; at least part of the orthographic projection of the third transistor T3 and the first transistor T1 on the substrate 1 is located on different sides of the orthographic projection of the fifth connecting portion 445 on the substrate 1; optionally, the main structure of the orthographic projection of the third transistor T3 and the first transistor T1 on the substrate 1 is located on different sides of the orthographic projection of the fifth connecting portion 445 on the substrate 1; optionally, as shown in Figure 2B , the active pattern 6 of the third transistor T3 and the active pattern 6 of the first transistor T1 are located on different sides of the orthographic projection of the fifth connecting portion 445 on the substrate 1.

[0293] In a possible implementation, as shown in Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5GAs shown, the pixel electrode further includes: a first adapter PZ1 extending along the first direction X, and a second adapter PZ2 extending along the second direction Y, and a second lap joint PD2; one end of the first adapter PZ1 is electrically connected to one end of the second sub-pixel electrode 412 towards the fourth sub-pixel electrode 422, and the other end of the first adapter PZ1 is electrically connected to one end of the second adapter PZ2; the other end of the second adapter PZ2 is electrically connected to the second lap joint PD2; the second electrode TB of the second transistor T2 is electrically connected to the second sub-pixel electrode 412 through the second lap joint PD2. In the embodiment of the present disclosure, one side of the second sub-pixel electrode 412 is also provided with the first adapter PZ1, the second adapter PZ2 extending along the second direction Y, and the second lap joint PD2, so as to realize the electrical connection between the second sub-pixel electrode 412 and the second electrode TB of the second transistor T2, and the wiring mode of the electrical connection between the second sub-pixel electrode 412 and the second electrode TB of the second transistor T2 is simple and regular, which is beneficial to the simple wiring between the gaps of the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit failure during etching and patterning when the layout of multiple patterns is complex.

[0294] In a possible implementation, the fifth connecting part 445 can be linear, as shown in Figures 2A-2G 、 Figures 3A-3G 、 Figures 4A-4G 、 Figures 5A-5G As shown, the fifth connecting part 445 extends along the second direction Y; the second adapter PZ2 is parallel to the extension direction of the fifth connecting part 445, so as to be beneficial to the simple wiring between the gaps of the first pixel electrode 41 and the second pixel electrode 42, and avoid the risk of short circuit failure during etching and patterning when the layout of multiple patterns is complex.

[0295] In a possible implementation, as shown in Figure 11B The control electrode TA of the third transistor T3 is electrically connected to the auxiliary gate line 20; at least part of the orthographic projection of the third transistor T3 and the first transistor T1 on the substrate 1 is located on the same side of the orthographic projection of the fifth connecting part 445 on the substrate 1; optionally, the main structure of the orthographic projection of the third transistor T3 and the first transistor T1 on the substrate 1 is located on the same side of the orthographic projection of the fifth connecting part 445 on the substrate 1; optionally, as shown in Figure 11B The active pattern 6 of the third transistor T3 and the active pattern 6 of the first transistor T1 are located on the same side of the orthographic projection of the fifth connecting part 445 on the substrate 1.

[0296] In a possible implementation, as shown in Figure 11B 、 Figure 11GAs shown, the fifth connecting part 445 can also be in a broken line shape, and the fifth connecting part 445 comprises a first sub connecting part LL1, a second sub connecting part LL2, and a third sub connecting part LL3; the first sub connecting part LL1 extends along the third direction Z, and one end thereof is electrically connected to the other end of the third connecting part 443, and the other end thereof is electrically connected to the second sub connecting part LL2; the third direction Z intersects the first direction X and the second direction Y; the second sub connecting part LL2 extends along the second direction Y, and the other end of the second sub connecting part LL2 is electrically connected to one end of the third sub connecting part LL3; the third sub connecting part LL3 extends along the third direction Z, and the other end of the third sub connecting part LL3 is electrically connected to the other end of the fourth connecting part 444.

[0297] In the embodiments of the present disclosure, the fifth connecting part 445 can also be in a broken line shape, and the fifth connecting part 445 can avoid the second electrode TC of the third transistor T3, reduce the overlapping area of the fifth connecting part 445 and the second electrode TC of the third transistor T3, and further reduce the coupling capacitance of the two.

[0298] In a possible implementation, referring to Figure 11B , Figure 11G As shown, the pixel electrode 4 further comprises a first transfer part PZ1 extending along a fourth direction G1, a second transfer part PZ2 extending along the second direction Y, and a second lap joint part PD2; one end of the first transfer part PZ1 is electrically connected to one end of the second sub pixel electrode 412 toward the fourth sub pixel electrode 422, and the other end of the first transfer part PZ1 is electrically connected to one end of the second transfer part PZ2; the other end of the second transfer part PZ2 is electrically connected to the second lap joint part PD2; and the second electrode TC of the second transistor T2 is electrically connected to the second sub pixel electrode 412 through the second lap joint part PD2.

[0299] In the embodiments of the present disclosure, the first transfer part PZ1 extends along the fourth direction G2, and can avoid the second electrode TC of the third transistor T3, reduce the overlapping area of the first transfer part PZ1 and the second electrode TC of the third transistor T3, and further reduce the coupling capacitance of the two.

[0300] In a possible implementation, the fourth direction G1 intersects the first direction X and the second direction Y; the fourth direction G1 can form an angle of 0-90° with the first direction X, specifically, the fourth direction G1 forms an angle of 30-60° with the first direction X, and specifically, the fourth direction G1 forms an angle of 45° with the first direction X.

[0301] In a possible implementation, referring to Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5GAs shown, the extension line of the first adapter PZ1 coincides with the extension line of the third connecting portion 443, and thus, the simple wiring between the first pixel electrode 41 and the second pixel electrode 42 is facilitated, and the risk of short circuit failure during etching and patterning is avoided when the multiple pattern layouts are complex.

[0302] In a possible implementation, referring to Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the pixel electrode 4 further includes a third adapter PZ3 extending along the first direction X and a third lap joint PD3; one end of the third adapter PZ3 is electrically connected to one end of the third sub-pixel electrode 421 facing the first sub-pixel electrode 411, and the other end of the third adapter PZ3 is electrically connected to the third lap joint PD3; the second electrode TC of the second transistor T2 is electrically connected to the third sub-pixel electrode 421 through the third lap joint PD3. In the embodiment of the present disclosure, one side of the third sub-pixel electrode 421 is further provided with the third adapter PZ3 and the third lap joint PD3, so as to realize the electrical connection between the third sub-pixel electrode 421 and the second electrode TB of the second transistor T2, and the wiring mode of the electrical connection between the third sub-pixel electrode 421 and the second electrode TB of the second transistor T2 is simple and regular, which is conducive to the simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit failure during etching and patterning when the multiple pattern layouts are complex.

[0303] In a possible implementation, referring to Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the extension line of the third adapter PZ3 coincides with the extension line of the fourth connecting portion 444, and thus, the simple wiring between the first pixel electrode 41 and the second pixel electrode 42 is facilitated, and the risk of short circuit failure during etching and patterning is avoided when the multiple pattern layouts are complex.

[0304] In a possible implementation, referring to Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the third connecting portion 443 and the first pixel electrode 41 have a first gap J1; the fourth connecting portion 444 and the second pixel electrode 42 have a second gap J2; the first adapter PZ1 and the first pixel electrode 41 have a third gap J3, and the third adapter PZ3 and the second pixel electrode 42 have a fourth gap J4. Specifically, for example, as Figure 2GIn the embodiment, the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 are two parts with relatively high brightness, the second sub-pixel electrode 412 and the third sub-pixel electrode 421 are two parts with relatively low brightness, the first adapter PZ1 is a structure electrically connected with the second sub-pixel electrode 412 with relatively low brightness, and the voltage loaded is also relatively low. The first sub-pixel electrode 411 has a relatively long relative arrangement area with the first sub-pixel electrode 411 with a relatively high voltage. By providing the third gap J3 between the first adapter PZ1 and the first sub-pixel electrode 411, the distance between the first adapter PZ1 and the first sub-pixel electrode 411 can be avoided to be too close, and the voltage difference is large, and the problem of breakdown and other problems is prone to occur. Similarly, the third adapter PZ3 and the fourth sub-pixel electrode 422 have the fourth gap J4, so that the distance between the third adapter PZ3 and the fourth sub-pixel electrode 422 can be avoided to be too close, and the voltage difference is large, and the problem of breakdown and other problems is prone to occur. The third connecting portion 443 and the first pixel electrode 41 have the first gap J1, and the fourth connecting portion 444 and the second pixel electrode 42 have the second gap J2, so that the third gap J3 and the fourth gap J4 can be relatively symmetrical, and the design is beneficial to the neat layout of the plurality of patterns.

[0305] In a possible implementation, referring to FIG. 1, Figures 2A-2G 、 Figures 3A-3G 、 Figures 4A-4G 、 Figures 5A-5G The array substrate further includes a fourth lap joint PD4, and the second electrode TC of the third transistor T3 is electrically connected with the first common wire 21 through the fourth lap joint PD4.

[0306] In a possible implementation, referring to FIG. 1, Figures 2A-2G 、 Figures 3A-3G 、 Figures 4A-4G 、 Figures 5A-5G The second electrode TC of the third transistor T3 can be electrically connected with the first common wire 21 through a fourth via K4.

[0307] In a possible implementation, referring to FIG. 1, Figure 2I , Figure 2I may be Figure 2B In the embodiment, the fourth via K4 can be a half-via design, and the fourth via K4 partially exposes the first common wire 21 and partially exposes the second electrode TC of the third transistor T3. The fourth lap joint PD4 partially contacts the first common wire 21 and partially contacts the second electrode TC of the third transistor T3 at the fourth via K4, so as to electrically connect the first common wire 21 and the second electrode TC of the third transistor T3 through the fourth lap joint PD4. Specifically, the fourth via K4 is a half-via design, which can form a step structure inside the fourth via K4, so as to guide the flow of the alignment liquid and avoid the moire phenomenon of the picture.

[0308] In a possible implementation, referring to FIG. 1, Figures 2A-2G 、 Figures 3A-3G 、 Figures 4A-4G 、 Figures 5A-5G As shown in FIG. 1, the fourth overlap portion PD4 has a fourth overlap portion outer edge f3 extending along the first direction X, and the second overlap portion PD2 has a second overlap portion outer edge f4 extending along the first direction X; the first overlap portion PD1 has a first overlap portion outer edge f5 extending along the second direction Y, and the third overlap portion PD3 has a third overlap portion outer edge f6 extending along the second direction Y; the extension line of the fourth overlap portion outer edge f3 coincides with the extension line of the second overlap portion outer edge f4; and the extension line of the first overlap portion outer edge f5 coincides with the extension line of the third overlap portion outer edge f6.

[0309] In the embodiment of the present disclosure, the extension line of the fourth overlap portion outer edge f3 coincides with the extension line of the second overlap portion outer edge f4; and the extension line of the first overlap portion outer edge f5 coincides with the extension line of the third overlap portion outer edge f6, so that the pattern distribution between the first pixel electrode 41 and the second pixel electrode 42 is simple and regular, and the risk of short circuit failure during etching and patterning is avoided when the multiple pattern layouts are complex.

[0310] In a possible implementation, referring to FIG. 1, Figures 2A-2G 、 Figures 3A-3G 、 Figures 4A-4G 、 Figures 5A-5G As shown in FIG. 1, the second electrode TC of the first transistor T1 includes a first transistor first portion T1C1 extending along the first direction X; and the orthogonal projection of the first transistor first portion T1C1 on the substrate 1 has an overlapping area with the orthogonal projection of the first overlap portion PD1 on the substrate 1. In this way, the first transistor first portion T1C1 and the first overlap portion PD1 are electrically connected through the first via hole K1.

[0311] In a possible implementation, referring to FIG. 1, Figures 2A-2G 、 Figures 3A-3G 、 Figures 4A-4G 、 Figures 5A-5G As shown in FIG. 1, the second electrode TC of the first transistor T1 includes a first transistor second portion T1C2 extending along the second direction Y and electrically connected with the first transistor first portion T1C1; and specifically, the orthogonal projection of the first transistor second portion T1C2 on the substrate 1 can have an overlapping area with the orthogonal projection of the active pattern 6 on the substrate 1.

[0312] In a possible implementation, referring to FIG. 1, Figures 2A-2G 、 Figures 3A-3G 、 Figures 4A-4G 、 Figures 5A-5GAs shown in FIG. 1, the second electrode TC of the second transistor T2 can include: a first part T2C1 of the second transistor extending along the first direction X, and a second part T2C2 of the second transistor extending along the second direction Y and electrically connected to one end of the first part T2C1 of the second transistor; the orthographic projection of the first part T2C1 of the second transistor on the substrate 1 has an overlapping area with the orthographic projection of the third overlap part PD3 on the substrate 1, so that the first part T2C1 of the second transistor and the third overlap part PD3 are electrically connected through the second via K2; the orthographic projection of the second part T2C2 of the second transistor on the substrate 1 has an overlapping area with the orthographic projection of the second overlap part PD2 on the substrate 1, so that the second part T2C2 of the second transistor and the second overlap part PD2 are electrically connected through the third via K3.

[0313] In a possible implementation, referring to FIG. 1, Figures 2A-2G 、 Figures 3A-3G 、 Figures 4A-4G 、 Figures 5A-5G As shown in FIG. 1, the second electrode TC of the second transistor T2 can further include: a third part T2C3 of the second transistor electrically connected to the other end of the first part T2C1 of the second transistor and extending along the second direction Y; specifically, the orthographic projection of the third part T2C3 of the second transistor on the substrate 1 can have an overlapping area with the orthographic projection of the active pattern 6 on the substrate 1.

[0314] In a possible implementation, referring to FIG. 1, Figures 2A-2G 、 Figures 3A-3G 、 Figures 4A-4G 、 Figures 5A-5G As shown in FIG. 1, the second electrode TC of the third transistor T3 can include: a first part T3C1 of the third transistor extending along the second direction Y, and a second part T3C2 of the third transistor extending along the first direction X and connected to the first part T3C1 of the third transistor.

[0315] In a possible implementation, referring to FIG. 1, Figures 2A-2G 、 Figures 3A-3G 、 Figures 4A-4G 、 Figures 5A-5G As shown in FIG. 1, the extending direction of the first part T3C1 of the third transistor is parallel to the extending direction of the second part T2C2 of the second transistor.

[0316] In a possible implementation, referring to FIG. 1, Figures 20A-20K 、 Figures 21A-21C 、 Figures 22A-22C 、 Figures 23A-23CAs shown in the figure, the array substrate further comprises: a plurality of transistors; the plurality of transistors T electrically connected to the same pixel electrode 4 are electrically connected to the same data line 3 and the same gate line 2; the second sub-pixel electrode 412 is located on the side of the first sub-pixel electrode 411 away from the electrically connected data line 3, and the fourth sub-pixel electrode 422 is located on the side of the third sub-pixel electrode 421 away from the electrically connected data line 3; the first sub-pixel electrode 411 is electrically connected to the third sub-pixel electrode 421, and the second sub-pixel electrode 412 is electrically connected to the fourth sub-pixel electrode 422.

[0317] In the embodiments of the present disclosure, the first sub-pixel electrode 411 is electrically connected to the third sub-pixel electrode 421, and the second sub-pixel electrode 412 is electrically connected to the fourth sub-pixel electrode 422, which can realize near connection and make the wiring more simple, and is beneficial to improving the yield of the display panel.

[0318] Optionally, the plurality of transistors T electrically connected to the same pixel electrode 4 can be transistors in a pixel circuit for driving the pixel electrode 4, that is, the plurality of transistors in the pixel circuit for driving the same pixel electrode 4 are electrically connected to the same data line 3 and the same gate line 2.

[0319] In a possible implementation, referring to Figure 20B As shown in the figure, the array substrate further comprises: a first signal line 5 extending along the second direction Y; the plurality of transistors comprise: a first transistor T1, a second transistor T2, and a third transistor T3; the control electrode TA of the first transistor T1 is electrically connected to the gate line 2, the first electrode TB of the first transistor T1 is electrically connected to the data line 3, and the second electrode TC of the first transistor T1 is electrically connected to the first sub-pixel electrode 411; specifically, the second electrode TC of the first transistor T1 can be electrically connected to the first sub-pixel electrode 411 through the first via hole K1; the control electrode TA of the second transistor T2 is electrically connected to the gate line 2, the first electrode TB of the second transistor T2 is electrically connected to the data line 3 (the first electrode TB of the second transistor T2 can be a part of the multiplexed data line 3), and the second electrode TC of the second transistor T2 is electrically connected to the fourth sub-pixel electrode 422; specifically, the second electrode TC of the second transistor T2 can be electrically connected to the fourth sub-pixel electrode 422 through the second via hole K2; the control electrode TA of the third transistor T3 is electrically connected to the gate line 2, the first electrode TB of the third transistor T3 multiplexes the second electrode TC of the second transistor T2, and the second electrode TC of the third transistor T3 multiplexes the first signal line 5.

[0320] In a possible implementation, referring to Figure 20B , Figure 20G As shown in the figure, the pixel electrode 4 further comprises: a connecting portion 44; the connecting portion 44 extends along the second direction Y and connects the first sub-pixel electrode 411 and the third sub-pixel electrode 421.

[0321] In one possible implementation, see Figure 20B , Figure 20G As shown, the connecting portion 44 is in the same layer and made of the same material as the first sub-pixel electrode 411 and the third sub-pixel electrode 421. The connecting portion 44 can be formed at the same time as the first sub-pixel electrode 411 and the third sub-pixel electrode 421 are formed, which simplifies the fabrication process of the array substrate.

[0322] In one possible implementation, see Figure 20B , Figure 20G As shown, the pixel electrode 4 further includes a connecting portion 45; the connecting portion 45 includes a first connecting portion 451 and a second connecting portion 452; the connecting portion 45 connects the second sub-pixel electrode 412 and the fourth sub-pixel electrode 422; the first connecting portion 451 extends along the first direction X, one end of which is electrically connected to the second sub-pixel electrode 412, and the other end of which is electrically connected to one end of the second connecting portion 452; the other end of the second connecting portion 452 is electrically connected to the fourth sub-pixel electrode 422.

[0323] In one possible implementation, see Figure 20B , Figure 20G As shown, the connecting portion 45 is in the same layer and made of the same material as the second sub-pixel electrode 412 and the fourth sub-pixel electrode 422. The connecting portion 45 can be formed at the same time as the second sub-pixel electrode 412 and the fourth sub-pixel electrode 422 are formed, which simplifies the fabrication process of the array substrate.

[0324] In one possible implementation, the second connecting portion 452 may be a straight line extending along the second direction Y; in another possible implementation, such as Figure 20B As shown, the second connecting part 452 can also be a broken line extending along the second direction Y as a whole, and there may be bends in some local positions.

[0325] In one possible implementation, see Figure 20G As shown, the first pixel electrode 41 has a notch 46 on the side facing the gate line 2; at least a portion of the connecting portion 45 is located in the orthographic projection of the notch 46 onto the substrate 1. In this embodiment of the present disclosure, the first pixel electrode 41 has a notch 46 on the side facing the gate line 2, thereby avoiding the first connecting portion 451.

[0326] In one possible implementation, see Figure 20G As shown, the notch 46 can be located in the first sub-pixel electrode 411 of the first pixel electrode 41; in another possible embodiment, the notch 46 can also be located in the second sub-pixel electrode 412 of the first pixel electrode 41.

[0327] In one possible implementation, see Figure 20B , Figure 20GAs shown, the pixel electrode 4 further includes: a first sub-pixel electrode protrusion 47 connected to the side of the first sub-pixel electrode 411 facing the third sub-pixel electrode 421; the second electrode TC of the first transistor T1 is electrically connected to the first sub-pixel electrode 411 through the first sub-pixel electrode protrusion 47.

[0328] The pixel electrode 4 also includes: a fourth sub-pixel electrode protrusion 48 connected to the side of the fourth sub-pixel electrode 422 facing the first sub-pixel electrode 411; the second electrode TC of the second transistor T2 is electrically connected to the fourth sub-pixel electrode 422 through the fourth sub-pixel electrode protrusion 48.

[0329] In one possible implementation, see Figure 20B , Figure 20G As shown, the orthographic projections of the first sub-pixel electrode protrusion 47 and the fourth sub-pixel electrode protrusion 48 onto the substrate 1 are both located between the orthographic projection of the connecting portion 44 onto the substrate 1 and the orthographic projection of the connecting portion 45 onto the substrate 1. In this way, on the one hand, the first electrode TB of the third transistor T3 can reuse the second electrode TC of the second transistor T2, thereby reducing the coupling capacitance Cgd between the gate line and the drain. On the other hand, the winding of the first signal line 5 can be reduced, thereby reducing the impedance of the first signal line 5, which is beneficial to improving the display effect. Moreover, more flat areas can be left empty around it, which is convenient for the placement of spacers.

[0330] In one possible implementation, see Figure 20G As shown, the first sub-pixel electrode protrusion 47 has a first sub-pixel electrode protrusion outer edge 471 extending along the second direction Y; the fourth sub-pixel electrode protrusion 48 has a fourth sub-pixel electrode protrusion outer edge 481 extending along the second direction Y; the extension line of the outer edge 471 of the first sub-pixel electrode protrusion at least partially overlaps with the fourth sub-pixel electrode protrusion 48.

[0331] In one possible implementation, the extension line of the outer edge 471 of the first sub-pixel electrode protrusion coincides with the outer edge 481 of the fourth sub-pixel electrode protrusion. This allows the first sub-pixel electrode protrusion 47 and the fourth sub-pixel electrode protrusion 48 to be located in the same second direction Y, simplifying the wiring space of the array substrate.

[0332] In one possible implementation, see Figures 1A-1G As shown, the array substrate further includes: a first common trace 21 located on one side of the gate line 2 and extending along the first direction; the first common trace 21 is disconnected at the position where it intersects with the data line 3. This is to avoid the first common trace 21 overlapping with the data line 3, which would increase the load on the data line 3 and affect the signal transmission of the data line 3.

[0333] In one possible implementation, see Figures 1A-1G , Figures 2A-2G, Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the array substrate further includes a second common trace group 22 electrically connected to the first common trace 21 and extending away from the gate line 2. The second common trace group 22 includes two second common traces 220. The orthographic projection of the data line 3 on the substrate 1 overlaps with the gap between the two second common traces 220 of the same second common trace group 22 on the orthographic projection of the data line 3 on the substrate 1. The orthographic projections of the second common traces 220 on the substrate 1 are located on both sides of the orthographic projection of the data line 3 on the substrate 1, which can improve the coupling capacitance between the data line 3 and the second pixel electrode 42.

[0334] In one possible implementation, see Figures 1A-1G , Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the array substrate further includes: a third common trace 23 located on the other side of the gate line 2 and extending along the first direction X, and a fourth common trace group 24 connected to the third common trace 23 and extending away from the gate line 2; the third common trace 23 is disconnected at the position where it intersects with the data line 3, so as to avoid the third common trace 23 overlapping with the data line 3, which would increase the load on the data line 3 and affect the signal transmission of the data line 3; the fourth common trace group 24 includes: two fourth common traces 240; the orthographic projection of the data line 3 on the substrate 1 and the gap between the two fourth common traces 240 of the same fourth common trace group 24 have an overlapping area in the orthographic projection of the substrate 1. The orthographic projection of the fourth common traces 240 on the substrate 1 is located on both sides of the orthographic projection of the data line 3 on the substrate 1, which can improve the coupling capacitance between the data line 3 and the first pixel electrode 41.

[0335] In one possible implementation, the first common trace 21 and the third common trace 23 can be electrically connected in the display area via a bridging method, or they can be electrically connected in the non-display area. In another possible implementation, the array substrate may further include a non-display area located around the outer edge of the display area. The non-display area may be provided with a ring-shaped common trace surrounding the display area. The first common trace 21 and the third common trace 23 may both be electrically connected to the ring-shaped common trace to have the same common voltage signal.

[0336] In one possible implementation, see Figures 1A-1G As shown, the array substrate further includes a fifth common trace 25 extending along the first direction X and electrically connected to the second common trace 220. The orthogonal projection of the fifth common trace 25 onto the substrate passes through the central region of the orthogonal projection of the second pixel electrode 42 onto the substrate 1.

[0337] In one possible implementation, see Figures 1A-1GAs shown in FIG. 1, the array substrate further includes a sixth common line 26 extending along the first direction X and electrically connected to the fourth common line 240, and a projection of the sixth common line 26 on the substrate 1 passes through the first pixel electrode 41 in a central region of the projection of the substrate 1.

[0338] In a possible implementation, referring to Figures 1A-1G , Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown in FIG. 1, the first sub-pixel electrode 411 and the second sub-pixel electrode 412 each include a first sub-electrode part P1 and a second sub-electrode part P2 distributed along the second direction Y, and the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422 each include a third sub-electrode part P3 and a fourth sub-electrode part P4 distributed along the second direction Y, the first sub-electrode part P1, the second sub-electrode part P2, the third sub-electrode part P3 and the fourth sub-electrode part P4 each have a plurality of slits F, and the extension direction of the slits F of the first sub-electrode part P1 is the same as the extension direction of the slits F of the fourth sub-electrode part P4, and the extension direction of the slits F of the second sub-electrode part P2 is the same as the extension direction of the slits F of the third sub-electrode part P3.

[0339] In a possible implementation, the length of the slit F in a direction perpendicular to the extension direction can be 2 μm to 4 μm. Specifically, the length of the slit F in a direction perpendicular to the extension direction can be 3 μm. In the array substrate provided in the embodiments of the present disclosure, when the length of the slit F in a direction perpendicular to the extension direction is reduced to 3 μm, the dark lines almost disappear.

[0340] Specifically, referring to Figures 1A-1G , Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown in FIG. 1, the extension direction of the slit F of the first sub-electrode part P1 forms an angle of 40° to 50° with the first direction X, for example, the angle can be 45°, the extension direction of the slit F of the second sub-electrode part P2 forms an angle of 130° to 140° with the first direction X, for example, the angle can be 135°, the extension direction of the slit F of the third sub-electrode part P3 forms an angle of 130° to 140° with the first direction X, for example, the angle can be 135°, and the extension direction of the slit F of the fourth sub-electrode part P4 forms an angle of 40° to 50° with the first direction X, for example, the angle can be 45°.

[0341] Specifically, the angle between the liquid crystal alignment direction of the region where the first sub-electrode part P1 is located and the first direction X can be 220°-230°, for example, 225°; the angle between the liquid crystal alignment direction of the region where the second sub-electrode part P2 is located and the first direction X can be 130°-140°, for example, 135°; the angle between the liquid crystal alignment direction of the region where the third sub-electrode part P3 is located and the first direction X can be 310°-320°, for example, 315°; and the angle between the liquid crystal alignment direction of the region where the fourth sub-electrode part P4 is located and the first direction X can be 40°-50°, for example, 45°. In the region where the pixel electrode 4 is located, four alignment directions are realized, and in combination with the segmented light and dark regions, an 8-domain alignment mode in a sub-pixel can be formed when the Super UV Photo Alignment (SUVA) technology is used.

[0342] In a possible implementation, as shown in FIG. 4, the first sub-pixel electrode 411, the second sub-pixel electrode 412, the third sub-pixel electrode 421, and the fourth sub-pixel electrode 422 are all rectangular in the orthographic projection shape on the substrate 1. Figures 1A-1G 、 Figures 4A-4G In a possible implementation, as shown in FIG. 4, the first sub-pixel electrode 411, the second sub-pixel electrode 412, the third sub-pixel electrode 421, and the fourth sub-pixel electrode 422 are all rectangular in the orthographic projection shape on the substrate 1.

[0343] In a possible implementation, as shown in FIG. 4, the first sub-pixel electrode 411, the second sub-pixel electrode 412, the third sub-pixel electrode 421, and the fourth sub-pixel electrode 422 are all rectangular in the orthographic projection shape on the substrate 1. Figures 2A-2G In a possible implementation, as shown in FIG. 4, the first sub-pixel electrode 411, the second sub-pixel electrode 412, the third sub-pixel electrode 421, and the fourth sub-pixel electrode 422 are all rectangular in the orthographic projection shape on the substrate 1.

[0344] In a possible implementation, as shown in FIG. 4, the first sub-pixel electrode 411, the second sub-pixel electrode 412, the third sub-pixel electrode 421, and the fourth sub-pixel electrode 422 are all rectangular in the orthographic projection shape on the substrate 1. Figures 3A-3GAs shown, the first sub-electrode portion P1, the second sub-electrode portion P2, the third sub-electrode portion P3, and the fourth sub-electrode portion P4 are all in the shape of a trapezoid in the orthographic projection of the substrate 1; among the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, the first sub-electrode portion P1 of the trapezoid and the second sub-electrode portion P2 of the trapezoid are arranged opposite to each other with the bottom edges (i.e., with the long edges); among the second sub-pixel electrode 412 and the third sub-pixel electrode 421, the first sub-electrode portion P1 of the trapezoid and the second sub-electrode portion P2 of the trapezoid are arranged opposite to each other with the top edges (i.e., with the short edges). In the embodiment of the present disclosure, the first pixel electrode 41 and the second pixel electrode 42 can be divided in the manner of the vertical slit F extending direction, and can have a better transmittance effect.

[0345] In a possible implementation, referring to Figures 5A-5G As shown, the first sub-pixel electrode 411 includes a first main portion PA1 extending along the second direction Y and connected to a second main portion PA2, a first side portion PC1 extending along the first direction X, a plurality of first branch portions PB1 extending from the first main portion PA1 and the first side portion PC1 along a fourth direction G1, and a plurality of second branch portions PB2 extending from the second main portion PA2 and the first side portion PC1 along a fifth direction G2; the second sub-pixel electrode 412 includes a third main portion PA3 extending along the second direction Y and connected to a fourth main portion PA4, a fifth main portion PA5 connected to one end of the third main portion PA3 and extending along the first direction X, a sixth main portion PA6 connected to one end of the fourth main portion PA4 and extending along the first direction X, a plurality of third branch portions PB3 extending from the third main portion PA3 and the fifth main portion PA5 along the fourth direction G1, and a plurality of fourth branch portions PB4 extending from the fourth main portion PA4 and the sixth main portion PA6 along the fifth direction G2; the plurality of first branch portions PB1 and the plurality of third branch portions PB3 are in a forked distribution, and the plurality of second branch portions PB2 and the plurality of fourth branch portions PB4 are in a forked distribution;

[0346] The third sub-pixel electrode 421 includes: a seventh main portion PA7 extending and connected along the second direction Y, an eighth main portion PA8, a ninth main portion PA9 connected to one end of the seventh main portion PA7 and extending along the first direction X, a tenth main portion PA10 connected to one end of the eighth main portion PA8 and extending along the first direction X, a plurality of fifth branches PB5 extending from the seventh main portion PA7 and the ninth main portion PA9 along the fourth direction G1, and a plurality of sixth branches PB6 extending from the eighth main portion PA8 and the tenth main portion PA10 along the fifth direction G2; the fourth sub-pixel electrode 421 includes: a seventh main portion PA7 extending along the second direction Y and connected along the second direction Y, an eighth main portion PA7 and the ninth main portion PA9 extending along the second direction Y, a ninth main portion PA9 connected along the third direction Y and the ninth main portion PA9 extending along the first direction X, a tenth main portion PA10 connected along the second direction Y, a tenth main portion PA10 extending along the third direction G2, and a tenth main portion PA10 extending along the fifth direction G2; the fourth sub-pixel electrode 421 includes: a seventh main portion PA7 extending along the second direction Y and connected along the second direction Y, an eighth main portion PA8 extending along the second direction Y, an eighth main portion PA7 extending along the second direction Y, an eighth main portion PA8 extending along the second direction Y, a tenth main portion PA10 extending along the third direction G2, and a tenth main portion PA10 extending along the third direction Y; the fourth sub-pixel electrode 421 includes: a seventh main portion PA7 extending along the second direction Y and connected along the second direction Y, an eighth main portion PA8 extending along the second direction Y, a ninth main portion PA9 extending along the first direction X, a tenth main portion PA10 extending along the second direction Y, a tenth main portion PA10 extending along the second direction Y, a tenth main portion PA10 extending along the third direction G2, and a tenth main portion PA10 extending along the third direction Y; the fourth sub-pi The pixel electrode 422 includes: an eleventh main portion PA11 extending and connected along the second direction Y, a twelfth main portion PA12, and a second side portion PC2 extending along the first direction X; a plurality of seventh branches PB7 extending from the eleventh main portion PA11 and the second side portion PC2 along the fourth direction G1; and a plurality of eighth branches PB8 extending from the twelfth main portion PA12 and the second side portion PC2 along the fifth direction G2; the plurality of fifth branches PB5 and the plurality of seventh branches PB7 are interdigitated, and the plurality of sixth branches PB6 and the plurality of eighth branches PB8 are interdigitated.

[0347] It should be noted that, for the embodiments provided in this disclosure... Figure 2A , Figure 3A , Figure 5A The corresponding array substrate structure can also achieve different brightness display effects by setting a first signal line 5 and releasing part of the voltage to the first signal line 5 through the third transistor T3; similarly, for the embodiments provided in this disclosure... Figure 1A The array substrate shown may also omit the first signal line 5 and release part of the voltage to the first common trace 21 through the third transistor T3 to achieve different brightness display effects. This disclosure does not limit this.

[0348] In one possible implementation, see Figures 6A-6J As shown, the array substrate further includes: a first conductive layer 7 located on the side of the pixel electrode 4 facing the substrate 1; the first conductive layer 7 has a first cutout L1, a second cutout L2, a third cutout L3, and a fourth cutout L4; at least a portion of the orthographic projection of the first cutout L1 onto the substrate 1 overlaps with at least a portion of the orthographic projection of the first sub-electrode P1 onto the substrate 1; at least a portion of the orthographic projection of the second cutout L2 onto the substrate 1 overlaps with at least a portion of the orthographic projection of the second sub-electrode P2 onto the substrate 1; at least a portion of the orthographic projection of the third cutout L3 onto the substrate 1 overlaps with at least a portion of the orthographic projection of the third sub-electrode P3 onto the substrate 1; at least a portion of the orthographic projection of the fourth cutout L4 onto the substrate 1 overlaps with at least a portion of the orthographic projection of the fourth sub-electrode P4 onto the substrate 1.

[0349] In the display panel of the VA display mode, the pixel electrode 4 is provided with the first conductive layer 7 on the side facing the substrate 1. The first conductive layer 7 has the first hollow L1, the second hollow L2, the third hollow L3, and the fourth hollow L4, which can make the liquid crystal twist more uniformly, reduce the dark lines corresponding to the pixel electrode, reduce the width of the black matrix, and improve the transmittance of the display panel. In addition, in the array substrate, in addition to the vertical electric field formed by the pixel electrode and the common electrode, the pixel electrode and the first conductive layer 7 form a horizontal electric field, which can increase the deflection direction of the liquid crystal and improve the color deviation problem of the display panel.

[0350] Specifically, the first conductive layer 7 can be located between the substrate 1 and the layer where the pixel electrode 4 is located. Specifically, the first conductive layer 7 can be the same signal loaded on the common electrode layer of the opposite substrate. The first conductive layer 7 can be a transparent electrode layer, and the material of the first conductive layer 7 can be indium tin oxide.

[0351] In a possible implementation, as shown in Figure 6G The first conductive layer 7 can further include a first conductive connection part 71. The first conductive connection part 71 covers the projection of the data line 3 on the substrate 1 and the projection of the gate line 2 on the substrate 1. In the display panel, the first conductive connection part 71 covers the projection of the data line 3 on the substrate 1, which can shield the coupling capacitance between the pixel electrode and the data line 3 and the coupling capacitance between the pixel electrode and the gate line 2 through the first conductive connection part 71. The second common line 220 (and / or the fourth common line 240) can be avoided or the number or line width of the second common line 220 (and / or the fourth common line 240) can be reduced, thereby increasing the transmittance of the display panel.

[0352] In a possible implementation, as shown in Figure 6G The first conductive layer 7 can further include a fifth hollow L5, a sixth hollow L6, a seventh hollow L7, and an eighth hollow L8. At least part of the projection of the fifth hollow L5 on the substrate 1 can overlap at least part of the projection of the first via K1 on the substrate 1. At least part of the projection of the sixth hollow L6 on the substrate 1 can overlap at least part of the projection of the second via K2 on the substrate 1. At least part of the projection of the seventh hollow L7 on the substrate 1 can overlap at least part of the projection of the third via K3 on the substrate 1. The fifth hollow L5, the sixth hollow L6, and the seventh hollow L7 are provided to facilitate the conduction of the transistor between the pixel electrode 4 above the first conductive layer 7 and the first conductive layer 7 below the transistor.

[0353] In the embodiment of the present disclosure, the first conductive layer 7 can further include an eighth hollow L8, which can avoid the overlapping capacitance between the gate line 2 and the first conductive layer 7, and affect the pixel charging rate; if the first conductive layer 7 is entirely provided with the eighth hollow L8 in the area where the gate line 2 is located, light leakage will occur. In the embodiment of the present disclosure, the eighth hollow L8 is only provided in the partial area where the first conductive layer 7 overlaps with the gate line 2, which can reduce the light leakage and the overlapping capacitance between the gate line 2 and the first conductive layer 7, and ensure the charging rate.

[0354] In a possible implementation, the length h2 of the eighth hollow L8 in the first direction X can be one fifth to four fifths of the length h1 of the second hollow L2 in the first direction; in a possible implementation, the length h2 of the eighth hollow L8 in the first direction X can be one fourth to three fourths of the length h1 of the second hollow L2 in the first direction; in a possible implementation, the length h2 of the eighth hollow L8 in the first direction X can be one half of the length h1 of the second hollow L2 in the first direction.

[0355] In a possible implementation, the length h4 of the eighth hollow L8 in the second direction Y can be one fifth to four fifths of the distance h3 between the second hollow L2 and the third hollow L3; in a possible implementation, the length h4 of the eighth hollow L8 in the second direction Y can be one fourth to three fourths of the distance h3 between the second hollow L2 and the third hollow L3; in a possible implementation, the length h4 of the eighth hollow L8 in the second direction Y can be one half of the distance h3 between the second hollow L2 and the third hollow L3.

[0356] In a possible implementation, the outer edge extension line of the eighth hollow L8 extending along the second direction Y and away from one side of the sixth hollow L6 coincides with the outer edge extension line of the second hollow L2 extending along the second direction Y.

[0357] In a possible implementation, in combination with Figures 6A-6J and Figure 10 as shown, the data line 3 can be located on the side of the gate line 2 away from the substrate 1, the first conductive layer 7 can be located on the side of the data line 3 away from the gate line 2, the pixel electrode 4 can be located on the side of the first conductive layer 7 away from the data line 3, and a gate insulating layer can be further provided between the layer where the gate line 2 is located and the layer where the data line 3 is located, a source layer (the source layer can include the active pattern 6, and the source layer material can be amorphous silicon, low-temperature polycrystalline silicon, metal oxide, etc., which is not limited herein) can be further provided between the gate insulating layer and the data line 3, a first insulating layer 91 can be further provided between the data line 3 and the first conductive layer 7, and a second insulating layer 92 can be provided between the first conductive layer 7 and the pixel electrode 4.

[0358] In a possible implementation, in combination with Figure 1H , Figure 2H 、 Figure 3H 、 Figure 4H 、 Figure 5H and Figure 6K , the present embodiment performs optical simulation on different array substrate structures, and by comparing the central horizontal dark lines of the sub-pixels, it can be determined that for the array substrate structure without the first conductive layer 7, Figure 1H 、 Figure 2H 、 Figure 3H 、 Figure 4H 、 FIG. 5H corresponding array substrate structure, wherein FIG. 2A the structure corresponds to the highest transmittance.

[0359] Based on the same inventive concept, the present embodiment also provides a display panel, which comprises: the array substrate provided by the present embodiment, and further comprises an opposite substrate arranged opposite to the array substrate, and the opposite substrate is provided with a common electrode layer.

[0360] In a possible implementation, as shown in FIG. 10 and FIG. 8 , the display panel further comprises a liquid crystal layer 10 located between the array substrate and the opposite substrate; the liquid crystal layer 10 comprises: a plurality of liquid crystal parts PJ, at least one liquid crystal part PJ in the plurality of liquid crystal parts PJ comprises: a first sub-liquid crystal part PJ1, a second sub-liquid crystal part PJ2, a third sub-liquid crystal part PJ3, and a fourth sub-liquid crystal part PJ4; the orthographic projection of the liquid crystal part PJ on the substrate 1 overlaps the orthographic projection of the pixel electrode 4 on the substrate 1; the orthographic projection of the first sub-liquid crystal part PJ1 on the substrate 1 overlaps the orthographic projection of the first sub-electrode part P1 on the substrate 1; the orthographic projection of the second sub-liquid crystal part PJ2 on the substrate 1 overlaps the orthographic projection of the second sub-electrode part P2 on the substrate 1; the orthographic projection of the third sub-liquid crystal part PJ3 on the substrate 1 overlaps the orthographic projection of the third sub-electrode part P3 on the substrate 1; and the orthographic projection of the fourth sub-liquid crystal part PJ4 on the substrate 1 overlaps the orthographic projection of the fourth sub-electrode part P4 on the substrate 1.

[0361] The initial alignment direction of the first sub-liquid crystal part PJ1, the initial alignment direction of the second sub-liquid crystal part PJ2, the initial alignment direction of the third sub-liquid crystal part PJ3, and the initial alignment direction of the fourth sub-liquid crystal part PJ4 are different from each other.

[0362] It can be understood that the initial alignment direction of the liquid crystal can be the orientation direction of the liquid crystal when no voltage is loaded.

[0363] In a possible implementation, in combination with FIG. 8As shown, the angle between the initial alignment direction of the first sub-liquid crystal part PJ1 and the first direction X ranges from 210° to 240°; the angle between the initial alignment direction of the second sub-liquid crystal part PJ2 and the first direction X ranges from 120° to 150°; the angle between the initial alignment direction of the third sub-liquid crystal part PJ3 and the first direction X ranges from 300° to 330°; and the angle between the initial alignment direction of the fourth sub-liquid crystal part PJ4 and the first direction X ranges from 30° to 60°.

[0364] In a possible implementation, the display panel further comprises a first sub-liquid crystal part PJ1, a second sub-liquid crystal part PJ2, a third sub-liquid crystal part PJ3, and a fourth sub-liquid crystal part PJ4. FIG. 8 As shown, the alignment direction of at least part of the liquid crystal at the junction of the first sub-liquid crystal part PJ1 and the second sub-liquid crystal part PJ2 is opposite to the alignment direction of at least part of the liquid crystal at the junction of the third sub-liquid crystal part PJ3 and the fourth sub-liquid crystal part PJ4.

[0365] In a possible implementation, the display panel further comprises a first sub-liquid crystal part PJ1, a second sub-liquid crystal part PJ2, a third sub-liquid crystal part PJ3, and a fourth sub-liquid crystal part PJ4. FIG. 8 As shown, the alignment direction of the liquid crystal at the junction of the first sub-liquid crystal part PJ1 and the second sub-liquid crystal part PJ2 is parallel to the first direction X and to the left, and the alignment direction of the liquid crystal at the junction of the third sub-liquid crystal part PJ3 and the fourth sub-liquid crystal part PJ4 is parallel to the first direction X and to the right. Compared with the conventional SUVA structure shown in FIG. 1, the liquid crystal angles can compensate for each other in the left and right viewing angles. FIG. 7 As shown, the liquid crystal in the lateral direction has both the left direction and the right direction, so that the lateral liquid crystal in the left and right directions can compensate for each other in the viewing angle, thereby improving the left and right viewing angle deviation. FIG. 8 As shown, the liquid crystal in the lateral direction has both the left direction and the right direction, so that the lateral liquid crystal in the left and right directions can compensate for each other in the viewing angle, thereby improving the left and right viewing angle deviation.

[0366] In a possible implementation, the display panel further comprises a first sub-liquid crystal part PJ1, a second sub-liquid crystal part PJ2, a third sub-liquid crystal part PJ3, and a fourth sub-liquid crystal part PJ4. FIGS. 6A-6J and FIG. 10 As shown, the display panel can further be provided with a black matrix 8, and the black matrix 8 can cover the orthogonal projection of the gate line 2 on the substrate 1 and the orthogonal projection of the data line 3 on the substrate 1. Specifically, the opposite substrate can include an opposite substrate 90, and the black matrix 8 can be located between the opposite substrate 90 and the common electrode layer (not shown in the figure). FIG. 10

[0367] In a possible implementation, the display panel further comprises a first sub-liquid crystal part PJ1, a second sub-liquid crystal part PJ2, a third sub-liquid crystal part PJ3, and a fourth sub-liquid crystal part PJ4. FIG. 10 ​As shown, the first conductive layer 7 is located on the side of the pixel electrode 4 away from the counter substrate. In this common embodiment, the first conductive layer 7 is located on the side of the pixel electrode 4 away from the counter substrate, which can isolate (or shield) the first overlap capacitance between the pixel electrode 4 and the gate line 2 and the second overlap capacitance between the pixel electrode 4 and the data line 3, greatly reducing the risk of crosstalk. At the same time, due to the presence of the first conductive layer 7, the distance between the pixel electrodes 4 can be reduced, so that the pixel electrode 4 overlaps with the gate line 2 and the pixel electrode 4 overlaps with the data line 3, reducing the risk of liquid crystal light leakage, thereby reducing the width of the black matrix, increasing the pixel aperture ratio, and improving the pixel transmittance.

[0368] Based on the same inventive concept, the embodiments of the present disclosure also provide a display device, which comprises the display panel provided by the embodiments of the present disclosure.

[0369] In specific implementation, in the embodiments of the present disclosure, the display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. Other essential components of the display device are understood by those skilled in the art, and are not described here in detail, nor should they be regarded as a limitation on the present disclosure.

[0370] Although the preferred embodiments of the present application have been described, those skilled in the art can make further changes and modifications to these embodiments once they understand the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0371] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, include: Substrate; Multiple gate lines are located on one side of the substrate and extend along a first direction; Multiple data lines extend along the second direction; A plurality of pixel electrodes, the pixel electrodes including: a first pixel electrode located on one side of the gate line, and a second pixel electrode located on the other side of the gate line; the first pixel electrode includes: a first sub-pixel electrode and a second sub-pixel electrode distributed along the first direction; the second pixel electrode includes: a third sub-pixel electrode and a fourth sub-pixel electrode distributed along the first direction; One of the first sub-pixel electrode and the second sub-pixel electrode is electrically connected to one of the third sub-pixel electrode and the fourth sub-pixel electrode; the array substrate further includes: a plurality of transistors; the plurality of transistors includes: a first transistor, a second transistor, and a third transistor; The pixel electrode further includes: a connection portion connecting the first sub-pixel electrode and the fourth sub-pixel electrode, and a first overlapping portion connected to the connection portion; the connection portion includes: a third connection portion, a fourth connection portion, and a fifth connection portion extending along the first direction; One end of the third connecting portion is connected to the first sub-pixel electrode, one end of the fourth connecting portion is connected to the fourth sub-pixel electrode, one end of the fifth connecting portion is connected to the other end of the third connecting portion, and the other end of the fifth connecting portion is connected to the other end of the fourth connecting portion; the first overlapping portion is electrically connected to the third connecting portion and is located away from the connected first sub-pixel electrode. The second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode through the first overlapping portion; The pixel electrode further includes: a first transition portion extending along the first direction, a second transition portion extending along the second direction, and a second overlapping portion; One end of the first adapter is electrically connected to one end of the second sub-pixel electrode facing the fourth sub-pixel electrode, and the other end of the first adapter is electrically connected to one end of the second adapter; the other end of the second adapter is electrically connected to the second overlapping portion. The second electrode of the second transistor is electrically connected to the second sub-pixel electrode through the second lap joint; the fifth connection portion extends along the second direction; the second transition portion is parallel to the extending direction of the fifth connection portion; The third transistor and the first transistor are located on different sides of the fifth connection portion in the orthographic projection of the substrate, respectively, in at least a portion of the orthographic projection of the substrate.

2. The array substrate as claimed in claim 1, wherein, The array substrate further includes: a plurality of transistors electrically connected to the same pixel electrode, all of which are electrically connected to the same data line and the same gate line; The second sub-pixel electrode is located on the side of the first sub-pixel electrode away from the electrically connected data line, and the fourth sub-pixel electrode is located on the side of the third sub-pixel electrode away from the electrically connected data line; the first sub-pixel electrode and the fourth sub-pixel electrode are electrically connected.

3. The array substrate as described in claim 2, wherein, The array substrate further includes: a first signal line extending along the second direction; The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode. The control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second sub-pixel electrode and the third sub-pixel electrode. The control electrode of the third transistor is electrically connected to the gate line, the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is multiplexed with the first signal line.

4. The array substrate as claimed in claim 3, wherein, The pixel electrode further includes: a first sub-pixel electrode protrusion connected to the side of the first sub-pixel electrode facing the third sub-pixel electrode; the second electrode of the first transistor is electrically connected to the first sub-pixel electrode through the first sub-pixel electrode protrusion.

5. The array substrate as claimed in claim 4, wherein, The pixel electrode further includes: a connection portion connecting the first sub-pixel electrode and the fourth sub-pixel electrode; the connection portion includes: a first connection portion extending along the second direction, and a second connection portion extending along a third direction; the third direction intersects the first direction and the second direction. One end of the first connecting portion is electrically connected to the end of the first sub-pixel electrode facing the third sub-pixel electrode, and the other end is electrically connected to the second connecting portion. The other end of the second connecting portion is electrically connected to the end of the fourth sub-pixel electrode facing the second sub-pixel electrode.

6. The array substrate as claimed in claim 5, wherein, The pixel electrode further includes: a third sub-pixel electrode protrusion connected to the side of the third sub-pixel electrode facing the first sub-pixel electrode; The second electrode of the second transistor is electrically connected to the third sub-pixel electrode through the protrusion of the third sub-pixel electrode.

7. The array substrate as claimed in claim 6, wherein, The pixel electrode further includes: a second sub-pixel electrode extension extending along the second direction, and a second sub-pixel electrode protrusion; one end of the second sub-pixel electrode extension is electrically connected to one end of the second sub-pixel electrode facing the fourth sub-pixel electrode, and the other end is electrically connected to the second sub-pixel electrode protrusion. The second electrode of the second transistor is electrically connected to the second sub-pixel electrode through the second sub-pixel electrode protrusion.

8. The array substrate as claimed in claim 7, wherein, The extension direction of the second sub-pixel electrode extension is parallel to the extension direction of the first connection portion.

9. The array substrate as claimed in claim 7, wherein, The second sub-pixel electrode protrusion has an outer edge of the second sub-pixel electrode protrusion that extends away from the second sub-pixel electrode and along the first direction; the third sub-pixel electrode protrusion has an outer edge of the third sub-pixel electrode protrusion that extends away from the third sub-pixel electrode and along the first direction. The extension line of the outer edge of the second sub-pixel electrode protrusion coincides with the extension line of the outer edge of the third sub-pixel electrode protrusion; or, the extension line of the outer edge of the second sub-pixel electrode protrusion at least partially overlaps with the third sub-pixel electrode protrusion; or, the extension line of the outer edge of the third sub-pixel electrode protrusion at least partially overlaps with the second sub-pixel electrode protrusion.

10. The array substrate as claimed in claim 7, wherein, The line connecting the center of the third sub-pixel electrode protrusion and the center of the first sub-pixel electrode protrusion is parallel to the second direction.

11. The array substrate as claimed in claim 4, wherein, The second electrode of the first transistor includes: a first portion of the first transistor extending along the first direction; The orthographic projection of the first part of the first transistor onto the substrate overlaps with the orthographic projection of the first sub-pixel electrode protrusion onto the substrate.

12. The array substrate as claimed in claim 8, wherein, The second electrode of the second transistor includes: a first portion of the second transistor extending along the first direction, and a second portion of the second transistor extending along the second direction and electrically connected to one end of the first portion of the second transistor; The orthographic projection of the first part of the second transistor onto the substrate overlaps with the orthographic projection of the third sub-pixel electrode protrusion onto the substrate; the orthographic projection of the second part of the second transistor onto the substrate overlaps with the orthographic projection of the second sub-pixel electrode protrusion onto the substrate.

13. The array substrate as claimed in claim 12, wherein, At least a portion of the second portion of the second transistor projected onto the substrate overlaps with at least a portion of the second sub-pixel electrode extension projected onto the substrate.

14. The array substrate as claimed in claim 13, wherein, The first signal line has a recess; at least a portion of the second part of the second transistor in the orthographic projection of the substrate is located in the region surrounded by the orthographic projection of the recess in the substrate.

15. The array substrate as claimed in claim 14, wherein, The first signal line includes: a first signal section, a second signal section, and a third signal section distributed sequentially along the second direction; a fourth signal section extending along the first direction and connecting the second signal section and the first signal section; and a fifth signal section extending along the first direction and connecting the second signal section and the third signal section. The extension line of the first signal portion coincides with the extension line of the third signal portion; the extension line of the second signal portion does not coincide with the extension line of the first signal portion; the second signal portion, the fourth signal portion, and the fifth signal portion constitute the recessed portion, and the fourth signal portion and / or the fifth signal portion at least partially overlap with the pixel electrode.

16. The array substrate as claimed in claim 2, wherein, The array substrate further includes: a first common trace located on one side of the gate line and extending along the first direction; the plurality of transistors includes: a first transistor, a second transistor, and a third transistor electrically connected to the data line; The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode. The control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second sub-pixel electrode and the third sub-pixel electrode. The control electrode of the third transistor is electrically connected to the gate line, the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is electrically connected to the first common trace.

17. The array substrate as claimed in claim 1, wherein, The array substrate further includes: a first common trace located on one side of the gate line and extending along the first direction; the first sub-pixel electrode is electrically connected to the fourth sub-pixel electrode; the array substrate further includes: a third common trace located on one side of the gate line and extending along the first direction, and an auxiliary gate line located between the gate line and the third common trace and extending along the first direction; the plurality of transistors includes: a first transistor, a second transistor, and a third transistor; The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode. The control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second sub-pixel electrode and the third sub-pixel electrode. The control electrode of the third transistor is electrically connected to the auxiliary gate line. The first electrode of the third transistor is multiplexed with the second electrode of the first transistor. The orthographic projection of the second electrode of the third transistor on the substrate overlaps with the orthographic projection of the third common trace on the substrate.

18. The array substrate as claimed in claim 17, wherein, The control electrode of the third transistor is electrically connected to the auxiliary gate line; at least a portion of the third transistor and at least a portion of the first transistor in the orthographic projection of the substrate are located on the same side of the fifth connection portion in the orthographic projection of the substrate.

19. The array substrate as claimed in claim 18, wherein, The fifth connecting part includes: a first sub-connecting part, a second sub-connecting part, and a third sub-connecting part; The first sub-connecting part extends along a third direction, with one end electrically connected to the other end of the third connecting part and the other end electrically connected to the second sub-connecting part; the third direction intersects the first direction and the second direction. The second sub-connecting portion extends along the second direction, and the other end of the second sub-connecting portion is electrically connected to one end of the third sub-connecting portion; The third sub-connecting portion extends along the third direction, and the other end of the third sub-connecting portion is electrically connected to the other end of the fourth connecting portion.

20. The array substrate as claimed in claim 18, wherein, The pixel electrode further includes: a first transition portion extending in a fourth direction, a second transition portion extending in a second direction, and a second overlapping portion; One end of the first adapter is electrically connected to one end of the second sub-pixel electrode facing the fourth sub-pixel electrode, and the other end of the first adapter is electrically connected to one end of the second adapter; the other end of the second adapter is electrically connected to the second overlapping portion. The second electrode of the second transistor is electrically connected to the second sub-pixel electrode through the second overlap portion.

21. The array substrate as claimed in claim 17, wherein, The pixel electrode further includes: a third transition portion extending along the first direction, and a third overlapping portion; One end of the third adapter is electrically connected to the end of the third sub-pixel electrode facing the first sub-pixel electrode, and the other end of the third adapter is electrically connected to the third overlap portion. The second electrode of the second transistor is electrically connected to the third sub-pixel electrode through the third overlap portion.

22. The array substrate as claimed in claim 21, wherein, The third connecting portion has a first gap with the first pixel electrode; the fourth connecting portion has a second gap with the second pixel electrode; There is a third gap between the first adapter and the first pixel electrode, and there is a fourth gap between the third adapter and the second pixel electrode.

23. The array substrate as claimed in claim 21, wherein, The array substrate further includes: a fourth overlap portion; the second electrode of the third transistor is electrically connected to the first common trace through the fourth overlap portion.

24. The array substrate as claimed in claim 23, wherein, The fourth overlapping portion has a fourth overlapping portion outer edge along the first direction, and the second overlapping portion has a second overlapping portion outer edge extending along the first direction; the first overlapping portion has a first overlapping portion outer edge extending along the second direction, and the third overlapping portion has a third overlapping portion outer edge extending along the second direction. The extension line of the outer edge of the fourth overlapping portion coincides with the extension line of the outer edge of the second overlapping portion; the extension line of the outer edge of the first overlapping portion coincides with the extension line of the outer edge of the third overlapping portion.

25. The array substrate as claimed in claim 21, wherein, The second electrode of the first transistor includes: a first portion of the first transistor extending along the first direction; The first portion of the first transistor has an overlapping region with the first overlapping portion in the substrate.

26. The array substrate as claimed in claim 21, wherein, The second electrode of the second transistor includes: a first portion of the second transistor extending along the first direction, and a second portion of the second transistor extending along the second direction and electrically connected to one end of the first portion of the second transistor; The orthographic projection of the first part of the second transistor on the substrate overlaps with the orthographic projection of the third overlapping part on the substrate; the orthographic projection of the second part of the second transistor on the substrate overlaps with the orthographic projection of the second overlapping part on the substrate.

27. The array substrate as claimed in claim 2, wherein, The array substrate further includes: a first common trace located on one side of the gate line and extending along the first direction; the first common trace is disconnected at the position where it intersects with the data line.

28. The array substrate as claimed in claim 16, wherein, The array substrate further includes: a second common trace group electrically connected to the first common trace and extending away from the gate trace, the second common trace group including: two second common traces; The data line, when projected onto the substrate, overlaps with the gap between two second common traces in the same second common trace group when projected onto the substrate.

29. The array substrate as claimed in claim 28, wherein, The array substrate further includes: a third common trace located on the other side of the gate line and extending along the first direction, and a fourth common trace group connected to the third common trace and extending away from the gate line. The third common trace is disconnected at the location where it intersects with the data line; the fourth common trace group includes: two fourth common traces; the data line, in its orthographic projection on the substrate, has an overlapping area with the gap between the two fourth common traces in the same fourth common trace group in its orthographic projection on the substrate.

30. The array substrate as claimed in claim 28, wherein, The array substrate further includes: a fifth common trace extending along the first direction and electrically connected to the second common trace, wherein the orthographic projection of the fifth common trace on the substrate passes through the central region of the orthographic projection of the second pixel electrode on the substrate.

31. The array substrate as claimed in claim 29, wherein, The array substrate further includes: a sixth common trace extending along the first direction and electrically connected to the fourth common trace, wherein the orthographic projection of the sixth common trace on the substrate passes through the central region of the orthographic projection of the first pixel electrode on the substrate.

32. The array substrate as claimed in claim 1, wherein, The first sub-pixel electrode and the second sub-pixel electrode each include: a first sub-electrode portion and a second sub-electrode portion distributed along the second direction; the third sub-pixel electrode and the fourth sub-pixel electrode each include: a third sub-electrode portion and a fourth sub-electrode portion distributed along the second direction. The first sub-electrode portion, the second sub-electrode portion, the third sub-electrode portion, and the fourth sub-electrode portion each have a plurality of slits; and the extension direction of the slits in the first sub-electrode portion is the same as the extension direction of the slits in the fourth sub-electrode portion; the extension direction of the slits in the second sub-electrode portion is the same as the extension direction of the slits in the third sub-electrode portion.

33. The array substrate as claimed in claim 32, wherein, The slit has a length of 2 μm to 4 μm perpendicular to the extension direction.

34. The array substrate as claimed in claim 32, wherein, The first sub-pixel electrode, the second sub-pixel electrode, the third sub-pixel electrode, and the fourth sub-pixel electrode all have rectangular shapes in their orthogonal projection onto the substrate.

35. The array substrate as claimed in claim 32, wherein, The first sub-electrode portion, the second sub-electrode portion, the third sub-electrode portion, and the fourth sub-electrode portion all have trapezoidal shapes in their orthogonal projection onto the substrate; In the first sub-pixel electrode and the fourth sub-pixel electrode, the trapezoidal first sub-pixel portion and the trapezoidal second sub-pixel portion are arranged with their top edges facing each other; in the second sub-pixel electrode and the third sub-pixel electrode, the trapezoidal first sub-pixel portion and the trapezoidal second sub-pixel portion are arranged with their bottom edges facing each other.

36. The array substrate as claimed in claim 32, wherein, The first sub-electrode portion, the second sub-electrode portion, the third sub-electrode portion, and the fourth sub-electrode portion all have trapezoidal shapes in their orthogonal projection onto the substrate; In the first sub-pixel electrode and the fourth sub-pixel electrode, the trapezoidal first sub-pixel portion and the trapezoidal second sub-pixel portion are arranged with their bottom edges facing each other; in the second sub-pixel electrode and the third sub-pixel electrode, the trapezoidal first sub-pixel portion and the trapezoidal second sub-pixel portion are arranged with their top edges facing each other.

37. The array substrate as claimed in claim 32, wherein, The first sub-pixel electrode includes: a first main portion, a second main portion, and a first side portion extending along the second direction and connected thereto; a plurality of first branches extending from the first main portion and the first side portion along the fourth direction; and a plurality of second branches extending from the second main portion and the first side portion along the fifth direction. The second sub-pixel electrode includes: a third main portion, a fourth main portion, and a fifth main portion extending along the second direction and connected thereto; a fifth main portion connected to one end of the third main portion and extending along the first direction; a sixth main portion connected to one end of the fourth main portion and extending along the first direction; a plurality of third branches extending from the third main portion and the fifth main portion along the fourth direction; and a plurality of fourth branches extending from the fourth main portion and the sixth main portion along the fifth direction. The plurality of first branches and the plurality of third branches are interdigitated, and the plurality of second branches and the plurality of fourth branches are interdigitated. The third sub-pixel electrode includes: a seventh main portion and an eighth main portion extending and connected along the second direction; a ninth main portion connected to one end of the seventh main portion and extending along the first direction; a tenth main portion connected to one end of the eighth main portion and extending along the first direction; a plurality of fifth branches extending from the seventh main portion and the ninth main portion along the fourth direction; and a plurality of sixth branches extending from the eighth main portion and the tenth main portion along the fifth direction. The fourth sub-pixel electrode includes: an eleventh main portion and a twelfth main portion extending and connected along the second direction; a second side portion extending along the first direction; a plurality of seventh branches extending from the eleventh main portion and the second side portion along the fourth direction; and a plurality of eighth branches extending from the twelfth main portion and the second side portion along the fifth direction. The plurality of fifth branches and the plurality of seventh branches are interdigitated, and the plurality of sixth branches and the plurality of eighth branches are interdigitated.

38. The array substrate as claimed in claim 1, wherein, The array substrate further includes: a first conductive layer located on the side of the pixel electrode facing the substrate; the first conductive layer has a first cutout, a second cutout, a third cutout, and a fourth cutout; At least a portion of the orthographic projection of the first cutout onto the substrate overlaps with at least a portion of the orthographic projection of the first sub-pixel electrode onto the substrate; at least a portion of the orthographic projection of the second cutout onto the substrate overlaps with at least a portion of the orthographic projection of the second sub-pixel electrode onto the substrate; at least a portion of the orthographic projection of the third cutout onto the substrate overlaps with at least a portion of the orthographic projection of the third sub-pixel electrode onto the substrate; and at least a portion of the orthographic projection of the fourth cutout onto the substrate overlaps with at least a portion of the orthographic projection of the fourth sub-pixel electrode onto the substrate.

39. A display panel, wherein, include: The array substrate according to any one of claims 1-38 further includes a counter substrate disposed opposite to the array substrate, the counter substrate being provided with a common electrode layer.

40. The display panel as claimed in claim 39, wherein, The display panel further includes a liquid crystal layer located between the array substrate and the opposing substrate; the first sub-pixel electrode and the second sub-pixel electrode each include: a first sub-electrode portion and a second sub-electrode portion distributed along the second direction; the third sub-pixel electrode and the fourth sub-pixel electrode each include: a third sub-electrode portion and a fourth sub-electrode portion distributed along the second direction; The liquid crystal layer includes a plurality of liquid crystal units, at least one of which includes a first sub-liquid crystal unit, a second sub-liquid crystal unit, a third sub-liquid crystal unit, and a fourth sub-liquid crystal unit; the orthographic projection of the liquid crystal unit onto the substrate overlaps with the orthographic projection of the pixel electrode onto the substrate; the orthographic projection of the first sub-liquid crystal unit onto the substrate overlaps with the orthographic projection of the first sub-electrode unit onto the substrate; the orthographic projection of the second sub-liquid crystal unit onto the substrate overlaps with the orthographic projection of the second sub-electrode unit onto the substrate; the orthographic projection of the third sub-liquid crystal unit onto the substrate overlaps with the orthographic projection of the third sub-electrode unit onto the substrate; the orthographic projection of the fourth sub-liquid crystal unit onto the substrate overlaps with the orthographic projection of the fourth sub-electrode unit onto the substrate. The initial alignment directions of the first sub-liquid crystal unit, the second sub-liquid crystal unit, the third sub-liquid crystal unit, and the fourth sub-liquid crystal unit are all different.

41. The display panel as claimed in claim 40, wherein, The angle between the initial alignment direction of the first sub-liquid crystal portion and the first direction is in the range of 210°. o ~240 o The initial alignment direction of the second sub-liquid crystal portion forms an angle of 120° with the first direction. o ~150 o The initial alignment direction of the third sub-liquid crystal portion forms an angle of 30° with the first direction. o ~330 o The initial alignment direction of the fourth sub-liquid crystal portion forms an angle of 30° with the first direction. o ~60 o .

42. The display panel as claimed in claim 40 or 41, wherein, The alignment direction of at least a portion of the liquid crystal at the junction of the first sub-liquid crystal section and the second sub-liquid crystal section is opposite to the alignment direction of at least a portion of the liquid crystal at the junction of the third sub-liquid crystal section and the fourth sub-liquid crystal section.

43. A display device, wherein, Includes the display panel as described in any one of claims 39-42.

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