Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer; and a circuit pattern layer disposed between the first insulating layer and the second insulating layer, in which the second insulating layer has a cavity passing through the upper surface and the lower surface, and the circuit pattern layer includes an electrode pattern extending from an inner side of the cavity to an outer side of the cavity.

Description

Technical Field

[0001] Embodiments relate to a circuit board and a semiconductor package including the circuit board. Background Art

[0002] As the performance of electrical / electronic products advances, technologies for arranging a greater number of packages on a circuit board of a limited size are being proposed and studied.

[0003] A typical semiconductor package has a structure in which a plurality of chips are arranged. In addition, recently, the specifications of products to which semiconductor packages are applied are becoming higher and higher, and a plurality of chips such as HBM (High Bandwidth Memory) are being adopted, and as a result, the size of semiconductor packages is increasing. Therefore, the semiconductor package includes an interposer for connecting the plurality of chips.

[0004] In addition, semiconductor packages used in products that provide the Internet of Things (IoT), autonomous vehicles, and high-performance servers require high performance and high reliability in line with the trend toward higher integration.

[0005] In addition, the semiconductor package has a vertical connection structure between a plurality of circuit boards, interposers, and semiconductor devices, and therefore, the thickness of the semiconductor package in the vertical direction may increase depending on the thickness and number of the circuit boards, interposers, and semiconductor devices.

[0006] Therefore, the thickness of the semiconductor package in the vertical direction is reduced by using a circuit board with a cavity. The cavity can be formed by processing the circuit board with a laser. To this end, a dummy pattern is set in the circuit board. In addition, the dummy pattern is used as a blocking member for performing laser processing to form the cavity.

[0007] According to the conventional technology, a process of forming a dummy pattern and a process of removing the dummy pattern must be performed, and there is a problem that a manufacturing process becomes complicated.

[0008] In addition, the circuit board of the conventional technology includes a pad exposed through a cavity. At this time, only the pad exists in the area exposed through the cavity. This is because, when an electrode pattern such as a trace exists in the area exposed through the cavity, a circuit short circuit problem occurs in which the traces are electrically connected to each other through a dummy pattern. Therefore, the circuit board of the conventional technology has a problem of reduced circuit integration.

[0009] (Patent Document 1) KR 10-2012-0045639 A Summary of the invention

[0010] Technical issues

[0011] Embodiments provide a circuit board having a novel structure and a semiconductor package including the same.

[0012] In addition, the embodiment provides a circuit board that can be thinned and a semiconductor package including the same.

[0013] In addition, the embodiment provides a circuit board capable of minimizing the length of a signal line connected to a connection member and a semiconductor package including the same.

[0014] In addition, the embodiment provides a circuit board capable of arranging an electrode pattern in a cavity region while including a thermosetting resin, and a semiconductor package including the same.

[0015] In addition, embodiments provide a circuit board having improved circuit integration and a semiconductor package including the same.

[0016] In addition, embodiments provide a circuit board having improved adhesion with a molding member and a semiconductor package including the same.

[0017] Technical problems to be solved by the proposed embodiments are not limited to the above-mentioned technical problems, and other technical problems not mentioned may be clearly understood by those skilled in the art to which the proposed embodiments belong from the following description.

[0018] Technical Solution

[0019] According to an embodiment, a circuit board includes a first insulating layer; a second insulating layer, which is arranged on the first insulating layer; and a circuit pattern layer, which is arranged between the first insulating layer and the second insulating layer, wherein the second insulating layer has a cavity passing through the upper surface and the lower surface, and wherein the circuit pattern layer includes an electrode pattern extending from the inside of the cavity to the outside of the cavity.

[0020] In addition, the circuit pattern layer further includes: a first pad, which is disposed on the inner side of the cavity and overlaps with the cavity in a vertical direction; and a second pad, which is disposed on the outer side of the cavity and does not overlap with the cavity vertically.

[0021] In addition, the second insulating layer has a concave portion that is concave in a direction from a lower end of a sidewall of the cavity toward an outside of the cavity.

[0022] In addition, the concave portion has a first portion that does not overlap with the electrode pattern in the vertical direction, and a second portion that overlaps with the electrode pattern in the vertical direction.

[0023] In addition, the circuit pattern layer is disposed to protrude on the first insulating layer, and the first portion of the concave portion is disposed along an edge of a lower end of a side wall of the cavity.

[0024] In addition, the first portion and the second portion of the concave portion have a step.

[0025] In addition, the first pad, the second pad and the electrode pattern each include: a first metal layer, which is disposed on the first insulating layer; and a second metal layer, which is disposed on the first metal layer, and wherein the length of the first portion of the concave portion in the vertical direction corresponds to the thickness of the first metal layer.

[0026] In addition, a horizontal distance from a lower end of a side wall of the cavity to an innermost end of the first portion of the concave portion satisfies a range of 5 μm to 17 μm.

[0027] In addition, a horizontal length of the first portion of the concave portion is different from a horizontal length of the second portion of the concave portion.

[0028] In addition, the thickness of the first pad is different from the thickness of the second pad.

[0029] In addition, the length of the first portion of the concave portion in the vertical direction satisfies the range of 1.0 μm to 4.0 μm.

[0030] In addition, a horizontal length of the first portion of the concave portion is smaller than a horizontal length of the second portion of the concave portion.

[0031] In addition, the thickness of the first pad is smaller than the thickness of the second pad.

[0032] In addition, the electrode pattern includes a region overlapping a sidewall of the cavity in a vertical direction and having a thickness varying in a horizontal direction.

[0033] In addition, the first pad, the second pad, and the electrode pattern are embedded in an upper surface of the first insulating layer, and an upper surface of a first region of the first insulating layer is positioned lower than an upper surface of a second region of the first insulating layer.

[0034] In addition, the concave portion is provided concavely from the upper surface of the first region of the first insulating layer toward the inner side of the first insulating layer.

[0035] In addition, at least one of the first pad, the second pad, and the electrode pattern has at least a different layer structure from each other.

[0036] In addition, the first circuit pattern layer includes a first metal layer and a second metal layer, the first pad of the first circuit pattern layer includes the second metal layer but not the first metal layer, the second pad of the first circuit pattern layer includes both the first metal layer and the second metal layer, and the electrode pattern includes a first portion including only the second metal layer and a second portion including both the first metal layer and the second metal layer.

[0037] In addition, the second insulating layer having the cavity includes a thermosetting resin.

[0038] Beneficial Effects

[0039] The circuit board of the embodiment includes a first insulating layer; a first circuit pattern layer disposed on the first insulating layer; and a second insulating layer disposed on the first insulating layer and the first circuit pattern layer. At this time, the second insulating layer includes a cavity passing through the upper surface and the lower surface. In addition, the first circuit pattern layer may include: a first pad disposed in a first region vertically overlapping the cavity; a second pad disposed in a second region not vertically overlapping the cavity; and an electrode pattern disposed in the first region and the second region and connecting the first pad and the second pad.

[0040] That is, the embodiment arranges an electrode pattern that directly connects the first pad and the second pad on the first insulating layer. Therefore, the embodiment can reduce the signal transmission distance between the first pad and the second pad. In addition, the embodiment can minimize the signal transmission loss by reducing the signal transmission distance. Therefore, the embodiment can improve the electrical characteristics of the circuit board and the semiconductor package including the circuit board.

[0041] In addition, embodiments may improve circuit integration by arranging electrode patterns in a region corresponding to a cavity.

[0042] In addition, the second insulating layer including the cavity includes a thermosetting resin. In addition, the embodiment can arrange the electrode pattern while the second insulating layer includes a thermosetting resin. By forming the insulating layer using a thermosetting resin, the embodiment can improve the adhesion between the plurality of insulating layers. Therefore, the embodiment can improve the physical properties of the circuit board and the semiconductor package including the circuit board.

[0043] In addition, a concave portion may be provided at the lower end of the side wall of the cavity along the circumferential direction of the lower surface of the cavity. The concave portion may have a closed loop shape along the circumferential direction of the lower surface of the cavity. At this time, the concave portion may include a portion with a step in one embodiment, and may not have a step in another embodiment.

[0044] Therefore, the embodiment arranges the connection member and the molding member for molding the connection member in the cavity. In addition, the molding member can fill the concave portion provided in the cavity. At this time, the embodiment can allow a portion of the entire area of ​​the molding member positioned in the concave portion to be used as an anchor. Therefore, the embodiment can improve the adhesion between the circuit board and the molding member. Therefore, the embodiment can protect the connection member more stably. In addition, the embodiment can further improve the product reliability of the semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1a is a cross-sectional view showing a semiconductor package according to a first embodiment.

[0046] Figure 1b is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0047] Figure 1c is a cross-sectional view showing a semiconductor package according to a third embodiment.

[0048] Figure 1d is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0049] Figure 1e is a cross-sectional view showing a semiconductor package according to a fifth embodiment.

[0050] Figure 1f is a cross-sectional view showing a semiconductor package according to a sixth embodiment.

[0051] Figure 1g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0052] Figure 2 is a cross-sectional view showing a circuit board according to the first embodiment.

[0053] Figure 3 It is shown Figure 2 A plan view of a first insulating layer and a first circuit pattern layer in a circuit board.

[0054] Figure 4 It is shown Figure 3 The circuit board has some of the construction removed from the plan view.

[0055] Figure 5 is along Figure 3 and Figure 4 A cross-sectional view taken along the A-A' direction.

[0056] Figure 6 is corresponding to Figure 5 Optical microscope photo of the actual product.

[0057] Figure 7 is along Figure 3 and Figure 4 Cross-sectional view taken along the B-B' direction.

[0058] Figure 8 is a cross-sectional view showing a circuit board according to a second embodiment.

[0059] Fig. 9 It is shown Figure 8 Magnified view of a portion of the cavity.

[0060] Fig.10 It is shown Figure 8 An enlarged view of another part of the cavity.

[0061] Fig.11 is a diagram showing a package substrate according to an embodiment.

[0062] Figures 12 to 22 The process sequence is shown according to the embodiment. Figure 2 FIG. 1 is a diagram of a method for manufacturing a circuit board. DETAILED DESCRIPTION

[0063] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein the same reference numerals are used to represent the same or similar elements, and redundant descriptions thereof will be omitted. The suffixes "module" and "part" of the components used in the following description are given or mixed only in consideration of ease of preparation of the description, and there is no meaning or function to distinguish one from another. In addition, in the following description of the embodiments of the present invention, when it is determined that the subject matter of the embodiments disclosed herein may be difficult to understand, the detailed description of the related art will be omitted. In addition, the accompanying drawings are included to provide a further understanding of the present invention, and the accompanying drawings are incorporated into and constitute a part of this specification, and it should be understood that the present invention is intended to cover all modifications, equivalents or substitutions that fall within the spirit and scope of the present invention.

[0064] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the components are not limited by these terms. These terms are only used to distinguish one component from another.

[0065] When a component is referred to as being "connected" or "in contact with" another component, it may be directly connected or joined to the other component, but it should be understood that other components may exist between them. When a component is referred to as being "directly connected" or "directly in contact with" another component, it should be understood that other components may not exist between them.

[0066] Unless the context clearly implies otherwise, a singular expression includes a plural expression.

[0067] In the present application, terms such as "including" or "having" are used to specify the presence of the described features, numbers, steps, operations, components, parts or combinations thereof in the specification, however, it should be understood that these terms do not exclude the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0068] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0069] -Electronic devices-

[0070] Before describing the embodiment, an electronic device to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device includes a mainboard (not shown). The mainboard can be physically and / or electrically connected to various components. For example, the mainboard can be connected to the semiconductor package of the embodiment. Various semiconductor devices can be mounted on the semiconductor package.

[0071] Semiconductor devices may include active devices and / or passive devices. Active devices may be semiconductor chips in the form of integrated circuits (ICs) in which hundreds to millions of devices are integrated into one semiconductor device. Semiconductor devices may be logic chips, memory chips, and the like. Logic chips may be central processing units (CPUs), graphics processing units (GPUs), and the like. For example, logic chips may be application processor (AP) chips including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an ASIC (application-specific IC, dedicated IC), and the like, or a chipset including a specific combination of those listed so far.

[0072] The memory chip may be a stacked memory such as HBM. The memory chip may also include a memory chip such as a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), or a flash memory.

[0073] On the other hand, the product group of the semiconductor package to which the implementation scheme is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package) and SIP (System In Package), but is not limited thereto.

[0074] In addition, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, the embodiment is not limited thereto, and may be any other electronic device that processes data in addition to these.

[0075] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package of the embodiment may have various package structures including a circuit board to be described later.

[0076] In addition, the circuit board in one embodiment may be the first circuit board described below.

[0077] In addition, the circuit board in another embodiment may be the second circuit board described below.

[0078] Figure 1a is a cross-sectional view showing a semiconductor package according to a first embodiment, Figure 1b is a cross-sectional view showing a semiconductor package according to a second embodiment, Figure 1c is a cross-sectional view showing a semiconductor package according to a third embodiment, Figure 1d is a cross-sectional view showing a semiconductor package according to a fourth embodiment, Figure 1e is a cross-sectional view showing a semiconductor package according to a fifth embodiment, Figure 1f is a cross-sectional view showing a semiconductor package according to a sixth embodiment, Figure 1g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0079] Reference Figure 1a , the semiconductor package according to the first embodiment includes a first circuit board 1100 , a second circuit board 1200 , and a semiconductor device 1300 .

[0080] The first circuit board 1100 represents a package substrate.

[0081] For example, the first circuit board 1100 may provide a space where at least one external circuit board is coupled. The external circuit board may refer to the second circuit board 1200 coupled to the first circuit board 1100. In addition, the external circuit board may refer to a main board included in the electronic device coupled to the lower portion of the first circuit board 1100.

[0082] In addition, although not shown in the figure, the first circuit board 1100 may provide a space in which at least one semiconductor device is mounted. To this end, the first circuit board 1100 may include a cavity. In addition, at least one semiconductor device may be disposed in the cavity of the first circuit board 1100.

[0083] The first circuit board 1100 includes at least one insulating layer, an electrode disposed on the at least one insulating layer, and a through portion passing through the at least one insulating layer.

[0084] The second circuit board 1200 is disposed on the first circuit board 1100 .

[0085] The second circuit board 1200 may be an interposer. For example, the second circuit board 1200 may provide a space in which at least one semiconductor device is mounted. The second circuit board 1200 may be connected to at least one semiconductor device 1300. For example, the second circuit board 1200 may provide a space in which a first semiconductor device 1310 and a second semiconductor device 1320 are mounted. The second circuit board 1200 may electrically connect the first semiconductor device 1310 and the second semiconductor device 1320 and the first circuit board 1100 while electrically connecting the first semiconductor device 1310 and the second semiconductor device 1320. That is, the second circuit board 1200 may perform a horizontal connection function between a plurality of semiconductor devices, and a vertical connection function between a semiconductor device and a package substrate.

[0086] Figure 1a It is shown that the first semiconductor device 1310 and the second semiconductor device 1320 are disposed on the second circuit board 1200, but is not limited thereto. For example, one semiconductor device may be disposed on the second circuit board 1200, or alternatively, three or more semiconductor devices may be disposed.

[0087] The second circuit board 1200 may be disposed between the at least one semiconductor device 1300 and the first circuit board 1100 .

[0088] In one embodiment, the second circuit board 1200 may be an active interposer used as a semiconductor device. When the second circuit board 1200 is used as a semiconductor device, the package of the embodiment may have a vertical stacking structure on the first circuit board 1100, and may have a plurality of logic chips mounted thereon. In addition, among the logic chips, the first logic chip corresponding to the active interposer may perform the function of the corresponding logic chip while performing the signal transmission function between the second logic chip disposed thereon and the first circuit board 1100.

[0089] According to another embodiment, the second circuit board 1200 may be a passive interposer. For example, the second circuit board 1200 may be used as a signal relay between the semiconductor device 1300 and the first circuit board 1100. That is, due to 5G, the Internet of Things (IOT), improved image quality, and increased communication speed, the number of terminals of the semiconductor device 1300 is gradually increasing. That is, the number of terminals provided in the semiconductor device 1300 increases, thereby reducing the width of the terminal or the interval between the plurality of terminals. In this case, the first circuit board 1100 is connected to the main board of the electronic device. There is a problem that in order to make the electrodes provided on the first circuit board 1100 have a width and interval respectively connected to the semiconductor device 1300 and the main board, the thickness of the first circuit board 1100 increases or the layer structure of the first circuit board 1100 becomes complicated. Therefore, in the first embodiment, the second circuit board 1200 is provided on the first circuit board 1100 and the semiconductor device 1300. In addition, the second circuit board 1200 may include electrodes having a fine width and interval corresponding to the terminals of the semiconductor device 1300.

[0090] The semiconductor device 1300 may be an application processor (AP) chip including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, an encryption processor, a microprocessor and a microcontroller, or an analog-to-digital converter, an ASIC (application-specific IC, dedicated IC), etc., or a chipset including a specific combination of those listed so far. The memory chip may be a stacked memory such as HBM. The memory chip may also include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, etc.

[0091] In addition, the second circuit board 1200 may include at least one cavity. In addition, the semiconductor device 1300 may be disposed in the cavity of the second circuit board 1200 .

[0092] In addition, the semiconductor package of the first embodiment may include a connection member.

[0093] For example, the semiconductor package includes a first connection member 1410 disposed between the first circuit board 1100 and the second circuit board 1200. The first connection member 1410 may electrically connect the second circuit board 1200 to the first circuit board 1100 while combining the second circuit board 1200 and the first circuit board 1100.

[0094] For example, the semiconductor package includes a second connection member 1420 disposed between the second circuit board 1200 and the semiconductor device 1300. The second connection member 1420 may electrically connect the semiconductor device 1300 to the second circuit board 1200 while combining the semiconductor device 1300 and the second circuit board 1200.

[0095] The semiconductor package includes a third connection member 1430 disposed on a lower surface of the first circuit board 1100. The third connection member 1430 may electrically connect the first circuit board 1100 to the main board while combining the first circuit board 1100 and the main board.

[0096] At this time, the first connection member 1410, the second connection member 1420, and the third connection member 1430 can be electrically connected between the plurality of components by using at least one bonding method of wire bonding, solder bonding, and metal-to-metal direct bonding. That is, since the first connection member 1410, the second connection member 1420, and the third connection member 1430 have the function of electrically connecting the plurality of components, when metal-to-metal direct bonding is used, the connection portion of the semiconductor package can be understood as an electrical connection portion, rather than solder or wire.

[0097] The wire bonding method may refer to electrically connecting multiple components using a conductive wire such as gold (Au). In addition, the solder bonding method may electrically connect multiple components using a material containing at least one of Sn, Ag, and Cu. In addition, the metal-to-metal direct bonding method may refer to direct bonding between multiple components by recrystallization through application of heat and pressure between multiple components in the absence of solder, wires, conductive adhesives, etc. In addition, the metal-to-metal direct bonding method may refer to a bonding method through the second connecting member 1420. In this case, the second connecting member 1420 may represent a metal layer formed between multiple components by recrystallization.

[0098] Specifically, the first connection member 1410 , the second connection member 1420 , and the third connection member 1430 may combine the plurality of components with each other by a TC (Thermal Compression) bonding method. TC bonding may refer to a method of directly combining the plurality of components by applying heat and pressure to the first connection member 1410 , the second connection member 1420 , and the third connection member 1430 .

[0099] At this time, at least one of the first circuit board 1100 and the second circuit board 1200 may have a protrusion disposed on the electrode provided with the first connection member 1410, the second connection member 1420, and the third connection member 1430. The protrusion may protrude outward from the first circuit board 1100 or the second circuit board 1200.

[0100] The protrusion may represent a bump. The protrusion may represent a post. The protrusion may refer to a pillar. Preferably, the protrusion may refer to an electrode of the second circuit board 1200 on which the second connection member 1420 for combining with the semiconductor device 1300 is disposed. That is, as the pitch of the terminals of the semiconductor device 1300 becomes finer, a short circuit may occur between the plurality of second connection members 1420 respectively connected to the plurality of terminals of the semiconductor device 1300. Therefore, the embodiment allows the protrusion to be included in the electrode of the second circuit board 1200 on which the second connection member 1420 is disposed so as to reduce the volume of the second connection member 1420. The protrusion can improve the alignment between the electrode of the second substrate 1200 and the terminal of the semiconductor device 1300, and can prevent the diffusion of the second connection member 1420.

[0101] In addition, refer to Figure 1b The semiconductor package of the second embodiment may be different from the semiconductor package of the first embodiment in that a connection substrate 1210 is provided on the second circuit board 1200. The connection substrate 1210 may be referred to as a bridge substrate. For example, the connection substrate 1210 may include a redistribution layer.

[0102] In one implementation, the connection substrate 1210 may be a silicon bridge. That is, the connection substrate 1210 may include a silicon substrate and a redistribution layer disposed on the silicon substrate.

[0103] In another embodiment, the connection substrate 1210 may be an organic bridge. For example, the connection substrate 1210 may include an organic material. For example, the connection substrate 1210 includes an organic substrate including an organic material, rather than a silicon substrate.

[0104] The connection substrate 1210 may be embedded in the second circuit board 1200, but is not limited thereto. For example, the connection substrate 1210 may be provided on the second circuit board 1200 to have a protruding structure.

[0105] Preferably, the second circuit board 1200 may include a cavity, and the connection substrate 1210 may be disposed in the cavity of the second circuit board 1200 .

[0106] The connection substrate 1210 may horizontally connect a plurality of semiconductor devices disposed on the second circuit board 1200 .

[0107] Reference Figure 1c , the semiconductor package according to the third embodiment includes a second circuit board 1200 and a semiconductor device 1300. In this case, the semiconductor package of the third embodiment may have a structure in which the first circuit board 1100 is removed, compared with the semiconductor package of the second embodiment.

[0108] That is, the second circuit board 1200 of the third embodiment may be used as a package substrate while performing the interposer function.

[0109] The first connection member 1410 disposed on the lower surface of the second circuit board 1200 may couple the second circuit board 1200 to a main board of the electronic device.

[0110] Reference Figure 1d , a semiconductor package according to the fourth embodiment includes a first circuit board 1100 and a semiconductor device 1300 .

[0111] In this case, the semiconductor package of the fourth embodiment may have a structure in which the second circuit board 1200 is removed, compared with the semiconductor package of the second embodiment.

[0112] That is, the first circuit board 1100 of the fourth embodiment can be used as a packaging substrate, and also performs the function of an interposer connecting the semiconductor device 1300 and the main board. To this end, the first circuit board 1100 includes a connecting member 1110 for connecting a plurality of semiconductor devices. The connecting member 1110 can be a silicon bridge or an organic material bridge connecting a plurality of semiconductor devices.

[0113] Reference Figure 1e Compared with the semiconductor package of the fourth embodiment, the semiconductor package of the fifth embodiment further includes a third semiconductor device 1330 .

[0114] To this end, a fourth connection portion 1440 may be provided on the lower surface of the first circuit board 1100 .

[0115] In addition, the third semiconductor device 1330 may be disposed on the fourth connection portion 1400. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor devices are mounted on the upper side and the lower side, respectively.

[0116] In this case, the third semiconductor device 1330 may have a configuration in which Figure 1c The structure on the lower surface of the second circuit board 1200 in the semiconductor package.

[0117] Reference Figure 1f , the semiconductor package according to the sixth embodiment includes a first circuit board 1100 .

[0118] The first semiconductor device 1310 may be disposed on the first circuit board 1100 . To this end, a first connection member 1410 may be disposed between the first circuit board 1100 and the first semiconductor device 1310 .

[0119] In addition, the first circuit board 1100 includes a conductive bonding portion 1450. The conductive bonding portion 1450 may also protrude from the first circuit board 1100 toward the second semiconductor device 1320. The conductive bonding portion 1450 may be referred to as a bump, or alternatively, may also be referred to as a column. The conductive bonding portion 1450 may be provided to have a protruding structure on an electrode provided on the uppermost side of the first circuit board 1100.

[0120] The second semiconductor device 1320 may be disposed on the conductive bonding portion 1450 of the first circuit board 1100. In this case, the second semiconductor device 1320 may be connected to the first circuit board 1100 through the conductive bonding portion 1450. In addition, a second connection member 1420 may be disposed on the first and second semiconductor devices 1310 and 1320.

[0121] Therefore, the second semiconductor device 1320 may be electrically connected to the first semiconductor device 1310 through the second connection member 1420 .

[0122] That is, the second semiconductor device 1320 may be connected to the first circuit board 1100 through the conductive bonding portion 1450 , and may also be connected to the first semiconductor device 1310 through the second connection member 1420 .

[0123] In this case, the second semiconductor device 1320 may receive a power signal through the conductive bonding portion 1450. In addition, the second semiconductor device 1320 may transmit and receive a communication signal to and from the first semiconductor device 1310 through the second connection member 1420.

[0124] The semiconductor package according to the sixth embodiment can provide a power signal to the second semiconductor device 1320 through the conductive bonding portion 1450, thereby providing sufficient power to drive the second semiconductor device 1320. Therefore, the embodiment can improve the driving characteristics of the second semiconductor device 1320. That is, the embodiment can solve the problem of insufficient power provided to the second semiconductor device 1320. In addition, in the embodiment, at least one of the power signal and the communication signal of the second semiconductor device 1320 is provided through different paths passing through the conductive bonding portion 1450 and the second connecting member 1420. Thus, the embodiment can solve the problem that the communication signal is lost due to the power signal. For example, the embodiment can minimize the mutual interference between the communication signal and the power signal.

[0125] In addition, the second semiconductor device 1320 in the sixth embodiment may have a POP (Package on Package) structure and may be provided on the first circuit board 1100. For example, the second semiconductor device 1320 may be a memory package including a memory chip. In addition, the memory package may be bonded to the conductive bonding portion 1450. In this case, the memory package may not be connected to the first semiconductor device 1310.

[0126] In addition, the semiconductor package in the sixth embodiment may include a molding member 1460. The molding member 1460 may be disposed between the first circuit board 1100 and the second semiconductor device 1320. For example, the molding member 1460 may mold the first connection member 1410, the second connection member 1420, the first semiconductor device 1310, and the conductive bonding portion 1450.

[0127] Reference Figure 1g , the semiconductor package according to the seventh embodiment includes a first circuit board 1100 , a first connection member 1410 , a first connection member 1410 , a semiconductor device 1300 , and a third connection member 1430 .

[0128] In this case, the semiconductor package of the seventh embodiment may be different from the semiconductor package of the fourth embodiment in that the first circuit board 1100 includes a plurality of substrate layers and at the same time the connection substrate 1110 is omitted.

[0129] The first circuit board 1100 includes a plurality of substrate layers. For example, the first circuit board 1100 may include a first substrate layer 1100A corresponding to a package substrate and a second substrate layer 1100B corresponding to a redistribution layer of a connection substrate.

[0130] That is, the embodiment may configure the first circuit board 1100 by disposing the second substrate layer 1100 b corresponding to the redistribution layer on the first substrate layer 1100 a .

[0131] That is, the semiconductor package of the seventh embodiment may include a first substrate layer 1100A and a second substrate layer 1100B formed integrally. The material of the insulating layer of the second substrate layer 1100B may be different from the material of the insulating layer of the first substrate layer 1100A. For example, the material of the insulating layer of the second substrate layer 1100B includes a photocurable material. For example, the second substrate layer 1100B may be a PID (Photo Imageable Dielectric). In addition, since the second substrate layer 1100B includes a photocurable material, miniaturization of the electrode is possible. Therefore, the seventh embodiment may form the second substrate layer 1100B by sequentially laminating an insulating layer of a photocurable material on the first substrate layer 1100A and forming fine electrodes on the insulating layer of the photocurable material. Thus, the second substrate layer 1100B may be a redistribution layer including fine electrodes.

[0132] -Circuit Boards-

[0133] The circuit board of the embodiment will be described below.

[0134] Figure 2 is a cross-sectional view showing a circuit board according to a first embodiment, Figure 3 It is shown Figure 2 A plan view of a first insulating layer and a first circuit pattern layer in a circuit board of Figure 4 It is shown Figure 3 The circuit board has some of the construction removed. Figure 5 is along Figure 3 and Figure 4 A cross-sectional view taken along the A-A' direction, Figure 6 is corresponding to Figure 5 Optical microscope photos of actual products, Figure 7 is along Figure 3 and Figure 4 Cross-sectional view taken along the B-B' direction.

[0135] Before describing a circuit board of an embodiment, a circuit board described below may represent any one of a plurality of boards included in a semiconductor package.

[0136] Preferably, the circuit board of the embodiment described below may be any one of the first circuit board 1100 and the second circuit board 1200 included in the semiconductor package. In addition, at least one of the first circuit board 1100 and the second circuit board 1200 may include a cavity described below.

[0137] At this time, a connecting member may be disposed in the cavity.

[0138] When the circuit board is the first circuit board 1100 , the connection member may be any one of a connection substrate, a second circuit board, and a semiconductor device.

[0139] In addition, when the circuit board is the second circuit board 1200, the connection member may be any one of a semiconductor device and a connection substrate.

[0140] Reference Figure 2 The circuit board of the embodiment includes a plurality of insulating layers. Each of the plurality of insulating layers may have a single-layer structure, or alternatively, may be composed of a plurality of layers.

[0141] Specifically, the circuit board may include a first insulating layer 111 and a second insulating layer 112 .

[0142] At this time, the first insulating layer 111 may have a Figure 2 The single-layer structure shown in , or alternatively, may have a multi-layer structure.

[0143] The second insulating layer 112 is disposed on the first insulating layer 111. The second insulating layer 112 may have a single layer structure, or alternatively, may have a multi-layer structure. The second insulating layer 112 includes a cavity 150. In addition, when the second insulating layer 112 has a multi-layer structure, the cavity 150 may pass through a plurality of second insulating layers.

[0144] However, for convenience of explanation, each of the first insulating layer 111 and the second insulating layer 112 is described below as having a single-layer structure.

[0145] In one implementation, the first insulating layer 111 and the second insulating layer 112 may include the same insulating material.

[0146] In another embodiment, the first insulating layer 111 and the second insulating layer 112 may include different insulating materials. At this time, when the first insulating layer 111 has a multi-layer structure, all of the plurality of first insulating layers may include the same insulating material, or alternatively, may include different insulating materials. In addition, when the second insulating layer 112 has a multi-layer structure, all of the plurality of second insulating layers may include the same insulating material, or alternatively, may include different insulating materials.

[0147] At least one of the first insulating layer 111 and the second insulating layer 112 may be rigid or flexible. For example, at least one of the first insulating layer 111 and the second insulating layer 112 may include glass or plastic. For example, at least one of the first insulating layer 111 and the second insulating layer 112 may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, at least one of the first insulating layer 111 and the second insulating layer 112 may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, at least one of the first insulating layer 111 and the second insulating layer 112 may include sapphire. For example, the insulating layer 110 of the circuit board 100 may include an optically isotropic film. For example, at least one of the first insulating layer 111 and the second insulating layer 112 may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, at least one of the first insulating layer 111 and the second insulating layer 112 may be formed of a material including an inorganic filler and an insulating resin. For example, at least one of the first insulating layer 111 and the second insulating layer 112 may have a structure in which an inorganic filler of silicon dioxide or aluminum oxide is provided in a thermosetting resin or a thermoplastic resin.

[0148] Specifically, in one embodiment, the first insulating layer 111 may be a core layer including reinforcing fibers, and the second insulating layer 112 may not include reinforcing fibers. Therefore, the circuit board may be a core board.

[0149] In another embodiment, the circuit board may be a coreless board that does not include a core layer.

[0150] The first insulating layer 111 and the second insulating layer 112 of one embodiment may include an organic material without a reinforcing member, which has excellent processability, excellent rigidity, enables thinning of the circuit board, and enables miniaturization of the circuit pattern layer. The reinforcing member may also be referred to as reinforcing fiber or glass fiber.

[0151] For example, the first insulating layer 111 and the second insulating layer 112 may be made of ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), BT, or the like.

[0152] At this time, when the first insulating layer 111 and the second insulating layer 112 of the circuit board are formed of ABF (Ajinomoto Build-up Film), the warpage characteristics of the circuit board may be deteriorated.

[0153] Therefore, when the first insulating layer 111 and the second insulating layer 112 of another embodiment are composed of ABF (Ajinomoto Build-up Film), at least one ABF of the plurality of insulating layers constituting the circuit board may include a reinforcing material capable of improving warpage characteristics.

[0154] For example, the circuit board may include a layer composed of a first ABF and a layer composed of a second ABF, and the second ABF further includes a reinforcing material in the ABF. At this time, the reinforcing material included in the second ABF may be glass fiber, or may include a GCP (Glass Core Primer) material, but is not limited thereto.

[0155] In addition, embodiments allow for providing an electrode pattern such as a trace in a region exposed by the cavity 150 while providing the cavity 150 in the second insulating layer 112. At this time, when the second insulating layer 112 including the cavity 150 includes a photocurable resin, there may be no significant limitation on the arrangement of the electrode pattern.

[0156] This is because the photocurable resin can form a cavity through exposure and development processes, and thus no barrier is required during the cavity formation process.

[0157] However, if the second insulating layer 112 includes a photocurable resin, the adhesion between the multiple insulating layers of the circuit board may be reduced. Specifically, if the multiple insulating layers included in the circuit board are all composed of photocurable resin, the rigidity of the circuit board may be reduced, and the warping characteristics may be significantly reduced accordingly. In addition, if the first insulating layer 111 is composed of a thermosetting resin and the second insulating layer 112 is composed of a photocurable resin, the adhesion between the photocurable resin and the thermosetting resin may be reduced according to the physical properties of the photocurable resin. That is, the photocurable resin has a higher curing shrinkage than the thermosetting resin. In addition, the content of ceramic particles such as SiO2 provided in the photocurable resin is higher than the content of ceramic particles provided in the thermosetting resin. The adhesion between the thermosetting resin and the photocurable resin may be reduced due to this difference in physical properties.

[0158] In addition, when both the first insulating layer 111 and the second insulating layer 112 include a thermosetting resin, it is difficult to arrange an electrode pattern in a region exposed by the cavity 150. That is, a blocking member must be included in order to form the cavity 150. In addition, when an electrode pattern is provided in a region exposed by the cavity 150, a circuit short circuit problem occurs in which a plurality of electrode patterns are electrically connected through the blocking member. Therefore, in the conventional art, when a cavity is provided in a thermosetting resin, it is difficult to place an electrode pattern in a region exposed by the cavity.

[0159] In contrast, the embodiment allows the pad and the electrode pattern connected to the pad to be disposed in the region exposed by the cavity 150 of the second insulating layer 112 while the second insulating layer 112 includes a thermosetting resin. This will be described in more detail below.

[0160] The first insulating layer 111 and the second insulating layer 112 may each have a thickness in the range of 10 μm to 60 μm. For example, the first insulating layer 111 and the second insulating layer 112 may each have a thickness in the range of 15 μm to 55 μm. For example, the first insulating layer 111 and the second insulating layer 112 may each have a thickness in the range of 20 μm to 50 μm. If the thickness of the first insulating layer 111 and the second insulating layer 112 is less than 10 μm, the circuit pattern layer included in the circuit board cannot be reliably protected. If the thickness of each of the first insulating layer 111 and the second insulating layer 112 exceeds 60 μm, the total thickness of the circuit board will increase. In addition, if the thickness of each of the first insulating layer 111 and the second insulating layer 112 exceeds 60 μm, the thickness of the circuit pattern layer or the through electrode will increase accordingly, and the loss of the signal transmitted through the circuit pattern will increase accordingly.

[0161] At this time, the thickness of the first insulating layer 111 and the second insulating layer 112 may correspond to the distance between the circuit pattern layers provided in different layers in the thickness direction.

[0162] For example, the thickness of the first insulating layer 111 may represent the vertical distance between the lower surface of the first circuit pattern layer 121 and the upper surface of the third circuit pattern layer 123. For example, the thickness of the second insulating layer 112 may represent the vertical straight-line distance between the upper surface of the first circuit pattern layer 121 and the lower surface of the second circuit pattern layer 122 in the thickness direction.

[0163] The second insulating layer 112 may include a cavity 150. The cavity 150 may pass through the upper and lower surfaces of the second insulating layer 112.

[0164] The cavity 150 may include a lower surface 150-1 adjacent to the lower surface of the second insulating layer 112. At this time, the cavity 150 passes through the second insulating layer 112. Therefore, the lower surface 150-1 of the cavity 150 may be a portion of the upper surface of the first insulating layer 111 vertically overlapping the cavity 150.

[0165] The cavity 150 may include a sidewall 150-2 extending obliquely from the lower surface 150-1 toward the upper surface of the second insulating layer 112. At this time, the sidewall 150-2 may have a slope in which the width of the cavity 150 increases from the lower surface of the second insulating layer 112 to the upper surface of the second insulating layer 112. However, the embodiment is not limited to this. For example, the sidewall 150-2 may have a slope in which the width of the cavity 150 decreases from the lower surface of the second insulating layer 112 to the upper surface of the second insulating layer 112. In addition, although the drawings show that the sidewall 150-2 has one slope, the embodiment is not limited to this. For example, the sidewall 150-2 may include at least one inflection portion, and may be inclined at different slopes in the inflection portion.

[0166] The cavity 150 may include a recessed portion 150-3 extending from a lower end of a sidewall 150-2 connected to the lower surface 150-1 in a direction away from the cavity 150. For example, the recessed portion 150-3 may be recessed in an inner direction toward the second insulating layer 112 at a lower end of a sidewall 150-2 of the second insulating layer 112 forming the cavity 150. Therefore, the recessed portion 150-3 may also be referred to as an undercut, a cavity expansion region, or a recessed portion.

[0167] The concave portion 150-3 is located adjacent to the edge region of the lower surface 150-1. The concave portion 150-3 may be connected to the lower surface 150-1. Therefore, a region of the upper surface of the first insulating layer 111 vertically overlapping the concave portion 150-3 may not be covered by the second insulating layer 112.

[0168] The concave portion 150-3 may be disposed in an edge region of the lower surface 150-1 along an edge direction of the lower surface 150-1. For example, the lower surface 150-1 may refer to a region of the upper surface of the first insulating layer 111 that vertically overlaps with the cavity 150 but does not vertically overlap with the first circuit pattern layer 121. In addition, the concave portion 150-3 may be disposed entirely along an edge direction of the lower surface 150-1.

[0169] Therefore, the first insulating layer 111 may be divided into a plurality of regions based on the horizontal direction. For example, the first insulating layer 111 may include a first region R1 vertically overlapping the cavity 150. At this time, when the cavity 150 has different widths in the thickness direction of the second insulating layer 112, the first region R1 may refer to a region vertically overlapping the lower region of the cavity 150 corresponding to the lower portion of the sidewall 150-2.

[0170] In addition, the first insulating layer 111 may include a second region R2 that does not vertically overlap the cavity 150. The second region R2 may refer to a region of the upper surface of the first insulating layer 111 covered by the second insulating layer 112.

[0171] In addition, the first insulating layer 111 may include a third region R3 between the first region R1 and the second region R2. The third region R3 may indicate a boundary region between the first region R1 and the second region R2. Preferably, the third region R3 may indicate a region vertically overlapping the concave portion 150-3.

[0172] In addition, a circuit pattern layer is provided on the surfaces of the first insulating layer 111 and the second insulating layer 112 .

[0173] For example, the first circuit pattern layer 121 may be disposed between the upper surface of the first insulating layer 111 and the lower surface of the second insulating layer 112. For example, the second circuit pattern layer 122 may be disposed on the upper surface of the second insulating layer 112. For example, the third circuit pattern layer 123 may be disposed on the lower surface of the first insulating layer 111.

[0174] The first circuit pattern layer 121 in the first embodiment may be disposed on the first insulating layer 111. For example, the first circuit pattern layer 121 may protrude on an upper surface of the first insulating layer 111.

[0175] The second circuit pattern layer 122 may protrude on an upper surface of the second insulating layer 112. The second circuit pattern layer 122 may refer to an uppermost circuit pattern layer disposed on an uppermost side of a circuit board.

[0176] The third circuit pattern layer 123 may protrude below the lower surface of the first insulating layer 111. The third circuit pattern layer 123 may refer to a lowermost circuit pattern layer disposed at a lowermost side of the circuit board.

[0177] The first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each include a pad and a trace (or electrode pattern) according to their functions. The pad may be a mounting pad on which a device or chip is mounted, or a terminal pad connected to an external substrate. The trace may be a long signal wiring line connected between a plurality of pads. The trace is a fine pattern having a smaller width than the pad. For example, the interval between the plurality of traces in the embodiment may be in the range of 2 μm to 15 μm, and the line width of each trace may be in the range of 2 μm to 15 μm.

[0178] The circuit pattern layer as described above may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the circuit pattern layer may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength. Preferably, the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may be formed of copper (Cu) having high conductivity and being relatively inexpensive.

[0179] The first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each have a thickness in the range of 10 μm to 25 μm. For example, the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each have a thickness in the range of 10 μm to 23 μm. The first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each have a thickness in the range of 10 μm to 20 μm.

[0180] If the thickness of each of the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 is less than 10 μm, the resistance of the circuit pattern will increase, and thus the signal transmission efficiency will decrease. For example, if the thickness of each of the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 is less than 10 μm, the signal transmission loss will increase. For example, if the thickness of each of the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 exceeds 25 μm, the line width of the circuit pattern will increase, and thus the total volume of the circuit board will increase.

[0181] The first circuit pattern layer 121, the second circuit pattern layer 122 and the third circuit pattern layer 123 can be manufactured using conventional printed circuit board manufacturing processes such as additive process, subtractive process, MSAP (Modified SemiAdditive Process) and SAP (Semi Additive Process), and a detailed description thereof is omitted herein.

[0182] The first circuit pattern layer 121 may include a plurality of pads and electrode patterns.

[0183] The first circuit pattern layer 121 may include a first pad 121-1 disposed on the first region R1 of the first insulating layer 111. The first pad 121-1 may vertically overlap the cavity 150. Therefore, the first pad 121-1 may not contact the second insulating layer 112.

[0184] The first circuit pattern layer 121 may include a second pad 121-2 disposed on the second region R2 of the first insulating layer 111. The second pad 121-2 may not vertically overlap the cavity 150. Therefore, the second pad 121-2 may be covered by the second insulating layer 112.

[0185] The first circuit pattern layer 121 may include an electrode pattern 121 - 3 . The electrode pattern 121 - 3 may be disposed in the first region R1 , the second region R2 , and the third region R3 of the first insulating layer 111 .

[0186] At this time, the first circuit pattern layer 121 may include a plurality of electrode patterns. In addition, the above-mentioned electrode pattern 121-3 may represent an electrode pattern directly connected to the first pad 121-1 among the plurality of electrode patterns.

[0187] The electrode pattern 121-3 may be directly connected between the first pad 121-1 disposed in the first region R1 and the second pad 121-2 disposed in the second region R2. That is, the embodiment forms a cavity 150 in the second insulating layer 112 including a thermosetting resin, and arranges the electrode pattern 121-3 on the upper surface of the first insulating layer 111 exposed by the formed cavity 150. Therefore, in the embodiment, the first pad 121-1 in the first region R1 and the second pad 121-2 disposed in the second region R2 may be directly connected to each other through the electrode pattern 121-3 on the upper surface of the first insulating layer 111. Therefore, the embodiment may improve the adhesion between the multiple insulating layers of the circuit board through the first insulating layer 111 and the second insulating layer 112 including a thermosetting resin. In addition, the embodiment may improve the circuit integration density while improving the adhesion. That is, in the conventional technology, when a cavity is provided in the thermosetting resin, the first pad 121-1 and the second pad 121-2 are connected to each other through at least one through electrode. Therefore, the signal transmission distance between the first pad 121-1 and the second pad 121-2 increases, and thus the signal transmission loss increases. In contrast, the embodiment directly connects the first pad 121-1 and the second pad 121-2 by using the electrode pattern 121-3 without the need for a through electrode. Therefore, the embodiment can reduce the signal transmission distance, thereby minimizing the signal transmission loss. Therefore, the embodiment can improve the electrical reliability of the circuit board.

[0188] At this time, at least a portion of the electrode pattern 121-3 is connected to the concave portion 150-3. Here, being connected to the concave portion 150-3 may mean that the concave portion 150-3 and the electrode pattern 121-3 overlap each other along the edge direction. For example, the concave portion 150-3 vertically overlaps the third region R3 of the first insulating layer 111. In addition, the electrode pattern 121-3 includes a portion disposed in the third region R3. At this time, the side surface of the portion of the electrode pattern 121-3 disposed in the third region R3 may be exposed through the concave portion 150-3. For example, at this time, through the concave portion 150-3, the side surface of the portion of the electrode pattern 121-3 disposed in the third region R3 may not be covered by the second insulating layer 112.

[0189] In addition, in one embodiment, the thicknesses of the first pad 121 - 1 , the second pad 121 - 2 , and the electrode pattern 121 - 3 may be the same.

[0190] In another embodiment, at least one of the first pad 121-1, the second pad 121-2, and the electrode pattern 121-3 may have at least different thicknesses from each other. For example, the thickness of the first pad 121-1 may be different from the thickness of the second pad 121-2. For example, the thickness of the first pad 121-1 may be less than the thickness of the second pad 121-2. This may be because the etching amount of the seed layer of the first pad 121-1 is greater than the etching amount of the seed layer of the second pad 121-2. That is, the first pad 121-1 and the second pad 121-2 include a seed layer having the same thickness. In addition, the thickness of the first pad 121-1 and the second pad 121-2 may be reduced respectively in the etching process of the seed layer. At this time, the etching process of the seed layer of the first pad 121-1 is performed together with the etching process of the barrier corresponding to the concave portion 150-3. At this time, the embodiment may etch the barrier with a relatively large etching amount to prevent the barrier from remaining during the etching process of the barrier. Therefore, the thickness of the first pad 121 - 1 may be smaller than the thickness of the second pad 121 - 2 .

[0191] The circuit board of the embodiment includes a through electrode. The through electrode may have a function of electrically connecting circuit pattern layers disposed on different layers to each other. The through electrode may also be called a "via".

[0192] The through electrode passes through the first insulating layer 111 and the second insulating layer 112 included in the circuit board, so that the circuit patterns provided on different layers can be electrically connected. At this time, the through electrode can be formed by passing through only one insulating layer, or alternatively, the through electrode can be formed by passing through at least two or more insulating layers together.

[0193] For example, the circuit board includes a first through electrode 131. The first through electrode 131 may be formed by passing through the first insulating layer 111. The first through electrode 131 may be electrically connected between the first circuit pattern layer 121 and the third circuit pattern layer 123. For example, the upper surface of the first through electrode 131 may be directly connected to the lower surface of the first circuit pattern layer 121. For example, the lower surface of the first through electrode 131 may be directly connected to the third circuit pattern layer 123.

[0194] Therefore, the first circuit pattern layer 121 and the third circuit pattern layer 123 may be electrically connected to each other through the first through electrode 131 to transmit a signal.

[0195] For example, the circuit board includes a second through electrode 132. The second through electrode 132 may be formed by passing through the second insulating layer 112. The second through electrode 132 may electrically connect the first circuit pattern layer 121 and the second circuit pattern layer 122. For example, the lower surface of the second through electrode 132 may be directly connected to the first circuit pattern layer 121. For example, the upper surface of the second through electrode 132 may be directly connected to the second circuit pattern layer 122. Therefore, the first circuit pattern layer 121 and the second circuit pattern layer 122 may be directly electrically connected to each other through the second through electrode 132 to transmit a signal.

[0196] The first and second through electrodes 131 and 132 may be formed by forming through holes penetrating the first and second insulating layers 111 and 112 and filling the insides of the formed through holes with a conductive material.

[0197] The through hole can be formed by any of mechanical, laser and chemical processing methods. When the through hole is formed by mechanical processing, methods such as milling, drilling and routing can be used, when the through hole is formed by laser processing, UV or CO2 laser methods can be used, and when the through hole is formed by chemical processing, chemical reagents including aminosilane, ketones, etc. can be used to open at least one of the multiple insulating layers.

[0198] When forming the through hole, the inside of the through hole may be filled with a conductive material to form the first through electrode 131 and the second through electrode 132. The metal material forming the first through electrode 131 and the second through electrode 132 may be any one selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni) and palladium (Pd), and the filling of the conductive material may use any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet and dispensing.

[0199] In addition, the circuit board of the embodiment may include a first protective layer 141 and a second protective layer 142. The first protective layer 141 and the second protective layer 142 may be disposed on the outermost side of the circuit board.

[0200] For example, the first protective layer 141 may be disposed on a first outermost side or a lowermost side of the circuit board. For example, the first protective layer 141 may be disposed on a lower surface of the first insulating layer 111 .

[0201] For example, the second protective layer 142 may be disposed on the second outermost side or the uppermost side of the circuit board. For example, the second protective layer 142 may be disposed on the upper surface of the second insulating layer 112 .

[0202] The first protective layer 141 may include at least one opening (not shown). For example, the first protective layer 141 may include an opening vertically overlapping at least one of the third circuit pattern layers 123. For example, the first protective layer 141 may include an opening vertically overlapping a terminal pad (not shown) of the third circuit pattern layer 123 on which a conductive bonding portion for connection with an external substrate is disposed.

[0203] The second protective layer 142 may include at least one opening (not shown). For example, the second protective layer 142 may include an opening vertically overlapping at least one of the second circuit pattern layers 122. For example, the second protective layer 142 may include an opening vertically overlapping a terminal pad (not shown) of the second circuit pattern layer 122 on which a conductive bonding portion for connecting to a memory substrate or an interposer substrate is to be disposed. In addition, the second protective layer 142 may include a through hole (not shown) vertically overlapping the cavity 121 of the second insulating layer 112.

[0204] The first protective layer 141 and the second protective layer 142 may include an insulating material. The first protective layer 141 and the second protective layer 142 may include various materials that can be applied and then cured by heating to protect the surface of the insulating layer and the surface of the circuit pattern layer. The first protective layer 141 and the second protective layer 142 may be an anti-etching layer. For example, the first protective layer 141 and the second protective layer 142 may be a solder resist layer including an organic polymer material. As an example, the first protective layer 141 and the second protective layer 142 may include an epoxy acrylate series resin. In detail, the first protective layer 141 and the second protective layer 142 may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, the embodiment is not limited thereto, and the first protective layer 141 and the second protective layer 142 may be any one of a photosensitive solder resist layer, a cover-lay, and a polymer material.

[0205] The thickness of the first protective layer 141 and the second protective layer 142 may be 1 μm to 20 μm. The thickness of the first protective layer 141 and the second protective layer 142 may be 1 μm to 15 μm. For example, the thickness of the first protective layer 141 and the second protective layer 142 may be 5 μm to 20 μm. If the thickness of the first protective layer 141 and the second protective layer 142 exceeds 20 μm, the thickness of the circuit board will increase. If the thickness of the first protective layer 141 and the second protective layer 142 is less than 1 μm, electrical reliability or physical reliability may be reduced because the circuit pattern layer included in the circuit board is not stably protected.

[0206] At this time, although not shown in the figure, a surface treatment layer (not shown) may be provided in the openings of the first protective layer 141 and the second protective layer 142 vertically overlapping the second circuit pattern layer 122 and the third circuit pattern layer 123. The surface treatment layer may be formed to prevent corrosion and oxidation of the surfaces of the third circuit pattern layer 123 vertically overlapping the opening of the first protective layer 141 and the second circuit pattern layer 122 vertically overlapping the opening of the second protective layer 142 while improving soldering characteristics.

[0207] The surface treatment layer may be an OSP (Organic Solderability Preservative) layer. For example, the surface treatment layer may be an organic layer formed of an organic material such as benzimidazole.

[0208] However, the embodiment is not limited thereto. For example, the surface treatment layer may be a plating layer. For example, the surface treatment layer may include at least one of a nickel (Ni) plating layer, a palladium (Pd) plating layer, and a gold (Au) plating layer.

[0209] Hereinafter, the structure of the cavity 150 of the embodiment and the arrangement structure of the first circuit pattern layer 121 according to the structure of the cavity 150 will be described in more detail.

[0210] Reference Figure 3 , the first circuit pattern layer 121 may be disposed on the first insulating layer 111. In addition, as described above, the first circuit pattern layer 121 may include a first pad 121-1, a second pad 121-2, and an electrode pattern 121-3.

[0211] The first pad 121 - 1 may be disposed in a first region R1 vertically overlapping the cavity 150 .

[0212] In addition, the second pad 121 - 2 may be disposed in the second region R2 not vertically overlapping the cavity 150 .

[0213] In addition, the electrode pattern 121-3 may be disposed in the first region R1, the second region R2, and the third region R3. The electrode pattern 121-3 may directly connect the first pad 121-1 and the second pad 121-2 on the first insulating layer 111. For example, one end of the electrode pattern 121-3 may be directly connected to the first pad 121-1, and the other end of the electrode pattern 121-3 may be directly connected to the second pad 121-2.

[0214] At this time, the figure shows that the first pad 121-1, the second pad 121-2 and the electrode pattern 121-3 are each provided with 6, but it is not limited thereto. For example, the first pad 121-1, the second pad 121-2 and the electrode pattern 121-3 may each have 5 or less or 7 or more. In addition, the number of the first pad 121-1, the second pad 121-2 and the electrode pattern 121-3 may be different from each other. Therefore, at least one of the plurality of first pads 121-1 may not be directly connected to the second pad 121-2.

[0215] In addition, refer to Figure 4 , the second insulating layer 112 may be disposed on the first insulating layer 111. The second insulating layer 112 may include a cavity 150. The cavity 150 may pass through the second insulating layer 112.

[0216] Therefore, the first pad 121 - 1 may not vertically overlap the second insulating layer 112 . For example, the first pad 121 - 1 may vertically overlap the cavity 150 .

[0217] In addition, the second pad 121-2 may vertically overlap the second insulating layer 112. For example, the second pad 121-2 may not vertically overlap the cavity 150.

[0218] In addition, the electrode pattern 121-3 may be divided into a plurality of parts according to positions. At this time, being divided into a plurality of parts may mean that one electrode pattern directly connecting one first pad and one second pad is divided into a plurality of parts.

[0219] The electrode pattern 121-3 may include a first portion 121-31 vertically overlapping the cavity 150 and connected to the first pad 121-1. The first portion 121-31 of the electrode pattern 121-3 may not vertically overlap the second insulating layer 112. For example, the first portion 121-31 of the electrode pattern 121-3 may not be covered by the second insulating layer 112.

[0220] In addition, the electrode pattern 121-3 may include a second portion 121-32 vertically overlapping the second insulating layer 112. The second portion 121-32 of the electrode pattern 121-3 may not vertically overlap the cavity 150. For example, the second portion 121-32 of the electrode pattern 121-3 may be covered with the second insulating layer 112.

[0221] The electrode pattern 121 - 3 may further include a third portion 121 - 33 between the first portion 121 - 31 and the second portion 121 - 32 .

[0222] The third portion 121-33 of the electrode pattern 121-3 may represent a portion adjacent to an edge region of the lower surface 150-1 of the cavity 150. For example, the third portion 121-33 of the electrode pattern 121-3 may represent a portion located at a boundary region of the cavity 150. For example, the third portion 121-33 of the electrode pattern 121-3 may represent a portion located adjacent to the concave portion 150-3. For example, the third portion 121-33 of the electrode pattern 121-3 may represent a portion disposed in the third region R3 as a boundary region between the first region R1 and the second region R2.

[0223] In addition, the concave portion 150-3 may be provided in the edge region of the lower surface 150-1 along the edge direction of the lower surface 150-1. For example, the concave portion 150-3 may be concave in the inner direction of the second insulating layer 112 at the lower end of the side wall 150-2 adjacent to the edge region of the lower surface 150-1. In short, the lower end portion of the side wall 150-2 of the second insulating layer 112 constituting the cavity 150 may be provided with the concave portion 150-3 concave toward the inner side along the edge direction of the lower surface 150-1.

[0224] At this time, the figure shows that the concave portion 150 - 3 is not provided in the region vertically overlapping with the electrode pattern 121 - 3 among the lower end portions of the sidewalls 150 - 2 , but is not limited thereto. This will be described as follows.

[0225] Reference Figures 5 to 7 , the first circuit pattern layer 121 includes a plurality of metal layers.

[0226] The first circuit pattern layer 121 includes a first metal layer 121a disposed on the first insulating layer 111. The first metal layer 121a may represent a seed layer for electrolytically plating the second metal layer 121b of the first circuit pattern layer 121.

[0227] For example, the first metal layer 121 a may be a chemically plated copper layer. For example, the first metal layer 121 a may be a copper foil layer (Cu foil).

[0228] In one implementation, the first metal layer 121 a may include only one of an electroless copper plating layer and a copper foil layer.

[0229] In another embodiment, the first metal layer 121 a may include both an electroless copper layer and a copper foil layer.

[0230] The thickness T1 of the first metal layer 121a may be within a range of 1.0 μm to 4.0 μm. Preferably, the thickness T1 of the first metal layer 121a may be within a range of 1.2 μm to 3.5 μm. More preferably, the thickness T1 of the first metal layer 121a may be within a range of 1.5 μm to 3.0 μm.

[0231] If the thickness T1 of the first metal layer 121a is less than 1.0 μm, the first metal layer 121a may not function as a seed layer. If the thickness T1 of the first metal layer 121a is less than 1.0 μm, it may be difficult to form the first metal layer 121a with a uniform thickness on the upper surface of the first insulating layer 111 .

[0232] If the thickness T1 of the first metal layer 121a exceeds 4.0 μm, the time required to etch the first metal layer 121a may increase. If the thickness T1 of the first metal layer 121a exceeds 4.0 μm, deformation of the second metal layer 121b may occur during etching of the first metal layer 121a. The deformation of the second metal layer 121b may indicate that the difference between the width of the upper surface and the width of the lower surface of the second metal layer 121b increases as the side of the first metal layer 121a is also etched. In addition, if the thickness T1 of the first metal layer 121a exceeds 4.0 μm, the reliability of the etching process of the first metal layer 121a used as a barrier in the cavity formation process may deteriorate. For example, a portion of the first metal layer 121a is used as a barrier in the process of forming the cavity. In addition, after the formation of the cavity 150 is completed, the first metal layer 121a used as a barrier is removed. At this time, if the thickness T1 of the first metal layer 121a exceeds 4.0 μm, a portion of the barrier in a portion corresponding to the concave portion 150-3 may not be removed during the etching process of the barrier. In addition, if a portion of the barrier is not removed, an electrical short circuit problem in which a plurality of adjacent electrode patterns are connected to each other through the barrier may occur.

[0233] The second metal layer 121b is disposed on the first metal layer 121a. The second metal layer 121b may be a plated layer in which the first metal layer 121a is plated as a seed layer.

[0234] The thickness T2 of the second metal layer 121b may correspond to a value obtained by subtracting the thickness of the first metal layer 121a from the total thickness of the first circuit pattern layer 121. Since the total thickness of the first circuit pattern layer 121 has been described above, a detailed description thereof will be omitted.

[0235] In addition, the first pad 121-1, the second pad 121-2, and the electrode pattern 121-3 of the first circuit pattern layer 121 each include a first metal layer 121a and a second metal layer 121b. At this time, the first pad 121-1, the second pad 121-2, and the electrode pattern 121-3 represent one circuit pattern including the same first metal layer 121a and the same second metal layer 121b, and can be distinguished only by arrangement position and function.

[0236] The electrode pattern 121 - 3 includes the first portion 121 - 31 , the second portion 121 - 32 , and the third portion 121 - 33 as described above.

[0237] At this time, the third portion 121-33 of the electrode pattern 121-3 may include an area with a varying thickness. For example, at least a portion of the third portion 121-31 of the electrode pattern 121-3 may include a portion having a thickness greater than that of the first portion 121-31. For example, at least a portion of the third portion 121-33 of the electrode pattern 121-3 may include a portion having a thickness greater than that of the second portion 121-32.

[0238] For example, at least a portion of the upper surface of the third portion 121-33 of the electrode pattern 121-3 may include a portion positioned higher than the upper surface of the first portion 121-31. For example, at least a portion of the upper surface of the third portion 121-33 of the electrode pattern 121-3 may include a portion positioned higher than the upper surface of the second portion 121-32.

[0239] For example, the third portion 121 - 32 of the electrode pattern 121 - 3 may include a protrusion 121 - 3P whose thickness or height varies from the first portion 121 - 31 to the second portion 121 - 32 or from the second portion 121 - 32 to the first portion 121 - 31.

[0240] In addition, the protrusion 121 - 3P may include a first portion whose height or thickness increases from the first portion 121 - 31 to the second portion 121 - 32 and a second portion whose height or thickness decreases based on the first portion.

[0241] At this time, the embodiment etches the first metal layer 121 a of the first circuit pattern layer 121 in a plurality of steps during the manufacturing process of the circuit board.

[0242] That is, in an embodiment, before the cavity 150 of the second insulating layer 112 is formed, the first metal layer 121 a of the first circuit pattern layer 121 disposed in the second region R2 is removed in the first etching process.

[0243] In addition, after the cavity 150 is formed, the first metal layer 121 a of the first circuit pattern layer 121 disposed in the first region R1 and the third region R3 is removed in the second etching process.

[0244] At this time, the second metal layer of the electrode pattern 121-3 may also be etched in two steps corresponding to the first metal layer. In addition, under ideal conditions, a portion of the second metal layer of the electrode pattern 121-3 may be removed in the first etching process, and the remaining portion of the second metal layer of the electrode pattern 121-3 may be removed in the second etching process. However, due to a processing error in the electrode pattern 121-3, it may be difficult to accurately distinguish between a portion where the first etching process is performed and a portion where the second etching process is performed.

[0245] Therefore, some of the second metal layer of the electrode pattern 121-3 may not be etched in both the first etching process and the second etching process. In addition, the portion where etching is not performed may be provided as a protrusion 121-3P. The protrusion 121-3P may be provided at a boundary between the third region R3 and the second region R2 in the third portion 121-32 of the electrode pattern 121-3.

[0246] In addition, on the contrary, some of the second metal layer may etch the electrode pattern 121-3 in both the first etching process and the second etching process. In addition, under the above conditions, the third portion 121-32 of the electrode pattern 121-3 may be provided with a concave portion (not shown) instead of the protrusion 121-3P.

[0247] In addition, the third portion 121 - 33 of the electrode pattern 121 - 3 is adjacent to the concave portion 150 - 3 .

[0248] At this time, at least a portion of the upper surface of the third portion 121 - 33 of the electrode pattern 121 - 3 may vertically overlap the second insulating layer 112 and may not contact the second insulating layer 112 .

[0249] For example, the second concave portion 150-4 may be provided in a region vertically overlapping the electrode pattern 121-3 at a lower end portion of the sidewall 150-2 of the cavity 150 of the second insulating layer 112. Therefore, the above-mentioned concave portion 150-3 may be referred to as a first concave portion. Hereinafter, the concave portion 150-3 will be described as a "first concave portion".

[0250] The first and second concave portions 150 - 3 and 150 - 4 are disposed at lower ends of the sidewalls 150 - 2 of the second insulating layer 112 adjacent to edge regions of the lower surface 150 - 1 .

[0251] At this time, the first concave portion 150-3 and the second concave portion 150-4 may have a step. That is, the first concave portion 150-3 is disposed in a region of the lower end of the sidewall 150-2 that does not vertically overlap with the electrode pattern 121-3.

[0252] In contrast, the second concave portion 150-4 is disposed in a region of the lower end of the sidewall 150-2 vertically overlapping the electrode pattern 121-3. Therefore, the first concave portion 150-3 and the second concave portion 150-4 may have a step equal to the thickness of the electrode pattern 121-3.

[0253] Therefore, the first and second concave portions 150 - 3 and 150 - 4 may be recessed toward the inside of the second insulating layer 112 in the edge direction of the lower surface 150 - 1 in the entire region of the lower portion of the sidewall 150 - 2 .

[0254] The first concave portion 150 - 3 may have a first horizontal distance W1 .

[0255] The first horizontal distance W1 may represent a horizontal distance from a lower end portion of the sidewall 150-2 adjacent to the first concave portion 150-3 to an innermost surface of the first concave portion 150-3. In addition, the first concave portion 150-3 is a space where the first metal layer used as a barrier in the process of forming the cavity 150 is removed.

[0256] The first horizontal distance W1 may satisfy the range of 5 μm to 17 μm. Preferably, the first horizontal distance W1 may satisfy the range of 7 μm to 15 μm. More preferably, the first horizontal distance W1 may satisfy the range of 8 μm to 13 μm.

[0257] If the first horizontal distance W1 is less than 5 μm, the cavity 150 may be processed all the way to the area where the blocking member is not provided due to a processing error in the process for forming the cavity 150. In this case, a portion of the upper surface of the first insulating layer 111 may also be processed in the process for forming the cavity. At this time, the first insulating layer 111 includes reinforcing fibers. In addition, the reinforcing fibers may be exposed by processing, and thus physical reliability problems and electrical reliability problems may occur.

[0258] In addition, if the first horizontal distance W1 exceeds 17 μm, a portion of the barrier may not be removed in the barrier removal process after the cavity 150 is formed. For example, the embodiment removes all the barrier by utilizing the over-etching phenomenon in the barrier removal process. That is, if the barrier removal process is performed after the cavity 150 is formed, only the portion vertically overlapping the cavity 150 is removed by etching under general conditions. However, the embodiment sets an over-etching condition in the barrier removal process and removes the barrier according to the set over-etching condition. In addition, when the barrier is removed according to the over-etching condition, the barrier covered by the second insulating layer 112 in the region adjacent to the cavity 150 is also removed. At this time, the fact that the first horizontal distance W1 exceeds 17 μm may indicate that the over-etching condition is set too excessively, which may cause damage to the first pad 121-1. In addition, the fact that the first horizontal distance W1 exceeds 17 μm may indicate that a portion of the barrier may not be removed even under the over-etching condition for removing the barrier. In addition, if a portion of the barrier is not removed, electrical reliability problems such as circuit short circuits may occur.

[0259] In addition, the first concave portion 150 - 3 is a space where the first metal layer 121 a is removed, and thus, a vertical distance T1 of the first concave portion 150 - 3 may correspond to a thickness T1 of the first metal layer 121 a .

[0260] In addition, the second concave portion 150-4 may have a second horizontal distance W2. At this time, the second horizontal distance W2 of the second concave portion 150-4 may be greater than or equal to the first horizontal distance W1 of the first concave portion 150-3. Preferably, the second horizontal distance W2 of the second concave portion 150-4 may be greater than the first horizontal distance W1 of the first concave portion 150-3.

[0261] This means that the first horizontal distance W1 and the second horizontal distance W2 being equal to each other may indicate that under the overetching condition for removing the blocking member, only the portion where the blocking member is located is overetched accurately. In this case, there may be a problem that a portion of the blocking member is not removed in some cases. Therefore, the embodiment allows the second horizontal distance W2 to be greater than the first horizontal distance W1. In addition, the fact that the second horizontal distance W2 is greater than the first horizontal distance W1 may indicate that under the overetching condition for removing the blocking member, overetching occurs in portions other than the portion where the blocking member is located. Therefore, the blocking member can be completely removed, thereby improving the electrical reliability of the circuit board.

[0262] Figure 8 is a cross-sectional view showing a circuit board according to a second embodiment, Fig. 9 It is shown Figure 8 A magnified view of a portion of the cavity. Fig.10 It is shown Figure 8 An enlarged view of another part of the cavity.

[0263] Reference Figures 8 to 10 The circuit board of the second embodiment includes a first insulating layer 211, a second insulating layer 212, a first circuit pattern layer 221, a second circuit pattern layer 222, a third circuit pattern layer 223, a first through electrode 231, a second through electrode 232, a first protective layer 241, and a second protective layer 242. In addition, the second insulating layer 212 may be provided with a cavity 250 including a lower surface 250-1 and a sidewall 250-2.

[0264] At this time, the circuit board of the second embodiment may have a structure in which a cavity is provided in the first insulating layer of the first embodiment when the circuit board of the first embodiment is inverted.

[0265] Therefore, the circuit board of the second embodiment may be different in the position of the first concave portion 250 - 3 and the layer structure of the first circuit pattern layer 221 .

[0266] Specifically, the first concave portion in the first embodiment is provided at the side wall of the second insulating layer.

[0267] Different from this, the first concave portion 250 - 3 in the second embodiment may be provided at the upper surface of the first insulating layer 211 .

[0268] That is, the first circuit pattern layer 221 includes a first metal layer 221 a and a second metal layer 221 b .

[0269] At this time, in the circuit board of the first embodiment, the second metal layer of the first circuit pattern layer is positioned closer to the cavity than the first metal layer.

[0270] In contrast, the circuit board of the second embodiment has the first metal layer 221 a located closer to the cavity 250 than the second metal layer 221 b of the first circuit pattern layer 221 .

[0271] Therefore, in the circuit board of the second embodiment, the upper surface of the first insulating layer 211 may have a step. For example, the upper surface of the first insulating layer 211 in the region vertically overlapping with the cavity 250 may have a first height. In addition, the upper surface of the first insulating layer 211 in the region not vertically overlapping with the cavity 250 may have a second height higher than the first height. At this time, the portion of the upper surface of the first insulating layer 211 that does not vertically overlap with the cavity 250 and is adjacent to the cavity 250 may include a first concave portion 250-3 having a first height. That is, the cavity 250 is formed in a state where the first metal layer 221a of the first circuit pattern layer 221 is disposed at a position corresponding to the first concave portion 250-3. In addition, when a portion of the first metal layer 221a is removed after the cavity 250 is formed, the upper surface of the first insulating layer 211 may have a step corresponding to the concave portion 250-3.

[0272] That is, the first concave portion 250 - 3 of the second embodiment may be recessed from the lower end of the sidewall 150 - 2 of the cavity 250 toward the inner side of the first insulating layer 211 .

[0273] In summary, the first concave portion and the second concave portion of the first embodiment have a structure that is recessed from the lower end of the side wall of the cavity toward the inner side of the second insulating layer. Therefore, the lower surface of the second insulating layer of the first embodiment has steps corresponding to the first concave portion and the second concave portion.

[0274] Unlike this, the first concave portion 250-3 of the second embodiment may have a structure recessed from the lower end of the sidewall 150-2 of the cavity 250 toward the inner side of the first insulating layer 211. Therefore, the upper surface of the first insulating layer 211 may have a step corresponding to the first concave portion 250-3.

[0275] In addition, the first circuit pattern layer 221 includes a first pad 221-1, a second pad 221-2, and an electrode pattern 221-3. In addition, the electrode pattern 221-3 may include a first portion 221-31, a second portion 221-32, and a third portion 221-33.

[0276] At this time, the first pad 221-1, the second pad 221-2, and the electrode pattern 221-3 may have different thicknesses. For example, the first pad 221-1, the second pad 221-2, and the electrode pattern 221-3 may have different layer structures.

[0277] Preferably, the first circuit pattern layer 221 may include a first metal layer 221 a and a second metal layer 221 b .

[0278] At this time, the first metal layer of the first pad 221-1 serves as a barrier in the process of forming the cavity 250. Accordingly, the first pad 221-1 may include only the second metal layer without including the first metal layer.

[0279] Different from this, the second pad 221 - 2 may include both the first metal layer 221 a and the second metal layer 221 b .

[0280] In addition, the electrode pattern 221 - 3 may have different layer structures or thicknesses according to locations.

[0281] The first portion 221 - 31 of the electrode pattern 221 - 3 may include only the second metal layer 221 b . This is because the first metal layer 221 a of the first portion 221 - 31 of the electrode pattern 221 - 3 serves as a barrier in the process of forming the cavity 250 .

[0282] In addition, the second portion 221 - 32 of the electrode pattern 221 - 3 may include both the first metal layer 221 a and the second metal layer 221 b .

[0283] In addition, the third portion 221-33 of the electrode pattern 221-3 may include only the second metal layer 221b because the first metal layer 221a of the third portion 221-33 of the electrode pattern 221-3 is removed due to over-etching in the process of removing the first metal layer of the first portion 221-31 of the electrode pattern 221-3 by etching.

[0284] The circuit board of the embodiment includes a first insulating layer; a first circuit pattern layer disposed on the first insulating layer; and a second insulating layer disposed on the first insulating layer and the first circuit pattern layer. At this time, the second insulating layer includes a cavity passing through the upper surface and the lower surface. In addition, the first circuit pattern layer may include a first pad disposed in a first region vertically overlapping the cavity; a second pad disposed in a second region not vertically overlapping the cavity; and an electrode pattern disposed in the first region and the second region and connecting the first pad and the second pad.

[0285] That is, the embodiment arranges an electrode pattern that directly connects the first pad and the second pad on the first insulating layer. Therefore, the embodiment can reduce the signal transmission distance between the first pad and the second pad. In addition, the embodiment can minimize the signal transmission loss by reducing the signal transmission distance. Therefore, the embodiment can improve the electrical characteristics of the circuit board and the semiconductor package including the circuit board.

[0286] In addition, embodiments may improve circuit integration by arranging electrode patterns in a region corresponding to a cavity.

[0287] In addition, the second insulating layer including the cavity includes a thermosetting resin. In addition, the embodiment can arrange the electrode pattern while the second insulating layer includes a thermosetting resin. By forming the insulating layer using a thermosetting resin, the embodiment can improve the adhesion between the plurality of insulating layers. Therefore, the embodiment can improve the physical properties of the circuit board and the semiconductor package including the circuit board.

[0288] In addition, a concave portion may be provided at the lower end of the side wall of the cavity along the circumferential direction of the lower surface of the cavity. The concave portion may have a closed loop shape along the circumferential direction of the lower surface of the cavity. At this time, the concave portion may include a portion with a step in one embodiment, and may not have a step in another embodiment.

[0289] Therefore, the embodiment arranges the connection member and the molding member for molding the connection member in the cavity. In addition, the molding member can fill the concave portion provided in the cavity. At this time, the embodiment can allow a portion of the entire area of ​​the molding member positioned in the concave portion to be used as an anchor. Therefore, the embodiment can improve the adhesion between the circuit board and the molding member. Therefore, the embodiment can protect the connection member more stably. In addition, the embodiment can further improve the product reliability of the semiconductor package.

[0290] Fig.11 is a diagram showing a package substrate according to an embodiment.

[0291] Reference Fig.11 , the package substrate may include a contact member 310 disposed on the first pad 121 - 1 and a connection member 320 disposed on the contact member 310 .

[0292] The connecting member may be Figure 1a to Figure 1g Any one of the second circuit board, the semiconductor device and the connection substrate shown in .

[0293] In addition, a molding member 330 may be provided in the cavity 150. The molding member 330 may be provided by molding the connection member 320 in the cavity 150.

[0294] At this time, at least a portion of the molding member 330 may be disposed to fill the first concave portion 150-3 and the second concave portion 150-4 disposed in the cavity 150. The portion of the molding member 330 disposed in the first concave portion 150-3 and the second concave portion 150-4 may serve as an anchor. Therefore, the embodiment may further improve the adhesion between the molding member 330 and the circuit board.

[0295] Hereinafter, a method for manufacturing a circuit board of the embodiment will be described.

[0296] Figures 12 to 22The process sequence is shown according to the embodiment. Figure 2 FIG. 1 is a diagram of a method for manufacturing a circuit board.

[0297] Reference Fig.12 , an embodiment prepares an insulating member as a basis for manufacturing a circuit board.

[0298] For example, the embodiment prepares an insulating member including a first insulating layer 111 and a metal layer on the first insulating layer 111 .

[0299] The metal layer may include a metal layer 121a disposed on the first insulating layer 111 and a metal layer 123a disposed under the first insulating layer 111. In addition, the metal layer 121a may be used as a seed layer for forming the first circuit pattern layer 121 by electrolytic plating. In addition, the metal layer 123a may be used as a seed layer for forming the third circuit pattern layer 123 by electrolytic plating.

[0300] Next, refer to Fig.13 , the embodiment performs electrolytic plating on the metal layers 121a and 123a as seed layers to form the second metal layer 121b of the first circuit pattern layer 121, the second metal layer 123b of the third circuit pattern layer 123, and the first through electrode 131 passing through the first insulating layer 111.

[0301] At this time, until Fig.13 The substrate manufactured by the process of may include a first region R1, a second region R2, and a third region R3. The first region R1 may be a region corresponding to the size of the actual cavity 150. In addition, the second region R2 may be a region where the cavity 150 is not formed. In addition, the third region R3 refers to a boundary region between the first region R1 and the second region R2. The third region R3 may be a region in which a processing error in the process of forming the cavity is taken into account.

[0302] Afterwards, refer to Fig.14 , the embodiment arranges a dry film DF1 on the first region R1 and the third region R3 of the first circuit pattern layer 121. The dry film DF1 may prevent the first metal layer 121a, which is to be used as a stopper in the first etching process, from being removed.

[0303] Next, refer to Fig.15 Embodiments may perform a process of removing the first metal layer 121a of the first circuit pattern layer 121 and the first metal layer 123a of the third circuit pattern layer 123 in the region where the dry film DF1 is not disposed. Thus, embodiments may form the second pads 121-2 of the first circuit pattern layer 121 and the third circuit pattern layer 123.

[0304] That is to say, refer to Fig.16, all portions of the first metal layer 121a disposed in the second region R1 that do not vertically overlap with the second metal layer 121b may be removed. Thus, the second pad 121-2 of the first circuit pattern layer 121 and a portion (e.g., the second portion 121-32) of the electrode pattern 221-3 may be formed. At this time, the first metal layer 121a disposed in the first region R1 and the third region R3 may be used as a first barrier S1 in the process of forming the cavity 150.

[0305] Next, refer to Fig.17 , embodiments may dispose the second insulating layer 112 on the first insulating layer 111. At this time, the first metal layer 122a of the second circuit pattern layer 122 as a seed layer of the second circuit pattern layer 122 may be disposed on an upper surface of the second insulating layer 112.

[0306] Next, refer to Fig.18 The embodiment may continue the process of forming the second metal layer 122b of the second circuit pattern layer 122 by performing electrolytic plating using the first metal layer 122a of the second circuit pattern layer 122 as a seed layer. At this time, the second through electrode 132 passing through the second insulating layer 112 may be formed together with the second metal layer 122b.

[0307] Next, refer to Fig.19 , the embodiment may perform a process of removing the first metal layer 122a of the second circuit pattern layer 122 by etching. At this time, the embodiment may not completely remove the first metal layer 122a of the second circuit pattern layer 122, but may leave some of the first metal layer 122a of the second circuit pattern layer 122. For example, the embodiment may completely remove a portion of the first metal layer 122a of the second circuit pattern layer 122 disposed in the first region R1. In addition, the embodiment does not remove a portion of the first metal layer 122a of the second circuit pattern layer 122 in the third region R3 and the second region R2 adjacent to the third region R3. This may be used as a second barrier S2 in the process of forming the cavity 150. In this case, the first barrier S1 and the second barrier S2 may include portions that overlap vertically with each other. For example, the first barrier S1 and the second barrier S2 may overlap vertically in the third region R3. Thus, the embodiment may prevent the size of the cavity 150 from expanding in the process of forming the cavity 150.

[0308] Next, refer to Fig. 20 , embodiments may form the cavity 150 through the second insulating layer 112 by using the first barrier member S1 and the second barrier member S2 .

[0309] In this case, the cavity 150 may not vertically overlap the third region R3 at a lower end of the sidewall 150 - 2 of the cavity 150 .

[0310] Afterwards, refer to Fig.21 , the embodiment may perform a process of removing the first barrier S1 and the second barrier S2 by etching. In this case, the second barrier S2 may be easily removed because there is no insulating layer covering the second barrier S2 thereon.

[0311] On the contrary, a portion of the entire region of the first barrier S1 corresponding to the third region R3 is covered by the second insulating layer 112. At this time, if etching is performed on a portion of the entire region of the first barrier S1 corresponding to the first region R1, over-etching may be performed. In addition, embodiments may easily remove the first barrier S1 in the third region R3 by utilizing over-etching. Therefore, a first concave portion 150-3 as a position where the first barrier S1 is removed may be provided at a lower end of the sidewall 150-2 of the cavity 150.

[0312] Next, refer to Fig. 22 , embodiments may perform a process of forming a first protective layer 141 under the first insulating layer 111 and forming a second protective layer 142 on the second insulating layer 112 .

[0313] On the other hand, when the circuit board having the above-mentioned features of the present invention is used for IT equipment or household appliances such as smart phones, server computers, TVs, etc., functions such as signal transmission or power supply can be stably performed. For example, when the circuit board having the features of the present invention performs a semiconductor packaging function, the circuit board can be used to safely protect the semiconductor chip from external moisture or pollutants, or alternatively, it can solve the problem of leakage current or electrical short circuit between terminals or electrical open circuit of terminals provided to the semiconductor chip. In addition, when the signal transmission function is dominant, the noise problem can be solved. Thus, the circuit board having the above-mentioned features of the present invention can maintain the stable function of IT equipment or household appliances, so that the entire product and circuit board to which the present invention is applied can achieve functional unification or technical linkage with each other.

[0314] When the circuit board having the above-mentioned features of the present invention is used in a transportation device such as a vehicle, it is possible to solve the problem of signal distortion transmitted to the transportation device, or alternatively, by safely protecting the semiconductor chip controlling the transportation device from the outside and solving the problem of leakage current or electrical short circuit between terminals or electrical open circuit of terminals provided to the semiconductor chip, the safety of the transportation device can be further improved. Therefore, the transportation device and the circuit board to which the present invention is applied can achieve functional integrity or technical linkage with each other.

[0315] The characteristics, structures, and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, a person skilled in the art to which the embodiments belong may even combine or modify the characteristics, structures, and effects shown in each embodiment relative to other embodiments. Therefore, it should be understood that the contents related to such combinations and such modifications are included in the scope of the embodiments.

[0316] The above description focuses on the embodiments, but it is merely illustrative and does not limit the embodiments. It will be appreciated by those skilled in the art that various modifications and applications not shown above may be made without departing from the basic features of the embodiments. For example, each component specifically indicated in the embodiments may be modified and implemented. In addition, it should be understood that the differences associated with these changes and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: a first insulating layer; a second insulating layer, the second insulating layer being disposed on the first insulating layer; as well as a circuit pattern layer, the circuit pattern layer being disposed between the first insulating layer and the second insulating layer, wherein the second insulating layer has a cavity passing through the upper surface and the lower surface, and The circuit pattern layer includes an electrode pattern extending from an inner side of the cavity to an outer side of the cavity.

2. The circuit board according to claim 1, wherein the circuit pattern layer further comprises: A first pad, the first pad being disposed on an inner side of the cavity and overlapping the cavity in a vertical direction; as well as A second pad is disposed on an outer side of the cavity and does not vertically overlap the cavity. 3 . The circuit board according to claim 2 , wherein the electrode pattern is directly connected between the first pad and the second pad. 4 . The circuit board according to claim 1 , wherein the second insulating layer has a concave portion that is concave in a direction from a lower end of a side wall of the cavity toward an outside of the cavity. 5 . The circuit board according to claim 4 , wherein the concave portion has a first portion that does not overlap with the electrode pattern in a vertical direction, and a second portion that overlaps with the electrode pattern in the vertical direction.

6. The circuit board according to claim 3, wherein the circuit pattern layer is provided to protrude on the first insulating layer, and The first portion of the recessed portion is disposed along an edge of a lower end of a side wall of the cavity. 7 . The circuit board according to claim 5 , wherein the first portion and the second portion of the concave portion have a step.

8. The circuit board according to claim 5, wherein the first pad, the second pad, and the electrode pattern each comprise: a first metal layer, the first metal layer being disposed on the first insulating layer; as well as a second metal layer, the second metal layer being disposed on the first metal layer, and The length of the first portion of the concave portion in the vertical direction corresponds to the thickness of the first metal layer. 9 . The circuit board according to claim 5 , wherein a horizontal distance from a lower end of a side wall of the cavity to an innermost end of the first portion of the concave portion satisfies a range of 5 μm to 17 μm. 10 . The circuit board according to claim 5 , wherein a horizontal length of the first portion of the concave portion is different from a horizontal length of the second portion of the concave portion.

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