Display substrate, preparation method thereof and display device

Abstract

The invention discloses a display substrate, a preparation method thereof and a display device. The display substrate comprises a plurality of repetitive units (100), each repetitive unit (100) comprises a plurality of sub-pixels, each sub-pixel at least comprises a pixel driving circuit, and each pixel driving circuit is connected with a first power line (51); the pixel driving circuit at least comprises a driving transistor (T2) and a power supply connecting electrode (20), and the driving transistor (T2) comprises a driving active layer (22); a first end of the power supply connecting electrode (20) is connected with a first power line (51) through a power supply via hole (K1), and a second end of the power supply connecting electrode (20) is connected with a first area of the driving active layer (22) through an active via hole (K2); the adjacent sub-pixels in the repeating units adjacent in the pixel row direction and the pixel column direction share the power supply via hole (K1).

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, display devices using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, comprising multiple repeating units, at least one repeating unit comprising multiple sub-pixels forming at least two pixel rows and at least two pixel columns, at least one sub-pixel comprising a pixel driving circuit, the pixel driving circuit being connected to a first power line, the first power line being configured to provide a first power signal to the pixel driving circuit; the pixel driving circuit comprising at least a driving transistor and a power connection electrode, the driving transistor comprising at least a driving active layer; in at least one sub-pixel, a first end of the power connection electrode is connected to the first power line through a power via, and a second end of the power connection electrode is connected to a first region of the driving active layer through an active via; two adjacent sub-pixels in two adjacent repeating units in the pixel row direction share the power via, and two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the power via.

[0006] In an exemplary embodiment, the first regions of the driving active layers of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction are connected to each other.

[0007] In an exemplary embodiment, the driving active layers of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction are an interconnected integral structure, and the driving active layer of the integral structure has a groove, and the openings of the adjacent grooves in at least one repeating unit are arranged opposite to each other, and the groove has a groove width and a groove depth, the groove width is smaller than the groove depth, the groove width is the dimension in the pixel column direction, and the groove depth is the dimension in the pixel row direction.

[0008] In an exemplary embodiment, first ends of the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are connected to each other, and two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the power connection electrode.

[0009] In an exemplary embodiment, the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are an integrated structure connected to each other.

[0010] In an exemplary embodiment, the pixel driving circuit further includes an active connection electrode, a first end of the active connection electrode being connected to the first area of ​​the driving active layer, and the power connection electrode being connected to the first power line and the second end of the active connection electrode at the same time through a switching via hole, the switching via hole including a shallow half hole and a deep half hole, the shallow half hole being an active via hole exposing the second end of the active connection electrode, and the deep half hole being a power via hole exposing the first power line.

[0011] In an exemplary embodiment, the active connection electrode and the driving active layer are an integral structure connected to each other.

[0012] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the pixel row direction share the transfer via hole, and two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the transfer via hole.

[0013] In an exemplary embodiment, adjacent sub-pixels in the repeating units adjacent in the pixel row direction and the pixel column direction share the transfer via hole.

[0014] In an exemplary embodiment, the second ends of the active connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are connected to each other, and the second ends of the active connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the active connection electrode.

[0015] In an exemplary embodiment, the active connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are connected to each other in an integrated structure.

[0016] In an exemplary embodiment, the first regions of the second active layers of adjacent sub-pixels in adjacent repeating units in the pixel row direction and the pixel column direction are connected to each other through the active connection electrode.

[0017] In an exemplary embodiment, adjacent sub-pixels in the repeating units adjacent in the pixel row direction and the pixel column direction share the power connection electrode.

[0018] In an exemplary embodiment, the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are interconnected as an integrated structure, and the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction are interconnected as an integrated structure.

[0019] In an exemplary embodiment, at least one repeating unit includes two first power lines, four data signal lines and one compensation signal line, the compensation signal line is located between adjacent pixel columns, the two first power lines are located on both sides of the repeating unit in the pixel row direction, and along the pixel row direction, the first first power line, the first data signal line, the second data signal line, the compensation signal line, the third data signal line, the fourth data signal line and the second first power line are arranged in sequence, and the driving transistor is arranged between the second data signal line and the compensation signal line or between the compensation signal line and the third data signal line.

[0020] In an exemplary embodiment, in at least one sub-pixel, the pixel driving circuit further includes a first connecting electrode, a second connecting electrode and a storage capacitor, the storage capacitor includes at least a first plate, the first connecting electrode and the second connecting electrode are arranged on both sides of the first plate in the pixel column direction, and are respectively connected to the first plate; in at least one sub-pixel, the width of the first connecting electrode is smaller than the width of the second connecting electrode, and the width is the dimension in the pixel row direction.

[0021] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes a second conductive layer, a semiconductor layer, and a third conductive layer sequentially arranged on a base, the first power line is arranged in the second conductive layer, the driving active layer is arranged in the semiconductor layer, and the power connection electrode is arranged in the third conductive layer.

[0022] In an exemplary embodiment, the widths of the driving active layers in adjacent sub-pixels in the pixel row direction are different, and the widths of the driving active layers in adjacent sub-pixels in the pixel column direction are different, and the width is the minimum dimension of the driving active layer in the pixel column direction.

[0023] In an exemplary embodiment, in the pixel row direction, the first sub-pixel and the second sub-pixel are alternately arranged, and the width of the driving active layer in the first sub-pixel is greater than the width of the driving active layer in the second sub-pixel; or, in the pixel row direction, the third sub-pixel and the fourth sub-pixel are alternately arranged, and the width of the driving active layer in the third sub-pixel is less than the width of the driving active layer in the fourth sub-pixel.

[0024] In an exemplary embodiment, in the pixel column direction, the first sub-pixel and the third sub-pixel are alternately arranged, and the width of the driving active layer in the first sub-pixel is greater than the width of the driving active layer in the third sub-pixel; or, in the pixel column direction, the second sub-pixel and the fourth sub-pixel are alternately arranged, and the width of the driving active layer in the second sub-pixel is less than the width of the driving active layer in the fourth sub-pixel.

[0025] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0026] In yet another aspect, the present disclosure further provides a method for preparing a display substrate, wherein the display substrate includes a plurality of repeating units, at least one repeating unit including a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns; the method comprising:

[0027] A pixel driving circuit is formed in at least one sub-pixel, and the pixel driving circuit is connected to a first power line, and the first power line is configured to provide a first power signal to the pixel driving circuit; the pixel driving circuit includes at least a driving transistor and a power connection electrode, and the driving transistor includes at least a driving active layer; in at least one sub-pixel, a first end of the power connection electrode is connected to the first power line through a power via, and a second end of the power connection electrode is connected to the first area of ​​the driving active layer through an active via; two adjacent sub-pixels in two adjacent repeating units in the pixel row direction share the power via, and two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the power via.

[0028] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0030] FIG1 is a schematic structural diagram of a display device;

[0031] FIG2 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0032] FIG3 is an equivalent circuit diagram of a pixel driving circuit in a repeating unit according to an exemplary embodiment of the present disclosure;

[0033] FIG4 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure;

[0034] FIG5 is a schematic diagram of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0035] 6A and 6B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0036] 7A and 7B are schematic diagrams of a display substrate after a semiconductor layer pattern is formed according to the present disclosure;

[0037] FIG8 is a schematic diagram of a display substrate after forming a second insulating layer pattern according to the present disclosure;

[0038] 9A and 9B are schematic diagrams of a display substrate after a third conductive layer pattern is formed according to the present disclosure;

[0039] FIG9C is a cross-sectional view taken along line AA in FIG9A ;

[0040] 9D to 9F are cross-sectional views taken along line BB in FIG. 9A ;

[0041] FIG10 is a schematic diagram of a display substrate after forming a third insulating layer and a planar layer pattern according to the present disclosure;

[0042] 11A and 11B are schematic diagrams of a display substrate after a fourth conductive layer pattern is formed thereon according to the present disclosure;

[0043] FIG12 is a schematic diagram of a display substrate according to the present disclosure after a pixel definition layer pattern is formed;

[0044] FIG13 is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure;

[0045] 14A and 14B are schematic diagrams of another display substrate after semiconductor layer patterns are formed according to the present disclosure;

[0046] FIG15 is a schematic diagram of another display substrate after forming a second insulating layer pattern according to the present disclosure;

[0047] 16A and 16B are schematic diagrams of another display substrate after forming a third conductive layer pattern according to the present disclosure;

[0048] FIG17 is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure;

[0049] 18A and 18B are schematic diagrams of another display substrate after a semiconductor layer pattern is formed according to the present disclosure;

[0050] FIG19 is a schematic diagram of another display substrate after forming a second insulating layer pattern according to the present disclosure;

[0051] 20A and 20B are schematic diagrams of another display substrate after forming a third conductive layer pattern according to the present disclosure.

[0052] Description of the accompanying drawings:

[0053] 10—substrate; 11—first connecting electrode; 12—second connecting electrode;

[0054] 13—third connecting electrode; 14—fourth connecting electrode; 15—fifth connecting electrode;

[0055] 16—sixth connecting electrode; 17—seventh connecting electrode; 18—eighth connecting electrode;

[0056] 20—power connection electrode; 21—first active layer; 22—second active layer;

[0057] 23—third active layer; 24—active connection electrode; 30—scanning signal line;

[0058] 31—first gate electrode; 32—second gate electrode; 33—third gate electrode;

[0059] 51—first power line; 52—data signal line; 53—compensation signal line;

[0060] 60—storage capacitor; 61—first plate; 62—second plate;

[0061] 63—first electrode; 64—anode connection electrode; 71—first insulating layer;

[0062] 72—second insulating layer; 81—first connecting block; 82—second connecting block;

[0063] 91—depression; 92—groove; 100—repeating unit. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other in any way.

[0065] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0066] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0067] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0068] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0069] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0070] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0071] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0072] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0073] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0074] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0075] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0076] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is respectively connected to the data driver and the scan driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line and a corresponding scan signal line. i and j may be natural numbers. At least one sub-pixel Pxij may include at least a circuit unit and a display unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal line and the data signal line. The display unit may include at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the circuit unit. Sub-pixel Pxij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and the j-th data signal line. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next level circuit under the control of a clock signal, where m can be a natural number. In an exemplary embodiment, the pixel array can be provided on a display substrate.

[0077] An exemplary embodiment of the present disclosure provides a display substrate, comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, at least one sub-pixel comprising a pixel driving circuit, the pixel driving circuit being connected to a first power line, the first power line being configured to provide a first power signal to the pixel driving circuit; the pixel driving circuit comprising at least a driving transistor and a power connection electrode, the driving transistor comprising at least a driving active layer; in at least one sub-pixel, a first end of the power connection electrode is connected to the first power line via a power via, and a second end of the power connection electrode is connected to a first region of the driving active layer via an active via; two adjacent sub-pixels in two adjacent repeating units in the pixel row direction share the power via, and two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the power via.

[0078] In an exemplary embodiment, the first regions of the driving active layers of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction are connected to each other.

[0079] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the active via hole.

[0080] In an exemplary embodiment, the pixel driving circuit further includes an active connection electrode, a first end of the active connection electrode being connected to the first area of ​​the driving active layer, and the power connection electrode being connected to the first power line and the second end of the active connection electrode at the same time through a switching via hole, the switching via hole including a shallow half hole and a deep half hole, the shallow half hole being an active via hole exposing the second end of the active connection electrode, and the deep half hole being a power via hole exposing the first power line.

[0081] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the pixel row direction share the transfer via hole, and two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the transfer via hole.

[0082] In an exemplary embodiment, the first ends of the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are connected to each other, and the first ends of the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction are connected to each other.

[0083] In an exemplary embodiment, the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are interconnected as an integrated structure, and the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction are interconnected as an integrated structure.

[0084] In an exemplary embodiment, the two adjacent sub-pixels in the two adjacent repeating units in the pixel row direction refer to the two adjacent repeating units in the pixel row direction, one of which includes an A sub-pixel and the other includes a B sub-pixel, and the A sub-pixel and the B sub-pixel are adjacent in the pixel row direction. The two adjacent sub-pixels in the two adjacent repeating units in the pixel column direction refer to the two adjacent repeating units in the pixel column direction, one of which includes a C sub-pixel and the other includes a D sub-pixel, and the C sub-pixel and the D sub-pixel are adjacent in the pixel column direction.

[0085] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0086] Figure 2 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 2, in an exemplary embodiment, the display substrate may include multiple repeating units 100 in a direction parallel to the display substrate. At least one repeating unit 100 may include multiple sub-pixels forming at least two pixel rows and at least two pixel columns. In an exemplary embodiment, a repeating unit is the basic unit that makes up the display substrate. The display substrate is formed by repeating and continuously arranging the repeating units along at least one direction. In other words, the display substrate is composed of multiple repeating units.

[0087] In an exemplary embodiment, a repeating unit 100 may include four sub-pixels, and the four sub-pixels may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, a third sub-pixel P3 that emits a third color light, and a fourth sub-pixel P4 that emits a fourth color light. The four sub-pixels may be arranged in a square manner, which can effectively increase the aperture ratio and the area of ​​the light-transmitting region.

[0088] In an exemplary embodiment, in at least one repeating unit 100, the second subpixel P2 may be arranged on one side of the first subpixel P1 in the first direction X, the third subpixel P3 may be arranged on one side of the first subpixel P1 in the second direction Y, and the fourth subpixel P4 may be arranged on one side of the third subpixel P3 in the first direction X. The plurality of subpixels arranged sequentially along the first direction X may be referred to as a pixel row, and the plurality of subpixels arranged sequentially along the second direction Y may be referred to as a pixel column. The plurality of pixel rows and the plurality of pixel columns constitute an array-arranged pixel array, and the first direction X intersects the second direction Y.

[0089] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, the third subpixel P3 may be a white subpixel (W) that emits white light, and the fourth subpixel P4 may be a green subpixel (G) that emits green light. In some possible embodiments, the arrangement of the RBWGs may be adjusted according to actual needs and is not specifically limited in this disclosure.

[0090] In one exemplary embodiment, the display substrate may include at least a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate, in a direction perpendicular to the display substrate. In at least one repeating unit, the driving circuit layer may include multiple circuit units, each of which may include at least a pixel driving circuit. The pixel driving circuits are connected to scan signal lines and data signal lines, respectively. The pixel driving circuits are configured to receive data voltages transmitted by the data signal lines under the control of the scan signal lines and output a corresponding current to the light-emitting device. The light-emitting structure layer may include multiple light-emitting units, each of which may include at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the circuit unit for the sub-pixel in which it is located. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0091] In another exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on a base, a color filter structure layer disposed on a side of the driving circuit layer remote from the base, and a light-emitting structure layer disposed on a side of the color filter structure layer remote from the base. In at least one repeating unit, the color filter structure layer may include multiple color filter units, each of which may include at least a color filter layer configured to cause corresponding sub-pixels to emit light of a desired color.

[0092] In exemplary embodiments, the circuit unit referred to in this disclosure refers to an area divided by pixel driver circuits. The color filter unit referred to in this disclosure refers to an area divided by color filter layers. The light-emitting unit referred to in this disclosure refers to an area divided by light-emitting devices. The orthographic projections of the circuit unit, the color filter layer, and the light-emitting unit on the substrate may correspond or may not correspond.

[0093] In the exemplary embodiment of the present disclosure, the positions of the circuit unit's orthographic projection on the substrate, the color filter layer's orthographic projection on the substrate, and the light-emitting unit's orthographic projection on the substrate are basically corresponding. The circuit unit, the color filter unit, and the light-emitting unit constitute sub-pixels. Therefore, in the following content, sub-pixels are uniformly used to refer to the circuit unit, the color filter unit, and the light-emitting unit.

[0094] Figure 3 is an equivalent circuit diagram of a pixel driving circuit in a repeating unit according to an exemplary embodiment of the present disclosure. As shown in Figure 3, at least one repeating unit may include four pixel driving circuits, which may be arranged in a square and may have a 3T1C structure.

[0095] In an exemplary embodiment, at least one pixel driving circuit may include three transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and a storage capacitor C, and the pixel driving circuit is respectively connected to the scanning signal line 30, the first power line 51, the data signal line 52, and the compensation signal line 53.

[0096] In an exemplary embodiment, each pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first end of the storage capacitor C, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second end of the storage capacitor C, respectively.

[0097] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , a second end of the storage capacitor C is connected to the second node N2 , and the storage capacitor C is used to store the potential of the gate electrode of the second transistor T2 .

[0098] In an exemplary embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor.

[0099] In the exemplary embodiment, a gate electrode of the first transistor T1 is connected to the scan signal line 30, a first electrode of the first transistor T1 is connected to the data signal line 52, and a second electrode of the first transistor T1 is connected to the first node N1. When a turn-on signal is applied to the scan signal line 30, the first transistor T1 inputs a data signal of the data signal line 52 to the gate electrode of the second transistor T2.

[0100] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the first node N1, a first electrode of the second transistor T2 is connected to the first power line 51, and a second electrode of the second transistor T2 is connected to the second node N2. The second transistor T2 generates a corresponding current at its second electrode under the control of the data signal received at its gate electrode.

[0101] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the scan signal line 30, a first electrode of the third transistor T3 is connected to the compensation signal line 53, and a second electrode of the third transistor T3 is connected to the second node N2. When a turn-on signal is applied to the scan signal line 30, the third transistor T3 extracts the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth.

[0102] In an exemplary embodiment, in the pixel driving circuit of at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 30 .

[0103] In an exemplary embodiment, in the plurality of pixel driving circuits of at least one pixel row, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 are connected to the same scan signal line 30 .

[0104] In an exemplary embodiment, in the plurality of pixel driving circuits of at least one repeating unit, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 are connected to the same scan signal line 30 .

[0105] In an exemplary embodiment, the light-emitting device EL may be an OLED, including a stacked first electrode, an organic light-emitting layer, and a second electrode, or a QLED, including a stacked first electrode, a quantum dot light-emitting layer, and a second electrode. The first electrode of the light-emitting device EL is connected to the second node N2, and the second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL emits light of a corresponding brightness in response to the current flowing through the second electrode of the second transistor T2. In an exemplary embodiment, the first electrode may be an anode, and the second electrode may be a cathode; alternatively, the first electrode may be a cathode, and the second electrode may be an anode.

[0106] In an exemplary embodiment, the signal of the first power line 51 is a continuously provided high level signal, and the signal of the second power line VSS is a continuously provided low level signal.

[0107] In an exemplary embodiment, the first to third transistors T1 to T3 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first to third transistors T1 to T3 may include P-type transistors and N-type transistors.

[0108] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, can leverage the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0109] FIG4 is a schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating a structure of four repeating units (sixteen subpixels) in a bottom-emission display substrate. In this exemplary embodiment, the four repeating units may include a first repeating unit Q1, a second repeating unit Q2, a third repeating unit Q3, and a fourth repeating unit Q4. The second repeating unit Q2 may be disposed on one side of the first repeating unit Q1 in the first direction (X), the third repeating unit Q3 may be disposed on one side of the first repeating unit Q1 in the second direction (Y), and the fourth repeating unit Q4 may be disposed on one side of the third repeating unit Q3 in the first direction (X). At least one repeating unit may include four subpixels forming two pixel rows and two pixel columns. The four subpixels may include a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4. The second subpixel P2 may be disposed on one side of the first subpixel P1 in the first direction (X), the third subpixel P3 may be disposed on one side of the first subpixel P1 in the second direction (Y), and the fourth subpixel P4 may be disposed on one side of the third subpixel P3 in the first direction (X). The first direction X and the second direction Y intersect, and a plurality of sub-pixels arranged sequentially along the first direction X can be referred to as a pixel row, and a plurality of sub-pixels arranged sequentially along the second direction Y can be referred to as a pixel column. The plurality of pixel rows and the plurality of pixel columns constitute an array-arranged pixel array.

[0110] In an exemplary embodiment, at least one repeating unit may include a scan signal line 30, two first power lines 51, four data signal lines 52 and a compensation signal line 53, and the above signal lines are respectively connected to the pixel driving circuits in the corresponding sub-pixels, the scan signal line 30 is configured to provide a scan signal to the pixel driving circuit, the first power line 51 is configured to provide a first power signal to the pixel driving circuit, the data signal line 52 is configured to provide a data signal to the pixel driving circuit, and the compensation signal line 53 is configured to provide a compensation signal to the pixel driving circuit.

[0111] In an exemplary embodiment, the scan signal line 30 may be in the form of a line with its main portion extending along the first direction X (pixel row direction), and the first power line 51, the data signal line 52, and the compensation signal line 53 may be in the form of a line with its main portion extending along the second direction Y (pixel column direction). In an exemplary embodiment, the scan signal line 30 may be arranged between adjacent pixel rows, for example, in the middle of the repeating unit in the second direction Y; one compensation signal line 53 may be located between adjacent pixel columns, for example, in the middle of the repeating unit in the first direction X; two first power lines 51 may be located on either side of the repeating unit in the first direction X; four data signal lines 52 and the compensation signal line 53 may be located between two adjacent first power lines 51; two of the four data signal lines 52 may be located on the side of one first power line 51 close to the compensation signal line 53; and the other two of the four data signal lines 52 may be located on the side of another first power line 51 close to the compensation signal line 53; and the storage capacitor 60 may be located between the data signal lines 52 and the compensation signal line 53. In this way, a scanning signal line 30 extending along the first direction X defines two pixel rows, and a compensation signal line 53 extending along the second direction Y can define two pixel columns, forming a repeating unit of a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3 and a fourth sub-pixel P4.

[0112] In an exemplary embodiment, each sub-pixel includes a pixel driving circuit, which may include a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor 60. Each transistor may include a gate electrode, an active layer, a first electrode and a second electrode. The storage capacitor 60 may include a first plate and a second plate.

[0113] In an exemplary embodiment, a first electrode of the first transistor T1 is connected to the data signal line 52, a second electrode of the first transistor T1 is respectively connected to the gate electrode of the second transistor T2 and the second plate of the storage capacitor 60, a first electrode of the second transistor T2 is connected to the first power line 51, a first electrode of the third transistor T3 is connected to the compensation signal line 53, and a second electrode of the third transistor T3 is respectively connected to the second electrode of the second transistor T2 and the first plate of the storage capacitor 60.

[0114] In an exemplary embodiment, the pixel driving circuit further includes a power connection electrode 20, the second transistor T2 serving as a driving transistor includes at least a second active layer 22 serving as a driving active layer, and in at least one sub-pixel, the first power line 51 is connected to the first region of the second active layer 22 through the power connection electrode 20.

[0115] In an exemplary embodiment, the power connection electrode 20 may be in the shape of a strip extending along the first direction X. In at least one sub-pixel, a first end of the power connection electrode 20 is connected to the first power line 51 through a power via K1, and a second end of the power connection electrode 20 is connected to the first region of the second active layer 22 through an active via K2.

[0116] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the first direction X (pixel row direction) share the same power via K1, and two adjacent sub-pixels in two adjacent repeating units in the second direction Y (pixel column direction) share the same power via K1.

[0117] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the first direction X refer to: in a first repeating unit Q1 and a second repeating unit Q2 adjacent in the first direction X, the first repeating unit Q1 includes a fourth sub-pixel, the second repeating unit Q2 includes a third sub-pixel, and the fourth sub-pixel of the first repeating unit Q1 and the third sub-pixel of the second repeating unit Q2 are adjacent in the first direction X. Two adjacent sub-pixels in two adjacent repeating units in the second direction Y refer to: in a first repeating unit Q1 and a third repeating unit Q3 adjacent in the second direction Y, the first repeating unit Q1 includes a fourth sub-pixel, the third repeating unit Q3 includes a second sub-pixel, and the fourth sub-pixel of the first repeating unit Q1 and the second sub-pixel of the third repeating unit Q3 are adjacent in the second direction Y.

[0118] In an exemplary embodiment, adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y share the same power via K1 .

[0119] In an exemplary embodiment, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the fourth subpixel P4 of the first repeating unit Q1 and the third subpixel P3 of the second repeating unit Q2 are two adjacent subpixels, for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the second subpixel P2 of the third repeating unit Q3 and the first subpixel P1 of the fourth repeating unit Q4 are two adjacent subpixels, for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the fourth subpixel P4 of the first repeating unit Q1 and the second subpixel P2 of the third repeating unit Q3 are two adjacent subpixels, and for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the third subpixel P3 of the second repeating unit Q2 and the first subpixel P1 of the fourth repeating unit Q4 are two adjacent subpixels. Therefore, the fourth subpixel P4 of the first repeating unit Q1, the third subpixel P3 of the second repeating unit Q2, the second subpixel P2 of the third repeating unit Q3, and the first subpixel P1 of the fourth repeating unit Q4 are adjacent subpixels in the repeating units adjacent in the first direction X and the second direction Y, and the above subpixels share the same power via K1.

[0120] In an exemplary embodiment, the first regions of the second active layers 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y are connected to each other. For example, for the first repeating unit Q1 and the third repeating unit Q3 adjacent to each other in the second direction Y, the first regions of the two second active layers 22 in the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 are connected to each other, and the first regions of the two second active layers 22 in the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q3 are connected to each other. For another example, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent to each other in the second direction Y, the first regions of the two second active layers 22 in the third sub-pixel P3 of the second repeating unit Q2 and the first sub-pixel P1 of the fourth repeating unit Q4 are connected to each other, and the first regions of the two second active layers 22 in the fourth sub-pixel P4 of the second repeating unit Q2 and the second sub-pixel P2 of the fourth repeating unit Q4 are connected to each other.

[0121] In an exemplary embodiment, the second active layers 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y are an integral structure connected to each other.

[0122] In an exemplary embodiment, two adjacent subpixels in two adjacent repeating units in the second direction Y share the same active via K2. For example, the third subpixel P3 of the first repeating unit Q1 and the first subpixel P1 of the third repeating unit Q3 share the same active via K2. In another example, the fourth subpixel P4 of the first repeating unit Q1 and the second subpixel P2 of the third repeating unit Q2 share the same active via K2.

[0123] In an exemplary embodiment, the first ends of the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are connected to each other. For example, the first ends of the two power connection electrodes 20 in the second sub-pixel P2 of the first repeating unit Q1 and the first sub-pixel P1 of the second repeating unit Q2 are connected to each other. For another example, the first ends of the two power connection electrodes 20 in the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 are connected to each other.

[0124] In an exemplary embodiment, the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are an integrated structure connected to each other.

[0125] In an exemplary embodiment, two adjacent subpixels in two adjacent repeating units in the second direction Y share the same power connection electrode 20. For example, the third subpixel P3 of the first repeating unit Q1 and the first subpixel P1 of the third repeating unit Q3 share the same power connection electrode 20. For another example, the fourth subpixel P4 of the first repeating unit Q1 and the second subpixel P2 of the third repeating unit Q2 share the same power connection electrode 20.

[0126] In an exemplary embodiment, the widths of the second active layer 22 in adjacent sub-pixels in the first direction X are different, and the widths of the second active layer 22 in adjacent sub-pixels in the second direction Y are different, and the width may be the minimum dimension of the second active layer 22 in the second direction Y.

[0127] In an exemplary embodiment, in the first direction X, the first subpixel P1 and the second subpixel P2 are alternately arranged, and the width of the second active layer 22 in the first subpixel P1 is greater than the width of the second active layer 22 in the second subpixel P2; or, in the first direction X, the third subpixel P3 and the fourth subpixel P4 are alternately arranged, and the width of the second active layer 22 in the third subpixel P3 is less than the width of the second active layer 22 in the fourth subpixel P4.

[0128] In an exemplary embodiment, in the second direction Y, the first subpixel P1 and the third subpixel P3 are alternately arranged, and the width of the second active layer 22 in the first subpixel P1 is greater than the width of the second active layer 22 in the third subpixel P3; or, in the second direction Y, the second subpixel P2 and the fourth subpixel P4 are alternately arranged, and the width of the second active layer 22 in the second subpixel P2 is smaller than the width of the second active layer 22 in the fourth subpixel P4.

[0129] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a first conductive layer, a second conductive layer, a semiconductor layer, and a third conductive layer sequentially arranged on a base, the first electrode plate of the storage capacitor 60 may be arranged in the first conductive layer, the first power line 51, the data signal line 52, and the compensation signal line 53 may be arranged in the second conductive layer, the second electrode plate of the storage capacitor 60 and the second active layer 22 may be arranged in the semiconductor layer, and the power connection electrode 20 and the scan signal line 30 may be arranged in the third conductive layer.

[0130] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0131] In an exemplary embodiment, taking four repeating units (a first repeating unit Q1 , a second repeating unit Q2 , a third repeating unit Q3 , and a fourth repeating unit Q4 ) as an example, this embodiment shows that the preparation process of the substrate may include the following operations.

[0132] (11) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern includes: depositing a first conductive film on a substrate, patterning the first conductive film through a patterning process, and forming the first conductive layer pattern on the substrate, as shown in FIG5 .

[0133] In an exemplary embodiment, the first conductive layer of each sub-pixel in each repeating unit may include at least a first connection electrode 11 , a second connection electrode 12 , and a first plate 61 of a storage capacitor.

[0134] In an exemplary embodiment, the shape of the first electrode plate 61 can be rectangular, and the corners of the rectangle can be chamfered. The first electrode plate 61 can serve as a transparent electrode plate of a transparent storage capacitor. The first electrode plate 61 is configured to form a transparent storage capacitor with the subsequently formed second electrode plate.

[0135] In an exemplary embodiment, the first connection electrode 11 and the second connection electrode 12 may be located on both sides of the first electrode plate 61 in the second direction Y, respectively.

[0136] In an exemplary embodiment, in the first subpixel P1 and the second subpixel P2, the first connection electrode 11 may be disposed on a side of the first electrode plate 61 opposite to the direction of extension of the second direction Y, and the second connection electrode 12 may be disposed on a side of the first electrode plate 61 in the direction of extension of the second direction Y. In the third subpixel P3 and the fourth subpixel P4, the first connection electrode 11 may be disposed on a side of the first electrode plate 61 in the direction of extension of the second direction Y, and the second connection electrode 12 may be disposed on a side of the first electrode plate 61 opposite to the direction of extension of the second direction Y.

[0137] In an exemplary embodiment, the shape of the first connection electrode 11 can be a strip shape with a main portion extending along the second direction Y, the first end of the first connection electrode 11 is connected to the first electrode plate 61, and the second end of the first connection electrode 11 extends in a direction away from the second connection electrode 12, and the first connection electrode 11 is configured to be connected to a third connection electrode formed subsequently.

[0138] In an exemplary embodiment, the shape of the second connection electrode 12 can be a strip shape with a main portion extending along the second direction Y, the first end of the second connection electrode 12 is connected to the first electrode plate 61, and the second end of the second connection electrode 12 extends in a direction away from the first connection electrode 11, and the second connection electrode 12 is configured to be connected to a fourth connection electrode formed subsequently.

[0139] In an exemplary embodiment, in the first pixel column, an edge of the first connection electrode 11 on a side close to the second pixel column may be substantially flush with an edge of the first electrode plate 61 on a side close to the second pixel column. In the second pixel column, an edge of the first connection electrode 11 on a side close to the first pixel column may be substantially flush with an edge of the first electrode plate 61 on a side close to the first pixel column.

[0140] In an exemplary embodiment, the first connection electrode 11 , the second connection electrode 12 , and the first electrode plate 61 of each sub-pixel may be an integrated structure connected to each other.

[0141] In an exemplary embodiment, in at least one sub-pixel, the width of the first connection electrode 11 may be smaller than the width of the second connection electrode 12 , and the width may be a dimension in the first direction X.

[0142] In an exemplary embodiment, in at least one sub-pixel, the first conductive layer pattern may further include a first connection block 81. The first connection block 81 may be block-shaped (e.g., rectangular) and may be disposed at a corner where the first connection electrode 11 connects to the first electrode plate 61. Two adjacent sides of the first connection block 81 are respectively connected to the first connection electrode 11 and the first electrode plate 61, forming a first corner structure. For example, the first sub-pixel may include the first connection block 81. For another example, the second sub-pixel may include the first connection block 81. For another example, the third sub-pixel may include the first connection block 81.

[0143] In an exemplary embodiment, in at least one sub-pixel, the first corner structure may have a first convex angle β1, and the first convex angle β1 may be a right angle.

[0144] In an exemplary embodiment, in at least one sub-pixel, the first conductive layer pattern may further include a second connection block 82. The second connection block 82 may be block-shaped and may be disposed at a corner where the second connection electrode 12 connects to the first electrode plate 61. Two adjacent sides of the second connection block 82 are respectively connected to the second connection electrode 12 and the first electrode plate 61, forming a second corner structure. For example, the first sub-pixel may include the second connection block 82.

[0145] In an exemplary embodiment, the second corner structure may have a second convex angle β2, and the second convex angle β2 may be an obtuse angle.

[0146] In an exemplary embodiment, in at least one sub-pixel, the first electrode 61 may be provided with a recess 91. The shape of the recess 91 may be block-shaped (such as rectangular) and may be provided on a side of the first electrode 61 away from the second connecting electrode 12. The recess 91 may have a recess width and a recess depth. The recess width may be greater than the recess depth. The recess width may be the dimension in the first direction X, and the recess depth may be the dimension in the second direction Y.

[0147] In an exemplary embodiment, in at least one repeating unit, the positions of the respective patterns in the first conductive layer in the first subpixel P1 and the positions of the respective patterns in the first conductive layer in the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line, the positions of the respective patterns in the first conductive layer in the second subpixel P2 and the positions of the respective patterns in the first conductive layer in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to the horizontal reference line, the positions of the respective patterns in the first conductive layer in the first subpixel P1 and the positions of the respective patterns in the first conductive layer in the second subpixel P2 may be substantially mirror-symmetrical with respect to a vertical reference line, and the positions of the respective patterns in the first conductive layer in the third subpixel P3 and the positions of the respective patterns in the first conductive layer in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a vertical reference line. The horizontal reference line may be a straight line extending along the first direction X and bisecting the repeating unit in the second direction Y, and the vertical reference line may be a straight line extending along the second direction Y and bisecting the repeating unit in the first direction X.

[0148] In an exemplary embodiment, the first conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0149] (12) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the second conductive film through a patterning process to form a second conductive layer, as shown in FIG6A and FIG6B , where FIG6B is a schematic diagram of the second conductive layer in FIG6A . In an exemplary embodiment, the second conductive layer may be referred to as a shield layer.

[0150] In an exemplary embodiment, the second conductive layer of each sub-pixel in each repeating unit may include at least a third connection electrode 13 and a fourth connection electrode 14 .

[0151] In an exemplary embodiment, the third connection electrode 13 may be block-shaped (e.g., rectangular) and may be located on a side of the first electrode plate 61 away from the second connection electrode 12. The orthographic projection of the third connection electrode 13 on the substrate at least partially overlaps the orthographic projection of the first connection electrode 11 on the substrate, and the third connection electrode 13 directly overlaps the first connection electrode 11. In an exemplary embodiment, the third connection electrode 13 is configured to connect to a subsequently formed fifth connection electrode and to shield the second transistor from light, thereby reducing the intensity of light incident on the second transistor and lowering leakage current of the second transistor, thereby alleviating the impact of light on the characteristics of the second transistor.

[0152] In an exemplary embodiment, the fourth connection electrode 14 can be in a block shape (such as a rectangle) and can be located on the side of the first electrode plate 61 away from the first connection electrode 11. The orthographic projection of the fourth connection electrode 14 on the substrate at least partially overlaps with the orthographic projection of the second connection electrode 12 on the substrate, and the fourth connection electrode 14 is directly overlapped with the second connection electrode 12. The fourth connection electrode 14 is configured to be connected to the sixth connection electrode formed subsequently.

[0153] In an exemplary embodiment, in at least one sub-pixel, an area of ​​an orthographic projection of the third connection electrode 13 on the substrate may be larger than an area of ​​an orthographic projection of the fourth connection electrode 14 on the substrate;

[0154] In an exemplary embodiment, in at least one repeating unit, an orthographic projection area of ​​the third connection electrode 13 in the first sub-pixel on the substrate may be larger than an orthographic projection area of ​​the third connection electrode 13 in other sub-pixels on the substrate.

[0155] In an exemplary embodiment, in at least one repeating unit, the orthographic projection areas of the fourth connection electrodes 14 in the respective sub-pixels on the substrate may be substantially equal.

[0156] In an exemplary embodiment, the second conductive layer of each repeating unit in the display substrate may include at least two first power lines 51 , four data signal lines 52 , and one compensation signal line 53 .

[0157] In an exemplary embodiment, the shapes of the first power line 51, the data signal line 52, and the compensation signal line 53 may be straight lines or zigzag lines with the main portion extending along the second direction Y. The compensation signal line 53 may be located between adjacent sub-pixel columns of the repeating unit, for example, in the middle of the repeating unit in the first direction X. The first first power line 51 may be located on a side opposite to the direction in which the repeating unit extends in the first direction X. The second first power line 51 may be located on a side in the direction in which the repeating unit extends in the first direction X. Two of the four data signal lines 52 may be located between the first first power line 51 and the compensation signal line 53. The other two of the four data signal lines 52 may be located between the second first power line 51 and the compensation signal line 53.

[0158] In an exemplary embodiment, the first power supply line 51 and the compensation signal line 53 may define a first pixel column, and the two data signal lines 52 are disposed in the first pixel column. The second first power supply line 51 and the compensation signal line 53 may define a second pixel column, and the two data signal lines 52 are disposed in the second pixel column.

[0159] In an exemplary embodiment, the four data signal lines 52 may include a first data signal line and a second data signal line disposed in a first pixel column, and a third data signal line and a fourth data signal line disposed in a second pixel column. Extending along the first direction X, the first first power line, the first data signal line, the second data signal line, the compensation signal line, the third data signal line, the fourth data signal line, and the second first power line are sequentially arranged. The first electrode 61 may be located between the second data signal line and the compensation signal line 53 or between the compensation signal line 53 and the third data signal line.

[0160] In an exemplary embodiment, in at least one repeating unit, the positions of the two first power lines 51 can be substantially mirror-symmetrical with respect to a vertical reference line, and the positions of the two data signal lines 52 located on the opposite side of the first direction X of the compensation signal line 53 and the positions of the two data signal lines 52 located on the side of the first direction X of the compensation signal line 53 can be substantially mirror-symmetrical with respect to the vertical reference line.

[0161] In an exemplary embodiment, in at least one repeating unit, positions of the third connection electrode 13 and the fourth connection electrode 14 in the first subpixel P1 and the positions of the third connection electrode 13 and the fourth connection electrode 14 in the second subpixel P2 are substantially mirror-symmetrical with respect to a vertical reference line, and positions of the third connection electrode 13 and the fourth connection electrode 14 in the third subpixel P3 and the positions of the third connection electrode 13 and the fourth connection electrode 14 in the fourth subpixel P4 are substantially mirror-symmetrical with respect to the vertical reference line. Positions of the third connection electrode 13 and the fourth connection electrode 14 in the first subpixel P1 and the positions of the third connection electrode 13 and the fourth connection electrode 14 in the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line, and positions of the third connection electrode 13 and the fourth connection electrode 14 in the second subpixel P2 and the positions of the third connection electrode 13 and the fourth connection electrode 14 in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a horizontal reference line.

[0162] In an exemplary embodiment, two adjacent repeating units in the first direction X can share the same first power line 51. For example, the first repeating unit Q1 and the second repeating unit Q2 can share the same first power line 51. In another example, the third repeating unit Q3 and the fourth repeating unit Q4 can share the same first power line 51. By having adjacent repeating units share the same first power line, the present disclosure can effectively reduce the number of signal lines and vias, thereby reducing the area occupied by the pixel driver circuit, increasing the pixel aperture ratio, and improving display resolution.

[0163] In an exemplary embodiment, the first power line 51 , the data signal line 52 and the compensation signal line 53 may be zigzag lines of unequal widths. Using zigzag lines of varying widths not only facilitates the layout of the pixel structure but also reduces parasitic capacitance.

[0164] (13) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the first conductive layer and the second conductive layer, and a semiconductor layer disposed on the first insulating layer, as shown in FIG7A and FIG7B , where FIG7B is a schematic diagram of the semiconductor layer in FIG7A .

[0165] In an exemplary embodiment, the semiconductor layer of each sub-pixel in each repeating unit may include at least a first active layer 21, a second active layer 22, a third active layer 23, and a second electrode 62 of a storage capacitor. The first active layer 21 may serve as an active layer of the first transistor T1, the second active layer 22 may serve as an active layer of the second transistor T2, and the third active layer 23 may serve as an active layer of the third transistor T3. The second electrode 62 may serve as another transparent electrode of a transparent storage capacitor. The second electrode 62 is configured to form a transparent storage capacitor with the first electrode 61.

[0166] In an exemplary embodiment, for the first subpixel P1 and the second subpixel P2, the first active layer 21 and the third active layer 23 can be arranged on one side of the second direction Y extension direction of the first electrode 61 of the subpixel, and the second active layer 22 can be arranged on the side opposite to the second direction Y extension direction of the first electrode 61 of the subpixel.

[0167] In an exemplary embodiment, for the first subpixel P1, the first active layer 21 may be disposed on a side of the subpixel away from the second subpixel P2, and the third active layer 23 may be disposed on a side of the subpixel closer to the second subpixel P2. For the second subpixel P2, the first active layer 21 may be disposed on a side of the subpixel away from the first subpixel P1, and the third active layer 23 may be disposed on a side of the subpixel closer to the first subpixel P1.

[0168] In an exemplary embodiment, for the third subpixel P3 and the fourth subpixel P4, the first active layer 21 and the third active layer 23 can be arranged on the side opposite to the second direction Y extension direction of the first electrode 61 of the subpixel, and the second active layer 22 can be arranged on the side of the second direction Y extension direction of the first electrode 61 of the subpixel.

[0169] In an exemplary embodiment, for the third subpixel P3, the first active layer 21 may be disposed on a side of the subpixel away from the fourth subpixel P4, and the third active layer 23 may be disposed on a side of the subpixel close to the fourth subpixel P4. For the fourth subpixel P4, the first active layer 21 may be disposed on a side of the subpixel away from the third subpixel P3, and the third active layer 23 may be disposed on a side of the subpixel close to the third subpixel P3.

[0170] In example embodiments, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.

[0171] In an exemplary embodiment, the orthographic projection of the first region of the first active layer 21 of each subpixel on the substrate at least partially overlaps with the orthographic projection of the corresponding data signal line 52 on the substrate, and the second region of the first active layer 21 is connected to the second electrode 62 .

[0172] In an exemplary embodiment, the orthographic projection of the first area of ​​the second active layer 22 of each sub-pixel on the substrate does not overlap with the orthographic projection of the third connection electrode 13 of the sub-pixel on the substrate, and the orthographic projection of the second area and the channel region of the second active layer 22 on the substrate at least partially overlaps with the orthographic projection of the third connection electrode 13 on the substrate, so that the third connection electrode 13 serving as a shielding layer can shield the channel region of the second transistor T2, thereby preventing light from affecting the channel and ensuring the electrical performance of the second transistor T2.

[0173] In an exemplary embodiment, in each sub-pixel, the distance between the first region of the second active layer 22 and the first power line 51 may be smaller than the distance between the second region of the second active layer 22 and the first power line 51, that is, relative to the channel region of the second active layer 22, the first region of the second active layer 22 is closer to the first power line 51.

[0174] In an exemplary embodiment, the first regions of the second active layer 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y may be connected to each other, so that the second transistors of the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y share the first region of the second active layer. For example, for the first repeating unit Q1 and the third repeating unit Q3 adjacent to each other in the second direction Y, the first region of the second active layer 22 of the third sub-pixel P3 in the first repeating unit Q1 and the first region of the second active layer 22 of the first sub-pixel P1 in the third repeating unit Q3 may be connected to each other, and the first region of the second active layer 22 of the fourth sub-pixel P4 in the first repeating unit Q1 and the first region of the second active layer 22 of the second sub-pixel P2 in the third repeating unit Q3 may be connected to each other. For another example, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent to each other in the second direction Y, the first area of ​​the second active layer 22 of the third subpixel P3 in the second repeating unit Q2 and the first area of ​​the second active layer 22 of the first subpixel P1 in the fourth repeating unit Q4 can be connected to each other, and the first area of ​​the second active layer 22 of the fourth subpixel P4 in the second repeating unit Q2 and the first area of ​​the second active layer 22 of the second subpixel P2 in the fourth repeating unit Q4 can be connected to each other.

[0175] In an exemplary embodiment, the second active layer 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y can be an interconnected, integral structure. The integrally structured second active layer 22 includes a groove 92, with the openings of adjacent grooves 92 in at least one repeating unit positioned opposite each other. The groove 92 can have a groove width and a groove depth. The groove width can be smaller than the groove depth. The groove width can be the dimension in the second direction Y, and the groove depth can be the dimension in the first direction X. By arranging the second transistors of two adjacent sub-pixels in two adjacent repeating units in the second direction Y to share the first region of the second active layer, the present disclosure not only effectively reduces the number of vias, reduces the area occupied by the pixel driver circuit, increases the pixel aperture ratio, and improves display resolution, but also simplifies the manufacturing process, reduces production costs, and improves product yield by reducing vias.

[0176] In an exemplary embodiment, the widths of the second active layers in adjacent sub-pixels in the first direction X may be different and the widths of the second active layers in adjacent sub-pixels in the second direction Y may be different, with the width being the minimum dimension of the second active layer in the second direction Y.

[0177] In an exemplary embodiment, a plurality of subpixels having a second active layer with a larger width and a plurality of subpixels having a second active layer with a smaller width may be alternately arranged in the first direction X. For example, the first subpixel P1 and the second subpixel P2 are alternately arranged in the first direction X, and the first width L1 of the second active layer 22 in the first subpixel P1 may be greater than the second width L2 of the second active layer 22 in the second subpixel P2. For another example, the third subpixel P3 and the fourth subpixel P4 are alternately arranged in the first direction X, and the third width L3 of the second active layer 22 in the third subpixel P3 may be smaller than the fourth width L4 of the second active layer 22 in the fourth subpixel P4.

[0178] In an exemplary embodiment, a plurality of subpixels having a second active layer with a larger width and a plurality of subpixels having a second active layer with a smaller width may be alternately arranged in the second direction Y. For example, the first subpixel P1 and the third subpixel P3 are alternately arranged in the second direction Y, and the first width L1 of the second active layer 22 in the first subpixel P1 may be greater than the third width L3 of the second active layer 22 in the third subpixel P3. For another example, the second subpixel P2 and the fourth subpixel P4 are alternately arranged in the second direction Y, and the second width L2 of the second active layer 22 in the second subpixel P2 may be smaller than the fourth width L4 of the second active layer 22 in the fourth subpixel P4.

[0179] In an exemplary embodiment, the widths of the second active layer 22 of the four sub-pixels in at least one repeating unit may be different. For example, the first width L1 of the second active layer 22 in the first sub-pixel P1 may be greater than the fourth width L4 of the second active layer 22 in the fourth sub-pixel P4. For another example, the second width L2 of the second active layer 22 in the second sub-pixel P2 may be greater than the third width L3 of the second active layer 22 in the third sub-pixel P3.

[0180] In an exemplary embodiment, the present disclosure arranges a second active layer with a larger width and a second active layer with a smaller width alternately in the first direction X and the second direction Y, which can not only effectively match the requirements of the single scanning signal line structure, but also effectively increase the uniformity of the four pixel driving circuit layouts in the repeating unit, and effectively increase the uniformity of the four sub-pixel pixel openings in the repeating unit.

[0181] In an exemplary embodiment, the orthographic projection of the first area of ​​the third active layer 23 of each sub-pixel on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 53 on the substrate, and the orthographic projection of the second area of ​​the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the fourth connection electrode 14 of the sub-pixel on the substrate.

[0182] In an exemplary embodiment, in at least one repeating unit, the first region of the third active layer 23 in the first subpixel P1 and the first region of the third active layer 23 in the second subpixel P2 may be connected to each other, and the first region of the third active layer 23 in the third subpixel P3 and the first region of the third active layer 23 in the fourth subpixel P4 may be connected to each other.

[0183] In an exemplary embodiment, the third active layer 23 in the first subpixel P1 and the third active layer 23 in the second subpixel P2 may be interconnected as a single unitary structure, and the third active layer 23 in the third subpixel P3 and the third active layer 23 in the fourth subpixel P4 may be interconnected as a single unitary structure. Thus, the third transistors of two adjacent subpixels in a pixel row share the first region of the third active layer. By arranging for the third transistors of two adjacent subpixels in a pixel row to share the first region of the third active layer, the present disclosure not only effectively reduces the number of vias, reduces the area occupied by the pixel driving circuit, increases the pixel aperture ratio, and improves display resolution, but also simplifies the manufacturing process, reduces production costs, and improves product yield.

[0184] In an exemplary embodiment, the shape of the second electrode plate 62 can be rectangular, the corners of the rectangle can be chamfered, and it can be arranged between the second active layer 22 and the third active layer 23 of the sub-pixel. The orthographic projection of the second electrode plate 62 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 61 on the substrate. The second electrode plate 62 can serve as another transparent electrode plate of the transparent storage capacitor, and the first electrode plate 61 and the second electrode plate 62 form a transparent storage capacitor.

[0185] In an exemplary embodiment, the second electrode plate 62 and the first active layer 21 of each sub-pixel may be an integral structure connected to each other.

[0186] In an exemplary embodiment, in each sub-pixel, the overlapping area of ​​the orthographic projection of the first electrode 61 and the orthographic projection of the second electrode 62 on the substrate may be substantially the same, so that the capacity of the storage capacitor in each sub-pixel is substantially the same.

[0187] In exemplary embodiments, the semiconductor layer may be formed of a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0188] In an exemplary embodiment, in at least one repeating unit, the position of each pattern in the semiconductor layer in the first subpixel P1 and the position of each pattern in the semiconductor layer in the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line, the position of each pattern in the semiconductor layer in the second subpixel P2 and the position of each pattern in the semiconductor layer in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a horizontal reference line, the position of each pattern in the semiconductor layer in the first subpixel P1 and the position of each pattern in the semiconductor layer in the second subpixel P2 may be substantially mirror-symmetrical with respect to a vertical reference line, and the position of each pattern in the semiconductor layer in the third subpixel P3 and the position of each pattern in the semiconductor layer in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a vertical reference line.

[0189] (14) Forming a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film through a patterning process to form a second insulating layer pattern covering the semiconductor layer, wherein a plurality of vias are provided on the second insulating layer, as shown in FIG8 .

[0190] In an exemplary embodiment, the plurality of via holes of each sub-pixel in each repeating unit includes at least a first via hole V1 , a second via hole V2 , a third via hole V3 , a fourth via hole V4 , a fifth via hole V5 , a sixth via hole V6 , and a seventh via hole V7 .

[0191] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer 21 and the data signal line 52 on the substrate. The first via hole V1 is a via hole in a transfer structure, comprising a shallow half-hole and a deep half-hole. The second insulating layer in the shallow half-hole is etched away, exposing the surface of the first region of the first active layer 21. The first and second insulating layers in the deep half-hole are etched away, exposing the surface of the data signal line 52. This allows the via hole in the transfer structure, consisting of the two half-holes, to simultaneously expose the first region of the first active layer 21 and the data signal line 52. The first via hole V1 is configured to allow a subsequently formed seventh connection electrode to be simultaneously connected to the first region of the first active layer 21 and the data signal line 52 through the via hole.

[0192] In the exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the orthographic projection of the first region of the second active layer 22 on the substrate. The second insulating layer within the second via hole V2 is etched away, exposing the surface of the first region of the second active layer 22. The second via hole V2 is configured to connect a subsequently formed power connection electrode to the first region of the second active layer 22 through the via hole. In the exemplary embodiment, the second via hole V2 serves as the active via hole of this embodiment.

[0193] In an exemplary embodiment, because the first regions of the second active layer 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y are interconnected, two adjacent sub-pixels in two adjacent repeating units in the second direction Y can share the same second via hole V2. For example, the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 share the same second via hole V2. In another example, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q2 share the same second via hole V2. By providing that two adjacent sub-pixels in two adjacent repeating units share the same second via hole V2, the present disclosure not only effectively reduces the number of via holes, reduces the area occupied by the pixel driving circuit, increases the pixel aperture ratio, and improves display resolution, but also simplifies the manufacturing process, reduces production costs, and improves product yield.

[0194] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the second region of the second active layer 22 and the third connecting electrode 13 on the substrate. The third via hole V3 is a via hole with a transition structure, including a shallow half-hole and a deep half-hole. The second insulating layer in the shallow half-hole is etched away, exposing the surface of the second region of the second active layer 22. The first and second insulating layers in the deep half-hole are etched away, exposing the surface of the third connecting electrode 13. This transition structure, consisting of the two half-holes, simultaneously exposes the second region of the second active layer 22 and the third connecting electrode 13. The third via hole V3 is configured to allow a subsequently formed fifth connecting electrode to be simultaneously connected to the second region of the second active layer 22 and the third connecting electrode 13 through the via hole.

[0195] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the first region of the third active layer 23 and the compensation signal line 53. The fourth via V4 is a via hole with a transition structure, comprising a shallow half-hole and a deep half-hole. The second insulating layer in the shallow half-hole is etched away, exposing the surface of the first region of the third active layer 23. The first and second insulating layers in the deep half-hole are etched away, exposing the surface of the compensation signal line 53. This transition structure, consisting of the two half-holes, simultaneously exposes the first region of the third active layer 23 and the compensation signal line 53. The fourth via V4 is configured to allow a subsequently formed eighth connecting electrode to be connected to both the first region of the third active layer 23 and the compensation signal line 53 through the via hole.

[0196] In an exemplary embodiment, because the first regions of the third active layer in the first subpixel P1 and the second subpixel P2 in a repeating unit are interconnected, and the first regions of the third active layer in the third subpixel P3 and the fourth subpixel P4 are interconnected, the first subpixel P1 and the second subpixel P2 in the repeating unit can share the same fourth via hole V4, and the third subpixel P3 and the fourth subpixel P4 can share the same fourth via hole V4. By having adjacent subpixels share the same fourth via hole V4, the present disclosure not only effectively reduces the number of via holes, reduces the area occupied by the pixel drive circuit, increases the pixel aperture ratio, and improves display resolution, but also simplifies the manufacturing process, reduces production costs, and improves product yield.

[0197] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the second region of the third active layer 23 and the fourth connecting electrode 14 on the substrate. The fifth via hole V5 is a via hole with a transition structure, including a shallow half-hole and a deep half-hole. The second insulating layer in the shallow half-hole is etched away, exposing the surface of the second region of the third active layer 23. The first and second insulating layers in the deep half-hole are etched away, exposing the surface of the fourth connecting electrode 14. This transition structure, consisting of the two half-holes, simultaneously exposes the second region of the third active layer 23 and the fourth connecting electrode 14. The fifth via hole V5 is configured to allow a subsequently formed sixth connecting electrode to be simultaneously connected to the second region of the third active layer 23 and the fourth connecting electrode 14 through the via hole.

[0198] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second electrode plate 62 on the substrate, the second insulating layer in the sixth via V6 is etched away to expose the surface of the second electrode plate 62, and the sixth via V6 is configured to connect the subsequently formed second gate electrode to the second electrode plate 62 through the via.

[0199] In the exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is within the range of the orthographic projection of the first power line 51 on the substrate. The first insulating layer and the second insulating layer within the seventh via V7 are etched away, exposing the surface of the first power line 51. The seventh via V7 is configured to connect a subsequently formed power connection electrode to the first power line 51 through the via. In the exemplary embodiment, the seventh via V7 serves as the power via of this embodiment.

[0200] In an exemplary embodiment, two adjacent subpixels in two adjacent repeating units in the first direction X share the same seventh via hole V7. For example, the second subpixel P2 of the first repeating unit Q1 and the first subpixel P1 of the second repeating unit Q2 share the same seventh via hole V7. In another example, the fourth subpixel P4 of the first repeating unit Q1 and the third subpixel P3 of the second repeating unit Q2 share the same seventh via hole V7. By providing that two adjacent subpixels in two adjacent repeating units in the first direction X share the same seventh via hole V7, the present disclosure not only effectively reduces the number of via holes, reduces the area occupied by the pixel driver circuit, increases the pixel aperture ratio, and improves display resolution, but also simplifies the manufacturing process, reduces production costs, and improves product yield.

[0201] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the same seventh via hole V7. For example, the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 share the same seventh via hole V7. In another example, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q2 share the same seventh via hole V7. By providing that two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the same seventh via hole V7, the present disclosure not only effectively reduces the number of via holes, reduces the area occupied by the pixel driver circuit, increases the pixel aperture ratio, and improves display resolution, but also simplifies the manufacturing process, reduces production costs, and improves product yield.

[0202] In an exemplary embodiment, adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y share the same seventh via hole V7 , that is, adjacent four sub-pixels in adjacent repeating units share the same seventh via hole V7 . For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the fourth subpixel P4 of the first repeating unit Q1 and the third subpixel P3 of the second repeating unit Q2 are two adjacent subpixels; for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the second subpixel P2 of the third repeating unit Q3 and the first subpixel P1 of the fourth repeating unit Q4 are two adjacent subpixels; for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the fourth subpixel P4 of the first repeating unit Q1 and the second subpixel P2 of the third repeating unit Q3 are two adjacent subpixels; for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the third subpixel P3 of the second repeating unit Q2 and the first subpixel P1 of the fourth repeating unit Q4 are two adjacent subpixels; the fourth subpixel P4 of the first repeating unit Q1, the third subpixel P3 of the second repeating unit Q2, the second subpixel P2 of the third repeating unit Q3, and the first subpixel P1 of the fourth repeating unit Q4 share the same seventh via hole V7. The present disclosure arranges that four adjacent sub-pixels in adjacent repeating units share the same seventh via V7, which can not only effectively reduce the number of vias, but also reduce the occupied area of ​​the pixel driving circuit, increase the pixel aperture ratio, and improve the display resolution. In addition, reducing the vias can simplify the preparation process, reduce production costs, and improve product yield.

[0203] In an exemplary embodiment, during the process of forming the second insulating layer pattern, a dry etching process is used to form a plurality of via holes. Simultaneously, a primary conductive process is performed on the semiconductor layer exposed within the via holes, thereby forming a primary conductive region within the semiconductor layer exposed within the via holes. During the primary conductive process, the edge portion of the semiconductor layer covered by the second insulating layer near the via hole is also conductively conductive, meaning that the primary conductive semiconductor layer extends away from the via hole.

[0204] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film through a patterning process, and forming a third conductive layer pattern on the second insulating layer, as shown in FIG. 9A and FIG. 9B , where FIG. 9B is a schematic diagram of the third conductive layer in FIG. 9A . In an exemplary embodiment, the third conductive layer may be referred to as a gate metal (GT) layer.

[0205] In an exemplary embodiment, the third conductive layer of each sub-pixel in each repeating unit may include at least a fifth connection electrode 15, a sixth connection electrode 16, a seventh connection electrode 17, an eighth connection electrode 18, a power connection electrode 20, a scan signal line 30, a first gate electrode 31, a second gate electrode 32 and a third gate electrode 33.

[0206] In an exemplary embodiment, the shape of the scanning signal line 30 can be a line shape in which the main portion extends along the first direction X, and can be arranged in the middle of the repeating unit in the second direction Y, that is, between the first sub-pixel P1 and the second sub-pixel P2 and the third sub-pixel P3 and the fourth sub-pixel P4. The scanning signal line 30 is configured to simultaneously control the conduction or disconnection of all the first transistors T1 and all the third transistors T3 in the four sub-pixels of the repeating unit.

[0207] In an exemplary embodiment, an orthographic projection of the scan signal line 30 on the substrate does not overlap with an orthographic projection of the first active layer 21 and the third active layer 23 on the substrate.

[0208] In an exemplary embodiment, the first gate electrode 31 may be in the shape of a strip extending along the second direction Y and may be disposed on a side of the scan signal line 30 close to the first active layer 21. A first end of the first gate electrode 31 is connected to the scan signal line 30, and a second end of the first gate electrode 31 extends toward the first active layer 21. The orthographic projection of the first gate electrode 31 on the substrate at least partially overlaps with the orthographic projection of the first active layer 21 on the substrate. In an exemplary embodiment, the first gate electrode 31 may serve as the gate electrode of the first transistor T1, so that the scan signal line 30 can control whether the first transistor T1 is turned on or off.

[0209] In an exemplary embodiment, the second gate electrode 32 may be in the shape of a strip extending along the second direction Y. A first end of the second gate electrode 32 is connected to the second electrode plate 62 via a sixth via V6, and a second end of the second gate electrode 32 extends toward the second active layer 22. The orthographic projection of the second gate electrode 32 on the substrate at least partially overlaps with the orthographic projection of the second active layer 22 on the substrate. In an exemplary embodiment, the second gate electrode 32 may serve as the gate electrode of the second transistor T2 and may control whether the second transistor T2 is turned on or off.

[0210] In an exemplary embodiment, since the second gate electrode 32 is connected to the second electrode plate 62, and the second electrode plate 62 is connected to the second region of the first active layer 21, the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second electrode plate 62 (the first end of the storage capacitor) have the same potential, forming a first node in the pixel driving circuit, and the second electrode plate 62 has the potential of the first node in the pixel driving circuit.

[0211] In an exemplary embodiment, the third gate electrode 33 may be in the shape of a strip extending along the second direction Y and may be disposed on a side of the scan signal line 30 close to the third active layer 23. A first end of the third gate electrode 33 is connected to the scan signal line 30, and a second end of the third gate electrode 33 extends toward the third active layer 23. The orthographic projection of the third gate electrode 33 on the substrate at least partially overlaps with the orthographic projection of the third active layer 23 on the substrate. In an exemplary embodiment, the third gate electrode 33 may serve as the gate electrode of the third transistor T3, so that the scan signal line 30 can control the conduction or disconnection of the third transistor T3.

[0212] In an exemplary embodiment, in one sub-pixel, one scan signal line 30 is connected to both the first gate electrode 31 and the third gate electrode 33 , so that the scan signal line 30 can control the on / off switching of the first transistor T1 and the third transistor T3 in one sub-pixel.

[0213] In an exemplary embodiment, in one pixel row, one scan signal line 30 is simultaneously connected to all first gate electrodes 31 and all third transistors 33 in a plurality of sub-pixels, so that the scan signal line 30 can control the on or off of all first transistors T1 and all third transistors T3 in one pixel row.

[0214] In an exemplary embodiment, in one repeating unit, one scan signal line 30 is simultaneously connected to all first gate electrodes 31 and all third transistors 33 in a plurality of sub-pixels, so that the scan signal line 30 can simultaneously control the on or off of all first transistors T1 and all third transistors T3 in the repeating unit.

[0215] In an exemplary embodiment, the fifth connection electrode 15 can be in a block shape (such as a rectangle) and can be arranged on a side of the second electrode plate 62 away from the scan signal line 30. The fifth connection electrode 15 is connected to the second region of the second active layer 22 and the third connection electrode 13 at the same time through the third via hole V3.

[0216] In the exemplary embodiment, the fifth connection electrode 15 is connected to both the second region of the second active layer 22 and the third connection electrode 13, the third connection electrode 13 is connected to the first connection electrode 11, and the first connection electrode 11 is connected to the first electrode plate 61. Therefore, the fifth connection electrode 15 allows the second electrode and the first electrode plate 61 of the second transistor to have the same potential. In the exemplary embodiment, the fifth connection electrode 15 is configured to be connected to an anode connection electrode to be formed later.

[0217] In an exemplary embodiment, the sixth connection electrode 16 can be in a block shape (such as a rectangle) and can be arranged on the side of the second electrode plate 62 close to the scan signal line 30. The sixth connection electrode 16 is simultaneously connected to the second region of the third active layer 23 and the fourth connection electrode 14 through the fifth via hole V5.

[0218] In an exemplary embodiment, since the sixth connection electrode 16 is connected to the second region of the third active layer 23 and the fourth connection electrode 14 at the same time, the fourth connection electrode 14 is connected to the second connection electrode 12, and the second connection electrode 12 is connected to the first electrode plate 61, the sixth connection electrode 16 enables the second electrode and the first electrode plate 61 of the third transistor to have the same potential.

[0219] In an exemplary embodiment, the fifth connecting electrode 15 and the sixth connecting electrode 16 realize the connection between the second electrode of the second transistor, the second electrode of the third transistor and the first electrode plate 61 (the second end of the storage capacitor), forming a second node in the pixel driving circuit, so that the first electrode plate 61 has the potential of the second node in the pixel driving circuit.

[0220] In an exemplary embodiment, since the first plate 61 has the potential of the second node in the pixel driving circuit and the second plate 62 has the potential of the first node in the pixel driving circuit, the first plate 61 having the potential of the second node and the second plate 62 having the potential of the first node form a storage capacitor.

[0221] In an exemplary embodiment, since the first electrode 61 is made of a transparent conductive material and the second electrode 62 is made of a transparent metal oxide, the storage capacitor is a transparent capacitor.

[0222] In an exemplary embodiment, the seventh connection electrode 17 may be in a block shape (e.g., a rectangle) and may be disposed between the first gate electrode 31 and the first power line 51. The seventh connection electrode 17 is simultaneously connected to the first region of the first active layer 21 and the data signal line 52 through the first via hole V1, thereby enabling the data signal line 52 to write a data signal into the first electrode of the first transistor T1. In an exemplary embodiment, each data signal line 52 may be connected to the first region of the first active layer in a sub-pixel through the first via hole V1, thereby enabling four data signal lines 52 to write data signals into the first electrodes of the first transistors T1 in a plurality of repeating units arranged along the second direction Y.

[0223] In an exemplary embodiment, the four data signal lines 52 may include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line. In each repeating unit, the first data signal line may be connected to the first region of the first active layer of the first subpixel P1 via the seventh connection electrode 17, the second data signal line may be connected to the first region of the first active layer in the third subpixel P3 via the seventh connection electrode 17, the third data signal line may be connected to the first region of the first active layer in the second subpixel P2 via the seventh connection electrode 17, and the fourth data signal line may be connected to the first region of the first active layer in the fourth subpixel P4 via the seventh connection electrode 17.

[0224] In an exemplary embodiment, the shape of the eighth connection electrode 18 can be a block shape (such as a rectangle) and can be arranged between the third gate electrodes 33 of two adjacent sub-pixels in the first direction X. The eighth connection electrode 18 is connected to the first area of ​​the third active layer 23 and the compensation signal line 53 at the same time through the fourth via hole V4, thereby enabling the compensation signal line 53 to write the compensation signal into the first electrode of the third transistor T3.

[0225] In an exemplary embodiment, because the first regions of the third active layers in the first and second subpixels P1 and P2 in a repeating unit are interconnected, the first and second subpixels P1 and P2 share the same fourth via hole V4, and thus the first and second subpixels P1 and P2 share the same eighth connection electrode 18. Because the first regions of the third active layers in the third and fourth subpixels P3 and P4 are interconnected, the third and fourth subpixels P3 and P4 share the same fourth via hole V4, and thus the third and fourth subpixels P3 and P4 share the same eighth connection electrode 18. By configuring adjacent subpixels in the first direction X in a repeating unit to share the same eighth connection electrode, the present disclosure not only effectively reduces the number of connection electrodes, reduces the area occupied by the pixel driving circuit, increases the pixel aperture ratio, and improves display resolution, but also simplifies the manufacturing process, reduces production costs, and improves product yield.

[0226] In an exemplary embodiment, within a repeating unit, compensation signal line 53 can simultaneously provide compensation signals to the pixel driver circuits in four sub-pixels. Thus, the four pixel driver circuits within a repeating unit can share a single compensation signal line 53, i.e., the compensation signal lines 53 within a repeating unit form a one-to-four structure. By designing the compensation signal lines as a one-to-four structure, the display substrate of the present disclosure reduces the number of signal lines and occupies less space. This results in a simple structure, a rational layout, and full utilization of layout space, improving space utilization, increasing pixel aperture ratio, and enhancing display resolution.

[0227] In an exemplary embodiment, the compensation signal line 53 is arranged between the first pixel column and the second pixel column, and the third transistor T3 of the first pixel column and the third transistor T3 of the second pixel column are symmetrically arranged with respect to the compensation signal line 53. This symmetrical structure of the present disclosure can ensure that the RC delay of the compensation signal written into the third transistor T3 is substantially the same, thereby ensuring display uniformity.

[0228] In an exemplary embodiment, the power connection electrode 20 can be in the shape of a strip extending along the first direction X, and can be arranged on the side of the second electrode plate 62 away from the scanning signal line 30. The first end of the power connection electrode 20 is connected to the first power line 51 through the seventh via V7, and the second end of the power connection electrode 20 is connected to the first area of ​​the second active layer 22 through the second via V2, thereby enabling the first power line 51 to write the first power signal into the first electrode of the second transistor T2.

[0229] In an exemplary embodiment, within each repeating unit, the first power line 51 of the first pixel column can simultaneously provide a first power signal to the pixel driving circuits in the first subpixel P1 and the third subpixel P3. The first power line 51 of the second pixel column can simultaneously provide a first power signal to the pixel driving circuits in the second subpixel P2 and the fourth subpixel P4. Thus, the first power lines 51 within a repeating unit form a one-to-two structure. By designing the first power lines as a one-to-two structure, the display substrate of the present disclosure reduces the number of signal lines and occupies less space. The resulting structure is simple, the layout is rational, and the layout space is fully utilized, improving space utilization, increasing the pixel aperture ratio, and enhancing display resolution.

[0230] In an exemplary embodiment, the two first power lines 51 in a repeating unit are symmetrically arranged relative to the compensation signal line 53, and the second transistor T2 of the first pixel column and the second transistor T2 of the second pixel column are symmetrically arranged relative to the compensation signal line 53. This symmetrical structure of the present disclosure can ensure that the voltage drop written by the first power line to the second transistor T2 is substantially the same, thereby ensuring display uniformity.

[0231] In an exemplary embodiment, the first ends of the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X may be connected to each other. For example, the first ends of the two power connection electrodes 20 in the second sub-pixel P2 of the first repeating unit Q1 and the first sub-pixel P1 of the second repeating unit Q2 may be connected to each other. For another example, the first ends of the two power connection electrodes 20 in the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 may be connected to each other.

[0232] In an exemplary embodiment, the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X may be an integrated structure connected to each other.

[0233] In an exemplary embodiment, because the second transistors of two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the first region of the second active layer, and because the two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the same second via hole V2, the two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the same power connection electrode 20. For example, the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 share the same power connection electrode 20. For another example, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q2 share the same power connection electrode 20. By providing that two sub-pixels in adjacent repeating units in the second direction Y share the same power connection electrode, the present disclosure not only effectively reduces the number of connection electrodes, reduces the area occupied by the pixel driving circuit, increases the pixel aperture ratio, and improves display resolution, but also simplifies the manufacturing process, reduces production costs, and improves product yield.

[0234] In an exemplary embodiment, in at least one repeating unit, the position of each pattern in the third conductive layer in the first subpixel P1 and the position of each pattern in the third conductive layer in the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line, the position of each pattern in the third conductive layer in the second subpixel P2 and the position of each pattern in the third conductive layer in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a horizontal reference line, the position of each pattern in the third conductive layer in the first subpixel P1 and the position of each pattern in the third conductive layer in the second subpixel P2 may be substantially mirror-symmetrical with respect to a vertical reference line, and the position of each pattern in the third conductive layer in the third subpixel P3 and the position of each pattern in the third conductive layer in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a vertical reference line.

[0235] In an exemplary embodiment, during the process of forming the third conductive layer pattern, a wet etching process is first used to form the third conductive layer pattern, thereby enabling at least one connecting electrode to simultaneously connect to the second conductive layer and the semiconductor layer through the via hole of the transition structure. The via hole of the transition structure can include at least two half-holes: a shallow half-hole and a deep half-hole. The second insulating layer in the shallow half-hole is removed, exposing the surface of the semiconductor layer. The second insulating layer and the first insulating layer in the deep half-hole are removed, exposing the surface of the second conductive layer. This allows the connecting electrode to simultaneously connect to the semiconductor layer and the second conductive layer through both the shallow and deep half-holes. In this exemplary embodiment, a distance is provided between the end of the connecting electrode located in the shallow half-hole region and the edge of the shallow half-hole, meaning that the connecting electrode does not fully cover the shallow half-hole.

[0236] In an exemplary embodiment, after the third conductive layer pattern is formed by a wet etching process, a self-alignment process using the third conductive layer as a mask is used to etch the second insulating layer in an area outside the third conductive layer by a dry etching process. While etching away the second insulating layer, the exposed semiconductor layer is subjected to a second conductorization to form a second conductorization area.

[0237] In an exemplary embodiment, during the second conductorization process, the edge portion of the semiconductor layer covered by the third conductive layer is also conductorized, that is, the semiconductor layer that is conductorized for the second time extends toward the area that was conductorized for the first time, forming a double conductorization area in the overlapping area of ​​the first conductorization area and the second conductorization area, thereby ensuring a reliable connection between the third conductive layer and the semiconductor layer.

[0238] In an exemplary embodiment, for the power connection electrode 20 connected to the first area of ​​the second active layer 22 through the second via V2, and the second gate electrode 32 connected to the second electrode plate 62 through the sixth via V6, the power connection electrode 20 and the second gate electrode 32 do not completely cover the vias, and a distance is set between the edge of the connection electrode and the edge of the via.

[0239] Figure 9C is a cross-sectional view taken along line AA in Figure 9A, and Figures 9D to 9F are cross-sectional views taken along line BB in Figure 9A. In a direction perpendicular to the display substrate, the display substrate may include at least a second conductive layer, a first insulating layer 71, a semiconductor layer, a second insulating layer 72, and a third conductive layer, which are sequentially disposed on the base 10. The second conductive layer may include at least a first power line 51 and a data signal line 52, the semiconductor layer may include at least a second active layer 22, and the third conductive layer may include at least a power connection electrode 20.

[0240] In an exemplary embodiment, a first end of the power connection electrode 20 is connected to the first power line 51 through a seventh via hole V7 , and a second end of the power connection electrode 20 is connected to the second active layer 22 through a second via hole V2 , as shown in FIG. 9C .

[0241] In an exemplary embodiment, in the process of forming the second insulating layer pattern, the second insulating layer in the second via hole V2 is etched away to expose the surface of the second active layer 22, and at the same time, the semiconductor layer exposed in the second via hole V2 is subjected to a first conductorization treatment, so that the semiconductor layer exposed in the second via hole V2 forms a first conductorization area, as shown in Figure 9D.

[0242] In this exemplary embodiment, during the process of forming the third conductive layer pattern, a wet etching process is first used to form the third conductive layer including the power connection electrode 20. The power connection electrode 20 is connected to the second active layer 22 via the second via V2, as shown in FIG9E . Subsequently, a dry etching process is used to etch the second insulating layer 72 in the area outside the third conductive layer using a self-aligned process using the third conductive layer as a mask. While the second insulating layer 72 is etched away, the exposed semiconductor layer is subjected to a second conductive process, forming a second conductive region, as shown in FIG9F .

[0243] (16) Forming a third insulating layer and a planar layer pattern. In an exemplary embodiment, forming the third insulating layer and the planar layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, then coating a planar film, patterning the planar film and the third insulating film through a patterning process to form a third insulating layer covering the third conductive layer and a planar layer pattern disposed on the third insulating layer, wherein a plurality of vias are disposed on the planar layer, as shown in FIG. 10 .

[0244] In an exemplary embodiment, the via holes of each sub-pixel in each repeating unit include at least an eleventh via hole V11 .

[0245] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 15 on the substrate, the third insulating layer and the flat layer in the eleventh via hole V11 are etched away to expose the surface of the fifth connecting electrode 15, and the eleventh via hole V11 is configured to connect a subsequently formed anode connecting electrode to the fifth connecting electrode 15 through the via hole.

[0246] In an exemplary embodiment, this process uses a single patterning process to simultaneously form vias on the third insulating layer and the planar layer, that is, the third insulating layer and the planar layer share a halftone or gray tone mask (MASK) process, effectively reducing the number of patterning processes.

[0247] (17) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film through a patterning process, and forming a fourth conductive layer pattern on the color filter layer, as shown in FIG11A and FIG11B , where FIG11B is a schematic diagram of the fourth conductive layer in FIG11A .

[0248] In an exemplary embodiment, the fourth conductive layer of each sub-pixel in each repeating unit may include at least the first electrode 63 and the anode connection electrode 64 .

[0249] In an exemplary embodiment, the first electrode 63 may be rectangular in shape, and the corners of the rectangle may be provided with chamfers, grooves or protrusions, and the orthographic projection of the first electrode 63 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 62 on the substrate.

[0250] In an exemplary embodiment, the shape of the anode connecting electrode 64 can be a block shape (such as a rectangle), and can be located on the side of the first electrode 63 away from the scanning signal line 30. The first end of the anode connecting electrode 64 is connected to the first electrode 63, and the second end of the anode connecting electrode 64 extends in a direction away from the scanning signal line 30 and is connected to the fifth connecting electrode 15 through the eleventh via hole V11.

[0251] In an exemplary embodiment, in at least one sub-pixel, the anode connection electrode 64 and the first electrode 63 may be an integral structure connected to each other.

[0252] In an exemplary embodiment, in at least one repeating unit, the four first electrodes 63 may be arranged in a square, with the upper left first electrode connected to the pixel driving circuit in the first subpixel P1, the upper right first electrode connected to the pixel driving circuit in the second subpixel P2, the lower left first electrode connected to the pixel driving circuit in the third subpixel P3, and the lower right first electrode connected to the pixel driving circuit in the fourth subpixel P4. In some possible implementations, the first electrodes may serve as anodes of the light-emitting device. The arrangement of the first electrodes may be adjusted according to actual needs and is not specifically limited in this disclosure.

[0253] In an exemplary embodiment, the first conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0254] In an exemplary embodiment, the first electrode 63 can also serve as an auxiliary capacitor of the storage capacitor. Since the first electrode 63 is connected to the anode connection electrode 64, and the anode connection electrode 64 is connected to the first plate 61 through the fifth connection electrode 15, the third connection electrode 13 and the first connection electrode 11, the first electrode 63 has the potential of the second node in the pixel driving circuit, so that the first electrode 63 having the second node potential and the second plate 62 having the first node potential form an auxiliary capacitor, and the auxiliary capacitor and the storage capacitor are connected in parallel. The present disclosure uses the first electrode to form an auxiliary capacitor, and the auxiliary capacitor and the storage capacitor are connected in parallel. On the one hand, it can effectively increase the capacitance value of the storage capacitor, and on the other hand, it can reduce the plate area while ensuring the capacitance value of the storage capacitor, effectively reducing the occupied area.

[0255] (18) Forming a pixel definition layer. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on the substrate having the aforementioned pattern formed thereon, and patterning the pixel definition film through a patterning process to form a pixel definition layer covering the fourth conductive layer, as shown in FIG. 12 .

[0256] In an exemplary embodiment, a pixel opening PK is opened on the pixel definition layer of each sub-pixel in each repeating unit, the pixel definition film within the pixel opening PK is removed to expose a portion of the surface of the first electrode 63, and the orthographic projection of the pixel opening PK on the substrate is within the range of the orthographic projection of the first electrode 63 on the substrate.

[0257] In an exemplary embodiment, the shape of the pixel opening PK in a plane parallel to the substrate may be similar to that of the first electrode 63 , and the cross-sectional shape of the pixel opening PK in a plane perpendicular to the substrate may be a rectangle or a trapezoid.

[0258] In exemplary embodiments, the shape of the pixel opening may include any one or more of a triangle, a rectangle, a trapezoid, a parallelogram, a pentagon, a hexagon, a circle, and an ellipse.

[0259] In an exemplary embodiment, the shapes of the pixel openings of the four sub-pixels in the repeating unit may be the same or different, and the areas of the pixel openings of the four sub-pixels may be the same or different.

[0260] In an exemplary embodiment, the shapes and areas of the pixel openings of the four sub-pixels in the repeating unit can be different to adapt to the transmittance of different sub-pixel filters, so that the light-emitting devices of the four sub-pixels can emit the same brightness at different currents, thereby maximizing the lifespan of the four sub-pixel light-emitting devices and ensuring the product life.

[0261] In an exemplary embodiment, at least one partitioning groove M may be provided on the pixel definition layer of each repeating unit. The partitioning groove M may be in the shape of a strip with a main portion extending along the second direction Y, and may be provided between adjacent pixel openings PK in the first direction X. For example, the partitioning groove M may be provided between the pixel opening PK of the first subpixel P1 and the pixel opening PK of the second subpixel P2. In another example, the partitioning groove M may be provided between the pixel opening PK of the third subpixel P3 and the pixel opening PK of the fourth subpixel P4. In an exemplary embodiment, the partitioning groove M is configured to interrupt the subsequently formed organic light-emitting layer, block the lateral propagation path of hole-type carriers, eliminate lateral leakage, and reduce lateral crosstalk between subpixels.

[0262] In an exemplary embodiment, the pixel definition layer may be made of polyimide, acryl, polyethylene terephthalate, or the like.

[0263] (19) Forming an organic light-emitting layer and a cathode pattern. In an exemplary embodiment, forming the organic light-emitting layer and the cathode pattern may include: first forming an organic light-emitting layer pattern, wherein the organic light-emitting layer is connected to the first electrode 63 through the pixel opening PK. Then, forming a second electrode, wherein the second electrode is connected to the organic light-emitting layer. In an exemplary embodiment, the second electrode may serve as a cathode of the light-emitting device.

[0264] In an exemplary embodiment, the organic light-emitting layer may include an emission layer (EML), and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the organic light-emitting layer may be formed using a fine metal mask (FMM) or open mask evaporation, or using an inkjet process.

[0265] (20) Forming a packaging structure layer pattern. In an exemplary embodiment, forming a packaging structure layer pattern may include: first using an open mask to deposit a first inorganic thin film to form a first packaging layer. Subsequently, using an inkjet printing process to inkjet print an organic material on the first packaging layer, and after curing into a film, forming a second packaging layer. Subsequently, using an open mask to deposit a second inorganic thin film to form a third packaging layer, the first packaging layer, the second packaging layer and the third packaging layer constitute a packaging structure layer. The first packaging layer and the third packaging layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbonitride (SiCN) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer. The second packaging layer can be made of a resin material to form a laminated structure of inorganic material / organic material / inorganic material. The organic material layer is arranged between the two inorganic material layers to ensure that external water vapor cannot enter the light-emitting structure layer.

[0266] At this point, the preparation of the display substrate of the exemplary embodiment of the present disclosure is completed. The display substrate may include a driving circuit layer arranged on a substrate, a light-emitting structure layer arranged on the side of the driving circuit layer away from the substrate, and an encapsulation structure layer arranged on the side of the light-emitting structure layer away from the substrate. In a direction perpendicular to the display substrate, the driving circuit layer may include a first conductive layer, a second conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a third conductive layer, a third insulating layer and a flat layer arranged in sequence on the substrate, the light-emitting structure layer may include a first electrode, a pixel definition layer, an organic light-emitting layer and a second electrode, and the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer.

[0267] In an exemplary embodiment, for a display substrate including a color filter structure layer, after forming the third conductive layer, a third insulating layer can be formed first, and then a red color filter layer, a green color filter layer and a blue color filter layer are formed in sequence, and then a flat layer is formed, which will not be repeated here.

[0268] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0269] In an exemplary embodiment, the second conductive layer and the third conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, and the third insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The planar layer can be made of an organic material, such as a resin.

[0270] The disclosed embodiments provide a bottom-emission display substrate. By positioning the first electrode of the second transistor in a subpixel near a first power line, and providing a power via connecting a gate metal layer to a second conductive layer between two adjacent subpixels in two adjacent repeating units in the first direction, and a power via connecting a gate metal layer to a second conductive layer between two adjacent subpixels in two adjacent repeating units in the second direction, the number of vias is reduced, effectively reducing the area occupied by the pixel drive circuit, increasing the pixel aperture ratio, and improving display resolution. Furthermore, reducing the number of vias can simplify the manufacturing process, reduce production costs, and improve product yield.

[0271] The display substrate of the embodiment of the present disclosure arranges the second active layers of two adjacent sub-pixels in two adjacent repeating units in the second direction into an interconnected integral structure, so that two adjacent sub-pixels in two adjacent repeating units in the second direction share an active via connecting the gate metal layer and the semiconductor layer, thereby further reducing the number of transfer vias, effectively reducing the occupied area of ​​the pixel driving circuit, increasing the pixel aperture ratio, and improving the display resolution.

[0272] The display substrate of the disclosed embodiment utilizes a structure in which the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the first direction are interconnected and integrated, while the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the second direction are shared. This reduces the number of connection electrodes, effectively reducing the area occupied by the pixel drive circuit, increasing the pixel aperture ratio, and improving display resolution. Furthermore, reducing the number of connection electrodes simplifies the manufacturing process, reduces production costs, and improves product yield.

[0273] The disclosed embodiment shows that the substrate can effectively meet the requirements of a single scanning signal line structure by arranging a second active layer with a larger width and a second active layer with a smaller width alternately in a first direction X and a second direction Y, and can effectively increase the uniformity of the four pixel driving circuit layouts within the repeating unit, and can effectively increase the uniformity of the pixel openings of the four sub-pixels within the repeating unit.

[0274] The disclosed embodiment of the display substrate arranges the first power line, data signal line, and compensation signal line in the SHIELD layer, located on the side of the semiconductor layer close to the substrate, and arranges the scan signal line and gate electrodes of multiple transistors in the GT layer, located on the side of the semiconductor layer away from the substrate. This not only reduces one conductive layer, but also reduces the patterning process of the transfer via and the patterning process of the transfer conductive layer, so that the preparation process of the drive structure layer only requires six patterning (MASK) processes. Compared with the existing preparation process that requires nine patterning processes, the disclosed display substrate reduces the number of patterning processes, effectively improves production efficiency, effectively reduces production costs, and maximizes product yield.

[0275] The display substrate of the disclosed embodiment utilizes a 3T1C pixel drive circuit with one scan signal line, where the scan signal line is connected to the first and third transistors in the pixel drive circuit. By reducing the number of scan signal lines, the structure of the pixel drive circuit can be simplified, reducing the area occupied by the pixel drive circuit, thereby facilitating high-resolution display. Furthermore, since a repeating unit only requires one scan signal line to drive, the number of corresponding gate drive circuits (GOA) and clock signal lines (CLK) can be reduced exponentially, effectively reducing the area occupied by the gate drive circuits and clock signal lines, thereby facilitating narrow bezels and enhancing product advantages.

[0276] The disclosed embodiment shows that the substrate is formed into a transparent storage capacitor by a transparent conductive layer and a transparent semiconductor layer, so that light can be emitted through the transparent storage capacitor. Therefore, the storage capacitor can be set in the pixel opening, which can not only effectively increase the capacitance of the storage capacitor, but also effectively increase the pixel aperture ratio.

[0277] The display substrate of the embodiment of the present disclosure arranges sub-pixels in a square manner and adopts a first power line structure with a non-mesh structure, which can effectively increase the pixel aperture ratio, improve the display effect, and is more suitable for display type display.

[0278] The preparation process disclosed in the present invention is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0279] Figure 13 is a schematic diagram of another display substrate structure according to an exemplary embodiment of the present disclosure, illustrating a structure of four repeating units (sixteen sub-pixels) in a bottom-emission display substrate. In this exemplary embodiment, the main structure of the display substrate of this embodiment is substantially the same as that of the previous embodiment, except that the pixel drive circuit further includes an active connection electrode 24, and the power connection electrode 20 is connected to both the first power line 51 and the active connection electrode 24 via a transfer via.

[0280] In an exemplary embodiment, the structures of the scan signal line 30, the first power line 51, the data signal line 52, the compensation signal line 53, the storage capacitor 60, the first transistor T1, the second transistor T2 and the third transistor T3 of this embodiment are basically the same as those of the previous embodiment and are not repeated here.

[0281] In an exemplary embodiment, the pixel driving circuit further includes an active connection electrode 24. The active connection electrode 24 may be in the shape of a strip extending along the first direction X. A first end of the active connection electrode 24 is connected to the first region of the second active layer 22 of the integrated structure, and a second end of the active connection electrode 24 extends away from the second active layer 22 to the region where the first power line 51 is located.

[0282] In exemplary embodiments, the second active layer 22 and the active connection electrode 24 may be an integral structure connected to each other.

[0283] In an exemplary embodiment, an orthographic projection of the second end of the active connecting electrode 24 on the substrate at least partially overlaps with an orthographic projection of the first power line 51 on the substrate.

[0284] In an exemplary embodiment, an orthographic projection of the active connection electrode 24 on the substrate at least partially overlaps an orthographic projection of the data signal line 52 on the substrate, forming a structure in which the second active layer 22 crosses the data signal line 52 .

[0285] In an exemplary embodiment, the power connection electrode 20 may be block-shaped (eg, rectangular) and is connected to both the first power line 51 and the second end of the active connection electrode 24 through the transfer via K3 .

[0286] In an exemplary embodiment, the transfer via K3 may include a shallow half hole and a deep half hole, the shallow half hole exposing the surface of the second end of the active connecting electrode 24, and the deep half hole exposing the surface of the first power line 51. The shallow half hole can serve as the active via of the present disclosure, and the deep half hole can serve as the power via of the present disclosure.

[0287] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the first direction X share the same transfer via K3. For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the fourth sub-pixel P4 in the first repeating unit Q1 and the third sub-pixel P3 in the second repeating unit Q2 share the same transfer via K3. For another example, for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the fourth sub-pixel P4 in the third repeating unit Q3 and the third sub-pixel P3 in the fourth repeating unit Q4 share the same transfer via K3.

[0288] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the same transfer via K3. For example, for the first repeating unit Q1 and the third repeating unit Q3 that are adjacent in the second direction Y, the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 can share the same transfer via K3, and the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 can share the same transfer via K3. For another example, for the second repeating unit Q2 and the fourth repeating unit Q4 that are adjacent in the second direction Y, the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 can share the same transfer via K3, and the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 can share the same transfer via K3.

[0289] In an exemplary embodiment, adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y share the same transfer via K3. That is, four adjacent sub-pixels in adjacent repeating units share the same transfer via K3. For example, the fourth sub-pixel P4 in the first repeating unit Q1, the third sub-pixel P3 in the second repeating unit Q2, the second sub-pixel P2 in the third repeating unit Q3, and the first sub-pixel P1 in the fourth repeating unit Q4 may share the same transfer via K3.

[0290] In an exemplary embodiment, the second ends of the active connection electrodes 24 of two adjacent sub-pixels in two adjacent repeating units in the first direction X may be connected to each other. Because the active connection electrode 24 of each sub-pixel is connected to the first region of the second active layer 22, the first regions of the second active layer 22 of two adjacent sub-pixels in the two adjacent repeating units in the first direction X are connected to each other via the active connection electrode 24. For example, in the first repeating unit Q1 and the second repeating unit Q2 adjacent to each other in the first direction X, the first region of the second active layer 22 of the fourth sub-pixel P4 in the first repeating unit Q1 and the first region of the second active layer 22 of the third sub-pixel P3 in the second repeating unit Q2 are connected to each other via the active connection electrode 24. For another example, in the third repeating unit Q3 and the fourth repeating unit Q4 adjacent to each other in the first direction X, the first region of the second active layer 22 of the fourth sub-pixel P4 in the third repeating unit Q3 and the first region of the second active layer 22 of the third sub-pixel P3 in the fourth repeating unit Q4 are connected to each other via the active connection electrode 24.

[0291] In an exemplary embodiment, the active connection electrodes 24 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are an integrated structure connected to each other.

[0292] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the second direction Y may share the same active connection electrode 24. For example, for the first repeating unit Q1 and the third repeating unit Q3 that are adjacent in the second direction Y, the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 may share the same active connection electrode 24, and the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 may share the same active connection electrode 24. For another example, for the second repeating unit Q2 and the fourth repeating unit Q4 that are adjacent in the second direction Y, the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 may share the same active connection electrode 24, and the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 may share the same active connection electrode 24.

[0293] In an exemplary embodiment, the first regions of the second active layers 22 of adjacent sub-pixels in the repeating units adjacent in the first direction X and the second direction Y may be connected to each other through the active connection electrode 24 .

[0294] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the first direction X share the same power connection electrode 20. For example, for the first repeating unit Q1 and the second repeating unit Q2 that are adjacent in the first direction X, the fourth sub-pixel P4 in the first repeating unit Q1 and the third sub-pixel P3 in the second repeating unit Q2 share the same power connection electrode 20. For another example, for the third repeating unit Q3 and the fourth repeating unit Q4 that are adjacent in the first direction X, the fourth sub-pixel P4 in the third repeating unit Q3 and the third sub-pixel P3 in the fourth repeating unit Q4 share the same power connection electrode 20.

[0295] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the second direction Y share a common power connection electrode 20. For example, for the first repeating unit Q1 and the third repeating unit Q3 that are adjacent in the second direction Y, the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 may share a common power connection electrode 20, and the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 may share a common power connection electrode 20. For another example, for the second repeating unit Q2 and the fourth repeating unit Q4 that are adjacent in the second direction Y, the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 may share a common power connection electrode 20, and the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 may share a common power connection electrode 20.

[0296] In an exemplary embodiment, adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y share the same power connection electrode 20, that is, four adjacent sub-pixels in adjacent repeating units share the same power connection electrode 20. For example, the fourth sub-pixel P4 of the first repeating unit Q1, the third sub-pixel P3 of the second repeating unit Q2, the second sub-pixel P2 of the third repeating unit Q3, and the first sub-pixel P1 of the fourth repeating unit Q4 share the same power connection electrode 20.

[0297] In an exemplary embodiment, the preparation process of the display substrate of this embodiment may include the following operations.

[0298] (21) A first conductive layer pattern is formed. The process and the structure of the formed first conductive layer are substantially the same as those in step (11) of the aforementioned embodiment.

[0299] (22) A second conductive layer pattern is formed. The process and the structure of the formed second conductive layer are basically the same as those in step (12) of the aforementioned embodiment.

[0300] (23) A semiconductor layer pattern is formed. The process and the structure of the formed semiconductor layer are basically the same as those in step (13) of the aforementioned embodiment. The difference is that the semiconductor layer also includes an active connecting electrode 24, as shown in Figures 14A and 14B. Figure 14B is a schematic diagram of the semiconductor layer in Figure 14A.

[0301] In an exemplary embodiment, the semiconductor layer of each sub-pixel in each repeating unit may include at least a first active layer 21, a second active layer 22, a third active layer 23 and a second plate 62 of a storage capacitor, and the above structure is substantially the same as the above embodiment.

[0302] In an exemplary embodiment, the semiconductor layer of each sub-pixel may further include an active connection electrode 24, and the active connection electrode 24 may be in the shape of a strip extending along the first direction X. The first end of the active connection electrode 24 is connected to the first region of the second active layer 22 of the integrated structure, and the second end of the active connection electrode 24 extends in a direction away from the second active layer 22 to the region where the first power line 51 is located. The second end of the active connection electrode 24 is configured to be connected to the first power line 51 through a subsequently formed power connection electrode.

[0303] In exemplary embodiments, the second active layer 22 and the active connection electrode 24 may be an integral structure connected to each other.

[0304] In an exemplary embodiment, an orthographic projection of the second end of the active connecting electrode 24 on the substrate at least partially overlaps with an orthographic projection of the first power line 51 on the substrate.

[0305] In an exemplary embodiment, an orthographic projection of the active connection electrode 24 on the substrate at least partially overlaps an orthographic projection of the data signal line 52 on the substrate, forming a structure in which the second active layer 22 crosses the data signal line 52 .

[0306] In an exemplary embodiment, the second active layers 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y may be interconnected and integrally structured, and thus the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y may share the same active connection electrode 24. For example, for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 may share the same active connection electrode 24, and the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 may share the same active connection electrode 24. For another example, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 may share the same active connection electrode 24, and the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 may share the same active connection electrode 24.

[0307] In an exemplary embodiment, the active connection electrodes 24 of two adjacent sub-pixels in two adjacent repeating units in the first direction X may be connected to each other. Because the active connection electrode 24 of each sub-pixel is connected to the first region of the second active layer 22, the first regions of the second active layer 22 of two adjacent sub-pixels in the two adjacent repeating units in the first direction X are connected to each other via the active connection electrode 24. For example, in the first repeating unit Q1 and the second repeating unit Q2 adjacent to each other in the first direction X, the first region of the second active layer 22 of the fourth sub-pixel P4 in the first repeating unit Q1 and the first region of the second active layer 22 of the third sub-pixel P3 in the second repeating unit Q2 are connected to each other via the active connection electrode 24. For another example, in the third repeating unit Q3 and the fourth repeating unit Q4 adjacent to each other in the first direction X, the first region of the second active layer 22 of the fourth sub-pixel P4 in the third repeating unit Q3 and the first region of the second active layer 22 of the third sub-pixel P3 in the fourth repeating unit Q4 are connected to each other via the active connection electrode 24.

[0308] In an exemplary embodiment, the active connection electrodes 24 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are an integrated structure connected to each other.

[0309] In an exemplary embodiment, the first regions of the second active layer 22 of adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y can be interconnected via the active connection electrode 24. For example, the first region of the second active layer 22 of the fourth sub-pixel P4 in the first repeating unit Q1, the first region of the second active layer 22 of the third sub-pixel P3 in the second repeating unit Q2, the first region of the second active layer 22 of the second sub-pixel P2 in the third repeating unit Q3, and the first region of the second active layer 22 of the first sub-pixel P1 in the fourth repeating unit Q4 can be interconnected via the active connection electrode 24. By configuring the second transistors of four adjacent sub-pixels in adjacent repeating units to share the first region of the second active layer, the present disclosure can effectively reduce the number of vias, reduce the area occupied by the pixel driving circuit, increase the pixel aperture ratio, and improve display resolution. Furthermore, reducing the number of vias can simplify the manufacturing process, reduce production costs, and improve product yield.

[0310] In an exemplary embodiment, the widths of the second active layers in adjacent sub-pixels in the first direction X are different, and the widths of the second active layers in adjacent sub-pixels in the second direction Y are different.

[0311] (24) A second insulating layer pattern is formed. The process and the structure of the formed second insulating layer are substantially the same as those in step (14) of the aforementioned embodiment. The difference is that the eighth via hole V8 is a via hole of a transfer structure, as shown in FIG15 .

[0312] In an exemplary embodiment, a plurality of via holes are provided on the second insulating layer, and the plurality of via holes of each sub-pixel in each repeating unit includes at least a first via hole V1 and third via holes V3 to sixth via holes V6, and the structures of the above via holes are substantially the same as those in the previous embodiment.

[0313] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is within the range of the orthographic projection of the second end of the active connection electrode 24 and the first power line 51 on the substrate. The eighth via V8 serves as a transfer via of the present disclosure and includes a shallow half-hole and a deep half-hole. The second insulating layer in the shallow half-hole is etched away, exposing the surface of the second end of the active connection electrode 24. The first and second insulating layers in the deep half-hole are etched away, exposing the surface of the first power line 51. This allows the via hole in the transfer structure, consisting of the two half-holes, to simultaneously expose the second end of the active connection electrode 24 and the first power line 51. The eighth via V8 is configured to allow a subsequently formed power connection electrode to be simultaneously connected to the second end of the active connection electrode 24 and the first power line 51 through this via. In an exemplary embodiment, the eighth via V8 serves as a transfer via of the present disclosure. The shallow half-hole can serve as the active via of the present disclosure, and the deep half-hole can serve as the power via of the present disclosure.

[0314] In an exemplary embodiment, because the active connection electrodes 24 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are interconnected and integrated, the two adjacent sub-pixels in the two adjacent repeating units in the first direction X share the same eighth via hole V8. For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the fourth sub-pixel P4 in the first repeating unit Q1 and the third sub-pixel P3 in the second repeating unit Q2 share the same eighth via hole V8. For another example, for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the fourth sub-pixel P4 in the third repeating unit Q3 and the third sub-pixel P3 in the fourth repeating unit Q4 share the same eighth via hole V8. By providing that two adjacent sub-pixels in two adjacent repeating units in the first direction X share the same eighth via hole V8, the present disclosure not only effectively reduces the number of via holes, reduces the area occupied by the pixel driving circuit, increases the pixel aperture ratio, and improves display resolution, but also simplifies the manufacturing process, reduces production costs, and improves product yield.

[0315] In an exemplary embodiment, since two adjacent sub-pixels in two adjacent repeating units in the second direction Y can share the same active connection electrode 24, two adjacent sub-pixels in two adjacent repeating units in the second direction Y can share the same eighth via hole V8. For example, for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 can share the same eighth via hole V8, and the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 can share the same eighth via hole V8. For another example, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 can share the same eighth via hole V8, and the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 can share the same eighth via hole V8. The present disclosure sets two adjacent sub-pixels in two adjacent repeating units in the second direction Y to share the same eighth via hole V8, which can not only effectively reduce the number of via holes, but also reduce the occupied area of ​​the pixel driving circuit, increase the pixel aperture ratio, and improve the display resolution. In addition, reducing the via holes can simplify the preparation process, reduce production costs, and improve product yield.

[0316] In an exemplary embodiment, adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y share the same transfer via K3, that is, four adjacent sub-pixels in adjacent repeating units share the same eighth via V8. For example, the fourth sub-pixel P4 in the first repeating unit Q1, the third sub-pixel P3 in the second repeating unit Q2, the second sub-pixel P2 in the third repeating unit Q3, and the first sub-pixel P1 in the fourth repeating unit Q4 can share the same eighth via V8.

[0317] (25) A third conductive layer pattern is formed. The process and the structure of the formed third conductive layer are basically the same as those in step (15) of the aforementioned embodiment. The difference is that the power connection electrode 20 is connected to the second end of the active connection electrode 24 and the first power line 51 at the same time through the eighth via V8 of the transfer structure, as shown in Figures 16A and 16B. Figure 16B is a schematic diagram of the third conductive layer in Figure 16A.

[0318] In an exemplary embodiment, the third conductive layer of each sub-pixel in each repeating unit may include at least a fifth connecting electrode 15, a sixth connecting electrode 16, a seventh connecting electrode 17, an eighth connecting electrode 18, a power connecting electrode 20, a scanning signal line 30, a first gate electrode 31, a second gate electrode 32 and a third gate electrode 33. Except for the power connecting electrode 20, the other structures are basically the same as those in the aforementioned embodiment.

[0319] In an exemplary embodiment, the power connection electrode 20 may be in a block shape (e.g., rectangular) and is connected to both the second end of the active connection electrode 24 and the first power line 51 through the eighth via V8 of the transfer structure. Since the active connection electrode 24 is connected to the first region of the second active layer, the first power line 51 writes the first power signal to the first electrode of the second transistor T2.

[0320] In an exemplary embodiment, because two adjacent sub-pixels in two adjacent repeating units in the first direction X share the same eighth via V8, two adjacent sub-pixels in the two adjacent repeating units in the first direction X share the same power connection electrode 20. For example, for the first repeating unit Q1 and the second repeating unit Q2, which are adjacent in the first direction X, the fourth sub-pixel P4 in the first repeating unit Q1 and the third sub-pixel P3 in the second repeating unit Q2 share the same power connection electrode 20. For another example, for the third repeating unit Q3 and the fourth repeating unit Q4, which are adjacent in the first direction X, the fourth sub-pixel P4 in the third repeating unit Q3 and the third sub-pixel P3 in the fourth repeating unit Q4 share the same power connection electrode 20. By providing that two adjacent sub-pixels in two adjacent repeating units in the first direction X share the same power connection electrode 20, the present disclosure not only effectively reduces the number of connection electrodes, reduces the area occupied by the pixel driving circuit, increases the pixel aperture ratio, and improves display resolution, but also simplifies the manufacturing process, reduces production costs, and improves product yield.

[0321] In an exemplary embodiment, since two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the same eighth via hole V8, the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y share the same power connection electrode 20. For example, for the first repeating unit Q1 and the third repeating unit Q3 that are adjacent in the second direction Y, the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 can share the same power connection electrode 20, and the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 can share the same power connection electrode 20. For another example, for the second repeating unit Q2 and the fourth repeating unit Q4 that are adjacent in the second direction Y, the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 can share the same power connection electrode 20, and the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 can share the same power connection electrode 20. The present disclosure sets two adjacent sub-pixels in two adjacent repeating units in the second direction Y to share the same power connection electrode 20, which can not only effectively reduce the number of connection electrodes, reduce the occupied area of ​​the pixel driving circuit, increase the pixel aperture ratio, and improve the display resolution, but also reduce the number of connection electrodes to simplify the preparation process, reduce production costs, and improve product yield.

[0322] In an exemplary embodiment, adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y share a common power connection electrode 20. That is, four adjacent sub-pixels in adjacent repeating units share a common power connection electrode 20. For example, the fourth sub-pixel P4 of the first repeating unit Q1, the third sub-pixel P3 of the second repeating unit Q2, the second sub-pixel P2 of the third repeating unit Q3, and the first sub-pixel P1 of the fourth repeating unit Q4 share a common power connection electrode 20. By providing that four adjacent sub-pixels in adjacent repeating units share a common power connection electrode 20, the present disclosure not only effectively reduces the number of connection electrodes, thus reducing the area occupied by the pixel driving circuit, increasing the pixel aperture ratio, and improving display resolution, but also simplifies the manufacturing process, reduces production costs, and improves product yield.

[0323] In an exemplary embodiment, the subsequent process of forming the third insulating layer, the planar layer, the fourth conductive layer, the pixel definition layer, the organic light-emitting layer, the cathode and the encapsulation structure layer and the formed structure are basically the same as those in the aforementioned embodiment and are not repeated here.

[0324] The disclosed embodiments provide a bottom-emission display substrate. By providing active connecting electrodes, adjacent sub-pixels in adjacent repeating units in first and second directions share a common gate metal layer with a semiconductor layer and a shield layer. This effectively reduces the number of these vias and electrodes, effectively reducing the area occupied by the pixel drive circuit, increasing the pixel aperture ratio, and improving display resolution. Furthermore, reducing the number of vias and electrodes can simplify the manufacturing process, reduce production costs, and improve product yield.

[0325] The display substrate of the disclosed embodiment also has the technical effects of reducing the number of patterning processes, reducing the number of scanning signal lines, and increasing the pixel aperture ratio.

[0326] FIG17 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of four repeating units (sixteen sub-pixels) in a bottom-emission display substrate. In this exemplary embodiment, the main structure of the display substrate of this embodiment is substantially the same as that of the previous embodiment, except that the first regions of the second active layer 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y are not connected, and the first ends of the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X and the second direction Y are connected to each other.

[0327] In an exemplary embodiment, the structures of the scan signal line 30, the first power line 51, the data signal line 52, the compensation signal line 53, the storage capacitor 60, the first transistor T1, the second transistor T2 and the third transistor T3 of this embodiment are basically the same as those of the previous embodiment and are not repeated here.

[0328] In an exemplary embodiment, in at least one repeating unit, the first regions of the second active layer 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y are not connected, and the first power line 51 is connected to the first region of the second active layer 22 in each sub-pixel through the power connection electrode 20.

[0329] In an exemplary embodiment, the power connection electrode 20 may be in the shape of a strip extending along the first direction X, a first end of the power connection electrode 20 is connected to the first power line 51 through a power via K1, and a second end of the power connection electrode 20 is connected to the first region of the second active layer 22 through an active via K2.

[0330] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the first direction X share the same power via K1 , and two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the same power via K1 .

[0331] In an exemplary embodiment, four adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y share the same power via K1. For example, the fourth sub-pixel P4 of the first repeating unit Q1, the third sub-pixel P3 of the second repeating unit Q2, the second sub-pixel P2 of the third repeating unit Q3, and the first sub-pixel P1 of the fourth repeating unit Q4 share the same power via K1.

[0332] In an exemplary embodiment, the first ends of the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are connected to each other. For example, the first ends of the two power connection electrodes 20 in the second sub-pixel P2 of the first repeating unit Q1 and the first sub-pixel P1 of the second repeating unit Q2 are connected to each other. For another example, the first ends of the two power connection electrodes 20 in the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 are connected to each other.

[0333] In an exemplary embodiment, the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are an integrated structure connected to each other.

[0334] In an exemplary embodiment, the first ends of the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y are connected to each other. For example, the first ends of the power connection electrodes 20 of the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 are connected to each other. For another example, the first ends of the power connection electrodes 20 of the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q2 are connected to each other.

[0335] In an exemplary embodiment, the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y are an integrated structure connected to each other.

[0336] In an exemplary embodiment, the power connection electrodes 20 of adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y are interconnected as an integrated structure. That is, the power connection electrodes 20 of four adjacent sub-pixels in adjacent repeating units are interconnected as an integrated structure. For example, the four power connection electrodes 20 in the fourth sub-pixel P4 of the first repeating unit Q1, the third sub-pixel P3 of the second repeating unit Q2, the second sub-pixel P2 of the third repeating unit Q3, and the first sub-pixel P1 of the fourth repeating unit Q4 are interconnected as an integrated structure.

[0337] In an exemplary embodiment, the preparation process of the display substrate of this embodiment may include the following operations.

[0338] (31) A first conductive layer pattern is formed. The process and the structure of the formed first conductive layer are basically the same as those in step (11) of the aforementioned embodiment.

[0339] (32) A second conductive layer pattern is formed. The process and the structure of the formed second conductive layer are basically the same as those in step (12) of the aforementioned embodiment.

[0340] (33) A semiconductor layer pattern is formed. The process and the structure of the formed semiconductor layer are basically the same as those in step (13) of the aforementioned embodiment. The difference is that the second active layer 22 of each sub-pixel is set separately, that is, the first areas of the second active layers 22 of adjacent sub-pixels are not connected, as shown in Figures 18A and 18B. Figure 18B is a schematic diagram of the semiconductor layer in Figure 18A.

[0341] In an exemplary embodiment, the orthographic projection of the second region and the channel region of the second active layer 22 of each sub-pixel on the substrate at least partially overlaps with the orthographic projection of the third connection electrode 13 on the substrate, so that the third connection electrode 13 serving as a shielding layer can shield the channel region of the second transistor T2, thereby preventing light from affecting the channel and ensuring the electrical performance of the second transistor T2.

[0342] In an exemplary embodiment, the first region of the second active layer 22 in each sub-pixel is provided separately, that is, the first regions of the second active layer 22 in adjacent sub-pixels are not connected. In at least one sub-pixel, the distance between the first region of the second active layer 22 and the first power line 51 may be smaller than the distance between the second region of the second active layer 22 and the first power line 51, that is, the first region of the second active layer 22 is closer to the first power line 51 than the second region of the second active layer 22.

[0343] In an exemplary embodiment, the widths of the second active layers in adjacent sub-pixels in a first direction X are different, and the widths of the second active layers in adjacent sub-pixels in a second direction Y are different. In the first direction X, a plurality of second active layers having a larger width and a plurality of second active layers having a smaller width are alternately arranged, and in the second direction Y, a plurality of second active layers having a larger width and a plurality of second active layers having a smaller width are alternately arranged.

[0344] In an exemplary embodiment, the first subpixels P1 and the second subpixels P2 are alternately arranged in the first direction X, and the first width L1 of the second active layer 22 in the first subpixel P1 may be greater than the second width L2 of the second active layer 22 in the second subpixel P2. The third subpixels P3 and the fourth subpixels P4 are alternately arranged in the first direction X, and the third width L3 of the second active layer 22 in the third subpixel P3 may be smaller than the fourth width L4 of the second active layer 22 in the fourth subpixel P4.

[0345] In an exemplary embodiment, the first subpixels P1 and the third subpixels P3 are alternately arranged in the second direction Y, and the first width L1 of the second active layer 22 in the first subpixel P1 may be greater than the third width L3 of the second active layer 22 in the third subpixel P3. The second subpixels P2 and the fourth subpixels P4 are alternately arranged in the second direction Y, and the second width L2 of the second active layer 22 in the second subpixel P2 may be smaller than the fourth width L4 of the second active layer 22 in the fourth subpixel P4.

[0346] In an exemplary embodiment, the widths of the second active layer 22 of the four sub-pixels in at least one repeating unit may be different. For example, the first width L1 of the second active layer 22 in the first sub-pixel P1 may be greater than the fourth width L4 of the second active layer 22 in the fourth sub-pixel P4. For another example, the second width L2 of the second active layer 22 in the second sub-pixel P2 may be greater than the third width L3 of the second active layer 22 in the third sub-pixel P3.

[0347] In an exemplary embodiment, the present disclosure arranges a second active layer with a larger width and a second active layer with a smaller width alternately in the first direction X and the second direction Y, which can not only effectively match the requirements of the single scanning signal line structure, but also effectively increase the uniformity of the four pixel driving circuit layouts in the repeating unit, and effectively increase the uniformity of the four sub-pixel pixel openings in the repeating unit.

[0348] (34) A second insulating layer pattern is formed. The process and the structure of the formed second insulating layer are basically the same as those in step (14) of the aforementioned embodiment. The difference is that the second via holes V2 of each sub-pixel are separately provided, that is, adjacent sub-pixels do not share the second via holes V2, as shown in FIG19 .

[0349] In an exemplary embodiment, a plurality of via holes are provided on the second insulating layer, and the plurality of via holes of each sub-pixel in each repeating unit includes at least first to seventh via holes V1 to V7 , and the structures of the via holes are substantially the same as those in the previous embodiment.

[0350] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the first direction X share the same seventh via hole V7 , and two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the same seventh via hole V7 .

[0351] In an exemplary embodiment, adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y share the same seventh via hole V7 , that is, adjacent four sub-pixels in adjacent repeating units share the same seventh via hole V7 .

[0352] (35) A third conductive layer pattern is formed. The process and the structure of the formed third conductive layer are basically the same as those in step (15) of the aforementioned embodiment. The difference is that the power connection electrode 20 is connected to the first area of ​​the second active layer 22 of the two sub-pixels at the same time through the second via holes V2 of the two sub-pixels, as shown in Figures 20A and 20B. Figure 20B is a schematic diagram of the third conductive layer in Figure 20A.

[0353] In an exemplary embodiment, the third conductive layer of each sub-pixel in each repeating unit may include at least a fifth connecting electrode 15, a sixth connecting electrode 16, a seventh connecting electrode 17, an eighth connecting electrode 18, a power connecting electrode 20, a scanning signal line 30, a first gate electrode 31, a second gate electrode 32 and a third gate electrode 33. Except for the power connecting electrode 20, the other structures are basically the same as those in the aforementioned embodiment.

[0354] In an exemplary embodiment, the power connection electrode 20 may be in the shape of a strip extending along the first direction X, the first end of the power connection electrode 20 is connected to the first power line 51 through the seventh via hole V7, and the second end of the power connection electrode 20 is connected to the first region of the second active layer 22 through the second via hole V2, thereby enabling the first power line 51 to write the first power signal into the first electrode of the second transistor T2.

[0355] In an exemplary embodiment, the first ends of the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X may be connected to each other. For example, the first ends of the two power connection electrodes 20 in the second sub-pixel P2 of the first repeating unit Q1 and the first sub-pixel P1 of the second repeating unit Q2 are connected to each other. For another example, the first ends of the two power connection electrodes 20 in the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 are connected to each other.

[0356] In an exemplary embodiment, the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are an integrated structure connected to each other.

[0357] In an exemplary embodiment, the first ends of the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y may be connected to each other. For example, for the first repeating unit Q1 and the third repeating unit Q3 that are adjacent to each other in the second direction Y, the first ends of the power connection electrodes 20 of the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 may be connected to each other, and the first ends of the power connection electrodes 20 of the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 may be connected to each other. For another example, for the second repeating unit Q2 and the fourth repeating unit Q4 that are adjacent to each other in the second direction Y, the first ends of the power connection electrodes 20 of the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 may be connected to each other, and the first ends of the power connection electrodes 20 of the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 may be connected to each other.

[0358] In an exemplary embodiment, the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y are an integrated structure connected to each other.

[0359] In an exemplary embodiment, the power connection electrodes 20 of adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y are interconnected as a single unit. That is, the power connection electrodes 20 of four adjacent sub-pixels in adjacent repeating units are interconnected as a single unit. For example, the power connection electrode 20 in the fourth sub-pixel P4 of the first repeating unit Q1, the power connection electrode 20 in the third sub-pixel P3 of the second repeating unit Q2, the power connection electrode 20 in the second sub-pixel P2 of the third repeating unit Q3, and the power connection electrode 20 in the first sub-pixel P1 of the fourth repeating unit Q4 are interconnected as a single unit. By providing the power connection electrodes 20 of four adjacent sub-pixels in adjacent repeating units as a single unit, the present disclosure not only effectively reduces the number of vias, reduces the area occupied by the pixel drive circuit, increases the pixel aperture ratio, and improves display resolution, but also simplifies the manufacturing process, reduces production costs, and improves product yield.

[0360] In an exemplary embodiment, the subsequent process of forming the third insulating layer, the planar layer, the fourth conductive layer, the pixel definition layer, the organic light-emitting layer, the cathode and the encapsulation structure layer and the formed structure are basically the same as those in the aforementioned embodiment and are not repeated here.

[0361] The disclosed embodiments provide a bottom-emission display substrate in which the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the first direction are interconnected as an integrated structure, and the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the second direction are interconnected as an integrated structure. This effectively reduces the number of transfer vias, effectively reducing the area occupied by the pixel drive circuit, increasing the pixel aperture ratio, and improving display resolution. Furthermore, reducing the number of transfer vias can simplify the manufacturing process, reduce production costs, and improve product yield.

[0362] The display substrate of the disclosed embodiment also has the technical effects of reducing the number of patterning processes, reducing the number of scanning signal lines, and increasing the pixel aperture ratio.

[0363] The structure and preparation process shown in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit them.

[0364] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0365] The exemplary embodiments of the present disclosure further provide a method for preparing a display substrate to prepare the aforementioned display substrate. In an exemplary embodiment, the display substrate includes a plurality of repeating units, at least one of which includes a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns; the preparation method includes:

[0366] A pixel driving circuit is formed in at least one sub-pixel, and the pixel driving circuit is connected to a first power line, and the first power line is configured to provide a first power signal to the pixel driving circuit; the pixel driving circuit includes at least a driving transistor and a power connection electrode, and the driving transistor includes at least a driving active layer; in at least one sub-pixel, a first end of the power connection electrode is connected to the first power line through a power via, and a second end of the power connection electrode is connected to the first area of ​​the driving active layer through an active via; two adjacent sub-pixels in two adjacent repeating units in the pixel row direction share the power via, and two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the power via.

[0367] The present disclosure also provides a display device comprising the display substrate of the aforementioned embodiment. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0368] While the embodiments disclosed herein are as described above, it should be noted that the embodiments described above are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a plurality of repeating units, at least one of the repeating units comprising a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, at least one of the sub-pixels comprising a pixel driving circuit, the pixel driving circuit being connected to a first power line, the first power line being configured to provide a first power signal to the pixel driving circuit; The pixel driving circuit comprises at least a driving transistor and a power connection electrode, and the driving transistor comprises at least a driving active layer; In at least one sub-pixel, the first end of the power connection electrode is connected to the first power line through a power via, and the second end of the power connection electrode is connected to the first area of ​​the driving active layer through an active via; two adjacent sub-pixels in two adjacent repeating units in the pixel row direction share the power via, or / and, two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the power via.

2. The display substrate according to claim 1, wherein: The first regions of the driving active layers of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction are connected to each other.

3. The display substrate according to claim 2, wherein: The driving active layers of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction are an integrated structure connected to each other, and the driving active layer of the integrated structure has a groove. The openings of the adjacent grooves in at least one repeating unit are relatively arranged, and the groove has a groove width and a groove depth. The groove width is smaller than the groove depth. The groove width is the dimension in the pixel column direction, and the groove depth is the dimension in the pixel row direction.

4. The display substrate according to claim 1, wherein: The first ends of the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are connected to each other, and the two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the power connection electrode.

5. The display substrate according to claim 4, wherein: The power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are an integrated structure connected to each other.

6. The display substrate according to claim 2, wherein: The pixel driving circuit also includes an active connection electrode, a first end of the active connection electrode is connected to the first area of ​​the driving active layer, and the power connection electrode is simultaneously connected to the first power line and the second end of the active connection electrode through a switching via, and the switching via includes a shallow half hole and a deep half hole, the shallow half hole is an active via that exposes the second end of the active connection electrode, and the deep half hole is a power via that exposes the first power line.

7. The display substrate according to claim 6, wherein: The active connection electrode and the driving active layer are interconnected as an integral structure.

8. The display substrate according to claim 6, wherein: Two adjacent sub-pixels in two adjacent repeating units in the pixel row direction share the switching via hole, and two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the switching via hole.

9. The display substrate according to claim 6, wherein: Adjacent sub-pixels in the repeated units adjacent to each other in the pixel row direction and the pixel column direction share the transfer via hole.

10. The display substrate according to claim 6, wherein: The second ends of the active connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are connected to each other, and the two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the active connection electrode.

11. The display substrate according to claim 10, wherein: The active connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are an integrated structure connected to each other.

12. The display substrate according to claim 6, wherein: The first regions of the second active layers of adjacent sub-pixels in the repeating units adjacent to each other in the pixel row direction and the pixel column direction are connected to each other through the active connection electrode.

13. The display substrate according to claim 6, wherein: Adjacent sub-pixels in the repeated units adjacent to each other in the pixel row direction and the pixel column direction share the power connection electrode.

14. The display substrate according to claim 1, wherein: The power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are interconnected as an integrated structure, and the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction are interconnected as an integrated structure.

15. The display substrate according to any one of claims 1 to 14, wherein: At least one repeating unit includes two first power lines, four data signal lines and one compensation signal line, the compensation signal line is located between adjacent pixel columns, the two first power lines are located on both sides of the pixel row direction of the repeating unit, along the pixel row direction, the first first power line, the first data signal line, the second data signal line, the compensation signal line, the third data signal line, the fourth data signal line and the second first power line are arranged in sequence, and the driving transistor is arranged between the second data signal line and the compensation signal line or between the compensation signal line and the third data signal line.

16. The display substrate according to any one of claims 1 to 14, wherein: In at least one sub-pixel, the pixel driving circuit also includes a first connecting electrode, a second connecting electrode and a storage capacitor, the storage capacitor includes at least a first electrode plate, the first connecting electrode and the second connecting electrode are arranged on both sides of the first electrode plate in the pixel column direction, and are respectively connected to the first electrode plate; in at least one sub-pixel, the width of the first connecting electrode is smaller than the width of the second connecting electrode, and the width is the dimension in the pixel row direction.

17. The display substrate according to any one of claims 1 to 14, wherein: In a direction perpendicular to the display substrate, the display substrate includes a second conductive layer, a semiconductor layer and a third conductive layer arranged in sequence on a base, the first power line is arranged in the second conductive layer, the driving active layer is arranged in the semiconductor layer, and the power connection electrode is arranged in the third conductive layer.

18. The display substrate according to any one of claims 1 to 14, wherein: The widths of the driving active layers in adjacent sub-pixels in the pixel row direction are different, and the widths of the driving active layers in adjacent sub-pixels in the pixel column direction are different, and the width is the minimum size of the driving active layer in the pixel column direction.

19. The display substrate according to claim 18, wherein: In the direction of pixel rows, the first sub-pixel and the second sub-pixel are alternately arranged, and the width of the driving active layer in the first sub-pixel is greater than the width of the driving active layer in the second sub-pixel; or, in the direction of pixel rows, the third sub-pixel and the fourth sub-pixel are alternately arranged, and the width of the driving active layer in the third sub-pixel is less than the width of the driving active layer in the fourth sub-pixel.

20. The display substrate according to claim 18, wherein: In the direction of pixel columns, the first sub-pixel and the third sub-pixel are alternately arranged, and the width of the driving active layer in the first sub-pixel is greater than the width of the driving active layer in the third sub-pixel; or, in the direction of pixel columns, the second sub-pixel and the fourth sub-pixel are alternately arranged, and the width of the driving active layer in the second sub-pixel is less than the width of the driving active layer in the fourth sub-pixel.

21. A display device comprising the display substrate according to any one of claims 1 to 20.

22. A method for preparing a display substrate, the display substrate comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns; the method comprising: forming a pixel driving circuit in at least one sub-pixel, wherein the pixel driving circuit is connected to a first power line, and the first power line is configured to provide a first power signal to the pixel driving circuit; The pixel driving circuit comprises at least a driving transistor and a power connection electrode, and the driving transistor comprises at least a driving active layer; In at least one sub-pixel, the first end of the power connection electrode is connected to the first power line through a power via, and the second end of the power connection electrode is connected to the first area of ​​the driving active layer through an active via; two adjacent sub-pixels in two adjacent repeating units in the pixel row direction share the power via, and two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the power via.

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