Abnormality early warning method of chip testing and sorting system and medium

Abstract

The invention discloses an abnormity early warning method of a chip testing and sorting system and a medium, and relates to the technical field of chip testing and sorting, and the abnormity early warning method comprises the following steps: collecting demand information; carrying out loading parameter and test parameter configuration optimization based on the demand information to obtain a loading parameter set and a test standard value set; debugging the loading module and the test module according to the sets, and performing chip positioning detection to obtain first abnormal information; the chip is detected, the sensor array is called to continuously monitor the test parameters, and a monitoring value set is obtained; identifying an exception based on the test standard value set, and generating second exception information; and sending the two types of abnormal information to a worker. According to the invention, the technical problems of low chip test efficiency and poor reliability caused by inaccurate chip placement position are solved, and the technical effects of continuously monitoring key test parameters in the preset monitoring window by calling the test sensor array and improving the chip placement accuracy and the chip test efficiency and reliability are achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing and sorting, and in particular to an abnormality early warning method and medium for a chip testing and sorting system. Background Art

[0002] With the continuous advancement of chip manufacturing technology, the chip test and sorting system, as an important link to ensure chip quality and performance, has become increasingly important. However, while pursuing higher production efficiency and lower costs, a key problem in the chip test and sorting process has gradually emerged. Traditional chip test and sorting systems often lack high-precision real-time monitoring and feedback mechanisms in the chip placement link, which makes the chip placement position prone to deviations. This deviation not only affects the accuracy of the test results, but may also damage the test equipment and reduce overall production efficiency. For example, if the chip is not accurately placed on the test pin, the test signal may not be transmitted correctly, resulting in misjudgment or missed detection; at the same time, the biased chip may also generate additional stress when in contact with the test equipment, accelerating the wear of the equipment. Summary of the invention

[0003] The present application provides an abnormal warning method and medium for a chip testing and sorting system, which are used to solve the technical problem of low chip testing efficiency and poor reliability due to inaccurate chip placement.

[0004] In view of the above problems, the present application provides an abnormal warning method and medium for a chip testing and sorting system.

[0005] The first aspect of the present application provides an abnormal warning method for a chip test sorting system, the method comprising: collecting test requirement information of a target chip test task, wherein the test requirement information includes the amount of test chips, the type of test chips, and the test items; optimizing the loading parameters and test parameter configurations of the chip test sorting system based on the amount of test chips, the type of test chips, and the test items, and obtaining a loading parameter set and a test parameter standard value set; debugging a loading module and a test module of the chip test sorting system according to the loading parameter set and the test parameter standard value set, and transferring a plurality of test chips on a loading vibration plate to a test position by using the debugged loading module. The method comprises the following steps: positioning and detecting the plurality of test chips at the test position by using a visual detection module to obtain first abnormal warning information; detecting the plurality of test chips at the test position in sequence by using the test module, calling a test sensor array to continuously monitor the parameters of the test module within a preset monitoring window, and obtaining a set of test parameter monitoring values; performing centralized abnormal identification on the set of test parameter monitoring values ​​based on the set of test parameter standard values, and generating second abnormal warning information; using the first abnormal warning information and the second abnormal warning information as system abnormal warning information of the chip test and sorting system, and sending the system abnormal warning information to staff.

[0006] According to a second aspect of the present application, a storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented: Collect test requirement information of the target chip test task, wherein the test requirement information includes the amount of test chips, the type of test chips and the test items; optimize the loading parameters and test parameter configuration of the chip test sorting system based on the amount of test chips, the type of test chips and the test items, and obtain a loading parameter set and a test parameter standard value set; debug the loading module and the test module of the chip test sorting system according to the loading parameter set and the test parameter standard value set, transfer a plurality of test chips on the loading vibration plate to the test position by using the debugged loading module, and perform positioning detection on the plurality of test chips at the test position by using the visual detection module to obtain first abnormal warning information; detect the plurality of test chips at the test position in turn by using the test module, call the test sensor array to continuously monitor the parameters of the test module within a preset monitoring window, and obtain a test parameter monitoring value set; perform centralized abnormal identification on the test parameter monitoring value set based on the test parameter standard value set, and generate second abnormal warning information; use the first abnormal warning information and the second abnormal warning information as system abnormal warning information of the chip test sorting system, and send the system abnormal warning information to the staff.

[0007] One or more technical solutions provided in this application have at least the following technical effects or advantages: The method provided in the embodiment of the present application collects test requirement information of a target chip test task, wherein the test requirement information includes the amount of test chips, the type of test chips and the test items; based on the amount of test chips, the type of test chips and the test items, the loading parameters and test parameter configuration of the chip test sorting system are optimized to obtain a loading parameter set and a test parameter standard value set; according to the loading parameter set and the test parameter standard value set, the loading module and the test module of the chip test sorting system are debugged, and the debugged loading module is used to transfer a plurality of test chips on a loading vibration plate to a test position, and the visual detection module is used to locate and detect the plurality of test chips at the test position to obtain first abnormal warning information; the test module is used to detect the plurality of test chips at the test position in turn, and the test sensor array is called to continuously monitor the parameters of the test module within a preset monitoring window to obtain a test parameter monitoring value set; based on the test parameter standard value set, the test parameter monitoring value set is centrally identified as abnormal, and a second abnormal warning information is generated; the first abnormal warning information and the second abnormal warning information are used as system abnormal warning information of the chip test sorting system, and the system abnormal warning information is sent to a staff member. The technical effect of continuously monitoring key test parameters within a preset monitoring window by calling the test sensor array is achieved, thereby improving the accuracy of chip placement, as well as the efficiency and reliability of chip testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic flow chart of the abnormal warning method for the chip testing and sorting system provided in this application.

[0009] Figure 2 A schematic diagram of the process of obtaining a loading parameter set and a test parameter standard value set in the abnormal warning method of the chip testing and sorting system provided in the present application. DETAILED DESCRIPTION

[0010] The present application provides an abnormal warning method and medium for a chip testing and sorting system, which is used to solve the technical problem of low chip testing efficiency and poor reliability due to inaccurate chip placement, and achieves the technical effect of continuously monitoring key test parameters within a preset monitoring window by calling a test sensor array, thereby improving the accuracy of chip placement, as well as the efficiency and reliability of chip testing.

[0011] Below, the technical solutions in the present invention will be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments of the present invention. It should be understood that the present invention is not limited to the example embodiments described herein. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. It should also be noted that, for the convenience of description, only the parts related to the present invention are shown in the accompanying drawings, rather than all of them.

[0012] Embodiment 1, as Figure 1 As shown, the present application provides an abnormal warning method for a chip testing and sorting system, the method comprising: The test requirement information of the target chip test task is collected, wherein the test requirement information includes the test chip quantity, test chip type and test items.

[0013] In the embodiment of the present application, in order to complete the test task efficiently and accurately, the system terminal first comprehensively collects the test requirement information about the target chip. This information is the key to guiding the entire test process, including the amount of test chips, the type of test chips and the test items. Among them, the amount of test chips refers to the total number of chips that need to be tested in the test task. Understanding the amount of test chips helps to rationally plan test resources, such as test equipment, time arrangements, etc., to ensure that the test task can be completed on time. The type of test chip refers to the type of chip that needs to be tested, and each chip has its specific functions, structures and performance requirements. Understanding the type of test chip is crucial to selecting appropriate test equipment, test parameters, etc. to ensure the accuracy and effectiveness of the test results. The test items list in detail the various test contents that need to be performed on the chip, such as functional testing, performance testing, reliability testing, etc. These test items are designed to comprehensively evaluate whether the various indicators of the chip meet the design requirements or customer standards. Clarifying the test items helps to develop a detailed test plan to ensure that the test process covers all key points and does not miss any important test links.

[0014] Based on the test chip quantity, test chip type and test items, the loading parameters and test parameter configurations of the chip test sorting system are optimized to obtain a loading parameter set and a test parameter standard value set.

[0015] In one embodiment, the system terminal performs a series of parameter configuration optimization processes for the chip test sorting system based on the collected test chip quantity, test chip type and test project information. This process aims to calculate the similarity with the pre-built chip test database by taking the collected test chip quantity, test chip type and test project information as the target, and arrange the calculation results in descending order to obtain multiple sample system configuration parameters that meet the standards, each sample system configuration parameter includes a sample loading parameter set and a sample test parameter standard value set. Then, these sample coefficient configuration parameters are averaged to obtain a loading parameter set and a test parameter standard value set.

[0016] Furthermore, the present application provides a set of loading parameters and a set of test parameter standard values, including: The loading parameter set includes carrier type, positioning method, chip placement position, single loading chip density, and loading speed; the test parameter standard value set includes test voltage standard value, test environment temperature standard value, and test signal frequency standard value.

[0017] Preferably, in the chip test sorting system, the loading parameter set and the test parameter standard value set are important foundations for ensuring the smooth progress of the test process and accurate and reliable results. The loading parameter set specifically covers multiple aspects. The first is the carrier type, which determines the support and fixation method of the chip during the loading process; the second is the positioning method, which ensures that the chip can be accurately placed in the test position; the chip placement position further refines the specific position of the chip on the carrier to ensure that the test pins or sensors can be accurately docked; the single loading chip density is related to the number of chips that can be processed simultaneously in a test, affecting the test efficiency; and the loading speed refers to the speed at which the chip is loaded from the test position, which also needs to be reasonably set according to the test requirements and equipment performance. On the other hand, the test parameter standard value set puts forward specific requirements for the test process itself, including the test voltage standard value, the test environment temperature standard value, and the test signal frequency standard value. The standard value of test voltage ensures that the voltage applied during the test is within the tolerable range of the chip and meets the test accuracy requirements; the standard value of test environment temperature takes into account the impact of temperature on chip performance and eliminates or reduces the error caused by this factor by controlling the test environment temperature; the standard value of test signal frequency is related to the test item, which determines the characteristics of the test signal and the choice of test method.

[0018] Further, if Figure 2 As shown, the present application provides a method for obtaining the loading parameter set and the test parameter standard value set, including: Construct a chip test database, wherein the chip test database includes multiple sample test requirement information and multiple sample system configuration parameters, wherein each sample system configuration parameter includes a sample loading parameter set and a sample test parameter standard value set; taking the test chip quantity, test chip type and test item as the target, perform similarity calculation with multiple sample test requirement information in the chip test database to obtain multiple sample similarities; perform mean calculation on K sample system configuration parameters corresponding to K sample test requirement information that are in the top k positions among the multiple sample similarities to obtain the loading parameter set and the test parameter standard value set.

[0019] Preferably, the system terminal first constructs a chip test database, which stores sample test requirement information and corresponding sample system configuration parameters when performing chip tests under various different circumstances. Each sample test requirement information includes the sample test chip quantity, sample test chip type and sample test item. Each sample system configuration parameter records in detail the sample loading parameter set and sample test parameter standard value set for a specific test, which are accumulated from past actual tests. When a new test task is performed, the system terminal traverses the sample test requirement information in the chip test database with the number, type and specific test items of the test chip as the target. Before traversal, the system terminal first normalizes the test chip quantity, that is, the difference between the test chip quantity and the minimum value of the sample test chip quantity in the chip test database is calculated, and then the calculation result is compared with the difference between the maximum and minimum values ​​of the sample test chip quantity in the chip test database to obtain a test chip quantity vector. Subsequently, the test chip type is converted into a unique hot encoding to obtain a unique hot encoding vector, and then the test item is converted into a numerical vector by word embedding. Afterwards, the system terminal merges the test chip quantity vector, the one-hot encoding vector and the numerical vector into a unified vector, namely the target feature vector. In each traversal, the system terminal performs the same operation on the sample test chip quantity, sample test chip type and sample test item in the current sample test requirement information to obtain the current sample feature vector. Then, the cosine similarity is used to calculate the angle between the current sample feature vector and the target feature vector to quantify the similarity between the test requirement information and the current sample test requirement information. By traversing the chip test database, the system terminal can obtain multiple similarities, each of which corresponds to a sample test requirement information. Finally, the system terminal arranges these similarities in descending order and extracts the top k sample test requirement information as reference. The sample system configuration parameters corresponding to these K sample test requirement information, namely the sample loading parameter set and the sample test parameter standard value set, are considered to be the most matched with the test requirement information. In order to obtain the final system configuration parameters, the system terminal calculates the mean of the K sample system configuration parameters. The purpose of this is to obtain a more balanced and optimized configuration scheme by integrating the configurations of multiple similar samples, namely, the loading parameter set and the test parameter standard value set. These two sets will provide strong support for subsequent chip testing.

[0020] The loading module and the testing module of the chip testing and sorting system are debugged according to the loading parameter set and the testing parameter standard value set, and the debugged loading module is used to transfer multiple test chips on the loading vibration plate to the testing position, and the visual inspection module is used to locate and inspect the multiple test chips at the testing position to obtain the first abnormal warning information.

[0021] In one embodiment, during the configuration optimization process of the chip test sorting system, once the loading parameter set and the test parameter standard value set are determined, the system terminal will debug the loading module and the test module of the chip test sorting system. This process is to ensure that the chip test sorting system can accurately perform the chip loading and testing tasks according to the predetermined parameter settings. After the debugging is completed, the loading module will start working, and it will take out multiple test chips from the feeding vibration plate one by one, and transfer them to the preset test position stably and accurately. In this process, the loading module will operate according to the previously set loading parameters to ensure that the chip can reach the test position smoothly and accurately. When the chip is placed in the test position, the system terminal will start the visual detection module to locate and detect them. The visual detection module uses image processing and recognition technology to accurately identify the specific position and posture of the chip at the test position. Through this step, the system terminal can promptly discover and handle any possible position deviation or posture error, thereby ensuring that the subsequent test process can proceed smoothly. If an abnormal situation is found during the positioning detection process, such as chip position deviation, incorrect posture, etc., the visual detection module will immediately generate the first abnormal warning information to ensure the accuracy and reliability of the entire test process.

[0022] Furthermore, the present application provides obtaining the first abnormal warning information, including: The visual inspection module is used to collect positioning images of the multiple test chips respectively to obtain multiple positioning images; a standard image of the test chip of the target chip test task at the test position is collected, and the standard image and the multiple positioning images are respectively input into the first comparison branch and the second comparison branch of the twin comparison network layer to obtain a standard image feature set and multiple positioning image feature sets, wherein the first comparison branch and the second comparison branch are shared weight network layers, and the number of features of the standard image feature set is consistent with that of any positioning image feature set.

[0023] Preferably, in the visual inspection process, the system terminal activates the visual inspection module, and performs positioning image acquisition on multiple test chips to generate a series of positioning images corresponding to the position of each test chip. These images provide basic data for subsequent analysis and comparison. Subsequently, in order to evaluate the accuracy and consistency of the test chip at the test position, the system terminal collects the standard image of the test chip in the target chip test task. This standard image represents the correct position and posture that the test chip should have at the test position. In order to efficiently and accurately compare the difference between the standard image and the multiple positioning images, the system terminal activates the pre-built twin comparison network layer. The twin comparison network layer is constructed based on the twin neural network. The system terminal inputs the standard image and each positioning image into two branches of the twin comparison network layer, namely the first comparison branch and the second comparison branch. These two branches are network layers that share weights, they have the same network structure and parameters, and can extract image features in the same way. Through this setting, the system terminal can obtain a standard image feature set and multiple positioning image feature sets respectively. Since the two comparison branches share weights, the number of features in the standard image feature set is consistent with that in any positioning image feature set, which facilitates subsequent feature comparison and similarity calculation.

[0024] For the twin comparison network layer, the system terminal first initializes two identical convolutional neural network architectures according to data characteristics and actual needs, and constructs the twin comparison network layer from these two convolutional neural network architectures. Subsequently, in the twin comparison network layer, the two convolutional neural network architecture structures are used as the first comparison branch and the second comparison branch with weight sharing. These two branches will process the standard image and the positioning image respectively. Since the weights are shared, the two branches will use the same parameters and calculation methods when extracting features. In each branch, the input image is feature extracted through structures such as convolutional layers and pooling layers. As the network goes deeper, the extracted features will gradually change from low-level edge and texture information to high-level semantic information. At the end of each branch, that is, after the last convolutional layer or pooling layer, this convolutional layer or pooling layer is directly connected to the output layer to directly output the output of the convolutional layer or pooling layer as a feature set. Afterwards, the system terminal uses the sample data set containing the sample standard image and the sample positioning image to construct positive and negative sample pairs, that is, select image pairs containing similar or identical content from the sample data set as positive sample pairs, for example, pair the standard image with the image of the test chip correctly placed at the test position. Select image pairs containing different content as negative sample pairs, for example, pair the standard image with the image of the test chip that is incorrectly placed or completely different at the test position. Then integrate the pre-built loss analysis function. Then, the sample standard image and the sample positioning image are respectively input into the two branches of the twin network for feature extraction. The loss between the feature sets output by the network is calculated using the loss analysis function. The weights of the network are optimized by the back propagation algorithm to minimize the positioning loss value. During the training process, the system terminal uses data augmentation technology to increase the diversity of positive sample pairs, such as cropping, rotating, flipping, etc. on the input image. Dynamic sampling is used to optimize the selection of negative samples to improve training efficiency and effect. Finally, when the positioning loss value meets the preset positioning loss threshold, the system terminal stops the training process and stores the current twin comparison network layer.

[0025] Call the loss analysis function of the twin comparison network layer, perform loss analysis on the standard image feature set and the multiple positioning image feature sets, and obtain multiple positioning loss values; determine whether there is a positioning loss value greater than or equal to a preset loss value among the multiple positioning loss values, and if so, obtain the first abnormal warning information.

[0026] Preferably, the system terminal uses the trained twin comparison network layer to extract features from the standard image and multiple positioning images respectively, and obtains a standard image feature set and multiple positioning image feature sets. These feature sets represent the representation of the image in the high-level semantic space. Subsequently, the loss analysis function built into the twin comparison network layer is called to compare the standard image feature set with each positioning image feature set, and calculate multiple positioning loss values ​​between them. Each positioning loss value reflects the degree of dissimilarity between the corresponding positioning image and the standard image. Afterwards, the system terminal sets a preset loss value according to actual needs and expert advice to determine whether the positioning is accurate. Then, by traversing all positioning loss values, check whether there is a loss value greater than or equal to the threshold. If such a loss value exists, it means that the difference between the corresponding positioning image and the standard image exceeds the acceptable range, that is, the positioning may be inaccurate. When a positioning loss value greater than or equal to the preset loss value is found, the system terminal generates a first abnormal warning message. The first abnormal warning message is used to remind the staff that there is currently an inaccurate positioning situation.

[0027] Furthermore, the present application provides a loss analysis function, including: The loss analysis function is: ; in, is the positioning loss value, is the i-th standard image feature in the standard image feature set, is the i-th positioning image feature in the positioning image feature set, m is the number of features in the standard image feature set, and m is a positive integer greater than or equal to 1.

[0028] Optionally, the loss analysis function pre-built in the system terminal calculates the sum of the squares of each feature in the standard image feature set and the positioning image feature set, takes the square root, and then calculates the sum of the products of the corresponding features in the standard image feature set and the positioning image feature set. Subsequently, the calculated square root result is ratioed with the second sum to calculate the positioning loss value. The loss analysis function is as follows: ;in, The positioning loss value is a scalar value used to quantify the difference between the standard image feature set and the positioning image feature set. The smaller the loss value, the more similar the two are; the larger the loss value, the greater the difference between the two. is the i-th standard image feature in the standard image feature set. In this set, there are m such features, and each feature describes different aspects of the standard image. is the i-th positioning image feature in the positioning image feature set, and m is the number of features in the standard image feature set, which is also the number of features corresponding to it in the positioning image feature set. m is a positive integer greater than or equal to 1.

[0029] The test module is used to detect multiple test chips at the test position in sequence, and a test sensor array is called to continuously monitor the parameters of the test module within a preset monitoring window to obtain a set of test parameter monitoring values.

[0030] In one embodiment, the system terminal uses the test module to detect multiple test chips located at the test position. The test module detects multiple test chips at the test position one by one. This process is intended to evaluate whether the performance, function or quality of each test chip meets the expected standards. While the test chip is being detected, the system terminal calls the test sensor array. This sensor array continuously monitors the key parameters of the test module and the test environment according to the preset monitoring window. These parameters include temperature, humidity, voltage, current, electromagnetic interference, etc., which are crucial to the accuracy and reliability of the test results. During the preset monitoring window, the test sensor array continuously collects and records the real-time data of these key parameters. This process ensures that the key environmental conditions and the status of the test module are accurately captured and recorded throughout the test process. Through continuous monitoring, the test sensor array generates a set of all key parameter monitoring values, that is, a test parameter monitoring value set. This set is an important basis for the subsequent analysis of the second abnormal warning information.

[0031] Based on the test parameter standard value set, the test parameter monitoring value set is centrally identified for abnormalities, and second abnormal warning information is generated.

[0032] In one embodiment, in order to evaluate whether the test process is carried out normally, the system terminal calculates the difference between the test parameter standard value set and the test parameter monitoring value set, and screens the calculation results according to the test parameter type. Subsequently, the system terminal constructs a box plot according to the screening results for judging abnormal values. When an abnormality is judged according to the box plot, the system terminal generates a second abnormal warning information.

[0033] Furthermore, the present application provides obtaining the second abnormal warning information, including: The differences between the test parameter standard value set and the test parameter monitoring value set are respectively calculated to obtain a test parameter deviation value set; the test parameter deviation value set is screened according to the test parameter type to obtain Q screened test parameter deviation value sets.

[0034] Preferably, the system terminal performs difference calculation on each corresponding element in the test parameter standard value set and the test parameter monitoring value set. This difference represents the deviation between the parameter value actually monitored and the preset standard value. By traversing these two sets, a set containing all parameter deviation values, i.e., the test parameter deviation value set, can be obtained. Each element in this set corresponds to the deviation of a specific parameter, which reflects the difference between the actual performance and the expected performance of the parameter during the test. In order to analyze these deviation values ​​more carefully, the system terminal screens the test parameter deviation value set according to the type of the test parameter. Different test parameters represent different physical quantities or performance indicators, and their influence on the test results and their importance may also be different. Therefore, classifying the deviation values ​​according to the parameter type helps to more clearly understand which types of parameters have large deviations during the test process, and the impact that these deviations may have on the test results. Through screening, the system terminal obtains Q screening test parameter deviation value sets, where Q represents the number of different types of test parameters. Each screening set contains deviation values ​​belonging to the same type of parameters, which is convenient for subsequent targeted analysis and processing.

[0035] Respectively calculate the Q first quartiles and the Q third quartiles of the Q screening test parameter deviation value sets; count the test parameter deviation values ​​between the Q first quartiles and the Q third quartiles to obtain Q first set screening test parameter deviation value sets.

[0036] Preferably, the system terminal performs statistical analysis on Q sets of screening test parameter deviation values, and calculates the first quartile (Q1) and the third quartile (Q3) for each set. Quartiles are numbers that divide a set of data into four equal parts, where the first quartile Q1 indicates that 25% of the data is smaller than it, and the third quartile Q3 indicates that 75% of the data is smaller than it. Subsequently, all deviation values ​​between Q1 and Q3 of each screening test parameter deviation value set are counted. This range is generally considered to be the main part of the data distribution, excluding extreme small and large values, so as to more accurately reflect the central trend and stability of the data. Through this process, the system terminal obtains Q sets of screening test parameter deviation values ​​in the first set, each set containing the main part of the corresponding type of parameter deviation values, that is, those deviation values ​​that are neither extremely small nor extremely large.

[0037] Calculate the mean of the Q first concentrated screening test parameter deviation value sets, and compare the calculation result with the Q test parameter standard values ​​in the test parameter standard value set to obtain Q first abnormal concentration coefficients; determine whether there is a first abnormal concentration coefficient less than a preset concentration coefficient threshold among the Q first abnormal concentration coefficients, and if not, obtain the second abnormal warning information.

[0038] Preferably, the system terminal performs mean calculation on the Q first concentrated screening test parameter deviation value sets. The mean is an important indicator reflecting the trend of data concentration, which can help understand the average level of each type of parameter deviation value. Subsequently, these means are compared with the corresponding test parameter standard values, and Q first abnormal concentration coefficients are obtained by calculating their ratios. These coefficients reflect the degree of deviation of the actual deviation mean relative to the standard value, and are an important basis for evaluating the stability and reliability of the test process. Subsequently, the system terminal sets a preset concentration coefficient threshold value to determine whether an abnormal deviation concentration phenomenon occurs during the test process. The system terminal compares the Q first abnormal concentration coefficients one by one to determine whether any coefficient is less than this threshold. If it is found that any first abnormal concentration coefficient is less than or equal to the preset concentration coefficient threshold value, it means that the test parameters of the corresponding type have abnormal deviation concentration during the actual test process, which may be caused by various reasons such as the instability of the test environment, the failure of the test equipment, and the defects of the test method. At this time, the system terminal generates a second abnormal warning information to remind the staff to ensure the accuracy and reliability of the test process.

[0039] Furthermore, the present application provides obtaining the second abnormal warning information, including: Perform difference calculation based on the Q first quartiles and the Q third quartiles to obtain Q interquartile ranges; obtain an abnormal upper edge based on the Q first quartiles and the Q interquartile ranges; obtain an abnormal lower edge based on the Q third quartiles and the Q interquartile ranges; count the amount of data located outside the abnormal upper edge and the abnormal lower edge in the Q screening test parameter deviation value sets to obtain Q abnormal data amounts; determine whether there is an abnormal data amount greater than or equal to a preset abnormal data amount among the Q abnormal data amounts, and if so, obtain the second abnormal warning information.

[0040] Optionally, the system terminal calculates the interquartile range (IQR) for each of the Q screening test parameter deviation value sets, that is, the difference between the third quartile and the first quartile of each set. The interquartile range is an indicator for measuring the width of data distribution and is of great significance in identifying outliers. Subsequently, these interquartile ranges are used to define the boundaries of outliers. Specifically, for each screening set, the system terminal obtains the abnormal upper edge by adding one or more interquartile ranges to its first quartile, which means that the deviation value greater than this value is considered abnormal; similarly, the abnormal lower edge is obtained by subtracting one or more interquartile ranges from its third quartile, which means that the deviation value less than this value is also considered abnormal. These boundaries help the system terminal distinguish between normal values ​​and abnormal values ​​in the data. Afterwards, the amount of data outside these abnormal boundaries in each screening set is counted, that is, the amount of abnormal data. This number reflects the proportion of abnormal values ​​in the deviation values ​​of the test parameters of this type, and is an important indicator for evaluating the stability and reliability of the test process. Then, a threshold value of abnormal data volume is preset to determine whether enough abnormal values ​​appear during the test process, so that an early warning needs to be issued. If the amount of abnormal data in any screening set is greater than or equal to this threshold, it means that there is a significant abnormality in the deviation value of the test parameter of this type, which may be caused by problems with the test environment or equipment. At this time, the system terminal generates a second abnormal warning message to alert the staff.

[0041] The first abnormal warning information and the second abnormal warning information are used as system abnormal warning information of the chip testing and sorting system, and the system abnormal warning information is sent to the staff.

[0042] In one embodiment, after obtaining the first abnormal warning information and the second abnormal warning information, the system terminal combines the two warning information as the system abnormal warning information of the chip test sorting system. This system abnormal warning information will be sent to the staff responsible for monitoring and maintaining the test sorting system in a timely manner to ensure the smooth progress of the test process and the accuracy of the test results.

[0043] In summary, the embodiments of the present application have at least the following technical effects: The embodiment of the present application optimizes the loading and test parameter configuration of the chip test sorting system according to the test demand information, and then ensures that the chip test sorting system is ready through debugging. During the test process, the visual detection module is used to locate the test chip, and once a deviation is found, the first abnormal warning information is generated. At the same time, when the test module detects the chip, the test sensor array continuously monitors the key parameters, compares them with the standard values, identifies the abnormal concentration phenomenon through statistical analysis, and generates the second abnormal warning information. If any warning information is triggered, the system terminal will send this information to the staff as the system abnormal warning information. In addition, a chip test database is constructed to assist in the optimization of configuration parameters, and the accuracy of visual positioning detection is verified by using a twin comparison network. Afterwards, by calculating statistical indicators such as deviation value, interquartile range and abnormal data volume, the process of abnormal identification is further refined to ensure the accuracy and timeliness of the warning information. These technical effects jointly solve the technical problems of low chip test efficiency and poor reliability due to inaccurate chip placement, and achieve the technical effects of continuously monitoring key test parameters in a preset monitoring window by calling the test sensor array, improving the accuracy of chip placement, and the efficiency and reliability of chip testing.

[0044] Embodiment 2, based on the same inventive concept as the abnormal warning method of the chip test sorting system in the aforementioned embodiment, the present application provides a storage medium, which can be a ROM or other types of static storage devices that can store static information and instructions, RAM or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to this. The memory can exist independently and be connected to the processor through a bus architecture. The memory can also be integrated with the processor.

[0045] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0046] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, if these modifications and variations of the present application belong to the scope of the present application and its equivalent technology, the present application intends to include these modifications and variations.

Claims

1. An abnormal warning method for a chip testing and sorting system, characterized in that: The method comprises: Collecting test requirement information of the target chip test task, wherein the test requirement information includes the test chip quantity, test chip type and test items; Based on the test chip quantity, test chip type and test items, optimize the loading parameters and test parameter configuration of the chip test sorting system to obtain a loading parameter set and a test parameter standard value set; Debugging the loading module and the testing module of the chip testing and sorting system according to the loading parameter set and the testing parameter standard value set, transferring a plurality of testing chips on the feeding vibration plate to a testing position by using the debugged loading module, and performing positioning detection on the plurality of testing chips at the testing position by using the visual detection module to obtain first abnormal warning information; Using the test module to detect multiple test chips at the test position in sequence, calling the test sensor array to continuously monitor the parameters of the test module within a preset monitoring window, and obtaining a set of test parameter monitoring values; Based on the test parameter standard value set, the test parameter monitoring value set is centrally identified as abnormal, and second abnormal warning information is generated; The first abnormal warning information and the second abnormal warning information are used as system abnormal warning information of the chip testing and sorting system, and the system abnormal warning information is sent to the staff.

2. The abnormality warning method of the chip testing and sorting system according to claim 1, characterized in that: The loading parameter set includes carrier type, positioning method, chip placement position, single loading chip density, and loading speed; The test parameter standard value set includes a test voltage standard value, a test environment temperature standard value, and a test signal frequency standard value.

3. The abnormality warning method of the chip testing and sorting system according to claim 1, characterized in that: include: Constructing a chip test database, wherein the chip test database includes a plurality of sample test requirement information and a plurality of sample system configuration parameters, wherein each sample system configuration parameter includes a sample loading parameter set and a sample test parameter standard value set; Taking the test chip quantity, test chip type and test items as targets, similarity calculation is performed with multiple sample test requirement information in the chip test database to obtain multiple sample similarities; The K sample system configuration parameters corresponding to the K sample test requirement information located in the top k positions among the multiple sample similarities are averaged to obtain the loading parameter set and the test parameter standard value set.

4. The abnormality warning method of the chip testing and sorting system according to claim 1, characterized in that: include: Using the visual inspection module to collect positioning images of the multiple test chips respectively to obtain multiple positioning images; Collecting a standard image of the test chip of the target chip test task at the test position, inputting the standard image and the multiple positioning images into a first comparison branch and a second comparison branch of a twin comparison network layer respectively, to obtain a standard image feature set and multiple positioning image feature sets, wherein the first comparison branch and the second comparison branch are shared weight network layers, and the number of features of the standard image feature set and any one of the positioning image feature sets is consistent; Calling the loss analysis function of the twin comparison network layer to perform loss analysis on the standard image feature set and the multiple positioning image feature sets to obtain multiple positioning loss values; It is determined whether there is a positioning loss value greater than or equal to a preset loss value among the multiple positioning loss values. If so, the first abnormal warning information is obtained.

5. The abnormality warning method of the chip testing and sorting system as claimed in claim 4, characterized in that: The loss analysis function is: ； in, is the positioning loss value, is the i-th standard image feature in the standard image feature set, is the i-th positioning image feature in the positioning image feature set, m is the number of features in the standard image feature set, and m is a positive integer greater than or equal to 1.

6. The abnormality warning method of the chip testing and sorting system according to claim 1, characterized in that: include: Calculate the difference between the test parameter standard value set and the test parameter monitoring value set respectively to obtain a test parameter deviation value set; Screening the test parameter deviation value set according to the test parameter type to obtain Q screened test parameter deviation value sets; Respectively calculating the Q first quartiles and Q third quartiles of the Q screening test parameter deviation value sets; Counting the test parameter deviation values ​​between the Q first quartiles and the Q third quartiles to obtain Q first concentrated screening test parameter deviation value sets; Calculate the mean of the Q first concentrated screening test parameter deviation value sets, and compare the calculated result with the Q test parameter standard values ​​in the test parameter standard value set to obtain Q first abnormal concentration coefficients; It is determined whether there is a first abnormal concentration coefficient less than a preset concentration coefficient threshold among the Q first abnormal concentration coefficients; if not, the second abnormal warning information is obtained.

7. The abnormality warning method of the chip testing and sorting system according to claim 6, characterized in that: include: Perform difference calculation based on the Q first quartiles and the Q third quartiles to obtain Q interquartile ranges; Based on the Q first quartiles and the Q interquartile ranges, obtaining an abnormal upper edge; Based on the Q third quartiles and the Q interquartile ranges, obtaining an abnormal lower edge; Counting the amount of data outside the abnormal upper edge and the abnormal lower edge in the Q screening test parameter deviation value sets to obtain Q abnormal data amounts; It is determined whether there is an abnormal data amount greater than or equal to a preset abnormal data amount among the Q abnormal data amounts. If so, the second abnormal warning information is obtained.

8. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the abnormality warning method for a chip testing and sorting system described in any one of claims 1 to 7 are implemented.

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