Display panel and display device

Abstract

The invention provides a display panel and a display device, relates to the technical field of display, and is used for improving the performance of a transistor structure in a display product. The display panel comprises a substrate, a plurality of scanning lines, a plurality of data lines and a plurality of pixel units, wherein the scanning lines, the data lines and the pixel units are arranged on the substrate; each pixel unit comprises a transistor structure and a pixel electrode; the transistor structure comprises at least two sub-transistors which are connected in parallel, the grid electrode of each sub-transistor is coupled with the corresponding scanning line, the first electrode of each sub-transistor is coupled with the corresponding data line, and the second electrode of each sub-transistor is coupled with the pixel electrode.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, there are more and more types of display products and their application fields are becoming more and more extensive. Common types of display products include electronic paper, liquid crystal display products, organic light-emitting diode display products, etc. These display products all include transistor structures, which can realize display functions through transistor structure control. However, the performance of the transistor structure in current display products is not compatible with many aspects such as current output capability, drift requirements, heat requirements, and voltage resistance requirements. Therefore, how to further optimize the performance of the transistor structure in display products has become a technical problem that needs to be solved urgently. Summary of the invention

[0003] An object of the present invention is to provide a display panel and a display device for improving the performance of a transistor structure in a display product.

[0004] In order to achieve the above object, the present invention provides the following technical solutions:

[0005] A first aspect of the present invention provides a display panel, comprising: a base substrate, and a plurality of scan lines, a plurality of data lines and a plurality of pixel units arranged on the base substrate; the pixel unit comprises a transistor structure and a pixel electrode; the transistor structure comprises at least two sub-transistors connected in parallel, the gate of each sub-transistor is coupled to the corresponding scan line, the first electrode of each sub-transistor is coupled to the corresponding data line, and the second electrode of each sub-transistor is coupled to the pixel electrode.

[0006] Optionally, the sub-transistor includes an active pattern, the active patterns in the at least two sub-transistors are arranged sequentially along the first direction, and the spacing d1 between adjacent active patterns satisfies: 1.5L1≤d1≤2.5L1, wherein L1 is the channel length of the sub-transistor.

[0007] Optionally, the gate of each sub-transistor is formed as a gate pattern of an integrated structure, the gate pattern extends along the first direction and is coupled to the corresponding scan line;

[0008] The first electrode of the sub-transistor is located at a first side of the sub-transistor along the second direction and extends in a direction away from the gate pattern along the second direction; the first electrodes of the sub-transistors are arranged along the first direction, and the first electrodes of the sub-transistors are respectively coupled to the corresponding data lines;

[0009] The second pole of the sub-transistor is located on the second side of the sub-transistor along the second direction and extends along the second direction in a direction away from the gate pattern; the second poles of each sub-transistor are arranged along the first direction, and the second poles of each sub-transistor are respectively coupled to the conductive connection pattern, and the conductive connection pattern is coupled to the pixel electrode.

[0010] Optionally, the pixel unit further includes a light shielding layer, and an orthographic projection of the light shielding layer on the base substrate at least partially overlaps with an orthographic projection of a channel region of each sub-transistor on the base substrate.

[0011] Optionally, the light shielding layer is coupled to the second electrode of each sub-transistor.

[0012] Optionally, the pixel unit further includes a first conductive connection portion and a storage capacitor; the gate of each sub-transistor in the pixel unit is coupled to the corresponding scan line through the first conductive connection portion, and the second electrode of each sub-transistor is coupled to the first electrode plate of the storage capacitor;

[0013] The first conductive connection portion extends along a first direction, and a length L2 of the first conductive connection portion along the first direction is ≥ (1 / 3)*L3, wherein L3 is a length of the first electrode plate of the storage capacitor along the first direction.

[0014] Optionally, an orthographic projection of the second electrode plate of the storage capacitor on the base substrate at least partially overlaps with an orthographic projection of the first conductive connecting portion on the base substrate.

[0015] Optionally, an orthographic projection of the second electrode plate of the storage capacitor on the substrate does not overlap with an orthographic projection of the first conductive connecting portion on the substrate;

[0016] The first electrode plate of the storage capacitor comprises a first electrode plate main body and a first electrode plate compensation part coupled to each other, wherein the orthographic projection of the first electrode plate main body on the substrate is located between the orthographic projection of the first electrode plate compensation part on the substrate and the orthographic projection of the first conductive connection part on the substrate;

[0017] The second electrode plate of the storage capacitor includes a second electrode plate main body and a second electrode plate compensation part coupled to each other, the orthographic projection of the second electrode plate main body on the substrate at least partially overlaps with the orthographic projection of the first electrode plate main body on the substrate, and the orthographic projection of the second electrode plate compensation part on the substrate at least partially overlaps with the orthographic projection of the first electrode plate compensation part on the substrate.

[0018] Optionally, the orthographic projection of the pixel electrode on the base substrate completely covers the orthographic projection of the transistor structure on the base substrate.

[0019] Optionally, the at least two sub-transistors have two sub-transistors with different channel region widths; the orthographic projection of the pixel electrode on the substrate covers the orthographic projection of the sub-transistor with the narrowest channel region width on the substrate; the orthographic projection of the pixel electrode on the substrate does not overlap with the orthographic projection of the sub-transistor with the widest channel region width on the substrate.

[0020] Optionally, the multiple pixel units are divided into multiple rows of pixel unit rows; the pixel electrode includes an electrode main area and an electrode hollow area; in the same row of pixel unit rows, the electrode hollow area in each pixel unit is located on the same side of the electrode main area; in at least some different pixel unit rows, the electrode hollow area is located on different sides of the electrode main area, and in adjacent pixel electrodes where the electrode hollow area is located on different sides of the electrode main area, the electrode main area is staggered along the extension direction of the scanning line.

[0021] Optionally, the display panel includes multiple repeating areas, each repeating area includes multiple rows of pixel unit rows, and among the multiple rows of pixel unit rows belonging to the same repeating area, in at least some different pixel unit rows, the electrode hollow area is located on different sides of the electrode main area, and the electrode hollow area is located in adjacent pixel electrodes on different sides of the electrode main area, and the electrode main area is staggered along the extension direction of the scanning line.

[0022] Optionally, the pixel electrode comprises an electrode hollow region, and an orthographic projection of the electrode hollow region on the base substrate at least partially overlaps with an orthographic projection of the data line on the base substrate.

[0023] Optionally, the scanning line includes a first scanning part and a second scanning part which are alternately arranged, the orthographic projection of the first scanning part on the substrate substrate at least partially overlaps with the orthographic projection of the data line on the substrate substrate, the orthographic projection of the second scanning part on the substrate substrate does not overlap with the orthographic projection of the data line on the substrate substrate, and in a direction perpendicular to the extension direction of the scanning line, the width of the first scanning part is smaller than the maximum width of the second scanning part.

[0024] Optionally, the plurality of pixel units are divided into a plurality of rows of pixel unit rows, the plurality of rows of pixel unit rows are divided into a plurality of unit row groups, each unit row group includes two adjacent rows of pixel unit rows, each unit row group corresponds to the same scan line, the same scan line is located between two rows of pixel unit rows in the unit row group, and the gates of the sub-transistors included in each pixel unit in the two rows of pixel unit rows are respectively coupled to the same scan line;

[0025] The multiple pixel cells are divided into multiple columns of pixel cell columns, each column of pixel cell columns corresponds to two of the data lines, the pixel cell column is located between the corresponding two data lines, the first electrode of the sub-transistor in the odd-numbered pixel cells in the pixel cell column is coupled to the corresponding first data line, and the first electrode of the sub-transistor in the even-numbered pixel cells in the pixel cell column is coupled to the corresponding second data line.

[0026] Optionally, the pixel unit further includes a storage capacitor, a first electrode of the storage capacitor is coupled to the second electrode of each of the sub-transistors, the second electrode of the storage capacitor serves as a common electrode, and the orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode on the substrate; in the same column of pixel units, at least partially adjacent second electrodes are coupled via a second conductive connection portion;

[0027] The second scanning portion includes two first sub-portions and one second sub-portion, the second sub-portion is located between the two first sub-portions, and the width of the second sub-portion is smaller than the width of the first sub-portion in a direction perpendicular to the extension direction of the scanning line; the orthographic projection of the second sub-portion on the substrate at least partially overlaps with the orthographic projection of the second conductive connecting portion on the substrate.

[0028] Based on the technical solution of the above display panel, a second aspect of the present invention provides a display device including the above display panel.

[0029] In the technical solution provided by the present invention, the transistor structure is arranged to include at least two sub-transistors in parallel, the gate of each sub-transistor is coupled to the corresponding scanning line, the first electrode of each sub-transistor is coupled to the corresponding data line, and the second electrode of each sub-transistor is coupled to the pixel electrode; the above-mentioned arrangement branches the transistor structure, so that the single transistor structure becomes a parallel structure of at least two sub-transistors, thereby optimizing the transistor structure, thereby effectively enhancing the performance of the transistor structure in the display product; therefore, the transistor structure included in the pixel unit in the technical solution provided by the present invention can be compatible with many requirements such as current output capability, drift requirements, heat requirements, and voltage resistance requirements, thereby ensuring the stability of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0031] Figure 1 A schematic diagram of a first layout of a gate metal layer in a display panel provided by an embodiment of the present invention;

[0032] Figure 2 For Figure 1 A schematic diagram of the layout of the active layer and the source and drain metal layer is added on the basis of FIG.

[0033] Figure 3 for Figure 2 Schematic diagram of the layout of the active layer and source-drain metal layer added in FIG.

[0034] Figure 4 For Figure 2 A schematic diagram of a layout with a conductive metal layer added on the basis of FIG.

[0035] Figure 5 A first schematic diagram of the layout of pixel electrodes in a display panel provided by an embodiment of the present invention;

[0036] Figure 6 For Figure 4 A schematic diagram of the layout of pixel electrodes is added on the basis of FIG.

[0037] Figure 7 For along Figure 6 Schematic diagram of the cross section along the A1A2 direction;

[0038] Figure 8 for Figure 6 An enlarged schematic diagram of a transistor structure;

[0039] Fig. 9 A schematic diagram of a transistor structure in a display panel provided by an embodiment of the present invention;

[0040] Fig.10 For Fig. 9 A schematic diagram of the layout of adding a shading layer on the basis of FIG.

[0041] Fig.11 A cross-sectional schematic diagram of a light shielding layer shielding an active pattern;

[0042] Fig.12 A schematic diagram of another transistor structure in a display panel provided by an embodiment of the present invention;

[0043] Fig.13 A second schematic diagram of the layout of a gate metal layer in a display panel provided by an embodiment of the present invention;

[0044] Fig.14 A second schematic layout diagram of the source / drain metal layer and the active layer in the display panel provided by an embodiment of the present invention;

[0045] Fig.15 For Fig.13 On the basis of increase Fig.14 Schematic diagram of the layout of the membrane layer and the conductive metal layer;

[0046] Fig.16 A second schematic diagram of the layout of pixel electrodes in a display panel provided by an embodiment of the present invention;

[0047] Fig.17 For Fig.15 On the basis of increase Fig.16 A schematic diagram of the layout of the pixel electrode;

[0048] Fig.18 A third schematic diagram of the layout of the gate metal layer in the display panel provided by an embodiment of the present invention;

[0049] Fig.19 A third schematic diagram of the layout of the source / drain metal layer and the active layer in the display panel provided by an embodiment of the present invention;

[0050] Fig. 20 For Fig.18 On the basis of increase Fig.19 Schematic diagram of the layout of the membrane layer and the conductive metal layer;

[0051] Fig.21 For Fig. 20 A schematic diagram of the layout of the first pixel electrode is added on the basis of FIG.

[0052] Fig. 22 For Fig. 20 A second schematic diagram of the layout of the pixel electrode is added on the basis of FIG.

[0053] Fig.23 for Fig. 22 A schematic diagram of the layout of the second pixel electrode added in FIG.

[0054] Fig.24 For Fig. 20 A third schematic diagram of the layout of the pixel electrode is added on the basis of FIG.

[0055] Fig.25 for Fig.24 A schematic diagram of the layout of a third pixel electrode added in FIG.

[0056] Fig.26 A schematic diagram of the layout of two rows of pixel units in a display panel provided by an embodiment of the present invention;

[0057] Fig. 27 for Fig.26 A schematic diagram of the layout of the pixel electrodes in FIG.

[0058] Fig.28 A schematic diagram of a first layout of pixel electrodes in a repeated area of ​​a display panel provided by an embodiment of the present invention;

[0059] Fig.29A schematic diagram of a second layout of pixel electrodes in a repeated area of ​​a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0060] In order to further illustrate the display panel and the display device provided by the embodiments of the present invention, a detailed description is given below in conjunction with the accompanying drawings.

[0061] See also Figures 1 to 12 An embodiment of the present invention provides a display panel, comprising: a base substrate 10, and a plurality of scan lines 11, a plurality of data lines 12 and a plurality of pixel units arranged on the base substrate 10; the pixel unit comprises a transistor structure 2 and a pixel electrode 13; the transistor structure 2 comprises at least two sub-transistors 20 connected in parallel, a gate of each sub-transistor 20 is coupled to the corresponding scan line 11, a first electrode 203 of each sub-transistor 20 is coupled to the corresponding data line 12, and a second electrode 204 of each sub-transistor 20 is coupled to the pixel electrode 13.

[0062] Exemplarily, the plurality of scan lines 11 are arranged along a first direction, and the scan lines 11 include at least a portion extending along a second direction, and the first direction intersects with the second direction, for example, the first direction includes a longitudinal direction, and the second direction includes a transverse direction, but is not limited thereto. The plurality of data lines 12 are arranged along a second direction, and the data lines 12 include at least a portion extending along the first direction. The scan lines 11 are used to transmit scan signals, and the data lines 12 are used to transmit data signals.

[0063] like Figures 8 to 12 As shown, exemplarily, the display panel includes a plurality of pixel units distributed in an array, and the pixel unit includes a transistor structure 2 and a pixel electrode 13; the transistor structure 2 includes at least two sub-transistors 20 in parallel, for example: the transistor structure 2 includes two sub-transistors 20, three sub-transistors 20, etc., but is not limited to this; in the same transistor structure 2, the gate of each sub-transistor 20 is coupled to the corresponding scanning line 11, the first pole 203 of each sub-transistor 20 is coupled to the corresponding data line 12, and the second pole 204 of each sub-transistor 20 is coupled to the pixel electrode 13.

[0064] Exemplarily, the display panel includes an electronic paper display panel, but is not limited thereto. The display panel includes a gate metal layer, a gate insulating layer, an active layer, a source-drain metal layer, an organic insulating layer, a first passivation layer, a conductive metal layer, a second passivation layer, and a pixel electrode film layer stacked in sequence in a direction away from the base substrate.

[0065] Exemplarily, the pixel unit further includes a storage capacitor Cst, and the storage capacitor Cst includes a first electrode plate Cst1 and a second electrode plate Cst2, wherein the orthographic projection of the first electrode plate Cst1 on the base substrate 10 at least partially overlaps with the orthographic projection of the second electrode plate Cst2 on the base substrate 10. The first electrode plate Cst1 serves as a charging electrode plate, and the second electrode plate Cst2 serves as a common electrode plate.

[0066] Exemplarily, the gate metal layer is used to form the gate (such as the gate pattern 202) of the sub-transistor 20 in the transistor structure 2, and the first plate Cst1 of the storage capacitor Cst; the active layer is used to form the active pattern 201 in the sub-transistor 20; the source-drain metal layer is used to form the first electrode 203 and the second electrode 204 of the sub-transistor 20, and the second plate Cst2 of the storage capacitor Cst. The pixel electrode film layer is used to form the pixel electrode 13 in each pixel unit, and the pixel electrode 13 can be a uniformly distributed square pattern, which is used to apply an electric field to drive the paper film ink to work.

[0067] It should be noted that in conventional transistor structures, a dual-gate transistor structure or a "one-line" transistor structure is usually adopted. In order to increase the pixel charging rate, it is usually necessary to enhance the current output capability of the transistor structure. For a dual-gate transistor structure, the channel length is twice that of a single transistor structure, and the current output capability is also attenuated by two times. For an one-line transistor structure, the current output capability can be improved by increasing the device length, but it also brings about problems such as excessive channel current, serious device performance drift, heat generation, and voltage resistance. Therefore, the above two designs are not applicable to some products with higher charging rate requirements or high-mobility device designs of similar oxide materials.

[0068] In the display panel provided by the embodiment of the present invention, the transistor structure 2 is arranged to include at least two sub-transistors 20 connected in parallel, the gate of each sub-transistor 20 is coupled to the corresponding scan line 11, the first pole 203 of each sub-transistor 20 is coupled to the corresponding data line 12, and the second pole 204 of each sub-transistor 20 is coupled to the pixel electrode 13; the above-mentioned arrangement branches the transistor structure 2, so that the single transistor structure 2 becomes a parallel structure of at least two sub-transistors 20, thereby optimizing the transistor structure 2, thereby effectively enhancing the performance of the transistor structure 2 in the display product, and is beneficial to improving the charging and reliability of the transistor structure; therefore, the transistor structure 2 included in the pixel unit in the display panel provided by the embodiment of the present invention can be compatible with many requirements such as current output capability, drift requirements, heat requirements, and voltage resistance requirements, thereby ensuring the stability of the display panel.

[0069] like Fig. 9 and Fig.10As shown, in some embodiments, the sub-transistor 20 includes an active pattern 201, and the active patterns 201 in the at least two sub-transistors 20 are arranged sequentially along the first direction, and the spacing d1 between adjacent active patterns 201 satisfies: 1.5L1≤d1≤2.5L1, where L1 is the channel length of the sub-transistor 20.

[0070] Exemplarily, the interval d1 between adjacent active patterns 201 may take values ​​such as 1.5L1, 2L1, 2.5L1, etc., but is not limited thereto.

[0071] It should be noted that L1 corresponds to the distance between the first electrode and the second electrode in the same sub-transistor.

[0072] The above configuration allows a wider distance between the active patterns 201 of adjacent sub-transistors 20 , which helps alleviate the heating problem caused by excessive channel current of the transistor structure 2 .

[0073] like Figures 1 to 12 As shown, in some embodiments, the gate of each sub-transistor 20 is formed as a gate pattern 202 of an integrated structure, and the gate pattern 202 extends along the first direction and is coupled to the corresponding scan line 11;

[0074] The first electrode 203 of the sub-transistor 20 is located at a first side of the sub-transistor 20 along the second direction, and extends along the second direction in a direction away from the gate pattern 202; the first electrodes 203 of each sub-transistor 20 are arranged along the first direction, and the first electrodes 203 of each sub-transistor 20 are respectively coupled to the corresponding data line 12;

[0075] The second pole 204 of the sub-transistor 20 is located on the second side of the sub-transistor 20 along the second direction, and extends along the second direction in a direction away from the gate pattern 202; the second pole 204 of each sub-transistor 20 is arranged along the first direction, and the second pole 204 of each sub-transistor 20 is coupled to the conductive connection pattern 205 respectively, and the conductive connection pattern 205 is coupled to the pixel electrode 13 through the light shielding layer 14.

[0076] Exemplarily, the first electrode 203 and the second electrode 204 of the sub-transistor 20 are respectively overlapped on the active pattern 201 included in the sub-transistor 20. The first side and the second side are opposite to each other along the second direction.

[0077] Exemplarily, the first electrode 203 of the sub-transistor 20 and the data line 12 coupled thereto form an integral structure, but not limited thereto. The second electrode 204 of the sub-transistor 20 and the conductive connection pattern 205 form an integral structure, but not limited thereto.

[0078] The above arrangement increases the overall length of the transistor structure 2 while branching the transistor structure 2, so that the single transistor structure 2 becomes a parallel structure of at least two sub-transistors 20, thereby optimizing the transistor structure 2. The above arrangement enables the first pole 203 and the second pole 204 of the sub-transistor 20 to be extended along the second direction away from the gate pattern 202 on the active pattern 201, so that the overlapping area of ​​the first pole 203 and the second pole 204 with the gate in the direction perpendicular to the base substrate 10 is reduced, thereby reducing the parasitic capacitance between the first pole 203 and the gate, and the parasitic capacitance between the second pole 204 and the gate, which is beneficial to improving the charging rate of the display panel and improving the display abnormality caused by the capacitance crosstalk within the display panel screen.

[0079] It should be noted that the above-mentioned increase in the overall length of the transistor structure 2 refers to the overall length of the transistor structure 2 along the thickness width direction, that is, the overall length in the first direction.

[0080] like Figures 1 to 4 As shown, in some embodiments, the pixel unit further includes a light shielding layer 14 , and an orthographic projection of the light shielding layer 14 on the base substrate 10 at least partially overlaps with an orthographic projection of a channel region of each sub-transistor 20 on the base substrate 10 .

[0081] Exemplarily, the conductive metal layer is used to form the light shielding layer 14 , but is not limited thereto.

[0082] Exemplarily, the orthographic projection of the light shielding layer 14 on the base substrate 10 completely covers the orthographic projection of the channel region of each sub-transistor 20 on the base substrate 10 .

[0083] Exemplarily, the light shielding layer 14 is coupled to the second electrode 204 of each sub-transistor 20. For example, the light shielding layer 14 is coupled to the conductive connection pattern 205 through the first sub-via, and the light shielding layer 14 is coupled to the pixel electrode 13 through the second sub-via, so that the conductive connection pattern 205 is coupled to the pixel electrode 13 through the light shielding layer 14. It should be noted that the first sub-via and the second sub-via form a sleeve hole structure Via2. The conductive connection pattern 205 is coupled to the first electrode plate Cst1 through the first via Via1.

[0084] The pixel unit is also configured to include the shading layer 14, so that the shading layer 14 can shield the transistor structure 2. When the display panel is exposed to light, the shading layer 14 can prevent the light from irradiating the transistor structure 2, which is beneficial to improving the device leakage problem of the transistor structure 2 caused by light.

[0085] At the same time, the light shielding layer 14 is coupled to the second electrode 204 of each sub-transistor 20 so that the signal of the light shielding layer 14 can be synchronized with the signal on the second electrode 204, and the pixel electric field driving disorder will not be caused by the light shielding layer 14 being in a floating state.

[0086] like Fig.11 As shown, it should be noted that the light shielding layer 14 should be able to completely cover the channel area of ​​each sub-transistor 20, considering the alignment accuracy c in the pattern making process, the length d of the light shielding layer 14 beyond the edge of the active pattern 201, the total thickness h of the insulating layer between the light shielding layer 14 and the active pattern 201 (such as: the organic insulating layer ORG and the first passivation layer PVX1), and the light shielding angle α is required to be less than 30°, and the following relationship should be satisfied:

[0087]

[0088] For example: product c = 1.5μm, h = 3μm, and the minimum excess distance d = 6.69μm to meet the shading angle of 30°.

[0089] It is worth noting that Fig.11 The arrows in the figure represent the irradiating rays.

[0090] like Figures 13 to 21 As shown, in some embodiments, the pixel unit further includes a first conductive connection portion 15 and a storage capacitor Cst; the gate of each sub-transistor 20 in the pixel unit is coupled to the corresponding scan line 11 through the first conductive connection portion 15, and the second electrode 204 of each sub-transistor 20 is coupled to the first electrode plate Cst1 of the storage capacitor Cst;

[0091] The first conductive connection portion 15 extends along a first direction, and a length L2 of the first conductive connection portion 15 along the first direction is ≥ (1 / 3)*L3, where L3 is a length of the first electrode plate Cst1 of the storage capacitor Cst along the first direction.

[0092] Exemplarily, the gate of each sub-transistor 20 is formed as a gate graphic 202 of an integrated structure, the gate graphic 202 extends along a first direction, the gate graphic 202 is coupled to the corresponding scan line 11 through the first conductive connection portion 15, the second electrode 204 of each sub-transistor 20 is coupled to the first electrode plate Cst1 of the storage capacitor Cst, and the orthographic projection of the second electrode 204 of each sub-transistor 20 on the base substrate 10 and the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base substrate 10 are arranged along the second direction.

[0093] Exemplarily, the length L2 of the first conductive connection portion 15 along the first direction is (1 / 2)*L3, but is not limited thereto.

[0094] It should be noted that, in conventional designs, the transistor structure 2 is generally disposed in an area adjacent to the scan line 11. When the product process does not include an organic insulating layer, in order to prevent the electric field formed by the pixel electrode 13 from affecting the leakage of the transistor structure 2, the pixel electrode 13 is usually designed not to cover directly above the transistor structure 2. However, this will cause a difference between the electric field in some areas and the electric field in the area where the pixel electrode 13 is located, resulting in ghosting or horizontal stripes along the extension direction of the scan line 11 during display.

[0095] The above arrangement can arrange the transistor structure 2 in the middle of the pixel unit, so that the transistor structure 2 will not be concentrated near the coupled scan line 11, so that the transistor structure 2 in the display panel can be scattered and evenly distributed in the display panel, so that regardless of whether the pixel electrode 13 is arranged to cover the transistor structure 2, the above-mentioned bad visual sense can be weakened, thereby overcoming the above-mentioned bad horizontal stripes. This improvement effect is particularly obvious for display panels that do not include an organic insulating layer ORG.

[0096] like Figures 13 to 17 As shown, in some embodiments, the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the base substrate 10 at least partially overlaps with the orthographic projection of the first conductive connection portion 15 on the base substrate 10 .

[0097] Exemplarily, the second electrode plate Cst2 has a notch K1, at which the first electrode plate Cst1 is not covered by the second electrode plate Cst2, and at which the first electrode plate Cst1 is coupled to the conductive connection pattern 205. The notch K1 is located at one side of the second electrode plate Cst2 along the second direction and is approximately located in the middle of the second electrode plate Cst2.

[0098] The above-mentioned setting method changes the shape of the second electrode plate Cst2 so that a facing area can be formed between the second electrode plate Cst2 and the first conductive connecting portion 15 in a direction perpendicular to the base substrate 10, thereby maintaining an overlapping area between the source and drain metal layer and the gate metal layer used to form the second electrode plate Cst2 without significant change compared to before the shape is changed, thereby maintaining the capacitance of the storage capacitor Cst unchanged and avoiding affecting the performance of the display panel.

[0099] like Figures 18 to 21 As shown, in some embodiments, the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the base substrate 10 does not overlap with the orthographic projection of the first conductive connection portion 15 on the base substrate 10;

[0100] The first electrode plate Cst1 of the storage capacitor Cst includes a first electrode plate main body 31 and a first electrode plate compensation part 32 coupled to each other, wherein the orthographic projection of the first electrode plate main body 31 on the base substrate 10 is located between the orthographic projection of the first electrode plate compensation part 32 on the base substrate 10 and the orthographic projection of the first conductive connection part 15 on the base substrate 10;

[0101] The second electrode plate Cst2 of the storage capacitor Cst includes a second electrode plate main body 33 and a second electrode plate compensation portion 34 coupled to each other, the orthographic projection of the second electrode plate main body 33 on the base substrate 10 at least partially overlaps with the orthographic projection of the first electrode plate main body 31 on the base substrate 10, and the orthographic projection of the second electrode plate compensation portion 34 on the base substrate 10 at least partially overlaps with the orthographic projection of the first electrode plate compensation portion 32 on the base substrate 10.

[0102] Exemplarily, the orthographic projection of the second electrode main body portion 33 on the base substrate 10 is located between the orthographic projection of the second electrode compensation portion 34 on the base substrate 10 and the orthographic projection of the first conductive connection portion 15 on the base substrate 10 .

[0103] The orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the base substrate 10 does not overlap with the orthographic projection of the first conductive connecting portion 15 on the base substrate 10, thereby reducing the crosstalk between the signal transmitted by the second electrode plate Cst2 and the signal transmitted by the first conductive connecting portion 15.

[0104] The above-mentioned setting method increases the facing area between the first plate compensation part 32 and the second plate compensation part 34 in the direction perpendicular to the base substrate 10 by changing the shapes of the first plate Cst1 and the second plate Cst2, that is, the facing area between the first plate Cst1 and the second plate Cst2 is increased in other vacant areas, thereby increasing the capacitance of the storage capacitor Cst, better adapting to the needs of display panels with sufficiently large pixel unit sizes and high requirements for the storage capacitor Cst, and ensuring the display performance of such display panels.

[0105] like Fig. 22 and Fig.23 As shown, in some embodiments, the orthographic projection of the pixel electrode 13 on the base substrate 10 is arranged not to overlap with the orthographic projection of the transistor structure 2 on the base substrate 10. This arrangement can prevent the electric field formed by the pixel electrode 13 from causing leakage to the transistor structure 2.

[0106] like Fig.21As shown, in some embodiments, the orthographic projection of the pixel electrode 13 on the base substrate 10 completely covers the orthographic projection of the transistor structure 2 on the base substrate 10 .

[0107] Exemplarily, the display panel includes an organic insulating layer, which is located between the pixel electrode 13 and the first electrode 203 and the second electrode 204 of each sub-transistor 20 to prevent the electric field formed by the pixel electrode 13 from causing leakage to the transistor structure 2 .

[0108] The above-mentioned setting of the pixel electrode 13 on the base substrate 10 completely covers the positive projection of the transistor structure 2 on the base substrate 10, so that the pixel electrode 13 can evenly cover the area where the pixel unit is located, thereby ensuring the uniformity of the electric field distribution in the area where the pixel unit is located, and avoiding the occurrence of ghosting afterimage defects or horizontal stripes along the extension direction of the scanning line 11 when the display panel displays the picture.

[0109] like Fig.24 and Fig.25 As shown, in some embodiments, the at least two sub-transistors 20 have two sub-transistors 20 with different channel region widths; the orthographic projection of the pixel electrode 13 on the substrate 10 covers the orthographic projection of the sub-transistor 20 with the narrowest channel region width on the substrate 10; the orthographic projection of the pixel electrode 13 on the substrate 10 does not overlap with the orthographic projection of the sub-transistor 20 with the widest channel region width on the substrate 10.

[0110] Exemplarily, the transistor structure 2 includes two sub-transistors 20, wherein the ratio between the width of the channel region of the first sub-transistor 20 and the width of the channel region of the second sub-transistor 20 may be 2:1 or 3:1, but is not limited thereto. The orthographic projection of the pixel electrode 13 on the base substrate 10 covers the orthographic projection of the second sub-transistor 20 on the base substrate 10; the orthographic projection of the pixel electrode 13 on the base substrate 10 does not overlap with the orthographic projection of the first sub-transistor 20 on the base substrate 10.

[0111] Exemplarily, the minimum distance between the boundary of the orthographic projection of the active pattern 201 of the sub-transistor 20 that does not overlap with the pixel electrode 13 on the base substrate 10 and the boundary of the orthographic projection of the pixel electrode 13 on the base substrate 10 is greater than or equal to 5 μm, which helps to reduce the impact of the electric field formed by the pixel electrode 13 on the performance of the sub-transistor 20.

[0112] When the above-mentioned setting method is adopted, the sub-transistor 20 with a narrower channel area width is covered by the pixel electrode 13. Since the branch current generated by the sub-transistor 20 with a narrower channel area width is smaller, the electric field formed by the pixel electrode 13 has a relatively small effect on the leakage of the sub-transistor 20; the above-mentioned setting method reduces the effect of the electric field formed by the pixel electrode 13 on the transistor structure 2, while reducing the area of ​​the area not covered by the pixel electrode 13 in the pixel unit, thereby ensuring that there is no obvious difference in the driving electric field of each area in the display panel.

[0113] like Fig.26 and Fig. 27 As shown, in some embodiments, the pixel electrode 13 includes an electrode hollow area 131 , and an orthographic projection of the electrode hollow area 131 on the base substrate 10 is set to at least partially overlap with an orthographic projection of the data line 12 on the base substrate 10 .

[0114] Exemplarily, the pixel electrode 13 includes two hollow regions, and the two hollow regions are located at the same side of the pixel electrode 13 ; or, the two hollow regions are located at different sides of the pixel electrode 13 and are arranged opposite to each other along the extension direction of the scan line 11 .

[0115] It should be noted that, taking the display panel including an electronic paper display panel as an example, the design of the electronic paper display panel is similar to the TN mode (English: Twisted Nematic, Chinese: twisted nematic) of the liquid crystal display panel design. During the operation of the electronic paper display panel, the ink is driven by the electric field formed by the pixel electrode and the common electrode on the paper film, so the area of ​​the pixel electrode 13 on the display panel should be increased as much as possible. Fig.26 and Fig. 27 As shown, under this principle, the pixel electrode 13 of a single pixel unit will cover the top of the data line 12. At this time, due to the large overlap area between the pixel electrode 13 and the data line 12, the parasitic capacitance will be increased, resulting in the generation of crosstalk. According to the above-mentioned setting method, the portion of the pixel electrode 13 located above the data line 12 is at least partially excavated, that is, the electrode hollow area 131 is formed, which can effectively reduce the overlap area between the pixel electrode 13 and the data line 12, reduce the parasitic capacitance formed between the pixel electrode 13 and the data line 12, and effectively reduce unnecessary signal crosstalk.

[0116] like Fig.26 and Fig. 27As shown, in some embodiments, the multiple pixel units are divided into multiple rows of pixel unit rows; the pixel electrode 13 includes an electrode main body area 130 and an electrode hollow area 131; in the same row of pixel unit rows, the electrode hollow area 131 in each pixel unit is located on the same side of the electrode main body area 130; in at least some different pixel unit rows, the electrode hollow area 131 is located on different sides of the electrode main body area 130, and in adjacent pixel electrodes 13 located on different sides of the electrode main body area 130, the electrode main body area 130 is staggered along the extension direction of the scanning line 11.

[0117] Exemplarily, the multiple rows of pixel units are arranged along the first direction, and each row of pixel units includes a plurality of pixel units arranged along the second direction.

[0118] Exemplarily, the pixel electrode 13 includes two electrode hollow areas 131 arranged along the second direction, and the electrode hollow areas 131 are formed as strip areas extending along the first direction. In each pixel unit, the two electrode hollow areas 131 are located on one side of the electrode main area 130 along the second direction; in the same row of pixel units, the electrode hollow areas 131 in each pixel unit are located on the same side of the electrode main area 130 along the second direction.

[0119] Exemplarily, in at least some different pixel unit rows, the electrode hollow region 131 is located on different sides of the electrode main region 130; for example: in a part of the pixel unit rows, the electrode hollow region 131 is located on one side of the electrode main region 130 along the second direction, and in another part of the pixel unit rows, the electrode hollow region 131 is located on the other side of the electrode main region 130 along the second direction.

[0120] Exemplarily, the display panel includes multiple repeating areas 40, each repeating area 40 includes multiple rows of pixel unit rows, and in the multiple rows of pixel unit rows belonging to the same repeating area 40, in at least some different pixel unit rows, the electrode hollow area 131 is located on different sides of the electrode main area 130, the electrode hollow area 131 is located in adjacent pixel electrodes 13 on different sides of the electrode main area 130, and the electrode main area 130 is staggered along the extension direction of the scanning line 11.

[0121] For example, the display panel includes n rows of pixel unit rows, each repeating region 40 includes m rows of pixel unit rows, and n / m repeating regions 40 are sequentially arranged in the display panel along the first direction. Fig.28 As shown, the positions of the electrode hollow regions 131 in the m rows of pixel units in the repeating area 40 are irregularly distributed in the manner of left-left-left-left-right…right-left. Fig.29As shown, the positions of the electrode hollow areas 131 in the m rows of pixel units in the repeating area 40 are irregularly distributed in the manner of left-right-right-left...right-left. There should be no regular repetition of pixel electrodes 13 in the m rows of pixel units, and the arrangement of pixel electrodes 13 on the overall panel can be irregularly staggered left and right to achieve different combination schemes and achieve irregular pixel unit distribution.

[0122] It should be noted that due to the ultra-large size of the electronic paper display panel, there is a problem that the panel size is larger than the mask size. Therefore, when actually producing the electronic paper display panel, it is necessary to adopt a splicing mask exposure solution. However, in conventional designs, the pixel units are arranged very regularly. After the actual production, the mask splicing area is prone to form splicing mura (defects) or obvious splicing lines.

[0123] Since the electronic paper drives the paper film ink movement by relying on the electric field generated by the pixel electrode 13 in the pixel unit, the movement of the pixel electrode 13 will not affect the overall driving effect when the area of ​​the pixel electrode 13 remains unchanged. Based on this principle, the pixel electrode 13 in the display panel is set in the above manner, and the overlap of the pixel electrode 13 with other metal film layers does not change substantially, but the pixel electrode 13 can be deformed to the effect of being displaced to the left or right, so that the pixel units in the display panel can achieve an irregular mosaic design, which can improve the splicing exposure effect and weaken the display boundary between the splicing area and the normal area while ensuring that the pixel drive is not affected, thereby reducing the visual difference caused by the splicing mask and improving the splicing mura.

[0124] like Figures 1 to 6 As shown, in some embodiments, the scanning line 11 includes a first scanning portion 111 and a second scanning portion 112 that are alternately arranged, the orthographic projection of the first scanning portion 111 on the substrate substrate 10 at least partially overlaps with the orthographic projection of the data line 12 on the substrate substrate 10, the orthographic projection of the second scanning portion 112 on the substrate substrate 10 does not overlap with the orthographic projection of the data line 12 on the substrate substrate 10, and in a direction perpendicular to the extension direction of the scanning line 11, the width of the first scanning portion 111 is smaller than the maximum width of the second scanning portion 112.

[0125] Exemplarily, the second scanning portion 112 includes two first sub-portions 1121 and one second sub-portion 1122, the second sub-portion 1122 is located between the two first sub-portions 1121, and in a direction perpendicular to the extension direction of the scanning line 11, the width of the second sub-portion 1122 is smaller than the width of the first sub-portion 1121; the width of the first scanning portion 111 is smaller than the width of the first sub-portion 1121.

[0126] The above configuration can reduce the parasitic capacitance formed between the scan line 11 and the data line 12 , which is beneficial to improving the working quality of the display panel and the display quality of the display panel.

[0127] like Figures 1 to 6 , Fig.26 As shown, in some embodiments, the plurality of pixel units are divided into a plurality of rows of pixel unit rows, the plurality of rows of pixel unit rows are divided into a plurality of unit row groups Z1, each unit row group Z1 includes two adjacent rows of pixel unit rows, each unit row group Z1 corresponds to the same scan line 11, the same scan line 11 is located between the two rows of pixel unit rows in the unit row group Z1, and the gates of the sub-transistors 20 included in each pixel unit in the two rows of pixel unit rows are respectively coupled to the same scan line 11;

[0128] The multiple pixel units are divided into multiple columns of pixel unit columns, each column of pixel unit columns corresponds to two of the data lines 12, and the pixel unit column is located between the corresponding two data lines 12. The first electrode 203 of the sub-transistor 20 in the odd-numbered pixel units in the pixel unit column is coupled to the corresponding first data line 12, and the first electrode 203 of the sub-transistor 20 in the even-numbered pixel units in the pixel unit column is coupled to the corresponding second data line 12.

[0129] Exemplarily, the plurality of pixel units are divided into a plurality of pixel unit columns arranged along the second direction, and each pixel unit column includes a plurality of pixel units arranged along the first direction.

[0130] The above configuration enables the scanning signal transmitted by the same scanning line 11 to control the opening of two rows of pixel units at the same time, and there are two independent data lines 12 between two adjacent columns of pixel units.

[0131] like Figures 1 to 6 As shown, in some embodiments, the pixel unit further includes a storage capacitor Cst, a first plate Cst1 of the storage capacitor Cst is coupled to the second electrode 204 of each of the sub-transistors 20, a second plate Cst2 of the storage capacitor Cst serves as a common electrode, and an orthographic projection of the second plate Cst2 on the base substrate 10 at least partially overlaps with an orthographic projection of the first plate Cst1 on the base substrate 10; in the same column of pixel units, at least partially adjacent second plates Cst2 are coupled via a second conductive connection portion 16;

[0132] The second scanning portion 112 includes two first sub-portions 1121 and one second sub-portion 1122, the second sub-portion 1122 is located between the two first sub-portions 1121, and the width of the second sub-portion 1122 is smaller than the width of the first sub-portion 1121 in the direction perpendicular to the extension direction of the scanning line 11; the orthographic projection of the second sub-portion 1122 on the base substrate 10 at least partially overlaps with the orthographic projection of the second conductive connecting portion 16 on the base substrate 10.

[0133] For example, in the same column of pixel units, when there is a scan line 11 between adjacent second plates Cst2, the adjacent second plates Cst2 are coupled via a second conductive connection portion 16, and the second conductive connection portion 16 spans the scan line 11. The second conductive connection portion 16 can form an integral structure with the second electrode coupled thereto.

[0134] Exemplarily, in the same column of pixel units, when there is no scan line 11 between adjacent second plates Cst2, the adjacent second plates Cst2 are directly formed into an integrated structure, and the width of the integrated structure along the second direction is greater than the width of the second conductive connection portion 16.

[0135] Exemplarily, the display panel further includes a plurality of common electrode lines 50, the common electrode lines 50 extending along the second direction, the common electrode lines 50 and the scan lines 11 being alternately arranged along the first direction, and the common electrode lines 50 being respectively coupled to a corresponding row of second electrodes Cst2 through third via holes Via3. The common electrode lines 50 are arranged in the same layer and material as the conductive metal layer, but are not limited thereto.

[0136] The above configuration can reduce the parasitic capacitance formed between the scanning line 11 and the second conductive connection portion 16 , which is beneficial to improving the working quality of the display panel and the display quality of the display panel.

[0137] An embodiment of the present invention further provides a display device, comprising the display panel provided by the above embodiment.

[0138] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, etc.

[0139] In the display panel provided in the above embodiment, the transistor structure 2 is arranged to include at least two sub-transistors 20 connected in parallel, the gate of each sub-transistor 20 is coupled to the corresponding scanning line 11, the first pole 203 of each sub-transistor 20 is coupled to the corresponding data line 12, and the second pole 204 of each sub-transistor 20 is coupled to the pixel electrode 13; the above arrangement branches the transistor structure 2, so that the single transistor structure 2 becomes a parallel structure of at least two sub-transistors 20, thereby optimizing the transistor structure 2, thereby effectively enhancing the performance of the transistor structure 2 in the display product; therefore, the transistor structure 2 included in the pixel unit in the display panel provided in the above embodiment can be compatible with many requirements such as current output capability, drift requirements, heat requirements, and voltage resistance requirements, thereby ensuring the stability of the display panel.

[0140] The display device provided by the embodiment of the present invention, when comprising the above-mentioned display panel, also has the above-mentioned beneficial effects, thereby ensuring the stability of the use of the display device.

[0141] It should be noted that the signal line extends along a certain direction means that: the signal line includes a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along a certain direction, and the length of the main part extending along the certain direction is greater than the length of the secondary part extending along other directions.

[0142] It should be noted that the "same layer" in the embodiment of the present invention may refer to a film layer on the same structural layer. Or, for example, a film layer on the same layer may be a film layer for forming a specific pattern formed by the same film forming process, and then the film layer is patterned by the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0143] In the various method embodiments of the present invention, the serial numbers of the steps cannot be used to limit the sequence of the steps. For ordinary technicians in this field, without paying creative work, changes to the sequence of the steps are also within the protection scope of the present invention.

[0144] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0145] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0146] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0147] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0148] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: include: A base substrate, and a plurality of scanning lines, a plurality of data lines and a plurality of pixel units arranged on the base substrate; The pixel unit includes a transistor structure and a pixel electrode; the transistor structure includes at least two sub-transistors connected in parallel, the gate of each sub-transistor is coupled to the corresponding scan line, the first electrode of each sub-transistor is coupled to the corresponding data line, and the second electrode of each sub-transistor is coupled to the pixel electrode.

2. The display panel according to claim 1, characterized in that: The sub-transistor comprises an active pattern, the active patterns in the at least two sub-transistors are arranged in sequence along a first direction, and a spacing d1 between adjacent active patterns satisfies: 1.5L1≤d1≤2.5L1, wherein L1 is a channel length of the sub-transistor.

3. The display panel according to claim 1, characterized in that: The gate of each sub-transistor is formed as a gate pattern of an integrated structure, the gate pattern extends along a first direction and is coupled to a corresponding scan line; The first electrode of the sub-transistor is located at a first side of the sub-transistor along the second direction and extends in a direction away from the gate pattern along the second direction; the first electrodes of the sub-transistors are arranged along the first direction, and the first electrodes of the sub-transistors are respectively coupled to the corresponding data lines; The second pole of the sub-transistor is located on the second side of the sub-transistor along the second direction and extends along the second direction in a direction away from the gate pattern; the second poles of each sub-transistor are arranged along the first direction, and the second poles of each sub-transistor are respectively coupled to the conductive connection pattern, and the conductive connection pattern is coupled to the pixel electrode.

4. The display panel according to claim 1, characterized in that: The pixel unit further includes a light shielding layer, and an orthographic projection of the light shielding layer on the base substrate at least partially overlaps with an orthographic projection of a channel region of each sub-transistor on the base substrate.

5. The display panel according to claim 4, characterized in that: The light shielding layer is coupled to the second electrode of each sub-transistor.

6. The display panel according to any one of claims 1 to 5, characterized in that: The pixel unit further includes a first conductive connection portion and a storage capacitor; the gate of each sub-transistor in the pixel unit is coupled to the corresponding scan line through the first conductive connection portion, and the second electrode of each sub-transistor is coupled to the first electrode plate of the storage capacitor; The first conductive connection portion extends along a first direction, and a length L2 of the first conductive connection portion along the first direction is ≥ (1 / 3)*L3, wherein L3 is a length of the first electrode plate of the storage capacitor along the first direction.

7. The display panel according to claim 6, characterized in that: An orthographic projection of the second electrode plate of the storage capacitor on the base substrate at least partially overlaps with an orthographic projection of the first conductive connection portion on the base substrate.

8. The display panel according to claim 6, characterized in that: The orthographic projection of the second electrode plate of the storage capacitor on the substrate does not overlap with the orthographic projection of the first conductive connecting portion on the substrate; The first electrode plate of the storage capacitor comprises a first electrode plate main body and a first electrode plate compensation part coupled to each other, wherein the orthographic projection of the first electrode plate main body on the substrate is located between the orthographic projection of the first electrode plate compensation part on the substrate and the orthographic projection of the first conductive connection part on the substrate; The second electrode plate of the storage capacitor includes a second electrode plate main body and a second electrode plate compensation part coupled to each other, the orthographic projection of the second electrode plate main body on the substrate at least partially overlaps with the orthographic projection of the first electrode plate main body on the substrate, and the orthographic projection of the second electrode plate compensation part on the substrate at least partially overlaps with the orthographic projection of the first electrode plate compensation part on the substrate.

9. The display panel according to claim 6, characterized in that: The orthographic projection of the pixel electrode on the base substrate completely covers the orthographic projection of the transistor structure on the base substrate.

10. The display panel according to claim 6, characterized in that: Among the at least two sub-transistors, there are two sub-transistors with different channel region widths; the orthographic projection of the pixel electrode on the substrate covers the orthographic projection of the sub-transistor with the narrowest channel region width on the substrate; the orthographic projection of the pixel electrode on the substrate does not overlap with the orthographic projection of the sub-transistor with the widest channel region width on the substrate.

11. The display panel according to any one of claims 1 to 5, characterized in that: The multiple pixel units are divided into multiple rows of pixel unit rows; the pixel electrode includes an electrode main body area and an electrode hollow area; in the same row of pixel unit rows, the electrode hollow area in each pixel unit is located on the same side of the electrode main body area; in at least some different pixel unit rows, the electrode hollow area is located on different sides of the electrode main body area, and in adjacent pixel electrodes where the electrode hollow area is located on different sides of the electrode main body area, the electrode main body areas are staggered along the extension direction of the scanning line.

12. The display panel according to claim 11, characterized in that: The display panel includes multiple repeating areas, each repeating area includes multiple rows of pixel unit rows, and among the multiple rows of pixel unit rows belonging to the same repeating area, in at least some different pixel unit rows, the electrode hollow areas are located on different sides of the electrode main area, and the electrode hollow areas are located in adjacent pixel electrodes on different sides of the electrode main area, and the electrode main area is staggered along the extension direction of the scanning line.

13. The display panel according to any one of claims 1 to 5, characterized in that: The pixel electrode comprises an electrode hollow region, and an orthographic projection of the electrode hollow region on the base substrate at least partially overlaps with an orthographic projection of the data line on the base substrate.

14. The display panel according to any one of claims 1 to 5, characterized in that: The scanning line includes a first scanning part and a second scanning part which are alternately arranged, wherein the orthographic projection of the first scanning part on the substrate substrate at least partially overlaps with the orthographic projection of the data line on the substrate substrate, and the orthographic projection of the second scanning part on the substrate substrate does not overlap with the orthographic projection of the data line on the substrate substrate, and in a direction perpendicular to the extension direction of the scanning line, the width of the first scanning part is smaller than the maximum width of the second scanning part.

15. The display panel according to claim 14, characterized in that: The plurality of pixel units are divided into a plurality of rows of pixel unit rows, the plurality of rows of pixel unit rows are divided into a plurality of unit row groups, each unit row group includes two adjacent rows of pixel unit rows, each unit row group corresponds to the same scan line, the same scan line is located between two rows of pixel unit rows in the unit row group, and the gates of the sub-transistors included in each pixel unit in the two rows of pixel unit rows are respectively coupled to the same scan line; The multiple pixel cells are divided into multiple columns of pixel cell columns, each column of pixel cell columns corresponds to two of the data lines, the pixel cell column is located between the corresponding two data lines, the first electrode of the sub-transistor in the odd-numbered pixel cells in the pixel cell column is coupled to the corresponding first data line, and the first electrode of the sub-transistor in the even-numbered pixel cells in the pixel cell column is coupled to the corresponding second data line.

16. The display panel according to claim 15, characterized in that: The pixel unit further includes a storage capacitor, a first electrode of the storage capacitor is coupled to the second electrode of each of the sub-transistors, a second electrode of the storage capacitor serves as a common electrode, and an orthographic projection of the second electrode on the substrate at least partially overlaps with an orthographic projection of the first electrode on the substrate; In the same column of pixel units, at least some of the adjacent second electrodes are coupled via the second conductive connection portion; The second scanning portion includes two first sub-portions and a second sub-portion, the second sub-portion is located between the two first sub-portions, and the width of the second sub-portion is smaller than the width of the first sub-portion in a direction perpendicular to the extending direction of the scanning line; An orthographic projection of the second sub-portion on the base substrate at least partially overlaps with an orthographic projection of the second conductive connection portion on the base substrate.

17. A display device, characterized in that: The invention comprises the display panel according to any one of claims 1 to 16.

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