Circuit for improving LDO high power supply rejection ratio

Abstract

The invention discloses a circuit for improving the LDO high power supply rejection ratio, and belongs to the technical field of LDO circuits. The feedback control amplifier mainly comprises a feedback control amplifier module opa1 and a power tube module, the power tube module comprises a power tube MP1 and a power tube MP2, the drain electrode of the power tube MP1 is connected with the source electrode of the power tube MP2, the in-phase input end of the feedback control amplifier module opa1 is connected with the source electrode of the power tube MP1, and the in-phase input end of the feedback control amplifier module opa2 is connected with the source electrode of the power tube MP2. The inverted input end of the feedback control amplifier module opa1 is connected with the drain electrode of the power tube MP1 and the source electrode of the power tube MP2, and the output end of the feedback control amplifier module opa1 is connected with the substrate potential of the power tube MP1. According to the circuit, through the special design of the feedback control amplifier module opa1, the gain at the low frequency band is low, the gain at the high frequency band is increased, and the gain at the high frequency band is increased; and in high frequency, the MP1 substrate potential is increased, and the impedance of the MP1 tube is increased, so that the power supply rejection ratio psrr of a high-frequency band is increased, the influence of high-frequency noise in the power supply on output voltage is effectively suppressed, and the requirement of the high-precision field on the power supply rejection ratio is met.

Description

Technical Field

[0001] The invention relates to the technical field of LDO circuits, and in particular to a circuit for improving a high power supply rejection ratio of an LDO. Background Art

[0002] As a core component of high-efficiency power management, low-dropout linear regulators (LDOs) are widely used in electronic systems with limited input / output voltage differences. With the rapid development of portable devices, IoT terminals, and wearable technologies, the defects of traditional switching power supplies, such as large electromagnetic interference and complex peripheral circuits, have become increasingly prominent. LDOs, with their low voltage difference, low noise, and fast dynamic response characteristics, have shown significant advantages in lithium battery-powered scenarios, especially in the fields of high-precision analog circuits (such as sensors, RF modules), medical electronics, and automotive-grade chips, which have high requirements for LDO power supply rejection ratio.

[0003] However, in the fields of high-precision analog circuits (such as sensors, RF modules), medical electronics and automotive-grade chips, these fields have extremely high requirements for the purity of the power supply. The noise and fluctuations in the power supply may cause inaccurate signal acquisition, unstable operation of medical equipment, and failure of automotive-grade chips. The traditional LDO architecture has an unsatisfactory power supply rejection ratio (PSRR) in the high-frequency range and cannot effectively suppress the high-frequency noise in the power supply, resulting in fluctuations and noise in the output voltage, which cannot meet the application requirements of these high-precision fields.

[0004] Therefore, it is necessary to provide a circuit for improving the high power supply rejection ratio of LDO to solve the above problems.

[0005] It should be noted that the above information disclosed in this background technology section is only for understanding the background technology of the present inventive concept, and therefore, it may contain information that does not constitute the prior art. Summary of the invention

[0006] The object of the present invention is to provide a circuit for improving the high power supply rejection ratio of an LDO, so as to solve the problems raised in the above background technology.

[0007] The technical solution adopted by the present invention to solve its technical problem is: A circuit for improving the high power supply rejection ratio of an LDO, comprising a feedback control amplifier module opa1 and a power tube module; The power tube module includes a power tube MP1 and a power tube MP2, the drain of the power tube MP1 is connected to the source of the power tube MP2, the in-phase input end of the feedback control amplifier module opa1 is connected to the source of the power tube MP1, the inverting input end of the feedback control amplifier module opa1 is respectively connected to the drain of the power tube MP1 and the source of the power tube MP2, and the output end of the feedback control amplifier module opa1 is connected to the substrate potential of the power tube MP1; After the feedback control amplifier module opa1 detects the signals of the source and drain of the power tube MP1, the output terminal vout0 of the feedback control amplifier module opa1 controls the substrate potential of the power tube MP1.

[0008] Preferably, it also includes an error amplifier opa0 and a feedback resistor module, wherein the non-inverting input terminal of the error amplifier opa0 is connected to the reference signal Vref, the inverting input terminal of the error amplifier opa0 is electrically connected to the feedback resistor module, and the output control terminal G of the error amplifier opa0 is respectively connected to the gates of the power tube MP1 and the power tube MP2; After the error amplifier opa0 compares the feedback signal input from the feedback resistor module with the reference signal Vref, the output control terminal G of the error amplifier opa0 outputs a control signal to the power tube MP1 and the power tube MP2.

[0009] Preferably, the feedback resistor module includes a resistor R1 and a resistor R2, the resistor R1 and the resistor R2 are connected in series, the series-connected resistor R1 is connected to the drain of the power tube MP2, and the drain of the power tube MP2 is the output voltage Vout, the resistor R2 is grounded, and the inverting input terminal of the error amplifier opa0 is connected to the common terminal of the resistor R1 and the resistor R2.

[0010] Preferably, the feedback control amplifier module opa1 includes an input stage unit, a frequency compensation unit and an output stage unit; The input stage unit includes a power tube NM9, a power tube NM7, a power tube NM8, a power tube NM1 and a power tube NM2, the drain of the power tube NM9 is connected to the current source Ib1, the drain of the power tube NM9 is connected to the gate of the power tube NM8, the gate of the power tube NM9 is connected to the gate of the power tube NM7, the drain of the power tube NM9 is also connected to the gate of the power tube NM9, the source electrodes of the power tubes NM9, NM7 and NM8 are grounded, the drain of the power tube NM7 and the drain of the power tube NM8 are respectively connected to the source electrodes of the power tube NM1 and the power tube NM2, and the gate electrodes of the power tubes NM1 and NM2 are respectively connected to the differential input signals Vinp and Vinn; The frequency compensation unit includes a resistor R1 and a capacitor C1, and both ends of the resistor R1 and the capacitor C1 are connected in parallel to the source electrodes of the power tube NM1 and the power tube NM2 respectively; The output stage unit includes power tube NM3, power tube NM4, power tube NM5, power tube NM6, power tube PM3, power tube PM4, power tube PM5, power tube PM6 and power tube PM7, and the power tube NM3, power tube NM4, power tube NM5 and power tube NM6 together form a current mirror; The gates of the power tubes PM3 and PM4 are connected in common and are connected to a bias voltage Vbias. The sources of the power tubes PM3 and PM4 are connected to the sources of the power tubes PM5 and PM6 respectively. The drains of the power tubes NM1 and NM2 are connected to the common terminals of the power tubes PM3 and PM5 and the common terminals of the power tubes PM4 and PM6 respectively. The drains of the power tubes PM5 and PM6 are grounded. The gates of the power tubes PM5 and PM6 are connected in common and are connected to the gate and source of the power tube PM7. The drain of the power tube PM7 is grounded. The drain of the power tube PM7 is connected to a current source Ib1. The drain of the power tube PM3 is connected to the drain of the power tube NM3, the drain of the power tube PM4 is connected to the drain of the power tube NM4, the gate of the power tube NM3 is connected to the gate of the power tube NM4, the gate of the power tube NM5 is connected to the gate of the power tube NM6, the drain of the power tube PM3 is also connected to the gates of the power tubes NM3, NM4, NM5 and NM6, the drain of the power tube PM4 is the output voltage Vout, and the sources of the power tubes NM5 and NM6 are grounded.

[0011] Preferably, the feedback control amplifier module opa1 includes an input stage unit, a frequency compensation unit and an output stage unit; The input stage unit includes a power tube NM9, a power tube NM7, a power tube NM8, a power tube NM1 and a power tube NM2, the drain of the power tube NM9 is connected to the current source Ib1, the drain of the power tube NM9 is connected to the gate of the power tube NM8, the gate of the power tube NM9 is connected to the gate of the power tube NM7, the drain of the power tube NM9 is also connected to the gate of the power tube NM9, the source electrodes of the power tubes NM9, NM7 and NM8 are grounded, the drain of the power tube NM7 and the drain of the power tube NM8 are respectively connected to the source electrodes of the power tube NM1 and the power tube NM2, and the gate electrodes of the power tubes NM1 and NM2 are respectively connected to the differential input signals Vinp and Vinn; The frequency compensation unit includes a capacitor C21, a capacitor C22, a resistor R21, a resistor R22 and a bias circuit, the capacitor C21 is connected in parallel with the resistor R21, the capacitor C22 is connected in parallel with the resistor R22, one end of the resistor R21 and the resistor R22 is grounded, the other end of the resistor R21 is connected to the substrate bias potential Vsub1 of the power tube NM1, and the other end of the resistor R22 is connected to the substrate bias potential Vsub2 of the power tube NM2; The bias circuit includes a power tube PM8, a power tube PM9 and a power tube PM10, the gate of the power tube PM8 is connected to the gate of the power tube PM9 and the gate of the power tube PM10, the source of the power tube PM8 is connected to the current source Ib3, the source of the power tube PM8 is connected to the gate of the power tube PM8, the drains of the power tubes PM8, PM9 and PM10 are grounded, the source of the power tube PM9 is connected to the substrate bias potential Vsub1, and the source of the power tube PM10 is connected to the substrate bias potential Vsub2; The output stage unit includes power tube NM3, power tube NM4, power tube NM5, power tube NM6, power tube PM3, power tube PM4, power tube PM5, power tube PM6 and power tube PM7, and the power tube NM3, power tube NM4, power tube NM5 and power tube NM6 together form a current mirror; The gates of the power tubes PM3 and PM4 are connected in common and are connected to a bias voltage Vbias. The sources of the power tubes PM3 and PM4 are connected to the sources of the power tubes PM5 and PM6 respectively. The drains of the power tubes NM1 and NM2 are connected to the common terminals of the power tubes PM3 and PM5 and the common terminals of the power tubes PM4 and PM6 respectively. The drains of the power tubes PM5 and PM6 are grounded. The gates of the power tubes PM5 and PM6 are connected in common and are connected to the gate and source of the power tube PM7. The drain of the power tube PM7 is grounded. The drain of the power tube PM7 is connected to a current source Ib1. The drain of the power tube PM3 is connected to the drain of the power tube NM3, the drain of the power tube PM4 is connected to the drain of the power tube NM4, the gate of the power tube NM3 is connected to the gate of the power tube NM4, the gate of the power tube NM5 is connected to the gate of the power tube NM6, the drain of the power tube PM3 is also connected to the gates of the power tubes NM3, NM4, NM5 and NM6, the drain of the power tube PM4 is the output voltage Vout, and the sources of the power tubes NM5 and NM6 are grounded.

[0012] Preferably, the feedback control amplifier module opa1 includes an input stage unit, a frequency compensation unit and an output stage unit; The input stage unit includes a power tube NM9, a power tube NM7, a power tube NM8, a power tube NM1 and a power tube NM2, the drain of the power tube NM9 is connected to the current source Ib1, the drain of the power tube NM9 is connected to the gate of the power tube NM8, the gate of the power tube NM9 is connected to the gate of the power tube NM7, the drain of the power tube NM9 is also connected to the gate of the power tube NM9, the source electrodes of the power tubes NM9, NM7 and NM8 are grounded, the drain of the power tube NM7 and the drain of the power tube NM8 are respectively connected to the source electrodes of the power tube NM1 and the power tube NM2, and the gate electrodes of the power tubes NM1 and NM2 are respectively connected to the differential input signals Vinp and Vinn; The frequency compensation unit includes a capacitor C21 and a resistor R21, wherein the capacitor C21 is connected in parallel with the resistor R21, one end of the resistor R21 is grounded, and the other end of the resistor R21 is connected to the substrate bias potential Vsub1 of the power tube NM1 and the power tube NM2; The bias circuit includes a power tube PM8 and a power tube PM9, the gate of the power tube PM8 is connected to the gate of the power tube PM9, the source of the power tube PM8 is connected to the current source Ib3, the source of the power tube PM8 is connected to the gate of the power tube PM8, the drains of the power tube PM8 and the power tube PM9 are grounded, and the source of the power tube PM9 is connected to the substrate bias potential Vsub1; The output stage unit includes power tube NM3, power tube NM4, power tube NM5, power tube NM6, power tube PM3, power tube PM4, power tube PM5, power tube PM6 and power tube PM7, and the power tube NM3, power tube NM4, power tube NM5 and power tube NM6 together form a current mirror; The gates of the power tubes PM3 and PM4 are connected in common and are connected to a bias voltage Vbias. The sources of the power tubes PM3 and PM4 are connected to the sources of the power tubes PM5 and PM6 respectively. The drains of the power tubes NM1 and NM2 are connected to the common terminals of the power tubes PM3 and PM5 and the common terminals of the power tubes PM4 and PM6 respectively. The drains of the power tubes PM5 and PM6 are grounded. The gates of the power tubes PM5 and PM6 are connected in common and are connected to the gate and source of the power tube PM7. The drain of the power tube PM7 is grounded. The drain of the power tube PM7 is connected to a current source Ib1. The drain of the power tube PM3 is connected to the drain of the power tube NM3, the drain of the power tube PM4 is connected to the drain of the power tube NM4, the gate of the power tube NM3 is connected to the gate of the power tube NM4, the gate of the power tube NM5 is connected to the gate of the power tube NM6, the drain of the power tube PM3 is also connected to the gates of the power tubes NM3, NM4, NM5 and NM6, the drain of the power tube PM4 is the output voltage Vout, and the sources of the power tubes NM5 and NM6 are grounded.

[0013] Preferably, the drain of the power tube MP2 is also connected to one end of the resistor Rload and the capacitor CL, and the other ends of the resistor Rload and the capacitor CL are grounded.

[0014] The beneficial effects of the present invention are: 1. This circuit uses a special design of feedback control amplifier module opa1. The gain is low in the low frequency band and increased in the high frequency band. At high frequencies, the impedance of the MP1 tube is increased by increasing the MP1 substrate potential, thereby improving the power supply rejection ratio PSRR in the high frequency band, effectively suppressing the influence of high-frequency noise in the power supply on the output voltage, and meeting the requirements of the power supply rejection ratio in the high-precision field.

[0015] 2. The different designs of the feedback control amplifier module opa1, especially the setting of the frequency compensation unit, such as different capacitor and resistor combinations, have different effects on the signal at different frequencies, realize frequency compensation, and make the circuit work stably in a specific frequency band, further optimize the circuit performance, and enhance the ability to suppress power supply noise.

[0016] In addition to the above-described purposes, features and advantages, the present invention has other purposes, features and advantages. The present invention will be further described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings: Figure 1 A system block diagram of a circuit for improving the high power supply rejection ratio of an LDO according to the present invention; Figure 2 A circuit diagram for improving the high power supply rejection ratio of an LDO according to the present invention; Figure 3 is a circuit diagram of a first feedback control amplifier of the present invention; Figure 4 is a circuit diagram of a second feedback control amplifier of the present invention; Figure 5is a circuit diagram of a third feedback control amplifier of the present invention; Figure 6 It is a comparison diagram of the PSRR waveform (dashed line) of the present invention and the PSRR waveform (solid line) of the traditional architecture. DETAILED DESCRIPTION

[0018] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0019] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only embodiments of a part of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present invention.

[0020] See also Figure 1-6 , the embodiment provided by the present invention: like Figure 1 and Figure 2 As shown, a circuit for improving the high power supply rejection ratio of an LDO includes a feedback control amplifier module opa1 and a power tube module; The power tube module includes a power tube MP1 and a power tube MP2, the drain of the power tube MP1 is connected to the source of the power tube MP2, the in-phase input end of the feedback control amplifier module opa1 is connected to the source of the power tube MP1, the inverting input end of the feedback control amplifier module opa1 is respectively connected to the drain of the power tube MP1 and the source of the power tube MP2, and the output end of the feedback control amplifier module opa1 is connected to the substrate potential of the power tube MP1; The feedback resistor module includes a resistor R1 and a resistor R2, which are connected in series. The series resistor R1 is connected to the drain of the power tube MP2, and the drain of the power tube MP2 is the output voltage Vout. The resistor R2 is grounded, and the inverting input terminal of the error amplifier opa0 is connected to the common terminal of the resistor R1 and the resistor R2. The resistors R1 and R2 detect the LDO output voltage Vout and feed it back to the error amplifier opa0.

[0021] The non-inverting input terminal of the error amplifier opa0 is connected to the reference signal Vref, the inverting input terminal of the error amplifier opa0 is electrically connected to the feedback resistor module, and the output control terminal G of the error amplifier opa0 is respectively connected to the gates of the power tube MP1 and the power tube MP2; After the error amplifier opa0 compares the feedback signal input by the feedback resistor module with the reference signal Vref, the output control terminal G of the error amplifier opa0 outputs a control signal to the power tube MP1 and the power tube MP2.

[0022] After the feedback control amplifier module opa1 detects the signals of the source and drain of the power tube MP1, the output terminal vout0 of the feedback control amplifier module opa1 controls the substrate potential of the power tube MP1. Through circuit design, the amplifier gain will only increase in the high frequency band.

[0023] The working principle is: The reference signal Vref is connected to the non-inverting input terminal of the error amplifier opa0. At the same time, the output voltage Vout is divided by the feedback resistor module, resistors R1 and R2 are connected in series, and the feedback signal FB is input to the inverting input terminal of the error amplifier opa0. The error amplifier opa0 compares the two signals to determine the deviation between the output voltage Vout and the reference signal Vref.

[0024] The error amplifier opa0 outputs a control signal from the output control terminal G to the gates of the power tubes MP1 and MP2 according to the comparison result. When the output voltage Vout deviates from the reference signal Vref, the control signal adjusts the conduction degree of the power tubes MP1 and MP2, thereby adjusting the output voltage Vout. For example, if Vout is lower than Vref, the control signal will increase the conduction degree of the power tube to increase Vout; conversely, if Vout is higher than Vref, the conduction degree of the power tube will be reduced to reduce Vout, thereby achieving a stable output voltage.

[0025] The in-phase input of the feedback control amplifier module opa1 is connected to the source of the power tube MP1, and the inverting input is connected to the drain of the power tube MP1, that is, the source of the power tube MP2. Under normal circumstances, the source voltage of MP1 is higher than the drain voltage, and the voltage difference between the two is v1=Vin-Vs2. The feedback control amplifier module opa1 processes the detected source and drain signals, and its output vout0=Gain*v1 (Gain is the auxiliary amplifier gain).

[0026] The feedback control amplifier is specially designed to have a low gain in the low frequency band, so the output Vout0 voltage is low, making the substrate voltage of MP1 low; when the frequency increases, the amplifier gain increases, Vout0 increases, and the MP1 substrate potential increases accordingly. Since the increase in the MP1 substrate potential will increase the impedance of the MP1 tube, the power supply rejection ratio (PSRR) in the high frequency band is improved, effectively suppressing the impact of high-frequency noise in the power supply on the output voltage.

[0027] Furthermore, the drain of the power tube MP2 is also connected to the resistor Rload and one end of the capacitor CL, and the other ends of the resistor Rload and the capacitor CL are grounded. The drain of the power tube MP2 outputs a stable voltage Vout to power the load. At the same time, the capacitor CL plays a filtering role, smoothing the output voltage, reducing voltage fluctuations and high-frequency ripples, and ensuring the stability and purity of the output voltage.

[0028] The specific circuit design of the feedback control amplifier module is as follows: like Figure 3 As shown, the feedback control amplifier module opa1 includes an input stage unit, a frequency compensation unit and an output stage unit; The input stage unit includes power tube NM9, power tube NM7, power tube NM8, power tube NM1 and power tube NM2. The drain of power tube NM9 is connected to the current source Ib1, the drain of power tube NM9 is connected to the gate of power tube NM8, the gate of power tube NM9 is connected to the gate of power tube NM7, the drain of power tube NM9 is also connected to the gate of power tube NM9, the sources of power tube NM9, power tube NM7 and power tube NM8 are grounded, the drain of power tube NM7 and the drain of power tube NM8 are respectively connected to the sources of power tube NM1 and power tube NM2, the gates of power tube NM1 and power tube NM2 are respectively connected to differential input signals Vinp and Vinn, power tube NM1 and power tube NM2 constitute a differential input pair tube, power tube NM9, power tube NM7 and power tube NM8 provide bias current for the input stage, and a suitable static operating point is determined by current source Ib1.

[0029] The frequency compensation unit includes a resistor R1 and a capacitor C1. Both ends of the resistor R1 and the capacitor C1 are connected in parallel to the source electrodes of the power tube NM1 and the power tube NM2 respectively. The resistor R1 and the capacitor C1 form a frequency compensation network. The output stage unit includes power tube NM3, power tube NM4, power tube NM5, power tube NM6, power tube PM3, power tube PM4, power tube PM5, power tube PM6 and power tube PM7. The power tube NM3, power tube NM4, power tube NM5 and power tube NM6 together form a current mirror for copying current. The gates of the power tubes PM3 and PM4 are connected in common and are connected to the bias voltage Vbias. The sources of the power tubes PM3 and PM4 are connected to the sources of the power tubes PM5 and PM6 respectively. The drains of the power tubes NM1 and NM2 are connected to the common terminals of the power tubes PM3 and PM5 and the common terminals of the power tubes PM4 and PM6 respectively. The drains of the power tubes PM5 and PM6 are grounded. The gates of the power tubes PM5 and PM6 are connected in common and are connected to the gate and source of the power tube PM7. The drain of the power tube PM7 is grounded. The drain of the power tube PM7 is connected to the current source Ib1. The drain of the power tube PM3 is connected to the drain of the power tube NM3, the drain of the power tube PM4 is connected to the drain of the power tube NM4, the gate of the power tube NM3 is connected to the gate of the power tube NM4, the gate of the power tube NM5 is connected to the gate of the power tube NM6, the drain of the power tube PM3 is also connected to the gates of the power tubes NM3, NM4, NM5 and NM6, the drain of the power tube PM4 is the output voltage Vout, and the sources of the power tubes NM5 and NM6 are grounded.

[0030] In the low frequency range, the capacitive reactance of capacitor C1 is large, which is equivalent to an open circuit. At this time, resistor R1 is connected to the source of power tubes NM1 and NM2, introducing negative feedback, resulting in a decrease in input stage gain. As the frequency increases, the capacitive reactance of capacitor C1 decreases, showing a high-pass characteristic, making the source end approximately short-circuited, and the negative feedback effect is weakened, thereby increasing the input stage gain. In this way, the entire amplifier circuit achieves characteristics with different gains at different frequencies. At the same time, the current mirror structure ensures the current distribution and signal transmission between each stage, and finally the output terminal Vout outputs the amplified signal.

[0031] The feedback control amplifier module opa1 can also be replaced with the following design: like Figure 4 As shown, the feedback control amplifier module opa1 includes an input stage unit, a frequency compensation unit and an output stage unit; the input stage unit includes a power tube NM9, a power tube NM7, a power tube NM8, a power tube NM1 and a power tube NM2, the drain of the power tube NM9 is connected to the current source Ib1, the drain of the power tube NM9 is connected to the gate of the power tube NM8, the gate of the power tube NM9 is connected to the gate of the power tube NM7, the drain of the power tube NM9 is also connected to the gate of the power tube NM9, the source electrodes of the power tubes NM9, NM7 and NM8 are grounded, the drain of the power tube NM7 and the drain of the power tube NM8 are respectively connected to the source electrodes of the power tube NM1 and the power tube NM2, and the gate electrodes of the power tube NM1 and the power tube NM2 are respectively connected to the differential input signals Vinp and Vinn; Power tubes NM1 and NM2 form a differential input pair for receiving differential input signals Vinp and Vinn. Power tubes NM9, NM7 and NM8 provide bias current for the input stage. Current source Ib1 is used to determine a suitable static operating point to ensure that power tubes NM1 and NM2 operate in a suitable area.

[0032] The frequency compensation unit includes a capacitor C21, a capacitor C22, a resistor R21, a resistor R22 and a bias circuit. The capacitor C21 is connected in parallel with the resistor R21, the capacitor C22 is connected in parallel with the resistor R22, one end of the resistor R21 and the resistor R22 are grounded, the other end of the resistor R21 is connected to the substrate bias potential Vsub1 of the power tube NM1, and the other end of the resistor R22 is connected to the substrate bias potential Vsub2 of the power tube NM2. The capacitor C21, the capacitor C22, the resistor R21 and the resistor R22 adjust the characteristics of the circuit at different frequencies. The network formed by the capacitor C21, the capacitor C22, the resistor R21 and the resistor R22 has different effects on the signal at different frequencies, realizing frequency compensation, so that the circuit can work stably in a specific frequency band. For example, at high frequencies, the capacitance reactance becomes smaller, the signal path changes, and the amplification characteristics are affected.

[0033] The bias circuit includes a power tube PM8, a power tube PM9 and a power tube PM10, the gate of the power tube PM8 is connected to the gate of the power tube PM9 and the gate of the power tube PM10, the source of the power tube PM8 is connected to the current source Ib3, the source of the power tube PM8 is connected to the gate of the power tube PM8, the drains of the power tubes PM8, PM9 and PM10 are grounded, the source of the power tube PM9 is connected to the substrate bias potential Vsub1, and the source of the power tube PM10 is connected to the substrate bias potential Vsub2; The output stage unit includes power tubes NM3, NM4, NM5, NM6, PM3, PM4, PM5, PM6 and PM7. The NM3, NM4, NM5 and NM6 together form a current mirror, which copies and transmits the current and transmits the processed signal current to the output stage. The gates of the power tubes PM3 and PM4 are connected in common and are connected to the bias voltage Vbias. The sources of the power tubes PM3 and PM4 are connected to the sources of the power tubes PM5 and PM6 respectively. The drains of the power tubes NM1 and NM2 are connected to the common terminals of the power tubes PM3 and PM5 and the common terminals of the power tubes PM4 and PM6 respectively. The drains of the power tubes PM5 and PM6 are grounded. The gates of the power tubes PM5 and PM6 are connected in common and are connected to the gate and source of the power tube PM7. The drain of the power tube PM7 is grounded. The drain of the power tube PM7 is connected to the current source Ib1. The drain of the power tube PM3 is connected to the drain of the power tube NM3, the drain of the power tube PM4 is connected to the drain of the power tube NM4, the gate of the power tube NM3 is connected to the gate of the power tube NM4, the gate of the power tube NM5 is connected to the gate of the power tube NM6, the drain of the power tube PM3 is also connected to the gates of the power tubes NM3, NM4, NM5 and NM6, the drain of the power tube PM4 is the output voltage Vout, and the sources of the power tubes NM5 and NM6 are grounded.

[0034] The output stage unit converts the current signal into a voltage signal Vout under the bias of the current source Ib2. The bias voltage Vbias and the bias circuit ensure that the transistors at each level are at a suitable operating point to maintain the normal operation of the circuit.

[0035] The feedback control amplifier module opa1 may also be replaced with the following design: the feedback control amplifier module opa1 includes an input stage unit, a frequency compensation unit and an output stage unit; like Figure 5 As shown, the input stage unit includes a power tube NM9, a power tube NM7, a power tube NM8, a power tube NM1 and a power tube NM2, the drain of the power tube NM9 is connected to the current source Ib1, the drain of the power tube NM9 is connected to the gate of the power tube NM8, the gate of the power tube NM9 is connected to the gate of the power tube NM7, the drain of the power tube NM9 is also connected to the gate of the power tube NM9, the source electrodes of the power tubes NM9, NM7 and NM8 are grounded, the drain of the power tube NM7 and the drain of the power tube NM8 are respectively connected to the source electrodes of the power tube NM1 and the power tube NM2, and the gate electrodes of the power tubes NM1 and NM2 are respectively connected to the differential input signals Vinp and Vinn; The frequency compensation unit includes a capacitor C21 and a resistor R21, the capacitor C21 is connected in parallel with the resistor R21, one end of the resistor R21 is grounded, and the other end of the resistor R21 is connected to the substrate bias potential Vsub1 of the power tube NM1 and the power tube NM2. The network composed of the resistor R21 and the capacitor C21 generates different impedances to the signal at different frequencies. At high frequencies, the capacitive reactance of C21 decreases, which will bypass part of the signal, thereby adjusting the high-frequency gain of the circuit, avoiding high-frequency self-excitation, and making the circuit work stably. The bias circuit includes a power tube PM8 and a power tube PM9, the gate of the power tube PM8 is connected to the gate of the power tube PM9, the source of the power tube PM8 is connected to the current source Ib3, the source of the power tube PM8 is connected to the gate of the power tube PM8, the drains of the power tube PM8 and the power tube PM9 are grounded, and the source of the power tube PM9 is connected to the substrate bias potential Vsub1, so as to provide appropriate bias voltages for transistors at various levels, ensure that they work in the best state, and maintain the stable operation of the entire circuit; The output stage unit includes power tube NM3, power tube NM4, power tube NM5, power tube NM6, power tube PM3, power tube PM4, power tube PM5, power tube PM6 and power tube PM7, and the power tube NM3, power tube NM4, power tube NM5 and power tube NM6 together form a current mirror; The gates of the power tubes PM3 and PM4 are connected in common and are connected to the bias voltage Vbias. The sources of the power tubes PM3 and PM4 are connected to the sources of the power tubes PM5 and PM6 respectively. The drains of the power tubes NM1 and NM2 are connected to the common terminals of the power tubes PM3 and PM5 and the common terminals of the power tubes PM4 and PM6 respectively. The drains of the power tubes PM5 and PM6 are grounded. The gates of the power tubes PM5 and PM6 are connected in common and are connected to the gate and source of the power tube PM7. The drain of the power tube PM7 is grounded. The drain of the power tube PM7 is connected to the current source Ib1. The drain of the power tube PM3 is connected to the drain of the power tube NM3, the drain of the power tube PM4 is connected to the drain of the power tube NM4, the gate of the power tube NM3 is connected to the gate of the power tube NM4, the gate of the power tube NM5 is connected to the gate of the power tube NM6, the drain of the power tube PM3 is also connected to the gates of the power tubes NM3, NM4, NM5 and NM6, the drain of the power tube PM4 is the output voltage Vout, and the sources of the power tubes NM5 and NM6 are grounded.

[0036] like Figure 6 As shown in the figure, after comparing the new high power supply rejection LDO architecture with the traditional LDO architecture, the dotted line in the figure is the PSRR waveform of the new high power supply rejection LDO architecture, and the solid line is the PSRR waveform of the traditional LDO architecture. In the high frequency range, the PSRR of the new high power supply rejection LDO architecture is improved compared with the traditional LDO architecture. Figure 6 A_LG: error amplifier open-loop gain; β: loop gain coefficient; β*A_LG: loop gain; f: indicates that the horizontal axis in the figure represents frequency; The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A circuit for improving the power supply rejection ratio of an LDO, characterized in that: Including feedback control amplifier module opa1 and power tube module; The power tube module includes a power tube MP1 and a power tube MP2, the drain of the power tube MP1 is connected to the source of the power tube MP2, the in-phase input end of the feedback control amplifier module opa1 is connected to the source of the power tube MP1, the inverting input end of the feedback control amplifier module opa1 is respectively connected to the drain of the power tube MP1 and the source of the power tube MP2, and the output end of the feedback control amplifier module opa1 is connected to the substrate potential of the power tube MP1; After the feedback control amplifier module opa1 detects the signals of the source and drain of the power tube MP1, the output terminal vout0 of the feedback control amplifier module opa1 controls the substrate potential of the power tube MP1.

2. A circuit for improving the high power supply rejection ratio of an LDO according to claim 1, characterized in that: It also includes an error amplifier opa0 and a feedback resistor module, wherein the in-phase input terminal of the error amplifier opa0 is connected to a reference signal Vref, the inverting input terminal of the error amplifier opa0 is electrically connected to the feedback resistor module, and the output control terminal G of the error amplifier opa0 is respectively connected to the gates of the power tube MP1 and the power tube MP2; After the error amplifier opa0 compares the feedback signal input from the feedback resistor module with the reference signal Vref, the output control terminal G of the error amplifier opa0 outputs a control signal to the power tube MP1 and the power tube MP2.

3. A circuit for improving the high power supply rejection ratio of an LDO according to claim 2, characterized in that: The feedback resistor module includes a resistor R1 and a resistor R2, the resistor R1 and the resistor R2 are connected in series, the series resistor R1 is connected to the drain of the power tube MP2, and the drain of the power tube MP2 is the output voltage Vout, the resistor R2 is grounded, and the inverting input terminal of the error amplifier opa0 is connected to the common terminal of the resistor R1 and the resistor R2.

4. A circuit for improving the high power supply rejection ratio of an LDO according to claim 3, characterized in that: The feedback control amplifier module opa1 includes an input stage unit, a frequency compensation unit and an output stage unit; The input stage unit includes a power tube NM9, a power tube NM7, a power tube NM8, a power tube NM1 and a power tube NM2, the drain of the power tube NM9 is connected to the current source Ib1, the drain of the power tube NM9 is connected to the gate of the power tube NM8, the gate of the power tube NM9 is connected to the gate of the power tube NM7, the drain of the power tube NM9 is also connected to the gate of the power tube NM9, the source electrodes of the power tubes NM9, NM7 and NM8 are grounded, the drain of the power tube NM7 and the drain of the power tube NM8 are respectively connected to the source electrodes of the power tube NM1 and the power tube NM2, and the gate electrodes of the power tubes NM1 and NM2 are respectively connected to the differential input signals Vinp and Vinn; The frequency compensation unit includes a resistor R1 and a capacitor C1, and both ends of the resistor R1 and the capacitor C1 are connected in parallel to the source electrodes of the power tube NM1 and the power tube NM2 respectively; The output stage unit includes power tube NM3, power tube NM4, power tube NM5, power tube NM6, power tube PM3, power tube PM4, power tube PM5, power tube PM6 and power tube PM7, and the power tube NM3, power tube NM4, power tube NM5 and power tube NM6 together form a current mirror; The gates of the power tubes PM3 and PM4 are connected in common and are connected to a bias voltage Vbias. The sources of the power tubes PM3 and PM4 are connected to the sources of the power tubes PM5 and PM6 respectively. The drains of the power tubes NM1 and NM2 are connected to the common terminals of the power tubes PM3 and PM5 and the common terminals of the power tubes PM4 and PM6 respectively. The drains of the power tubes PM5 and PM6 are grounded. The gates of the power tubes PM5 and PM6 are connected in common and are connected to the gate and source of the power tube PM7. The drain of the power tube PM7 is grounded. The drain of the power tube PM7 is connected to a current source Ib1. The drain of the power tube PM3 is connected to the drain of the power tube NM3, the drain of the power tube PM4 is connected to the drain of the power tube NM4, the gate of the power tube NM3 is connected to the gate of the power tube NM4, the gate of the power tube NM5 is connected to the gate of the power tube NM6, the drain of the power tube PM3 is also connected to the gates of the power tubes NM3, NM4, NM5 and NM6, the drain of the power tube PM4 is the output voltage Vout, and the sources of the power tubes NM5 and NM6 are grounded.

5. The circuit for improving the power supply rejection ratio of an LDO according to claim 1, characterized in that: The feedback control amplifier module opa1 includes an input stage unit, a frequency compensation unit and an output stage unit; The input stage unit includes a power tube NM9, a power tube NM7, a power tube NM8, a power tube NM1 and a power tube NM2, the drain of the power tube NM9 is connected to the current source Ib1, the drain of the power tube NM9 is connected to the gate of the power tube NM8, the gate of the power tube NM9 is connected to the gate of the power tube NM7, the drain of the power tube NM9 is also connected to the gate of the power tube NM9, the source electrodes of the power tubes NM9, NM7 and NM8 are grounded, the drain of the power tube NM7 and the drain of the power tube NM8 are respectively connected to the source electrodes of the power tube NM1 and the power tube NM2, and the gate electrodes of the power tubes NM1 and NM2 are respectively connected to the differential input signals Vinp and Vinn; The frequency compensation unit includes a capacitor C21, a capacitor C22, a resistor R21, a resistor R22 and a bias circuit, the capacitor C21 is connected in parallel with the resistor R21, the capacitor C22 is connected in parallel with the resistor R22, one end of the resistor R21 and the resistor R22 is grounded, the other end of the resistor R21 is connected to the substrate bias potential Vsub1 of the power tube NM1, and the other end of the resistor R22 is connected to the substrate bias potential Vsub2 of the power tube NM2; The bias circuit includes a power tube PM8, a power tube PM9 and a power tube PM10, the gate of the power tube PM8 is connected to the gate of the power tube PM9 and the gate of the power tube PM10, the source of the power tube PM8 is connected to the current source Ib3, the source of the power tube PM8 is connected to the gate of the power tube PM8, the drains of the power tubes PM8, PM9 and PM10 are grounded, the source of the power tube PM9 is connected to the substrate bias potential Vsub1, and the source of the power tube PM10 is connected to the substrate bias potential Vsub2; The output stage unit includes power tube NM3, power tube NM4, power tube NM5, power tube NM6, power tube PM3, power tube PM4, power tube PM5, power tube PM6 and power tube PM7, and the power tube NM3, power tube NM4, power tube NM5 and power tube NM6 together form a current mirror; The gates of the power tubes PM3 and PM4 are connected in common and are connected to a bias voltage Vbias. The sources of the power tubes PM3 and PM4 are connected to the sources of the power tubes PM5 and PM6 respectively. The drains of the power tubes NM1 and NM2 are connected to the common terminals of the power tubes PM3 and PM5 and the common terminals of the power tubes PM4 and PM6 respectively. The drains of the power tubes PM5 and PM6 are grounded. The gates of the power tubes PM5 and PM6 are connected in common and are connected to the gate and source of the power tube PM7. The drain of the power tube PM7 is grounded. The drain of the power tube PM7 is connected to a current source Ib1. The drain of the power tube PM3 is connected to the drain of the power tube NM3, the drain of the power tube PM4 is connected to the drain of the power tube NM4, the gate of the power tube NM3 is connected to the gate of the power tube NM4, the gate of the power tube NM5 is connected to the gate of the power tube NM6, the drain of the power tube PM3 is also connected to the gates of the power tubes NM3, NM4, NM5 and NM6, the drain of the power tube PM4 is the output voltage Vout, and the sources of the power tubes NM5 and NM6 are grounded.

6. A circuit for improving the power supply rejection ratio of an LDO according to claim 1, characterized in that: The feedback control amplifier module opa1 includes an input stage unit, a frequency compensation unit and an output stage unit; The input stage unit includes a power tube NM9, a power tube NM7, a power tube NM8, a power tube NM1 and a power tube NM2, the drain of the power tube NM9 is connected to the current source Ib1, the drain of the power tube NM9 is connected to the gate of the power tube NM8, the gate of the power tube NM9 is connected to the gate of the power tube NM7, the drain of the power tube NM9 is also connected to the gate of the power tube NM9, the source electrodes of the power tubes NM9, NM7 and NM8 are grounded, the drain of the power tube NM7 and the drain of the power tube NM8 are respectively connected to the source electrodes of the power tube NM1 and the power tube NM2, and the gate electrodes of the power tubes NM1 and NM2 are respectively connected to the differential input signals Vinp and Vinn; The frequency compensation unit includes a bias circuit, a capacitor C21 and a resistor R21, wherein the capacitor C21 is connected in parallel with the resistor R21, one end of the resistor R21 is grounded, and the other end of the resistor R21 is connected to the substrate bias potential Vsub1 of the power tube NM1 and the power tube NM2; The bias circuit includes a power tube PM8 and a power tube PM9, the gate of the power tube PM8 is connected to the gate of the power tube PM9, the source of the power tube PM8 is connected to the current source Ib3, the source of the power tube PM8 is connected to the gate of the power tube PM8, the drains of the power tube PM8 and the power tube PM9 are grounded, and the source of the power tube PM9 is connected to the substrate bias potential Vsub1; The output stage unit includes power tube NM3, power tube NM4, power tube NM5, power tube NM6, power tube PM3, power tube PM4, power tube PM5, power tube PM6 and power tube PM7, and the power tube NM3, power tube NM4, power tube NM5 and power tube NM6 together form a current mirror; The gates of the power tubes PM3 and PM4 are connected in common and are connected to a bias voltage Vbias. The sources of the power tubes PM3 and PM4 are connected to the sources of the power tubes PM5 and PM6 respectively. The drains of the power tubes NM1 and NM2 are connected to the common terminals of the power tubes PM3 and PM5 and the common terminals of the power tubes PM4 and PM6 respectively. The drains of the power tubes PM5 and PM6 are grounded. The gates of the power tubes PM5 and PM6 are connected in common and are connected to the gate and source of the power tube PM7. The drain of the power tube PM7 is grounded. The drain of the power tube PM7 is connected to a current source Ib1. The drain of the power tube PM3 is connected to the drain of the power tube NM3, the drain of the power tube PM4 is connected to the drain of the power tube NM4, the gate of the power tube NM3 is connected to the gate of the power tube NM4, the gate of the power tube NM5 is connected to the gate of the power tube NM6, the drain of the power tube PM3 is also connected to the gates of the power tubes NM3, NM4, NM5 and NM6, the drain of the power tube PM4 is the output voltage Vout, and the sources of the power tubes NM5 and NM6 are grounded.

7. The circuit for improving the power supply rejection ratio of an LDO according to claim 3, characterized in that: The drain of the power tube MP2 is also connected to the resistor Rload and one end of the capacitor CL, and the other ends of the resistor Rload and the capacitor CL are grounded.

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