Multi-mode input and output function board card capable of switching clock level types

Abstract

The invention discloses a multimode input and output function board card capable of switching clock level types, which comprises a clock chip supporting multi-channel clock input and output and at least comprises a first input, a second input, a first output, a second output, a third output and a fourth output, and the input and the output are both differential clocks; the differential clock of the first input pin is externally connected with at least one input interface, and the differential clock of the second input pin is externally connected with a crystal. The differential clocks connected with the four output pins are all connected with the output interfaces used for outputting differential clock signals, the output interfaces connected with the four output pins are different, clocks of different levels can be provided, use is flexible, and the use requirements of various differential clock level types can be met.

Description

Technical Field

[0001] The invention relates to the field of electronic design, and in particular to a multi-mode input and output function board card capable of switching clock level types. Background Art

[0002] The technical application of differential clocks has been relatively complete and is widely used in high-speed circuit design. However, the current application methods are mostly for the circuit board's own clock design or the test equipment to provide a single clock. The application environment, provision method and clock type are relatively simple and cannot meet the current multi-functional and multi-scenario complex hardware test environment. The existing technical shortcomings include: 1. The clock design in the current circuit board has a relatively clear purpose, so most of them are single-level. If other clock levels are needed in the test environment, it will be difficult to handle and even require redesigning the circuit board; 2. Although some test equipment can provide differential clocks, since the equipment itself is not used to provide clocks, and the type and method of providing clocks are very single, it is difficult for such equipment to meet the usage conditions in actual application environments. Summary of the invention

[0003] To achieve the above-mentioned purpose and other related purposes, the present invention discloses a multi-mode input and output function board capable of switching clock level types, comprising: A clock chip that supports multiple clock inputs and outputs, including at least input 1, input 2, output 1, output 2, output 3, and output 4, and both the input and output are differential clocks; The differential clock of input pin one is externally connected to at least one input interface, and the differential clock of input pin two is externally connected to a crystal; The differential clocks of output one, output two, output three and output four are all connected to output interfaces for outputting differential clock signals, and the connected output interfaces are different.

[0004] Furthermore, the clock chip is connected to a DIP switch for switching input one and input two.

[0005] Furthermore, the clock chip is provided with reserved configuration pins for connecting to an external host computer, flash, or EEPROM to configure the clock chip.

[0006] Furthermore, the input 1, input 2, output 1 and output 2 are all provided with matching resistors with adjustable resistance values.

[0007] Furthermore, the input interface type of the input one connection includes a 2.4mm coaxial interface, a 2.92mm coaxial interface or a PCIe slot.

[0008] Furthermore, the output interface types connected to output one, output two, output three, and output four include a 2.4mm coaxial interface, a 2.92mm coaxial interface, a PCIe slot, or a SATA socket.

[0009] By adopting the above technical solution, a variety of high-speed interfaces for connecting the master device and the slave device can be connected to various test interfaces on the market. Even if there is a special high-speed interface requirement, it can be replaced with the required high-speed interface during design, which is convenient and practical; clocks of different levels can be provided, which is flexible to use and can meet the use requirements of various differential clocks; at least two inputs can meet the test scenarios of homologous clocks or non-homologous clocks in various situations, and the application is convenient; the configuration is simple, and for different differential clocks, different clock levels can be output by configuring the configuration pins of the clock buffer, which is flexible in application; the matching resistors of various differential clocks are easy to replace, and the matching of the termination resistors can be achieved by using the dial code, which is simple and easy to use and has strong reusability; the design is simple and the cost is low, which is suitable for use in various high-speed circuit testing fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, among which: Figure 1 is a circuit schematic diagram of the present invention; Figure 2 A pin diagram of a four-terminal capacitor used in the present invention; Figure 3 It is a schematic diagram of Case 1 in the present invention; Figure 4 It is a schematic diagram of Case 2 in the present invention. DETAILED DESCRIPTION

[0011] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0012] Reference Figure 1 The embodiment of the present invention provides a multi-mode input and output function board capable of switching clock level types, comprising: A clock chip 1 that supports multiple clock inputs and outputs. The prior art includes a variety of chips that meet this requirement. The embodiment of the present invention preferably uses the Si5330X chip, which supports two inputs and four outputs, namely input one, input two, output one, output two, output three and output four, and both the input and output are connected to differential clocks.

[0013] The differential clock of input 1 is connected to four-terminal capacitor 4 and four-terminal capacitor 5 respectively. The pin arrangement of the four-terminal capacitor is as follows: Figure 2 , wherein the a pin of the four-terminal capacitor 4 is connected to the P terminal of a differential clock input, and the b, c, and d pins of the four-terminal capacitor 4 are connected to the 2.4mm coaxial interface 6, the 2.92mm coaxial interface 7, and the PCIe slot 8 in sequence, and other interfaces can also be connected according to actual use requirements. The a pin of the four-terminal capacitor 5 is connected to the N terminal of a differential clock input, and the b, c, and d pins of the four-terminal capacitor 5 are connected to the 2.4mm coaxial interface 9, the 2.92mm coaxial interface 10, and the PCIe slot 8 in sequence.

[0014] Input one is also externally connected to a matching resistor with adjustable resistance, including resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, a two-position dip switch 12 and a two-position dip switch 13. One end of one of the pins of the dip switch 12 is connected to the power supply VDD, and the other end is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the a pin of the four-terminal capacitor 4. One end of another pin of the dip switch 12 is connected to the power supply VDD, and the other end is connected to one end of the resistor R2. The other end of the resistor R2 is connected to the a pin of the four-terminal capacitor 5. The resistor R3 is located at the P end of the differential clock, and the resistor R3 is connected between the resistor R1 and input one. The resistor R5 is located at the N end of the differential clock, and the resistor R5 is connected between the resistor R2 and input one. One end of the resistor R4 is connected between the resistor R1 and the resistor R3, and the other end of the resistor R4 is connected between the resistor R5 and input one.

[0015] One end of one pin of the DIP switch 13 is connected to the P terminal, and the connection point is between the resistor R1 and the resistor R4, and the other end of the pin is connected to one end of the resistor R7, and the other end of the resistor R7 is grounded. Another pin of the DIP switch 13 is connected to the N terminal, and the connection point is between the resistor R2 and the resistor R5, and the other end of the pin is connected to one end of the resistor R6, and the other end of the resistor R6 is grounded.

[0016] The differential clock of input two is connected to crystal 2, and two pins of crystal 2 are respectively connected to the P end and N end of the differential clock of input two. Input two is also externally connected to a matching resistor with adjustable resistance, including resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13, resistor R14, a two-position dip switch 14 and a two-position dip switch 15. One end of one of the pins of the dip switch 14 is connected to the power supply VDD, and the other end is connected to one end of the resistor R8. The other end of the resistor R8 is connected to the P end of the differential clock. One end of another pin of the dip switch 14 is connected to the power supply VDD, and the other end is connected to one end of the resistor R9. The other end of the resistor R9 is connected to the N end of the differential clock. The resistor R10 is located at the P end of the differential clock, and the resistor R10 is connected between the resistor R8 and the input two. The resistor R12 is located at the N end of the differential clock, and the resistor R12 is connected between the resistor R9 and the input two. One end of the resistor R11 is connected between the resistor R8 and the resistor R10, and the other end of the resistor R11 is connected between the resistor R12 and the input two.

[0017] One end of one pin of the DIP switch 15 is connected to the P terminal, and the connection point is between the resistor R8 and the resistor R11, and the other end of the pin is connected to one end of the resistor R14, and the other end of the resistor R14 is grounded. Another pin of the DIP switch 15 is connected to the N terminal, and the connection point is between the resistor R9 and the resistor R12, and the other end of the pin is connected to one end of the resistor R13, and the other end of the resistor R13 is grounded.

[0018] The clock chip is also externally connected to a DIP switch 3, which is a two-position DIP switch for switching between input 1 and input 2.

[0019] The clock chip also has a reserved configuration pin 11, which can be connected to an external host computer, flash, EEPROM, etc. for configuration.

[0020] The output interface types connected to Output 1, Output 2, Output 3 and Output 4 include 2.4mm coaxial interface, 2.92mm coaxial interface, PCIe slot or SATA socket, and other interfaces can also be connected according to actual usage requirements.

[0021] The P end of the differential clock output one is connected to a 2.4 mm coaxial interface 14 , and the N end is connected to a 2.4 mm coaxial interface 15 . Output 1 is also externally connected to a matching resistor with adjustable resistance, including resistor R15, resistor R16, resistor R17, resistor R18, resistor R19, resistor R20, resistor R21, a two-position dip switch 16 and a two-position dip switch 17. One end of one of the pins of the dip switch 16 is connected to the power supply VDD, and the other end is connected to one end of the resistor R15. The other end of the resistor R15 is connected to the P end of the differential clock. One end of another pin of the dip switch 16 is connected to the power supply VDD, and the other end is connected to one end of the resistor R16. The other end of the resistor R16 is connected to the N end of the differential clock. The resistor R17 is located at the P end of the differential clock, and the resistor R17 is connected between the resistor R15 and output 1. The resistor R19 is located at the N end of the differential clock, and the resistor R19 is connected between the resistor R16 and output 1. One end of the resistor R18 is connected between output 1 and the resistor R17, and the other end of the resistor R18 is connected between the resistor R19 and the resistor R16.

[0022] One end of one pin of the DIP switch 17 is connected to the P terminal, and the connection point is between the resistor R15 and the 2.4 mm coaxial interface 14, and the other end of the pin is connected to one end of the resistor R21, and the other end of the resistor R21 is grounded. Another pin of the DIP switch 17 is connected to the N terminal, and the connection point is between the resistor R16 and the 2.4 mm coaxial interface 15, and the other end of the pin is connected to one end of the resistor R20, and the other end of the resistor R20 is grounded.

[0023] The P end of the differential clock of output 2 is connected to a 2.92 mm coaxial interface 16 , and the N end is connected to a 2.92 mm coaxial interface 17 . Output 2 is also externally connected to a matching resistor with adjustable resistance, including resistor R22, resistor R23, resistor R24, resistor R25, resistor R26, resistor R27, resistor R28, a two-position dip switch 18 and a two-position dip switch 19. One end of one of the pins of the dip switch 18 is connected to the power supply VDD, and the other end is connected to one end of the resistor R22. The other end of the resistor R22 is connected to the P end of the differential clock. One end of another pin of the dip switch 18 is connected to the power supply VDD, and the other end is connected to one end of the resistor R23. The other end of the resistor R23 is connected to the N end of the differential clock. The resistor R24 ​​is located at the P end of the differential clock, and the resistor R24 ​​is connected between the resistor R22 and output 2. The resistor R26 is located at the N end of the differential clock, and the resistor R26 is connected between the resistor R23 and output 2. One end of the resistor R25 is connected between output 2 and the resistor R24, and the other end of the resistor R25 is connected between the resistor R26 and the resistor R23.

[0024] One end of one pin of the DIP switch 19 is connected to the P terminal, and the connection point is between the resistor R22 and the 2.92mm coaxial interface 16, and the other end of the pin is connected to one end of the resistor R28, and the other end of the resistor R28 is grounded. Another pin of the DIP switch 19 is connected to the N terminal, and the connection point is between the resistor R23 and the 2.92mm coaxial interface 17, and the other end of the pin is connected to one end of the resistor R27, and the other end of the resistor R27 is grounded.

[0025] The differential clock of output three is connected to the PCIe slot 18, and output three is also externally connected to a matching resistor with adjustable resistance, including resistor R29, resistor R30, resistor R31, resistor R32, resistor R33, resistor R34, resistor R35, a two-position dip switch 20 and a two-position dip switch 21, one end of one of the pins of the dip switch 20 is connected to the power supply VDD, and the other end is connected to one end of the resistor R29, the other end of the resistor R29 is connected to the P end of the differential clock, and the other end of the dip switch 20 is connected to the P end of the differential clock. One end of the pin is connected to the power supply VDD, and the other end is connected to one end of the resistor R30. The other end of the resistor R30 is connected to the N end of the differential clock. The resistor R31 is located at the P end of the differential clock, and the resistor R31 is connected between the resistor R29 and the output three. The resistor R33 is located at the N end of the differential clock, and the resistor R33 is connected between the resistor R30 and the output three. One end of the resistor R32 is connected between the output three and the resistor R31, and the other end of the resistor R32 is connected between the resistor R33 and the resistor R30.

[0026] One end of one pin of the DIP switch 21 is connected to the P terminal, and the connection point is located between the resistor R29 and the PCIe slot 18, and the other end of the pin is connected to one end of the resistor R35, and the other end of the resistor R35 is grounded. Another pin of the DIP switch 21 is connected to the N terminal, and the connection point is located between the resistor R30 and the PCIe slot 18, and the other end of the pin is connected to one end of the resistor R34, and the other end of the resistor R34 is grounded.

[0027] The differential clock of output four is connected to the SATA socket 19, and output four is also externally connected to a matching resistor with adjustable resistance, including resistor R36, resistor R37, resistor R38, resistor R39, resistor R40, resistor R41, resistor R42, a two-position dip switch 22, and a two-position dip switch 23. One end of one of the pins of the dip switch 22 is connected to the power supply VDD, and the other end is connected to one end of the resistor R36. The other end of the resistor R36 is connected to the P end of the differential clock. The other pin of the dip switch 22 is connected to the P end of the differential clock. One end of the pin is connected to the power supply VDD, and the other end is connected to one end of resistor R37, the other end of resistor R37 is connected to the N end of the differential clock, resistor R38 is located at the P end of the differential clock, and resistor R38 is connected between resistor R36 and output four, resistor R40 is located at the N end of the differential clock, and resistor R40 is connected between resistor R37 and output four, one end of resistor R39 is connected between output four and resistor R38, and the other end of resistor R39 is connected between resistor R40 and resistor R37.

[0028] One end of one pin of the DIP switch 23 is connected to the P terminal, and the connection point is between the resistor R36 and the SATA socket 19, and the other end of the pin is connected to one end of the resistor R42, and the other end of the resistor R42 is grounded. Another pin of the DIP switch 23 is connected to the N terminal, and the connection point is between the resistor R37 and the SATA socket 19, and the other end of the pin is connected to one end of the resistor R41, and the other end of the resistor R41 is grounded.

[0029] The following is an example of how to use the present invention: Reference Figure 3 , when the master device and the test version need to use the same source clock, the differential clock level type is LVDS, and the configuration uses input 1. Because it is LVDS level, there is no need for pull-up and pull-down resistors, that is, remove resistors R1, R2, R6, and R7, replace resistors R3 and R5 with 0 ohm resistors, and solder 100 ohm resistors to R4. The connection method between the master device and the multi-level differential clock function board is: if the external interface of the master device is a PCIe slot, use a PCIe extension cable to connect the master device to the PCIe slot 8 of the input 1 of this multi-level differential clock function board.

[0030] For the output end, LVDS level, replace resistors R31 and R33 with 0 ohm resistors, and remove resistors R29, R30, R32, R34, and R35. The test board is connected to the multi-level differential clock function board as follows: Use a PCIe extension cable to connect the test board to the PCIe slot 18 of the output three of the multi-level differential clock function board.

[0031] Reference Figure 4 , provide clock to a certain device or board separately, the differential clock level type is HCSL, and the configuration uses input two: The input end uses a crystal to provide HCSL differential clock, and the matching resistors R10 and R12 are replaced with 33 ohms, and the pull-down resistor is 50 ohms, so the resistors R8 and R9 need to be removed, the resistors R13 and R14 are replaced with 50 ohms, and the resistor R11 can be removed.

[0032] The output HCSL differential clock source matching resistor removes resistor R18, replaces resistors R17 and R19 with 42.2 ohms, and pulls down 86.6 ohm resistors, so resistors R15 and R16 need to be removed, and resistors R20 and R21 are replaced with 86.6 ohms. The connection method between the test board and the multi-level differential clock function board is: use two 2.4mm RF cables to connect to the 2.4mm coaxial interface 14 and 2.4mm coaxial interface 15 of the multi-level differential clock function board output 1 and the 2.4mm coaxial interface of the test board.

[0033] The present embodiment provides a multi-mode input and output function board with switchable clock level types. The high-speed interfaces for connecting the master device and the slave device are various, and can be connected to various test interfaces currently on the market. Even if there is a special high-speed interface requirement, it can be replaced with the required high-speed interface during design, which is convenient and practical; different levels of clocks (such as LVPECL, LVDS, CML, HCSL and other types of clocks) can be provided, which is flexible to use and can meet the use requirements of all differential clocks; two-way input can meet the test scenarios of homologous clocks or non-homologous clocks in various situations, and is easy to use; the configuration is simple, and for different differential clocks, different clock levels can be output by configuring the configuration pins of the clock buffer, which is flexible to use; the matching resistors of various differential clocks are easy to replace, and the matching of the termination resistors can be achieved by using the dial code, which is simple and easy to use and has strong reusability; the design is simple and the cost is low, which is suitable for use in various high-speed circuit testing fields.

[0034] Those skilled in the art will appreciate that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined.

[0035] For the method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0036] It can be known from the description of the above implementation modes that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly contributed to the prior art in the form of a software product, which can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc.) to execute the methods described in the various implementation modes of the present application or certain parts of the implementation modes.

[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-mode input and output function board capable of switching clock level types, characterized in that: include: A clock chip that supports multiple clock inputs and outputs, including at least input 1, input 2, output 1, output 2, output 3, and output 4, and both the input and output are differential clocks; The differential clock of input pin one is externally connected to at least one input interface, and the differential clock of input pin two is externally connected to a crystal; The differential clocks of output one, output two, output three and output four are all connected to output interfaces for outputting differential clock signals, and the connected output interfaces are different.

2. A multi-mode input / output function board with switchable clock level type according to claim 1, characterized in that: The clock chip is connected with a dial switch for switching input one and input two.

3. A multi-mode input / output function board with switchable clock level type according to claim 1, characterized in that: The clock chip is provided with reserved configuration pins for connecting to an external host computer, flash, or EEPROM to configure the clock chip.

4. A multi-mode input / output function board with switchable clock level type according to claim 1, characterized in that: The input 1, input 2, output 1 and output 2 are all provided with matching resistors with adjustable resistance values.

5. A multi-mode input / output function board with switchable clock level type according to claim 1, characterized in that: The input interface type of the input one connection includes a 2.4mm coaxial interface, a 2.92mm coaxial interface or a PCIe slot.

6. A multi-mode input / output function board with switchable clock level type according to claim 1, characterized in that: The output interface types of the output one, output two, output three and output four connections include a 2.4mm coaxial interface, a 2.92mm coaxial interface, a PCIe slot or a SATA socket.

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