A linear frequency digital generation method and system

Abstract

The present invention relates to a method and system for generating linear frequency. The method includes: determining a total cycle period, a maximum frequency coefficient, a minimum frequency division accuracy, a frequency coefficient, and a linear frequency range based on the application scenario; obtaining a current frequency division clock corresponding to the current application scenario, and calculating control parameters required for current frequency division control; waiting for the control parameters to be calculated and take effect; performing frequency division control based on the control parameters, and when the falling edge of the original clock arrives, generating a clock gating signal according to the value of the counter within the period; and alternating in sequence until the total cycle period is reached. The present invention combines the generation of linear frequency with the application scenario, and realizes frequency division control in a digital logic manner, which can adapt to different requirements of different application scenarios and effectively improve the EMC performance.

Description

Technical Field

[0001] The present invention belongs to the technical field of clock control, and particularly relates to a method and system for generating a linear frequency digitally. Background Art

[0002] Clock signals can be distributed throughout a processor to facilitate the operation of the processor. For example, state elements (such as flip - flops, latches, etc.) located at different points on a processor chip can operate synchronously by operating in accordance with the clock signal. When there is a large, sudden current demand, the on - chip voltage supply provided to the state elements will "drop" (e.g., within a few nanoseconds), while the PLL continues to generate a clock signal at a fixed frequency. Traditional fractional - division phase - locked loop multi - modulus dividers (MMD); a reference frequency source (Reference), for generating the basic comparison frequency of the phase - locked loop; a voltage - controlled oscillator (VCO), for outputting a signal whose frequency is N times (N can be an integer or a fraction) the output frequency of the reference source; a phase - frequency detector (PFD), for comparing the phase difference between the reference frequency and the feedback output frequency of the divider; a charge pump (CP) and a loop filter circuit (LPF), for performing negative - feedback control on the output frequency of the voltage - controlled oscillator to generate the required output frequency; and a fractional modulator (Modulator), for controlling the multi - modulus divider to generate the required fractional - division ratio.

[0003] The main methods for generating a linear frequency (such as a linear frequency - modulated signal, LFM) based on digital circuits are to implement linear frequency modulation based on DDS (Direct Digital Synthesis) technology; DDS technology is a high - precision frequency - synthesis method that generates frequency signals digitally and has advantages such as high frequency resolution, fast switching speed, and continuous phase. DDS generates a linear frequency - modulated signal by changing the frequency control word (Fword) so that the output frequency changes linearly with time. In terms of hardware implementation, an FPGA can be used to implement the DDS module, such as the FPGA of Xilinx and the DDS IP core provided by it;

[0004] The problems existing in the prior art are: on the one hand, traditional N - division of the clock frequency means changing the clock frequency to , the frequency division only follows the inverse proportional curve and cannot generate a dynamic linear frequency adapted to specific application scenarios. On the other hand, the traditional use of PLL to achieve accurate clock output will significantly increase the cost of the chip. Finally, the traditional clock frequency generation method cannot adapt to specific application scenarios, thus cannot provide sufficient flexibility and give the maximum adaptability support to the application implementation. In some application scenarios, for example, in medical scenarios, PLL is not required. For high-voltage chips with on-chip integrated charge pumps, the clock signal of the charge pump can achieve linear frequency through digital design. Similarly, the PWM control signal of the switching power supply application can also use the clock with linear frequency to generate, so as to achieve low-cost and high-precision control. Based on the above problems, the present invention combines the generation of linear frequency with application scenarios and uses digital logic to implement frequency division control, which can adapt to different requirements of different application scenarios. For example, for scenarios concerned about electromagnetic compatibility, the EMC performance can be effectively improved. Summary of the Invention

[0005] To solve the above problems in the prior art, the present invention proposes a method and system for generating digital linear frequency. The method includes:

[0006] Step S1: Determine the total cycle period , the maximum frequency coefficient , the minimum frequency division accuracy , the frequency coefficient and the linear frequency range ; where: is the total cycle period of the original clock; i.e., the value corresponding to when the linear frequency coefficient takes the maximum value; represents the minimum frequency division accuracy; N represents the frequency coefficient, and its value range is ; and respectively represent the minimum and maximum frequency clocks;

[0007] Step S2: For each divided clock , set two cycle periods, namely the first cycle period and the second cycle period, for frequency division control; obtain the current divided clock corresponding to the current application scenario and its frequency division coefficient N, and calculate the control parameters required for the current frequency division control, including: the first cycle period , the first cycle number of the first cycle period, the second cycle period , the second cycle number of the second cycle period, which are used for parameter control during the generation of each divided clock;

[0008] Step S3: Wait for the control parameter calculation to be completed and take effect;

[0009] Step S4: Period type counter When it is 0, the counter within the preloading period is or ; reset the first loop count and the second loop count to the default values; when reaches N, reset it to the default value; when first entering this step, set the counter within the period , and set ; when entering this step again, set the counter within the period to , and set ; alternate in turn until the total loop period is reached;

[0010] Step S5: When the falling edge of the original clock arrives, generate a clock gating signal according to the value of the counter within the period ; update the counter within the period, and set .

[0011] Furthermore, the application scenarios include system scenarios, application program scenarios, and user scenarios; system scenarios are information related to the operating system and / or underlying chips, application scenario information is information related to the application program type and its usage, and user information is information related to the current user;

[0012] When the falling edge of the original clock arrives, generating a clock gating signal according to the value of the counter within the period is specifically as follows: within each period when the counter within the period is counting, each such period is the first loop period or the second loop period. When the falling edge of the original clock arrives, judge the value of the counter within the period . If , set the clock gating signal to 1, otherwise clear it to 0; when the clock gating signal is set to 1, the corresponding clock gating signal is , mask the clock pulse of the current original clock , generate the partial clock after frequency division within this period , set , and return to step S4; when the clock gating signal is 0, do not mask the clock pulse of the current original clock ; within fixed total loop periods, mask N clock pulses to achieve the linear frequency as shown in , and make the N masked clock pulses evenly distributed within the total loop period.

[0013] Furthermore, set The initial value is the original clock , that is, when N = 0 ; is the minimum frequency clock and is the linear frequency coefficient The corresponding frequency when

[0014] Furthermore, the calculation of the expected maximum frequency clock , specifically: set the maximum frequency clock .

[0015] Furthermore, the determination of the expected minimum frequency clock based on the application scenario in the application scenario , specifically: obtain the required expected minimum frequency clock from the demand information of the application scenario .

[0016] Furthermore, the divided clock In addition to meeting , In addition, it is necessary to further optimize the parameters to meet the digital circuit design logic requirements on the premise of meeting the application scenario.

[0017] A linear frequency digital generation system, which is used to implement the above linear frequency digital generation method.

[0018] A linear frequency digital generation control device, which is used to implement the above linear frequency digital generation method.

[0019] A linear frequency digital generation control chip, which is used to implement the above linear frequency digital generation method.

[0020] A linear frequency digital generation control circuit, and the linear frequency digital generation module is used to implement the above linear frequency digital generation method.

[0021] The beneficial effects of the present invention include:

[0022] (1) Adapt to and subdivide the requirements of the application scenario. It is necessary to perform clock change intervals and frequency division settings according to different hierarchical requirements of the application scenario, and then make specific frequency selections according to different system settings, application program types, user characteristics, and stages in this application scenario; it can combine the frequency division settings of the underlying hardware with the application scenarios of the operating system layer and the application layer, so that the frequency division settings can cross the operating system layer to provide an application scenario adaptation interface; thus, for scenarios that pay attention to electromagnetic compatibility, the EMC performance can be effectively improved; starting from the resource demand characteristics, the present invention guides the entry of the operating mode or the low-power mode through quantitative analysis based on the combination of dynamic and static information, improving the accuracy of entering the operating mode or the low-power mode.

[0023] (2) Uniform generation of linear frequency is carried out in a digital logic manner, so that the linear frequency uniformly distributed in the frequency interval meeting the requirements of the application scenario is realized based on digital logic design to achieve low-cost and high-precision control, solving the problem that the gear distribution of the inverse proportional frequency division curve is less in the high-frequency region. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are used to provide a further understanding of the present invention, form a part of this application, but do not constitute an improper limitation to the present invention. In the drawings:

[0025] Figure 1 It is a schematic diagram of the linear frequency digital generation method provided by the present invention.

[0026] Figure 2 When the maximum frequency coefficient for the linear frequency digital generation waveform diagram provided by the present invention.

[0027] Figure 3 When the maximum frequency coefficient for the control parameter schematic diagram provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] The present invention will be described in detail below in conjunction with the drawings and specific embodiments, in which the illustrative embodiments and descriptions are only used to explain the present invention, but do not limit the present invention.

[0029] The present invention proposes a linear frequency digital generation method and system, as Figure 1 shown, the method includes the following steps:

[0030] Step S1: Determine the total cycle period , the maximum frequency coefficient , the minimum frequency division accuracy , the frequency coefficient and the linear frequency range ; where: is the total cycle period of the original clock; i.e., the value corresponding to when the linear frequency coefficient takes the maximum value; where: represents the minimum frequency division accuracy or the minimum step size of the frequency change; N represents the linear frequency coefficient, and the value range is ; and respectively represent the minimum and maximum frequency clocks; where: the application scenarios include system scenarios, application scenarios, and user scenarios; system scenarios are information related to the operating system and / or underlying chips, application scenario information is information related to the type of application and its usage, and user information is information related to the current user;

[0031] Preferably: set The initial value of to the original clock , that is, when N = 0 ; is the minimum frequency clock and is the linear frequency coefficient The corresponding frequency when ;

[0032] The specific steps of step S1 are as follows:

[0033] Step S11: Obtain the original clock according to the application scenario , the expected frequency division accuracy Or the expected maximum frequency coefficient One of, the expected minimum frequency clock , the expected maximum frequency clock ; Specifically: Obtain the original clock based on the system scenario in the application scenario ; Determine the expected frequency division accuracy based on the application scenario in the application scenario Or the expected maximum frequency coefficient , the expected minimum frequency clock , calculate the expected maximum frequency clock ; These parameters are limited by the corresponding frequency division requirements of the application scenario;

[0034] The calculation of the expected maximum frequency clock , specifically: Set the maximum frequency clock ;

[0035] Alternatively: The calculation of the expected maximum frequency clock , specifically: Determine the expected maximum frequency clock based on the application scenario in the application scenario ;

[0036] The determination of the expected minimum frequency clock based on the application scenario in the application scenario , specifically: Obtain the required expected minimum frequency clock from the requirement information of the application scenario ;

[0037] Step S12: Determine the pre-minimum frequency clock based on the expected minimum frequency clock ; Specifically: Set ; Of course, the pre-minimum frequency clock can be adjusted according to the system resource settings. For example, the accuracy of specific digits can be adjusted to reduce the accuracy limit to meet the system resource settings or the implementation requirements of the underlying hardware.

[0038] Step S13: Determine the prescaler accuracy , the pre-maximum frequency coefficient Specifically: Obtain the application type from the application scenario. When the application type is sensitive to frequency accuracy, obtain the desired minimum frequency division accuracy from the application scenario , and when the application scenario is sensitive to the number of divided clocks, obtain the desired maximum frequency coefficient from the application scenario ;

[0039] Step S14: Obtain or from one of the obtained from the application scenario or ; Specifically:

[0040] The obtaining or from one of the obtained from the application scenario or , specifically: When in the application scenario is known, calculate the parameter through the following formulas (1) and (2):

[0041] (1);

[0042] (2);

[0043] When is known, calculate the parameter through the following formulas (3) and (4):

[0044] (3);

[0045] (4);

[0046] The divided clock In addition to meeting , it is also necessary to further optimize the parameters to meet the digital circuit design logic requirements on the premise of meeting the application scenario, mainly involving the adjustment of and ;

[0047] Step S15: Fine-tune the parameters or , , to obtain those that meet the requirements of digital circuit design or 、 ; The parameters obtained from the above steps or 、 may not necessarily meet the requirements of digital circuit design. For example: is the frequency, and the calculated may be a decimal, but the frequency is usually an integer; In addition, needs to satisfy is an integer in order to meet one of the requirements of digital circuit design;

[0048] The specific step S14 is: perform fine-tuning based on the following conditions 1 - condition 4;

[0049] Condition 1: , and is close to ;

[0050] Condition 2: , and is close to ;

[0051] Condition 3: , and is close to ;

[0052] Condition 4: is an integer;

[0053] Step S16: Calculate the total cycle period ; Specifically: Set the total cycle period of the original clock; And can be divided evenly, that is is an integer; By shielding N clock pulses within a fixed number of cycle periods, to achieve the linear frequency as shown in ; Further, evenly distributing the shielded N clock pulses within the total cycle period can better meet the requirements of the application scenario; Therefore, it is necessary to determine the total cycle period according to the specific application scenario;

[0054] Step S2: For each current divided-frequency clock , set two cycle periods, namely the first cycle period and the second cycle period, for frequency division control; Obtain the current divided-frequency clock corresponding to the current application scenario and its frequency division coefficient N, and calculate the control parameters required for the current frequency division control, including: the first cycle period , the first number of cycles in the first cycle period , the second cycle period , the second number of cycles in the second cycle period , used for parameter control during the generation of each divided-frequency clock;

[0055] obtaining the current divided-frequency clock corresponding to the current application scenario and its division coefficient N, specifically: obtaining the user divided-frequency clock based on the user scenario in the application scenario ; determining the user divided-frequency clock required at the maximum frequency corresponding to the closest calculated current divided-frequency clock and its division coefficient N; using the current divided-frequency clock and its division coefficient N for the calculation of control parameters; when the user uses an application program (this application program may need to work together with the supporting hardware, which will not be elaborated here), obtaining the user divided-frequency clock based on the user attributes or user settings to meet this user scenario;

[0056] Preferably: the user sets the gear value corresponding to the user divided-frequency clock in a software or hardware manner , and the application program obtains the corresponding user divided-frequency clock based on this gear value ;

[0057] obtaining the user divided-frequency clock based on the user scenario in the application scenario ; specifically: the application program writes the user divided-frequency clock corresponding to the user attributes or user settings into the shared storage space based on the user requirements, where: the shared storage space is set in the operating system; obtaining the user divided-frequency clock in the shared storage space by reading ;

[0058] One implementation method is: the shared storage space is shared by the hardware part of the linear frequency digital generation system and the software part where the application scenario-related data is located; the software part obtains the application scenario based on the application program scenario, and obtains the maximum frequency from the application scenario , and the current divided-frequency clock and its division coefficient N determined based on the user requirements of the current user of the application program; writing the current divided-frequency clock and its division coefficient N into the shared storage space; of course, the linear frequency digital generation system itself can be set to include the hardware part and the software part where the application scenario-related data is located, and this software part is used to interact with the application program to obtain application scenario-related information; the software part where the application scenario-related data is located can also be set as a part of the application program itself;

[0059] The control parameters required for calculating the current frequency division control; specifically: calculate the first cycle period based on the following formulas (5) to (8). , the first cycle count of the first cycle period , the second cycle period , the second cycle count of the second cycle period ; where: and ; ; It can be seen that the quotient of formula (5) is the cycle period value of the first cycle period ; the remainder of formula (4) is the cycle count of the second cycle period ; N = 0 means maintaining the maximum frequency. When , due to the symmetry relationship , , and select the corresponding values; ;

[0060] (5);

[0061] (6);

[0062] (7);

[0063] (8);

[0064] Preferably: set , , , , so that it satisfies formula (9); within a fixed cycle period, it is divided into two types of cycle periods, namely the first cycle period and the second cycle period. The total count of the two cycle periods is equivalent to the fixed cycle count period; ;

[0065] (9);

[0066] Preferably: the linear frequency digital generation hardware device is used to calculate the control parameters required for the current frequency division control;

[0067] Step S3: Wait for the control parameter calculation to complete and take effect; specifically: wait for the digital logic to complete the calculation and take effect of the control parameters;

[0068] The waiting for the digital logic to complete the calculation and take effect of the control parameters is specifically as follows: after the digital logic of the hardware part of the linear frequency digital generation system completes the calculation of the control parameters, it writes them into the storage space of the hardware part of the linear frequency digital generation system; after reading the storage space of this hardware part and being able to read out valid values, it indicates that the calculation of the control parameters is completed and , , , the loading of has been completed; set the valid flag FLAG for the control parameters to take effect; at this time: the storage space of the hardware part is implemented by a register device;

[0069] Alternatively: when the calculation of the control parameters is completed by the software part, after the software part completes the calculation of the control parameters, it writes them into the storage space of the hardware part of the linear frequency digital generation system;

[0070] Step S4: Period type counter When it is 0, the counter within the preloading period is or ; reset the first loop count and the second loop count to the default values; when reaches N, reset it to the default value; when first entering this step, set the counter within the period , and set ; when entering this step again, set the counter within the period to , and set ; alternate in turn;

[0071] Preferably: during the alternation process, if or is 0, then set the counter within the period to the corresponding cycle period (the first cycle period or the second cycle period) of the non-zero one; when both are 0, will also reach N correspondingly and then be reset to the default value, and at this time, enter a new round of the cycle of the total cycle period;

[0072] Preferably: the default value of the period type counter is 0. Obviously, when first entering the total cycle period, the period type counter is the default value; the default values of the first loop count and the second loop count are the values calculated and taken effect in step S3;

[0073] Alternatively: when first entering this step, set the counter within the period , when entering this step again, set the counter within the period to ; alternate in turn;

[0074] Step S5: When the falling edge of the original clock arrives, a clock gating signal is generated according to the value of the counter within a period; update the counter within the period, and set ; ;

[0075] As Figure 2 shown, when the falling edge of the original clock arrives, a clock gating signal is generated according to the value of the counter within a period. Specifically: within each period (the first cycle period or the second cycle period) when the counter within the period is counting, when the falling edge of the original clock arrives, judge the value of the counter within the period . If , set the clock gating signal to 1; otherwise, clear it to 0. When the clock gating signal is set to 1, the corresponding clock gating signal is , mask the clock pulse of the current original clock , generate the partial clock after frequency division within this period , set , and return to step S4. When the clock gating signal is 0, do not mask the clock pulse of the current original clock ; that is to say, within fixed total cycle periods, mask N clock pulses to achieve the linear frequency as shown in , and make the N masked clock pulses evenly distributed within the total cycle period; ;

[0076] The masking of the clock pulse of the current original clock to generate the clock after frequency division ; specifically: generate the gating signal signal; generate the divided clock signal ; by repeating the first cycle period or the second cycle period and the total cycle period , and continuously repeating the above process to cyclically generate the divided clock that meets the requirements of the application scenario;

[0077] Furthermore: when performing frequency division control, use the period type counter to perform period type counting, so that the first cycle period and the second cycle period are evenly distributed in the total cycle period, and the value of the counter within the period is counted cyclically in a uniformly distributed manner; the sequential alternating control method is: when setting ; set the period type controller . If , then set ; otherwise, set , and return to step S5; it can be seen that every time After decreasing to 1, according to judge the next load or , to achieve uniform distribution, Count cyclically in this way; of course, during the alternation process, if or is 0, then set the counter within the period to the cycle period (the first cycle period or the second cycle period) corresponding to the non-zero one; when both are 0, will also reach N correspondingly, and then be reset to the default value. At this time, enter a new round of the cycle of the total cycle period; during the sequential alternation process, if or is 0, then set the counter within the period to the cycle period (the first cycle period or the second cycle period) corresponding to the non-zero one; when both are 0, will also reach N correspondingly, and then be reset to the default value. At this time, enter a new round of the cycle of the total cycle period;

[0078] To further improve the uniformity, alternatively, the sequential alternation control method is such that the first cycle period and the second cycle period are uniformly alternately arranged in the total cycle period ; thus, within the total cycle period , make the N original clock pulses to be masked evenly distributed in cycle periods; specifically: within each total cycle period , make the first cycle period and the second cycle period be evenly cross-distributed based on the first cycle count and the second cycle count respectively; on the basis of satisfying , overall evenly cross-distribute the two types of cycle periods and cycle counts to achieve that the N masked clock pulses are evenly distributed in the total cycle period; set the binary control variable , overall evenly cross-distribute the two types of cycle periods and cycle counts to achieve that the N masked clock pulses are evenly distributed in the total cycle period; due to the symmetry relationship, only consider the situation, therefore, set the bit width of the binary control variable to be , for the current frequency coefficient N, the high bit is invalid and ignored, and each bit in the low bit [N - 1:0] is respectively used to indicate within the total cycle period The cycle period type for each of the N times of loops executed inside, each bit is used to control the loop type of the current loop. Being 1 represents executing the second cycle period, and being 0 represents executing the first cycle period;

[0079] Said setting the binary control variable , cross - distributes the two types of cycle periods and the number of loops reasonably, specifically as follows:

[0080] Case 1: If and N≠0, then set CTRL[N - 1:0] all to 0;

[0081] Case 2: If , N≠0, and , then set the corresponding bit in equal to 0, ; the remaining bits are equal to 1; where: ;

[0082] Case 3: If , N≠0, and , then set the corresponding bit in equal to 1, ; the remaining bits are equal to 0; where: ;

[0083] Case 4: , N≠0, , then set according to the symmetry relationship;

[0084] The symbol is a mathematical symbol used to represent rounding up.

[0085] For example, in Figure 2 , several cases when are exemplified, specifically showing the cases of the current frequency coefficients N = 3, 8, and 12; the frequency N = 3 means that within a total cycle period , three original clocks pulses need to be masked, Figure 2 indicates the gating signal signal in , and the position where the gating signal is set to 1 indicates the position of the original clock

[0086] Example 1

[0087] The actual application scenario is , , ; Optimization parameter ; ; Substitute to obtain , to ensure that is an integer, select , at this time, , and satisfy ; Therefore, the optimized parameters are obtained: , , , the range of values that N can take is 0 to 15; the current value of N can be determined according to the user scenario; based on the linear frequency division calculation formula: ; Then when , the first cycle period , the first cycle count of the first cycle period , the second cycle period , the second cycle count of the second cycle period will change as N changes within the range of values 0 to 15, and for the uniformly distributed control variable in, after calculation, the control parameters at are as follows Figure 3 shown; Based on the same inventive concept, the present invention also provides a linear frequency digital generation system, and the system is used to complete the above linear frequency digital generation method;

[0088] The linear frequency digital generation system is implemented in a hardware manner, for example: digital logic circuits, which obtain application scenario-related data through a shared storage space; after the digital logic of the hardware part of the linear frequency digital generation system completes the calculation of the control parameters, it writes them into the storage space of the hardware part of the linear frequency digital generation system; after reading the storage space of this hardware part and being able to read out valid values, it indicates that the calculation of the control parameters is completed and , , , the loading of has been completed; set the valid flag FLAG for the control parameters to take effect;

[0089] Alternatively: The linear frequency digital generation system includes a hardware part and a software part; the hardware part works after waiting for the digital logic to complete the calculation and take effect of the control parameters, while the software part works before waiting for the digital logic to complete the calculation and take effect of the control parameters; the software part obtains application scenario-related data through the application layer data interaction method; after the digital logic of the hardware part of the linear frequency digital generation system completes the calculation of the control parameters, it writes them into the storage space of the hardware part of the linear frequency digital generation system; after reading the storage space of this hardware part and being able to read out valid values, it indicates that the calculation of the control parameters is completed and , , , The loading of has been completed; the valid flag FLAG is set to take effect as a control parameter;

[0090] A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including assembly or interpreted languages, declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may or may not correspond to a file in a file system. The program can be stored as part of a file that holds other programs or data (such as one or more scripts stored in a markup language document), in a single file dedicated to the program, or in multiple cooperating files (such as files that store one or more modules, subroutines, or portions of code). A computer program can be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communication network.

[0091] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, system, or computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) that contain computer-usable program code.

[0092] The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing device produce means for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0093] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufactured article including instruction means that implement the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0094] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus, so that a series of operation steps are executed on the computer or other programmable apparatus to produce a computer-implemented process, thereby the instructions executed on the computer or other programmable apparatus provide steps for realizing the functions specified in one process or a plurality of processes and / or one block or a plurality of blocks in the flow Figure 1 one process or a plurality of processes and / or blocks Figure 1 steps for realizing the functions specified in one block or a plurality of blocks.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: still modifications or equivalent replacements can be made to the specific embodiments of the present invention, and any modifications or equivalent replacements that do not depart from the spirit and scope of the present invention shall be covered by the protection scope of the claims of the present invention.

Claims

1. A method for generating a linear frequency digitally, characterized in that, The method includes: Step S1: Determine the total cycle period based on the application scenario , the maximum frequency coefficient , the minimum frequency division accuracy , the frequency coefficient , and the linear frequency range ; where: is the total cycle period of the original clock; that is, the value corresponding to when the linear frequency coefficient takes the maximum value; represents the minimum frequency division accuracy; N represents the frequency coefficient, and its value range is ; and respectively represent the minimum and maximum frequency clocks; the application scenario includes the system scenario, the application program scenario, and the user scenario; the system scenario is information related to the operating system and / or the underlying chip, the application scenario information is information related to the application program type and its usage, and the user information is information related to the current user; Step S2: For each divided-frequency clock , set two cycle periods, namely the first cycle period and the second cycle period, for divided-frequency control; obtain the current divided-frequency clock corresponding to the current application scenario and its divided-frequency coefficient N, and calculate the control parameters required for the current divided-frequency control, including: the first cycle period , the first cycle count of the first cycle period , the second cycle period , the second cycle count of the second cycle period , which are used for parameter control during the generation of each divided-frequency clock; Step S3: Wait for the control parameter calculation to be completed and take effect; Step S4: Period type counter When it is 0, the counter within the preloading period is or ; reset the first loop count and the second loop count to default values; when reaches N, reset it to the default value; when first entering this step, set the counter within the period , and set ; when entering this step again, set the counter within the period to , and set ; alternate in turn until the total cycle period is reached; Step S5: When the falling edge of the original clock arrives, a clock gating signal is generated according to the value of the counter within the period; update the counter within the period, and set . .

2. The linear frequency digital generation method according to claim 1, characterized in that When the falling edge of the original clock arrives, a clock gating signal is generated according to the value of the counter within the period, specifically: within each period during which the counter within the period counts, each such period is the first cycle period or the second cycle period. When the falling edge of the original clock arrives, the value of the counter within the period is judged. If , the clock gating signal is set to 1, otherwise it is cleared to 0; when the clock gating signal is set to 1, the corresponding clock gating signal is , the clock pulse of the current original clock is masked, and the partial clock after frequency division within the period is generated. is set, and step S4 is returned; when the clock gating signal is 0, the clock pulse of the current original clock is not masked; within fixed total cycle periods, N clock pulses are masked to achieve the linear frequency as shown in , and the N masked clock pulses are evenly distributed within the total cycle period .

3. The linear frequency digital generation method according to claim 2, wherein Set the initial value to the original clock , that is, when N = 0 ; is the minimum frequency clock and is the linear frequency coefficient at the corresponding frequency when 4. The linear frequency digital generation method according to claim 3, wherein Calculate the expected maximum frequency clock , specifically: set the maximum frequency clock .

5. The linear frequency digital generation method according to claim 4, characterized in that, Determining the desired minimum frequency clock based on the application program scenario in the application scenario , specifically: obtaining the required desired minimum frequency clock from the requirement information of the application program scenario .

6. The linear frequency digital generation method according to claim 5, characterized in that, Frequency-divided clock In addition to meeting the requirements of , it is also necessary to further optimize the parameters to meet the logic requirements of digital circuit design on the premise of meeting the application scenarios.

7. A linear frequency digital generation system, characterized in that The linear frequency digital generation system is used to implement the linear frequency digital generation method described in any one of claims 1-6 above.

8. A linear frequency digital generation control device, characterized in that The linear frequency digital generation control device is used to implement the linear frequency digital generation method described in any one of claims 1-6 above.

9. A linear frequency digital generation control chip, characterized in that, The linear frequency digital generation control chip is used to implement the linear frequency digital generation method described in any one of claims 1-6 above.

10. A linear frequency digital generation control circuit, characterized in that The linear frequency digital generation module is used to implement the linear frequency digital generation method described in any one of claims 1-6 above.

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