SOC Chip Clock Calibration Method Based on 2.4GHz Airborne Signal

Abstract

The present invention discloses a method for calibrating the clock of an SOC chip based on a 2.4GHz signal in the air, belonging to the technical field of chip clock calibration. The method for calibrating the clock of an SOC chip based on a 2.4GHz signal in the air includes the following specific steps: Step 1: 2.4GHz signal reception and preprocessing: A miniaturized ceramic patch antenna is used, and an integrated low-noise amplifier (LNA) is used to amplify the signal to above -20dBm, with a noise figure ≤ 3dB. The 2.4GHz carrier is down-converted to the baseband through a quadrature mixer, and the image interference is suppressed by a 10MHz low-pass filter. The present invention does not require an external crystal oscillator design for calibrating the clock of the SOC chip through a 2.4GHz signal, and completely relies on the wireless signal in the air to achieve clock synchronization. At the same time, it experiments with multi-protocol compatibility: supports 2.4GHz protocols such as Wi-Fi 802.11b / g / n, Bluetooth 5.0, and ZigBee, and automatically adjusts the calibration period and compensation strategy according to the signal quality.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip clock calibration, and particularly relates to a method for calibrating the clock of an SOC chip based on a 2.4GHz signal in the air. Background Art

[0002] SOC chip clock calibration refers to the process of adjusting the clock frequency or phase inside a System-on-a-Chip through specific technical means to make it reach the design target or synchronize with an external reference signal. This technology is crucial for ensuring the timing consistency and performance stability of each module of the chip (such as CPU, wireless communication, peripheral interfaces, etc.).

[0003] The limitations of traditional clock calibration methods are: relying on external crystal oscillators or temperature-compensated crystal oscillators (TCXOs), which increases the system cost and volume. The crystal oscillator is vulnerable to environmental factors such as temperature and voltage, resulting in frequency drift. In complex scenarios, additional circuits are required for compensation, reducing the SOC integration. At the same time, calibration methods based on wired reference signals are not suitable for wireless terminal devices, and traditional wireless calibration methods have problems such as high power consumption and response delay. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the above-mentioned shortcomings of the prior art and provide a method for calibrating the clock of an SOC chip based on a 2.4GHz signal in the air.

[0005] The technical solution adopted to solve the above technical problem is: a method for calibrating the clock of an SOC chip based on a 2.4GHz signal in the air, including the following specific steps:

[0006] Step 1: 2.4GHz signal reception and preprocessing:

[0007] Adopt a miniaturized ceramic patch antenna, use an integrated low-noise amplifier LNA to amplify the signal to above -20dBm, with a noise figure ≤ 3dB. Down-convert the 2.4GHz carrier to the baseband through a quadrature mixer, and suppress image interference through a 10MHz low-pass filter;

[0008] Step 2: Timestamp extraction and synchronization sequence detection:

[0009] Use a sliding correlator to match the preamble and output the peak position , calculate the signal propagation delay, and correct the timestamp;

[0010] Step 3: Phase error calculation and frequency deviation estimation:

[0011] Establish a phase model, generate the clock phase and the reference signal phase by the DCO, and then calculate the phase error;

[0012] Step 4: Adaptive clock frequency adjustment:

[0013] Adjust using the PID control algorithm, with the constraint that the adjusted frequency must satisfy ;

[0014] Calculate the signal-to-noise ratio through the received signal strength indication for SNR detection;

[0015] Step 5: Anti-interference and robustness enhancement:

[0016] Convert the signal strength to linear power, synthesize the phase error, perform moving average filtering, and then eliminate outliers;

[0017] Step 6: Calibration result feedback and verification:

[0018] Update the DCO control code, calculate the DAC value according to and synchronously update the system clock divider parameters to ensure that the working frequencies of all modules are consistent. Then, verify the calibration accuracy, continuously collect 100 groups of calibration data, and calculate the standard deviation of the frequency deviation.

[0019] Through the above technical solutions, there is no need to rely on external crystal oscillators or temperature-compensated crystal oscillators (TCXOs), which reduces the system cost and volume, does not produce frequency drift, improves the integration of the SOC, and at the same time has low power consumption and fast response.

[0020] Further, the said Step 2 includes:

[0021] Wi-Fi Beacon frame processing: Detect the frame header signature, and then parse the MAC address field to extract the timestamp;

[0022] Bluetooth broadcast packet processing: Identify the access address and extract the synchronization word.

[0023] Further, the output peak position in the said Step 2 adopts the following specific formula:

[0024] ;

[0025] where is the preamble sequence stored locally, and N = 128 is the sequence length;

[0026] The corrected timestamp adopts the following specific formula:

[0027] Calculate the signal propagation delay (d is the transceiver distance, c is the speed of light), and the corrected timestamp is:

[0028] .

[0029] Through the above technical solution, the accuracy of the timestamp is greatly improved, and errors are avoided.

[0030] Further, the clock phase generated by the DCO in step three is:

[0031] ;

[0032] The reference signal phase is: , where is the carrier frequency;

[0033] The phase error is calculated using the following formula:

[0034] The phase error at the timestamp is:

[0035] ;

[0036] The frequency deviation is calculated by calibrating the timestamps and on both sides:

[0037] .

[0038] Further, the frequency update formula of the PID control algorithm in step four is:

[0039] ,

[0040] where, , , .

[0041] Further, the SNR detection uses the following formula:

[0042] ;

[0043] where B = 20MHz is the channel bandwidth.

[0044] Further, the linear power conversion formula is as follows:

[0045] ;

[0046] where is the signal strength.

[0047] Further, the standard deviation of the frequency deviation in step six uses the following formula:

[0048] ;

[0049] Test results .

[0050] Through the above technical solutions, anti-interference calibration can be achieved through signal quality monitoring, greatly improving the overall accuracy.

[0051] The beneficial effects of the present invention are as follows: The present invention calibrates the clock of the SOC chip through a 2.4GHz signal without the need for an external crystal oscillator design, and fully relies on the wireless signal in the air to achieve clock synchronization. At the same time, it experiments with multi-protocol compatibility: supports 2.4GHz protocols such as Wi-Fi802.11b / g / n, Bluetooth 5.0, ZigBee, etc., and automatically adjusts the calibration period and compensation strategy according to the signal quality. Brief Description of the Drawings

[0052] Figure 1 is a flowchart of the present invention. Detailed Embodiments

[0053] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0054] As Figure 1 shown, the method for calibrating the clock of the SOC chip based on the 2.4GHz signal in the air in this embodiment includes the following specific steps:

[0055] Step 1: 2.4GHz signal reception and preprocessing:

[0056] Adopt a miniaturized ceramic patch antenna, use an integrated low-noise amplifier LNA to amplify the signal to above -20dBm, with a noise figure ≤ 3dB, down-convert the 2.4GHz carrier to the baseband through a quadrature mixer, and suppress image interference through a 10MHz low-pass filter;

[0057] Step 2: Timestamp extraction and synchronization sequence detection:

[0058] Use a sliding correlator to match the preamble and output the peak position , calculate the signal propagation delay, and correct the timestamp;

[0059] Step 3: Phase error calculation and frequency deviation estimation:

[0060] Establish a phase model, generate the clock phase and the reference signal phase by the DCO, and then calculate the phase error;

[0061] Step 4: Adaptive clock frequency adjustment:

[0062] Adopt a PID control algorithm for adjustment, and the constraint condition is that the adjusted frequency needs to satisfy ;

[0063] Calculate the signal-to-noise ratio through the received signal strength indication for SNR detection;

[0064] Step Five: Anti-interference and Robustness Enhancement:

[0065] Convert the signal strength to linear power, synthesize the phase error, perform moving average filtering, and then remove outliers;

[0066] Step Six: Calibration Result Feedback and Verification:

[0067] Update the DCO control code. According to Calculate the DAC value and synchronously update the system clock divider parameters to ensure that the operating frequencies of all modules are consistent. Then, verify the calibration accuracy, continuously collect 100 groups of calibration data, calculate the standard deviation of the frequency deviation, without relying on an external crystal oscillator or a temperature-compensated crystal oscillator (TCXO), reduce the system cost and volume, avoid frequency drift, improve the integration of the SOC, and at the same time have low power consumption and fast response.

[0068] The said Step Two includes:

[0069] Wi-Fi Beacon frame processing: Detect the frame header signature, and then parse the MAC address field to extract the timestamp;

[0070] Bluetooth broadcast packet processing: Identify the access address and extract the synchronization word.

[0071] The output peak position in the said Step Two Adopts the following specific formula:

[0072] ;

[0073] where is the preamble sequence stored locally, and N = 128 is the sequence length;

[0074] The corrected timestamp adopts the following specific formula:

[0075] Calculate the signal propagation delay (d is the transceiver distance, c is the speed of light), and the corrected timestamp is:

[0076] ;

[0077] Greatly improves the accuracy of the timestamp and avoids generating errors.

[0078] The clock phase generated by the DCO in the said Step Three is:

[0079] ;

[0080] The reference signal phase is: , where is the carrier frequency;

[0081] The phase error is calculated using the following formula:

[0082] At the timestamp the phase error is:

[0083] ;

[0084] The frequency deviation is calculated by calibrating the timestamps and on both sides:

[0085] .

[0086] The frequency update formula of the PID control algorithm in step four is:

[0087] ;

[0088] where , , .

[0089] The SNR detection uses the following formula:

[0090] ;

[0091] where B = 20 MHz is the channel bandwidth.

[0092] The linear power conversion formula is as follows:

[0093] ;

[0094] where is the signal strength.

[0095] The standard deviation of the frequency deviation in step six uses the following formula:

[0096] ;

[0097] Test results , anti-interference calibration can be achieved through signal quality monitoring, greatly improving the overall accuracy.

[0098] The above is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention.

Claims

1. A SOC chip clock calibration method based on 2.4GHz signals in the air, characterized in that: The specific steps include: Step 1: 2.4GHz signal reception and preprocessing: Adopt miniaturized ceramic patch antenna, use integrated low noise amplifier LNA to amplify the signal to above -20dBm, noise figure ≤3dB, down-convert 2.4GHz carrier to baseband through orthogonal mixer, and suppress image interference through 10MHz low-pass filter; Step 2: Timestamp extraction and synchronization sequence detection: Use sliding correlator to match the preamble and output the peak position , calculate the signal propagation delay and correct the timestamp; Step 3: Phase error calculation and frequency deviation estimation: Establish a phase model, generate the clock phase by DCO, reference signal phase, and then calculate the phase error; Step 4: Adaptive clock frequency adjustment: The PID control algorithm is used for adjustment, and the constraint condition is that the frequency after adjustment must meet ; Calculate the signal-to-noise ratio through the received signal strength indication and perform SNR detection; Step 5: Anti-interference and robustness enhancement: The signal strength is converted into linear power, the phase error is integrated, and then the outliers are removed through sliding average filtering; Step 6: Calibration result feedback and verification: Update the DCO control code according to Calculate the DAC value and update the system clock divider parameters synchronously to ensure that the operating frequency of each module is consistent. Then perform calibration accuracy verification, continuously collect 100 sets of calibration data, and calculate the standard deviation of frequency deviation. The second step comprises: Wi-Fi Beacon frame processing: detect the frame header signature, then parse the MAC address field and extract the timestamp; Bluetooth advertising packet processing: identifying access address and extracting synchronization word.

2. The SOC chip clock calibration method based on the 2.4 GHz signal in the air according to claim 1 is characterized in that: The output peak position in step 2 The following specific formula is used: ； in is the preamble sequence stored locally, N=128 is the sequence length; The timestamp is modified using the following specific formula: Calculate signal propagation delay , where d is the sending and receiving distance, c is the speed of light, and the corrected timestamp is: 。 3. The SOC chip clock calibration method based on the 2.4 GHz signal in the air according to claim 1 is characterized in that: The clock phase generated by the DCO in step 3 is: ； The reference signal phase is: ,in Carrier frequency; The phase error is calculated using the following formula: In timestamp The phase error at is: ； By calibrating the time stamp on both sides and Calculate the frequency deviation: 。 4. The SOC chip clock calibration method based on the 2.4 GHz signal in the air according to claim 1, characterized in that: The frequency update formula of the PID control algorithm in step 4 is: ,in, , , .

5. The SOC chip clock calibration method based on 2.4 GHz signal in the air according to claim 1, characterized in that: The SNR detection adopts the following formula: ； Where B=20MHz is the channel bandwidth.

6. The SOC chip clock calibration method based on 2.4 GHz signal in the air according to claim 1, characterized in that: The linear power conversion formula is as follows: ； in is the signal strength.

7. The SOC chip clock calibration method based on 2.4 GHz signal in the air according to claim 1, characterized in that: The frequency deviation standard deviation in step 6 adopts the following formula: ； Test Results .

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