Data reading method and device of memory, computer equipment and storage medium

Abstract

The invention relates to the field of servers, and discloses a data reading method and device of a memory, computer equipment and a storage medium, the method comprises the following steps: obtaining a first address set from a reset circuit, the first address set comprising a plurality of first addresses in the memory, and the first address set being dynamically generated by a system according to a preset condition or configuration; a plurality of first data corresponding to a plurality of first addresses of the first address set are read from the memory, and one first address corresponds to one first data; and sending the plurality of first data to the register through the second controller. Therefore, the memory data can be transmitted and stored in the register, so that a subsequent processor directly reads the first data of the memory from the register, and compared with reading from the memory, the method has the advantages that the delay of obtaining the first data by the processor is reduced, and the reading rate is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of servers, and in particular to a method and device for reading data from a memory, a computer device, and a storage medium. Background Art

[0002] Inside the BMC (Baseboard Management Controller), a One Time Programmable Read Only Memory (OTP ROM) is used to store critical data, such as key information and configuration information. The confidentiality and integrity of this type of data is critical because once tampered with, it may lead to serious security vulnerabilities in the system. OTP ROM has the characteristic of being non-rewritable, which means that after data is written, its value cannot be changed, but it can still be read. This feature makes OTP ROM an ideal choice for storing sensitive information and can effectively prevent data from being maliciously modified.

[0003] Although OTP ROM has advantages in security, its programming and reading time is usually in microseconds, which is relatively long compared to the nanosecond reaction time of the processor. This delay causes the system to waste multiple cycles while waiting for the OTP ROM to respond, reducing the overall processing efficiency. Summary of the invention

[0004] In view of this, the present invention provides a method, an apparatus, a computer device, and a storage medium for reading data from a memory to solve the problem of how to optimize the communication efficiency between a processor and a memory to improve the response speed of the system.

[0005] In a first aspect, the present invention provides a method for reading data from a memory, the method is applied to a first controller, the first controller is connected to a reset circuit, a second controller and a memory respectively, and the method comprises:

[0006] During the system reset process, a first address set is obtained from the reset circuit, the first address set includes a plurality of first addresses in the memory, and the first address set is dynamically generated by the system according to a preset condition or configuration;

[0007] Reading a plurality of first data corresponding to a plurality of first addresses of a first address set from a memory, wherein one first address corresponds to one first data;

[0008] The plurality of first data are sent to the register through the second controller.

[0009] The present invention provides a method for reading data from a memory, which has the following advantages:

[0010] First, a first address set from a reset circuit is obtained through a first controller, and multiple first data corresponding to multiple first addresses are read from a memory according to the first address set, and then the multiple first data read are sent to a register through a second controller, so that the memory data can be transmitted and stored in the register, so that a subsequent processor can directly read the first data of the memory from the register. Compared with reading from the memory, this method reduces the delay of the processor in obtaining the first data and improves the reading rate. In addition, based on the corresponding data in the synchronization memory of the first address set from the reset circuit, the storage resources of the register can be saved, thereby reducing the hardware volume and cost.

[0011] In combination with the first aspect, in an optional implementation, the first controller is connected to the processor;

[0012] After sending the plurality of first data to the register through the second controller, the method further includes:

[0013] Receive first programming information sent by the processor, the first programming information including: first programming data and a second address, the first programming data is generated by a logic operation between second data obtained by the processor from the register and first initial programming data, the first initial programming data is generated by the processor according to the first configuration instruction, and the second data is the first data corresponding to the second address among a plurality of first data stored in the register;

[0014] According to the first programming information, the first programming data is written into the memory according to the second address.

[0015] Specifically, in the steps of the method, after synchronizing multiple first data to the register, the first programming information with the second address and the first programming data sent by the processor is received, and the first programming data is generated by the processor first obtaining the second data from the register, and performing a logical operation with the first initial programming data generated based on the first configuration instruction, and then writing the first programming data to the second address of the memory. Therefore, before the processor writes the first programming data to the memory, it can be verified with the data in the register through a logical operation, and the first programming data can be written to the memory after ensuring the data consistency, thereby ensuring the security of data writing.

[0016] In combination with the first aspect, in another optional implementation manner, after writing the first programming data into the memory, the method further includes:

[0017] Get the working status of the memory in real time;

[0018] Determining whether the memory can perform a write operation according to the working state;

[0019] If yes, generating a first status signal;

[0020] When receiving a first detection instruction sent by the processor, sending a first state signal to the processor;

[0021] receiving second programming information sent by the processor, the second programming information comprising: second programming data and a third address, the second programming information is sent by the processor when the first state signal is received, the second programming data is generated by performing a logic operation between the third data obtained by the processor from the register and the second initial programming data, the second initial programming data is generated by the processor according to the second configuration instruction, and the third data is the first data corresponding to the third address among the multiple first data stored in the register;

[0022] Writing the second programming data into the memory at the third address according to the second programming information;

[0023] The first state signal is updated to a second state signal to indicate that the memory cannot perform a write operation.

[0024] Specifically, in the steps of the method, by acquiring the working state of the memory in real time, it is determined whether the memory can perform a write operation, and if it can, a first state signal is generated. Then, after receiving the first detection instruction sent by the processor, the first state signal is sent to the processor. The processor obtains the third data from the register, generates the second programming data after performing a logical operation with the second initial programming data generated based on the second configuration instruction, and then sends it to the first controller together with the third address. The first controller writes the second programming data to the third address of the memory, and updates the first state signal to the second state signal, indicating that the memory cannot perform a write operation. Therefore, before the processor writes the second programming data to the memory, it can be verified with the data in the register through a logical operation, and the second programming data can be written to the memory after ensuring the consistency of the data, thereby ensuring the security of data writing. At the same time, by first determining the working state of the memory and then receiving the second programming data, it is avoided that the memory receives a second write operation while writing one piece of data, thereby ensuring the orderliness of the memory data writing process and the security of the memory data.

[0025] In an optional implementation, after determining that the memory cannot perform a write operation, the method further includes:

[0026] generating a second state signal;

[0027] When receiving a second detection instruction sent by the processor, sending a second state signal to the processor;

[0028] or, after updating the first state signal to the second state signal, receiving a third detection instruction sent by the processor;

[0029] In response to the third detection instruction, a second state signal is sent to the processor.

[0030] Specifically, in the steps of the method, a second state signal is generated when it is determined that the working state of the memory cannot perform a write operation. Then, when a second detection instruction sent by the processor is received, the second state signal is sent to the processor, or after the first state signal is updated to the second state signal, in response to a third detection instruction sent by the processor, the second state signal is sent to the processor, instructing the processor to stop sending other programming information and wait for the memory to complete the write operation corresponding to the current programming data, thereby ensuring the orderliness of the memory data writing process and the security of the memory data.

[0031] In a second aspect, the present invention provides a method for reading data from a memory, the method being applied to a second controller, the method comprising:

[0032] During the system reset process, a plurality of first data are received from the first controller; the plurality of first data are read by the first controller from the memory and correspond to a plurality of first addresses of the first address set, wherein one first address corresponds to one first data;

[0033] Determine a plurality of fourth addresses corresponding to each first data in the register according to a preset corresponding relationship, wherein the preset corresponding relationship is a corresponding relationship between at least one first data and a fourth address in the register;

[0034] According to the determined at least one fourth address, the plurality of first data are stored in the register.

[0035] The server data processing method provided by the present invention has the following advantages:

[0036] First, multiple first data corresponding to multiple first addresses of a first address set are received from a memory by a first controller. Then, according to a preset correspondence relationship set, the multiple first data are stored in multiple addresses in a register, so that the memory data can be transmitted and stored in the register, so that the subsequent processor can directly read the first data of the memory from the register. Compared with reading from the memory, this method reduces the delay of the processor in obtaining the first data and improves the reading rate.

[0037] In addition, based on the corresponding data in the first address set synchronous memory from the reset circuit, the storage resources of the register can be saved, thereby reducing the hardware volume and cost.

[0038] In an optional implementation, after storing the plurality of first data in the register, the method further includes:

[0039] receiving a first read instruction sent by the processor, wherein the first read instruction includes a target fourth address of the register;

[0040] Reading the corresponding first data in the register according to the target fourth address as the target first data;

[0041] The target first data is sent to the processor.

[0042] Specifically, in the method steps, after receiving the first read instruction sent by the processor, the first data is read from the register based on the fourth address in the first read instruction. Then the found fourth data is fed back to the processor, thereby realizing the technical effect that the processor directly reads the first data of the memory from the register, and reduces the delay of the processor in obtaining the first data.

[0043] In an optional implementation manner, after sending the target first data to the processor, the method further includes:

[0044] receiving a second read instruction sent by the processor, where the second read instruction includes a fifth address of the register;

[0045] Reading fourth data from the register according to the fifth address;

[0046] sending fourth data to the processor;

[0047] receiving third programming data sent by the processor, where the third programming data is obtained by performing a logic operation on the third initial programming data and the fourth data, and the third initial programming data is generated by the processor according to the third configuration instruction;

[0048] In the register, the fourth data is updated to the third programming data.

[0049] Specifically, in the steps of the method, the fourth data corresponding to the fifth address in the second read instruction is read from the register according to the second read instruction sent by the processor. Then the fourth data is fed back to the processor. The processor can perform a logical operation on the fourth data according to the third initial programming data, and use the obtained third programming data to update the fourth data. Therefore, before the processor writes the third programming data to the memory, it can first verify with the data in the register through a logical operation, and then write the third programming data to the register and the memory after ensuring that the data is consistent, thereby ensuring the consistency and security of data writing.

[0050] In a third aspect, the present invention provides a data reading device for a memory, the device is applied to a first controller, the first controller is connected to a reset circuit, a second controller and a memory respectively, and the device comprises:

[0051] A first acquisition module, used for acquiring a first address set from a reset circuit during a system reset process, the first address set including a plurality of first addresses in a memory, and the first address set is dynamically generated by the system according to a preset condition or configuration;

[0052] A first reading module is used to read a plurality of first data corresponding to a plurality of first addresses of a first address set from a memory, wherein one first address corresponds to one first data;

[0053] The first sending module is used to send a plurality of first data to the register through the second controller.

[0054] The present invention provides a memory data reading device, which first obtains a first address set from a reset circuit through a first controller, reads a plurality of first data corresponding to a plurality of first addresses from the memory according to the first address set, and then sends the read plurality of first data to a register through a second controller, thereby realizing transmission and storage of memory data in the register, so that a subsequent processor directly reads the first data of the memory from the register. Compared with reading from the memory, the method reduces the delay of the processor in obtaining the first data and improves the reading rate. In addition, the corresponding data in the memory is synchronized based on the first address set from the reset circuit, saving the storage resources of the register and reducing the cost.

[0055] In a fourth aspect, the present invention provides a data reading device for a memory, the device is applied to a second controller, and the device includes:

[0056] A fourth receiving module is used to receive a plurality of first data from the first controller during the system reset process; the plurality of first data are read by the first controller from the memory and correspond to a plurality of first addresses of the first address set, wherein one first address corresponds to one first data;

[0057] A second determining module, configured to determine a fourth address corresponding to each first data in the register according to a preset corresponding relationship, wherein the preset corresponding relationship is a corresponding relationship between at least one first data and the fourth addresses in the plurality of registers;

[0058] The storage module is used to store the plurality of first data in the register according to the determined at least one fourth address.

[0059] The server data processing device provided by the present invention has the following advantages:

[0060] First, multiple first data corresponding to multiple first addresses of a first address set are received from a memory by a first controller. Then, according to a preset correspondence set, the multiple first data are stored in multiple addresses in a register, so that the memory data can be transmitted and stored in the register, so that the subsequent processor can directly read the first data of the memory from the register. Compared with reading from the memory, this method reduces the delay of the processor in obtaining the first data and improves the reading rate. In addition, based on the first address set, the corresponding data in the synchronous memory can save the storage resources of the register, thereby reducing the hardware volume and cost.

[0061] In a fifth aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, computer instructions being stored in the memory, and the processor executing the data reading method of the memory of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0062] In a sixth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the data reading method of a memory of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0064] Figure 1 is a schematic diagram of hardware connection relationships of a method for reading data from a memory according to an embodiment of the present invention;

[0065] Figure 2 is one of the flow charts of the data reading method of the memory according to the embodiment of the present invention;

[0066] Figure 3 is a second flowchart of a method for reading data from a memory according to an embodiment of the present invention;

[0067] Figure 4 is a schematic diagram of a process of performing data synchronization from an OTP controller to a register according to an embodiment of the present invention;

[0068] Figure 5 is a third flowchart of a method for reading data from a memory according to an embodiment of the present invention;

[0069] Figure 6 is a fourth flowchart of a method for reading data from a memory according to an embodiment of the present invention;

[0070] Figure 7 This is one of the structural schematic diagrams of a data reading device of a memory according to an embodiment of the present invention;

[0071] Figure 8 This is a second structural schematic diagram of a data reading device of a memory according to an embodiment of the present invention;

[0072] Fig. 9 It is a structural schematic diagram of a computer device provided by an optional embodiment of the present invention. DETAILED DESCRIPTION

[0073] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0074] According to an embodiment of the present invention, an embodiment of a method for reading data from a memory is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0075] Figure 1 FIG. 1 is a schematic diagram of hardware connection relationship of a method for reading data from a memory according to an embodiment of the present invention. Figure 1 As shown, the BMC includes: a memory, a first controller, a reset circuit, a second controller, a register, and a processor.

[0076] The first controller is connected to the processor, the reset circuit, the second controller and the memory respectively, and the second controller is connected to the register.

[0077] Optionally, the first controller and the second controller may be connected to the processor via an AHB bus (Advanced High-performance Bus). The first controller may be connected to the memory via a memory bus. The first controller may be connected to the reset circuit and the second controller via a read-write control line, an address bus, and a data bus.

[0078] The second controller may be connected to the register via a bus of the register.

[0079] Optionally, the first controller may be an OTP ROM controller, the second controller may be a register controller, the memory may be an OTP ROM, and the register may be a data register.

[0080] In this embodiment, a method for reading data from a memory is provided. The method can be used for a first controller. Figure 2 FIG. 1 is one of the flow charts of the method for reading data from a memory according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0081] Step S201: During a system reset process, a first address set is obtained from a reset circuit.

[0082] The first address set includes multiple first addresses in the memory, and the first address set is dynamically generated by the system according to preset conditions or configurations. The first data can be common data or important data. After determining the multiple first data that need to be synchronized, it can be retrieved from the memory. Retrieving multiple first data requires knowing the multiple addresses storing the multiple first data, that is, the first address set.

[0083] A method for dynamically generating a first address set is: during the working process before the system is reset, the number of times each data is read by the processor is obtained, and based on preset conditions or configurations, multiple first data whose number of read times is greater than a preset value are determined, and the multiple addresses corresponding to the multiple first data in the memory are used as the first address set.

[0084] Step S202: read a plurality of first data corresponding to a plurality of first addresses of a first address set from a memory.

[0085] Wherein, one first address corresponds to one first data.

[0086] The memory is composed of a plurality of storage units, each storage unit is used to store a first data and corresponds to a first address, so the corresponding storage unit can be found by reading the first address, and the corresponding first data can be read from the storage unit.

[0087] Step S203: sending the plurality of first data to the register via the second controller.

[0088] Specifically, the first controller sends the multiple first data to the second controller via the data bus between the first controller and the second controller. After receiving the multiple first data, the second controller writes the multiple first data into corresponding addresses in the register via the bus of the register.

[0089] The present embodiment provides a method for reading data from a memory, which obtains a first address set from a reset circuit through a first controller, reads multiple first data corresponding to multiple first addresses from the memory according to the first address set, and then sends the read multiple first data to a register through a second controller, thereby realizing transmission and storage of memory data in the register, so that a subsequent processor can directly read the first data of the memory from the register. Compared with reading from the memory, the present method reduces the delay of the processor in obtaining the first data and improves the reading rate.

[0090] In addition, based on the corresponding data in the first address set synchronous memory from the reset circuit, the storage resources of the register can be saved, thereby reducing the hardware volume and cost.

[0091] In an optional implementation, in order to further implement the processor's function of writing data to the memory, the first controller is connected to the processor. Figure 3 FIG. 2 is a second flow chart of a method for reading data from a memory according to an embodiment of the present invention. Figure 3 As shown, after step S203, the following further includes:

[0092] Step S204, receiving first programming information sent by the processor.

[0093] The first programming information may be sent by the processor to the first controller through the AHB bus, and is used to write the first programming data into the memory.

[0094] The first programming information includes: first programming data and a second address. The first programming data is generated by a logic operation between the second data obtained by the processor from the register and the first initial programming data. The first initial programming data is generated by the processor according to the first configuration instruction. The second data is the first data corresponding to the second address among multiple first data stored in the register.

[0095] The first configuration instruction may be generated according to business requirements or administrator instructions, and the first initial programming data is programming data that the business requirements or administrator want to write to the second address in the memory. The logic operation may specifically be, when the data bit state of the OTP ROM is 0 when it is not programmed, the second data and the first programming data are ORed; or, when the data bit state of the OTP ROM is 1 when it is not programmed, the second data and the first programming data are ANDed.

[0096] Step S205 , writing the first programming data into the memory according to the second address based on the first programming information.

[0097] The memory may be an OTP ROM, which includes a plurality of data bits, each of which stores data in binary form, that is, two states of 0 or 1.

[0098] A specific implementation method is: converting the first programming data into binary form to ensure that it is suitable for the address specified in the OTPROM. Determining the target address to be written, that is, the second address in the OTPROM. According to the binary form of the first programming data, changing the data bit state of the second address in the OTPROM: for each bit, if the corresponding bit of the first programming data is 1, then set the bit to 1; if it is 0, then set the bit to 0.

[0099] The method provided in this embodiment receives first programming information with a second address and first programming data sent by a processor after synchronizing multiple first data to a register, wherein the first programming data is generated by the processor first obtaining the second data from the register, performing a logical operation with the first initial programming data generated based on the first configuration instruction, and then writing the first programming data to the second address of the memory. Therefore, before the processor writes the first programming data to the memory, it can first verify the data in the register through a logical operation, and then write the first programming data to the memory after ensuring the data consistency, thereby ensuring the security of data writing.

[0100] In this implementation, after step S205, the following steps are further included:

[0101] Get the working status of the storage in real time.

[0102] The working state can be an idle state or a busy state, corresponding to the completion of the write operation and the execution of the write operation. In order to avoid writing data when the memory working state is busy, it is necessary to obtain the working state of the memory in real time. Specifically, it can be monitored according to the specific timing of the write operation of the memory.

[0103] Based on the working status, it is determined whether the memory can perform a write operation.

[0104] The write operation is the process of storing data in the memory.

[0105] Taking the method of obtaining the working status as an example, during the writing process, the controller can track the changes of the data line and the control line to confirm whether the writing operation can be performed.

[0106] If so, a first status signal is generated.

[0107] The first state signal is used to indicate that the memory is in an idle state. Specifically, a state bit may be set in the encoding register of the first controller, and when the state bit is set to 0, the first state signal is generated.

[0108] When a first detection instruction sent by the processor is received, a first state signal is sent to the processor.

[0109] Specifically, the first detection instruction may be to directly read a status bit set in the encoding register, and a logic signal of the status bit may be directly sent to the processor through the AHB bus.

[0110] Receive second programming information sent by the processor, the second programming information includes: second programming data and a third address, the second programming information is sent by the processor when the first state signal is received, the second programming data is generated by the processor after a logical operation of the third data obtained from the register and the second initial programming data, the second initial programming data is generated by the processor according to the second configuration instruction, and the third data is the first data corresponding to the third address among multiple first data stored in the register.

[0111] The second configuration instruction may be generated according to business requirements or administrator instructions, and the second initial programming data is programming data to be written to the third address in the memory according to business requirements or administrators. The logic operation may specifically be, when the data bit state of the OTP ROM is 0 when it is not programmed, the second data and the first programming data are ORed; or, when the data bit state of the OTP ROM is 1 when it is not programmed, the third data and the second programming data are ANDed.

[0112] According to the second programming information, the second programming data is written into the memory according to the third address.

[0113] Taking the writing of the second programming data into the OTP ROM as an example, the data bit state of the third address of the OTP ROM may be directly changed. The first state signal is updated to the second state signal to indicate that the memory cannot perform the write operation. The update method may be to pull up the level of the state bit set in the encoding register, that is, change from 0 to 1.

[0114] The method provided in this embodiment determines whether the memory can perform a write operation by acquiring the working state of the memory in real time, and if so, generates a first state signal. Then, after receiving the first detection instruction sent by the processor, the first state signal is sent to the processor. The processor obtains the third data from the register, generates the second programming data after performing a logical operation with the second initial programming data generated based on the second configuration instruction, and then sends it to the first controller together with the third address. The first controller writes the second programming data to the third address of the memory, and updates the first state signal to the second state signal, indicating that the memory cannot perform a write operation. Therefore, before the processor writes the second programming data to the memory, it can be verified with the data in the register through a logical operation, and the second programming data can be written to the memory after ensuring the consistency of the data, thereby ensuring the security of data writing. At the same time, by first determining the working state of the memory and then receiving the second programming data, it is avoided that the memory receives a second write operation while writing one piece of data, thereby ensuring the orderliness of the memory data writing process and the security of the memory data.

[0115] In another implementation manner of this embodiment, after determining that the memory cannot perform the write operation, the method further includes:

[0116] Generate a second state signal. Specifically, one generation method includes: raising the level of a state bit set in the encoding register to indicate that the current memory is busy and cannot perform a write operation, thereby generating the second state signal.

[0117] When the second detection instruction sent by the processor is received, the second state signal is sent to the processor.

[0118] The second detection instruction may be sent when the processor needs to write other programming data into the memory, and is used to obtain the first state signal or the second state signal, and may be sent via the AHB bus.

[0119] Or, after the first state signal is updated to the second state signal, a third detection instruction sent by the processor is received.

[0120] The third instruction may have the same content, generation method, and sending method as the second instruction.

[0121] In response to the third detection instruction, a second state signal is sent to the processor.

[0122] The method provided in this embodiment generates a second state signal when it is determined that the working state of the memory cannot perform a write operation. Then, when receiving a second detection instruction sent by the processor, the second state signal is sent to the processor, or after the first state signal is updated to the second state signal, in response to a third detection instruction sent by the processor, the second state signal is sent to the processor, instructing the processor to stop sending other programming information and wait for the memory to complete the write operation corresponding to the current programming data, thereby ensuring the orderliness of the memory data write process and the security of the memory data.

[0123] Optionally, the first data may be OTP data, and the first controller may be an OTP controller. Specifically, Figure 4 is a schematic diagram of a flow chart of data synchronization from an OTP controller to a register according to an embodiment of the present invention. Figure 4 As shown, including:

[0124] Step S401, system power-on initialization reset or system reset.

[0125] Specifically, a reset signal may be generated to the OTP ROM controller (ie, the first controller) when the system is powered on and initialized or when the system is reset.

[0126] Step S402, reading a preset OTP ROM address to be read.

[0127] That is, the first address set is obtained from the reset circuit.

[0128] Step S403, waiting for the OTP ROM to return data.

[0129] That is, multiple first data are returned.

[0130] Step S404, writing the data into the register of the corresponding address.

[0131] That is, in step S203, a plurality of first data are sent to the register via the second controller.

[0132] Step S405, determine whether all OTP ROM data has been written into the register. If yes, execute step S406. If not, return to execute step S402.

[0133] Wherein, all OTP ROM data is all first data. The judging method may be that the second controller judges whether the register has completed the corresponding write operation.

[0134] Step S406, setting the OTP ROM preparation end signal.

[0135] The OTP ROM preparation completion signal is the first status signal.

[0136] In another embodiment, the present invention further provides a method for reading data from a memory, the method being applied to a second controller, the second controller being connected to a register, Figure 5 FIG. 3 is a flowchart of a method for reading data from a memory according to an embodiment of the present invention. Figure 5 As shown, the method includes:

[0137] During the system reset process, in step S501, a plurality of first data are received from a first controller.

[0138] The plurality of first data are read from the memory by the first controller, corresponding to the plurality of first addresses of the first address set, wherein one first address corresponds to one first data.

[0139] The first address set includes a plurality of first addresses in the memory, and the first address set is dynamically generated by the system according to preset conditions or configurations. The first data may be common data or important data. After determining the plurality of first data to be synchronized, the data may be retrieved from the memory.

[0140] Step S502: determining a plurality of fourth addresses corresponding to each first data in the register according to a preset corresponding relationship.

[0141] Storing a plurality of first data in a register requires knowing the addresses where the plurality of first data are stored, that is, a preset corresponding relationship. The preset corresponding relationship may be pre-stored in the reset circuit.

[0142] The preset corresponding relationship is a corresponding relationship between at least one first data and a fourth address in the register.

[0143] Step S503: storing the plurality of first data in a register according to the determined at least one fourth address.

[0144] Specifically, the write operations corresponding to the multiple first data may be input into the register through the bus of the register.

[0145] The server data processing method provided by the present invention has the following advantages:

[0146] First, multiple first data corresponding to multiple first addresses of a first address set are received from a memory by a first controller. Then, according to a preset correspondence relationship set, the multiple first data are stored in multiple addresses in a register, so that the memory data can be transmitted and stored in the register, so that the subsequent processor can directly read the first data of the memory from the register. Compared with reading from the memory, this method reduces the delay of the processor in obtaining the first data and improves the reading rate.

[0147] In addition, based on the corresponding data in the first address set synchronous memory from the reset circuit, the storage resources of the register can be saved, thereby reducing the hardware volume and cost.

[0148] In an optional implementation, in order to further consider that the processor obtains the first data of the memory from the register, Figure 6 FIG. 4 is a flowchart of a method for reading data from a memory according to an embodiment of the present invention. Figure 6 As shown, after step S503, the method further includes:

[0149] Step S504: receiving a first read instruction sent by a processor.

[0150] The first read instruction includes a target fourth address of the register. The first read instruction may be sent to the second controller via the AHB bus.

[0151] Step S505 , reading corresponding first data in the register according to the target fourth address as target first data.

[0152] The target first data is first data corresponding to the fourth address among the plurality of first data stored in the register.

[0153] Step S506: Send the target first data to the processor.

[0154] The target first data may be transmitted to the processor via a data bus number in the AHB bus.

[0155] The method provided in this embodiment reads the first data from the register based on the fourth address in the first read instruction after receiving the first read instruction sent by the processor, and then feeds back the found fourth data to the processor, thereby realizing the technical effect that the processor directly reads the first data of the memory from the register, and reduces the delay of the processor in obtaining the first data.

[0156] In an optional implementation, in order to further implement the data synchronization function in the register when the processor writes data to the memory, after step S506, it also includes:

[0157] A second read instruction sent by the processor is received, where the second read instruction includes the fifth address of the register.

[0158] Before the processor writes data into the memory, it needs to check the third initial programming data with the corresponding data in the register to ensure the consistency of the data in the register and the memory, so it needs to read the corresponding data in the register based on the fifth address.

[0159] According to the fifth address, fourth data is read from the register.

[0160] The fourth data is one of the plurality of first data.

[0161] The fourth data is sent to the processor.

[0162] The fourth data may be transmitted to the processor via a data bus number in the AHB bus.

[0163] The third programming data sent by the processor is received, where the third programming data is obtained by performing a logic operation on the third initial programming data and the fourth data, and the third initial programming data is generated by the processor according to the third configuration instruction.

[0164] The third configuration instruction may be generated according to business requirements or administrator instructions, and the third initial programming data is programming data to be written to the fifth address in the memory according to business requirements or administrator instructions. The logic operation may specifically be, when the data bit state is 0 when the OTP ROM is not programmed, the fourth data and the third programming data are ORed; or, when the data bit state is 1 when the OTP ROM is not programmed, the fourth data and the third programming data are ANDed.

[0165] In the register, the fourth data is updated to the third programming data.

[0166] The updating method may be to directly change the data bit state of the fifth address.

[0167] Specifically, in the steps of the method, the fourth data corresponding to the fifth address in the second read instruction is read from the register according to the second read instruction sent by the processor. Then the fourth data is fed back to the processor. The processor can perform a logical operation on the fourth data according to the third initial programming data, and use the obtained third programming data to update the fourth data. Therefore, before the processor writes the third programming data to the memory, it can first verify with the data in the register through a logical operation, and then write the third programming data to the register and the memory after ensuring that the data is consistent, thereby ensuring the consistency and security of data writing.

[0168] In an optional implementation, after the fifth data is updated to the third programming data, the method further includes:

[0169] Monitor the working status of registers and memories in real time to ensure data consistency between the two.

[0170] During the monitoring process, if an abnormal register state or inconsistent data is detected, an error status signal is generated to indicate a system abnormality.

[0171] Receive an error handling instruction sent by the processor, and perform corresponding error recovery operations according to the instruction, including but not limited to resetting register content, reloading data, or rolling back to a previous stable state.

[0172] After error recovery is completed, the recovered status information is sent to the processor for further decision making and processing.

[0173] At the same time, relevant operation logs are recorded to facilitate subsequent fault analysis and system optimization.

[0174] In another embodiment, the present invention further provides a memory data reading device, the device is applied to a first controller, the first controller is connected to the reset circuit, the second controller and the memory respectively, Figure 7 FIG. 1 is a schematic diagram of a data reading device of a memory according to an embodiment of the present invention. Figure 7 As shown, the device comprises:

[0175] The first acquisition module 701 is used to acquire a first address set from a reset circuit during a system reset process. The first address set includes a plurality of first addresses in a memory. The first address set is dynamically generated by the system according to a preset condition or configuration.

[0176] The first reading module 702 is used to read a plurality of first data corresponding to a plurality of first addresses of a first address set from a memory, wherein one first address corresponds to one first data.

[0177] The first sending module 703 is used to send a plurality of first data to the register through the second controller.

[0178] In an optional embodiment, the first controller is connected to the processor; the device further comprises:

[0179] The first receiving module is used to receive first programming information sent by the processor.

[0180] The first programming information includes: first programming data and a second address. The first programming data is generated by a logic operation between the second data obtained by the processor from the register and the first initial programming data. The first initial programming data is generated by the processor according to the first configuration instruction. The second data is the first data corresponding to the second address among multiple first data stored in the register.

[0181] The first writing module is used to write the first programming data into the memory according to the second address based on the first programming information.

[0182] In an optional embodiment, the device further comprises:

[0183] The second acquisition module is used to acquire the working status of the memory in real time.

[0184] The first determination module is used to determine whether the memory can perform a write operation according to the working state.

[0185] The first generating module is configured to generate a first state signal if yes.

[0186] The second sending module is used to send a first state signal to the processor when receiving a first detection instruction sent by the processor.

[0187] The second receiving module is used to receive second programming information sent by the processor.

[0188] The second programming information includes: second programming data and a third address. The second programming information is sent by the processor when the first state signal is received. The second programming data is generated by the processor after a logical operation of the third data obtained from the register and the second initial programming data. The second initial programming data is generated by the processor according to the second configuration instruction. The third data is the first data corresponding to the third address among multiple first data stored in the register.

[0189] The second writing module is used to write the second programming data into the memory according to the third address based on the second programming information.

[0190] The first updating module is used to update the first state signal to a second state signal, which is used to indicate that the memory cannot perform a write operation.

[0191] In an optional embodiment, the device further comprises:

[0192] The second generating module is used to generate a second state signal.

[0193] The third sending module is used to send a second state signal to the processor when receiving a second detection instruction sent by the processor.

[0194] Or, a third receiving module is used to receive a third detection instruction sent by the processor after the first state signal is updated to the second state signal.

[0195] The fourth sending module is used to respond to the third detection instruction and send the second state signal to the processor.

[0196] The data reading device of a memory provided by the present invention has the following advantages:

[0197] First, a first address set from a reset circuit is obtained through a first controller, and multiple first data corresponding to multiple first addresses are read from a memory according to the first address set, and then the multiple first data read are sent to a register through a second controller, so that the memory data can be transmitted and stored in the register, so that a subsequent processor can directly read the first data of the memory from the register. Compared with reading from the memory, this method reduces the delay of the processor in obtaining the first data and improves the reading rate. In addition, based on the corresponding data in the synchronization memory of the first address set from the reset circuit, the storage resources of the register can be saved, thereby reducing the hardware volume and cost.

[0198] In another embodiment, the present invention further provides a data reading device for a memory, the device being applied to a second controller. Figure 8 FIG. 2 is a second structural diagram of a data reading device of a memory according to an embodiment of the present invention. Figure 8 As shown, the device comprises:

[0199] The fourth receiving module 801 is used to receive a plurality of first data from the first controller during the system reset process. The plurality of first data are read from the memory by the first controller and correspond to a plurality of first addresses of the first address set, wherein one first address corresponds to one first data.

[0200] The second determining module 802 is used to determine the fourth address corresponding to each first data in the register according to a preset corresponding relationship, where the preset corresponding relationship is a corresponding relationship between at least one first data and the fourth addresses in multiple registers.

[0201] The storage module 803 is used to store the plurality of first data in the register according to the determined at least one fourth address.

[0202] In an optional embodiment, the device further comprises:

[0203] The fifth receiving module is used to receive a first read instruction sent by the processor.

[0204] The first read instruction includes a target fourth address of the register.

[0205] The second reading module is used to read the corresponding first data in the register according to the target fourth address as the target first data.

[0206] The fourth data is first data corresponding to the fourth address among the plurality of first data stored in the register.

[0207] The fifth sending module is used to send the target first data to the processor.

[0208] In an optional embodiment, the device further comprises:

[0209] The sixth receiving module is used to receive a second read instruction sent by the processor, where the second read instruction includes a fifth address of the register.

[0210] The third reading module is used to read fourth data from the register according to the fifth address.

[0211] The sixth sending module is used to send the fourth data to the processor.

[0212] The seventh receiving module is used to receive the third programming data sent by the processor.

[0213] The third programming data is obtained by performing a logic operation on the third initial programming data and the fourth data, and the third initial programming data is generated by the processor according to the third configuration instruction.

[0214] The second updating module is used to update the fourth data to the third programming data in the register.

[0215] The server data processing device provided by the present invention has the following advantages:

[0216] First, multiple first data corresponding to multiple first addresses of a first address set are received from a memory by a first controller. Then, according to a preset correspondence relationship set, the multiple first data are stored in multiple addresses in a register, so that the memory data can be transmitted and stored in the register, so that the subsequent processor can directly read the first data of the memory from the register. Compared with reading from the memory, this method reduces the delay of the processor in obtaining the first data and improves the reading rate.

[0217] In addition, based on the corresponding data in the first address set synchronous memory from the reset circuit, the storage resources of the register can be saved, thereby reducing the hardware volume and cost.

[0218] The further functional description of each module and unit is the same as that of the corresponding embodiment and will not be repeated here.

[0219] The data reading device of the memory in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide functions.

[0220] The embodiment of the present invention also provides a computer device having Figure 7 Or the data reading device of the memory shown in 8.

[0221] See also Fig. 9 , Fig. 9 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Fig. 9 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig. 9 A processor 10 is taken as an example.

[0222] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include an integrated circuit. The integrated circuit may be an application specific integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0223] The memory 20 stores instructions executable by at least one processor 10 so as to enable at least one processor 10 to implement the method shown in the embodiment.

[0224] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function. The data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0225] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of types of memories.

[0226] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0227] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium and downloaded through a network, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk, or a solid-state hard disk, etc.; further, the storage medium can also include a combination of types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the embodiment is implemented.

[0228] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for reading data from a memory, characterized in that: The method is applied to a first controller, the first controller is connected to a reset circuit, a second controller and a memory respectively, and the method includes: During a system reset process, obtaining a first address set from the reset circuit, the first address set including a plurality of first addresses in the memory, the first address set being dynamically generated by the system according to a preset condition or configuration; Reading, from the memory, a plurality of first data corresponding to a plurality of first addresses of the first address set, wherein one first address corresponds to one first data; The plurality of first data are sent to a register through the second controller.

2. The method according to claim 1, characterized in that The first controller is connected to the processor; After sending the plurality of first data to the register through the second controller, the method further includes: Receive first programming information sent by the processor, the first programming information including: first programming data and a second address, the first programming data is generated by performing a logic operation on second data obtained by the processor from the register and first initial programming data, the first initial programming data is generated by the processor according to a first configuration instruction, and the second data is a first data corresponding to the second address among a plurality of first data stored in the register; According to the first programming information, the first programming data is written into the memory according to the second address.

3. The method according to claim 2, characterized in that After writing the first programming data into the memory, the method further comprises: Acquire the working status of the memory in real time; Determining whether the memory can perform a write operation according to the working state; If yes, generating a first status signal; When receiving the first detection instruction sent by the processor, sending the first state signal to the processor; receiving second programming information sent by the processor, the second programming information comprising: second programming data and a third address, the second programming information is sent by the processor when the first state signal is received, the second programming data is generated by performing a logic operation between third data obtained by the processor from the register and second initial programming data, the second initial programming data is generated by the processor according to a second configuration instruction, and the third data is a first data corresponding to the third address among a plurality of first data stored in the register; writing the second programming data into the memory according to the third address according to the second programming information; The first state signal is updated to a second state signal to indicate that the memory cannot perform a write operation.

4. The method according to claim 3, characterized in that After determining that the memory cannot perform a write operation, the method further includes: generating the second state signal; When receiving the second detection instruction sent by the processor, sending the second state signal to the processor; or, after updating the first state signal to the second state signal, receiving a third detection instruction sent by the processor; In response to the third detection instruction, the second state signal is sent to the processor.

5. A method for reading data from a memory, characterized in that: The method is applied to a second controller, and the method comprises: During the system reset process, a plurality of first data are received from the first controller; the plurality of first data are read by the first controller from the memory and correspond to a plurality of first addresses of the first address set, wherein one first address corresponds to one first data; Determine, according to a preset corresponding relationship, a fourth address corresponding to each first data in the register, wherein the preset corresponding relationship is a corresponding relationship between at least one first data and the fourth address in the register; According to the determined at least one fourth address, a plurality of first data are stored in the register.

6. The method according to claim 5, characterized in that After storing the plurality of first data in the register, the method further comprises: receiving a first read instruction sent by a processor, wherein the first read instruction includes a target fourth address of the register; Reading the corresponding first data in the register according to the target fourth address as the target first data; The target first data is sent to the processor.

7. The method according to claim 6, characterized in that After sending the target first data to the processor, the method further includes: receiving a second read instruction sent by the processor, wherein the second read instruction includes a fifth address of the register; Reading fourth data from the register according to the fifth address; sending the fourth data to the processor; receiving third programming data sent by the processor, wherein the third programming data is obtained by performing a logic operation on third initial programming data and fourth data, and the third initial programming data is generated by the processor according to a third configuration instruction; In the register, the fourth data is updated to the third programming data.

8. A data reading device for a memory, characterized in that: The device is applied to a first controller, the first controller is connected to a reset circuit, a second controller and a memory respectively, and the device comprises: A first acquisition module, used for acquiring a first address set from the reset circuit during a system reset process, wherein the first address set includes a plurality of first addresses in the memory, and the first address set is dynamically generated by the system according to a preset condition or configuration; A first reading module, configured to read a plurality of first data corresponding to a plurality of first addresses of the first address set from the memory, wherein one first address corresponds to one first data; The first sending module is used to send the plurality of first data to the register through the second controller.

9. A data reading device for a memory, characterized in that: The device is applied to a second controller, and the device comprises: A fourth receiving module is used to receive a plurality of first data from the first controller during the system reset process; the plurality of first data are read by the first controller from the memory and correspond to a plurality of first addresses of the first address set, wherein one first address corresponds to one first data; A second determining module, configured to determine a fourth address corresponding to each first data in the register according to a preset corresponding relationship, wherein the preset corresponding relationship is a corresponding relationship between at least one first data and the fourth addresses in the plurality of registers; The storage module is used to store the plurality of first data in the register according to the determined at least one fourth address.

10. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the data reading method of the memory according to any one of claims 1 to 7 by executing the computer instructions.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the data reading method of the memory according to any one of claims 1 to 7.

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