Abnormal recovery method and device and electronic equipment

Abstract

The embodiment of the invention provides an exception recovery method and device and electronic equipment, and is applied to a binary translation system, the binary translation system is used for translating a source program in a client into a target program in a host machine, and the method comprises the following steps: under the condition that an exception occurs, translating the target program into a target program in the host machine; determining a source instruction and a basic block corresponding to the target instruction which is triggered abnormally in the source program, and marking a target position corresponding to the source instruction in the source program; determining an offset value corresponding to the target register according to the target position and a register delay calculation algorithm; the target register comprises a register corresponding to each instruction within a register delay calculation algorithm correction range between the initial position and the target position of the basic block; and correcting the value of the target register according to the offset value. According to the embodiment of the invention, the problems of register value errors and the like caused by delay optimization of the register in the binary translation process can be solved under the special conditions of exceptions, self-modification codes and the like, and the exception recovery efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an abnormality recovery method, device and electronic equipment. Background Art

[0002] Register delay calculation is mainly proposed to solve the timing problem in hardware design and optimize the instruction execution performance. It also has important applications in binary translation, which can help optimize the instruction translation process and improve translation efficiency.

[0003] The optimization of register delay calculation type faces a problem: dynamic binary translation cannot always be fully executed when executing the translated basic block. In some special cases, the execution flow may be transferred to the exception handling function at an instruction in the middle of a basic block. These special cases include but are not limited to the generation of exceptions, the occurrence of self-modifying code, etc. In this case, the exception handler needs to restore the current scene, including the values ​​of each register. However, the principle of register delay calculation type optimization is to reduce or merge the calculation of some register values ​​in a basic block, and only ensure that the values ​​of all registers are consistent with expectations after a basic block is fully executed. Therefore, if an exception occurs when executing a certain instruction, a corresponding mechanism is needed to restore the value of the register to avoid errors in future program execution. Summary of the invention

[0004] The embodiments of the present invention provide an exception recovery method, device and electronic device, which can solve the problem that the optimization of the binary translation system in the prior art leads to register value errors under special circumstances such as the generation of exceptions and the occurrence of self-modifying codes.

[0005] In order to solve the above problem, an embodiment of the present invention discloses an exception recovery method, which is applied to a binary translation system, wherein the binary translation system is used to translate a source program in a client into a target program in a host machine, and the method comprises: In the event of an exception, determining a source instruction and a basic block corresponding to a target instruction triggering the exception in the source program, and marking a target position corresponding to the source instruction in the source program; Determine an offset value corresponding to a target register according to the target position and a register delay calculation algorithm; the target register includes registers corresponding to each instruction between the start position of the basic block and the target position and within a correction range of the register delay calculation algorithm; The value of the target register is modified according to the offset value.

[0006] On the other hand, an embodiment of the present invention discloses an abnormality recovery device, which is applied to a binary translation system, wherein the binary translation system is used to translate a source program in a client into a target program in a host, and the device includes: A determination unit is used to determine, in the event of an exception, a source instruction and a basic block corresponding to a target instruction triggering the exception in the source program, and mark a target position corresponding to the source instruction in the source program; determine an offset value corresponding to a target register according to the target position and a register delay calculation algorithm; the target register includes registers corresponding to each instruction between the start position of the basic block and the target position and within a correction range of the register delay calculation algorithm; The correction unit is used to correct the value of the target register according to the offset value.

[0007] On the other hand, an embodiment of the present invention further discloses an electronic device, which includes a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors to perform the aforementioned exception recovery method.

[0008] An embodiment of the present invention further discloses a readable storage medium. When instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned abnormality recovery method.

[0009] The embodiments of the present invention include the following advantages: In the process of executing exception recovery, in the case of an exception, the embodiment of the present invention can first determine the source instruction and basic block corresponding to the target instruction that triggers the exception in the source program, and mark the target position corresponding to the source instruction in the source program; then, the offset value corresponding to the target register can be determined according to the target position and the register delay calculation algorithm; the target register includes the registers corresponding to each instruction between the starting position of the basic block and the target position within the correction range of the register delay calculation algorithm; finally, the value of the target register can be corrected according to the offset value. Therefore, in special cases such as the occurrence of exceptions and self-modifying codes, problems such as register value errors caused by register delay optimization in the binary translation process can be solved, and the efficiency of exception recovery can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0011] Figure 1 This is a dynamic binary translator operation process of the present invention Figure 1 ; Figure 2 This is a schematic diagram of the process of dynamic binary translation of the present invention. Figure 2 ; Figure 3 is a flowchart of steps of an abnormal recovery method embodiment of the present invention; Figure 4 It is a flowchart of the execution of an instruction sequence under an abnormal situation of the present invention; Figure 5 It is a schematic diagram of a flow chart of the execution of an instruction sequence under normal circumstances of the present invention; Figure 6 It is a flow chart of optimizing and restoring register delay calculation in abnormal situation of the present invention; Figure 7 It is a structural block diagram of an abnormality recovery device of the present invention; Figure 8 The invention is a structural block diagram of an electronic device for abnormal recovery. DETAILED DESCRIPTION

[0012] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] There are many differences in the instructions that can be supported by hardware designs of different instruction set architectures (ISAs), which makes executable files compiled based on one ISA incompatible with other platforms.

[0014] Binary translation technology enables programs compiled based on one architecture to run on a hardware platform of another architecture, thus making executable files compatible across ISAs. Figure 1 As shown, Figure 1 The following is a schematic diagram of a dynamic binary translation process provided by an embodiment of the present application. Figure 1Dynamic binary translation uses the "translate while running" method to translate the instructions of the client (Guest) architecture into host (HOST) architecture instructions and run them at runtime. After the translator reads the binary file, it usually translates and executes it according to the granularity of the translation basic block (TB). Before executing a basic block, it first searches the code cache. If a translated basic block is found, the code block can be executed. If the basic block is not found in the code cache, the translation will be performed and the translated code will be placed in the code cache, and then the basic block will be executed. After executing a basic block, the code cache will be searched for the next basic block, and this cycle will be repeated until the program execution ends.

[0015] With the continuous improvement of microprocessor performance, the feasibility of running the source program of another CPU architecture under one central processing unit (CPU) architecture through binary translation is becoming stronger and stronger, which has led to more development of binary translation technology. However, this technology still has technical problems such as low translation efficiency and too many redundant operations. When translating from complex instruction set (CISC) to reduced instruction set (RISC), due to the powerful instructions of CISC architecture, one instruction can perform complex operations, such as memory access arithmetic operations and logical operations. However, RISC architecture tends to use simple fixed-length instructions, and each instruction usually only performs a simple operation. In order to realize complex functions, multiple instructions need to be combined and implemented under RISC architecture. Therefore, for binary translators translating from CISC architecture to RISC, the instructions of the original instruction set will be converted into more instructions. In order to solve the problem of low efficiency of binary translators, many optimization methods have been proposed from various angles, such as flag information delay generation, instruction elimination, register value delay calculation and other solutions, to reduce the generation of instructions as much as possible.

[0016] Binary translation technology enables programs compiled based on one architecture to run on a hardware platform of another architecture, realizing the function of making executable files compatible across ISAs. It is of great significance for migrating the software ecology of mature CPU architectures to new CPU architectures, promoting the construction of their software ecology, and promoting the development of new architectures. In binary translation, the HOST platform refers to the architecture hardware platform that actually runs the program, and the GUEST platform refers to the architecture platform simulated by the binary translator, such as running an x86 program on a LoongArch platform. In an embodiment of the present invention, the HOST platform is LoongArch and the GUEST platform is x86.

[0017] like Figure 2 As shown, Figure 2 The following is a schematic diagram of a dynamic binary translation process provided by an embodiment of the present application. Figure 2 , the dynamic binary translation process specifically includes steps 201 to 204: Step 201: The target program reads the client platform executable program.

[0018] In an embodiment of the present invention, during the dynamic binary translation process, the target program reads the client platform executable program.

[0019] Step 202: perform a basic block search in the code cache.

[0020] After the target program reads the client platform executable program, it performs a basic block lookup in the code cache.

[0021] Step 203: If there is a translated basic block, execute the code block through the translated basic block.

[0022] After searching the code cache for a basic block, if there is a translated basic block, the code block is executed through the translated basic block.

[0023] Step 204: If there is no translated basic block, perform basic block code translation, store the translated basic block in the code buffer, and execute the code block.

[0024] After searching the code cache for a basic block, if there is no translated basic block, the basic block code is translated, the translated basic block is stored in the code cache, and the code block is executed.

[0025] Optimizations of register delay calculation type all face a problem, because dynamic binary translation does not always execute the translated basic blocks completely. There are some special cases that will cause the execution flow to transfer a certain instruction in the middle of a basic block to the exception handling function. Special cases include but are not limited to the generation of exceptions, the occurrence of self-modification, etc. The exception handler needs to restore the scene at this time, including the values ​​of each register. However, since the principle of optimization of register delay calculation type is to reduce / merge the values ​​of certain registers calculated in a basic block, it only guarantees that the values ​​of all registers are consistent with expectations after a basic block is fully executed. Therefore, if an exception occurs when executing a certain instruction, a corresponding mechanism is needed to restore the value of the register to avoid future program execution errors.

[0026] The exception recovery method in the prior art includes retaining the difference information generated by instruction optimization during the instruction optimization process, and implementing instruction correction according to the recorded difference information when an exception occurs, so as to improve the correctness of the translated program operation. In the process of translating a basic block, the difference information generated between the optimized instruction sequence and the instruction sequence before optimization, as well as the position information corresponding to the difference information are recorded in a designated area of ​​the basic block, and the position information includes the entry address of the optimized instruction, etc.

[0027] However, the abnormality recovery method retains the difference information generated by instruction optimization for each TB during the instruction optimization process, but not every TB will have an abnormality, which wastes time and space.

[0028] In order to solve the problems of register value errors caused by optimization in the binary translation system in the prior art under special circumstances such as exceptions and self-modifying code, refer to Figure 3 , shows a flowchart of an abnormal recovery method embodiment of the present invention, which is applied to a binary translation system. The method may specifically include the following steps: Step 101 : When an exception occurs, determine the source instruction and basic block corresponding to the target instruction that triggers the exception in the source program, and mark the target position corresponding to the source instruction in the source program.

[0029] Step 102: Determine the offset value corresponding to the target register according to the target position and the register delay calculation algorithm; the target register includes the registers corresponding to each instruction between the start position of the basic block and the target position and within the correction range of the register delay calculation algorithm.

[0030] Step 103: Correct the value of the target register according to the offset value.

[0031] The abnormality recovery method provided by the embodiment of the present invention can be applied to a binary translation system, and the binary translation system is used to translate a source program in a client machine (Guest) into a target program in a host machine (Host).

[0032] It should be noted that the source program is binary code. During the translation process, the binary translation system can only obtain the compiled binary code (i.e., the source program), and after disassembling the binary code, obtain the assembly-level code; at this time, it is impossible to divide the code based on the functions in the source program as the basic unit. Normally, the binary translation system divides the obtained source program into basic blocks one by one, and the last instruction of each basic block is usually the jump instruction in the source program. The binary translation system works with basic blocks as the basic units.

[0033] The corresponding source instructions in the source program refer to the instructions before translation. The source instructions are the basic units in the source program, which can be an assignment statement, a function call, a conditional judgment, etc.

[0034] Source instructions are the basic building blocks for constructing source programs. By combining these instructions, developers can create programs with complex functions and strict logic.

[0035] It should be noted that the specific form and meaning of source instructions may vary in different programming languages ​​and programming paradigms. For example, in functional programming languages, source instructions may be more about function definitions and calls, while in object-oriented programming languages, they may be more about class and object operations.

[0036] The target program refers to the program generated by translating the source program in the client (Guest) and can be directly executed on the host (Host).

[0037] In the embodiment of the present invention, the abnormal situation may include the generation of an abnormality, the occurrence of self-modification, etc.

[0038] The technical problem to be solved by the present invention is that due to instruction optimization in a binary translation system, especially instruction optimization of register delay calculation, the optimization may cause register value errors and other problems in special circumstances such as the occurrence of exceptions and self-modifying codes.

[0039] To address the high instruction inflation problem when translating from complex instruction sets to reduced instruction sets, binary translators often use some instruction optimization algorithms to reduce the number of instructions after translation. For example, they perform delay calculation on a register within a basic block to reduce the number of code instructions generated after translation, thereby improving the operating efficiency of the binary translator. However, in some special cases, the value of the delayed calculation register cannot provide an accurate register value, resulting in program errors.

[0040] In the case of an exception, the control flow of the instruction will be transferred to the exception handling logic for execution, and after the exception handling is completed, it may not return to the original instruction sequence to continue execution. Therefore, the translator needs to accurately restore the register state at the time when the special situation occurs.

[0041] like Figure 4 As shown, Figure 4 A flowchart of an instruction sequence execution under abnormal circumstances provided by an embodiment of the present application is shown. As shown in the figure, the instructions are executed in sequence according to the instruction order.

[0042] like Figure 5 As shown, Figure 5 A schematic flow chart of the execution of an instruction sequence under normal circumstances provided by an embodiment of the present application is shown. As shown in the figure, in the process of sequentially executing the instruction sequence, when encountering an exception handling, the control flow at instruction c is transferred to the exception handling. After the exception handling is completed, the instruction d below instruction c is not continued to be executed, but jumps to instruction x for subsequent execution. If the basic block is optimized by the register delay calculation algorithm, the value of the register may not be calculated in real time when instruction c is executed. When the instruction x sequence is subsequently executed, an incorrect register state will be obtained, which will lead to a program execution error.

[0043] Due to register delay calculation optimization, the value of the register when an exception occurs may not be calculated in real time. If the current possibly erroneous register state is used directly, program execution errors may occur.

[0044] The target instruction that triggers the exception refers to the host instruction that triggers the exception in the target program. It is understandable that, in the event of an exception, the basic block corresponding to the target instruction can be determined by obtaining the instruction address of the target instruction that triggers the exception.

[0045] Exemplarily, the binary translation system may capture the exception processing and determine the address that needs to be modified for the instruction that triggers the exception through a signal processing function corresponding to a segmentation fault signal (Segmentation Violation Signal, SIGSEGV).

[0046] It should be noted that the instruction address refers to the address of the CPU instruction that triggers the exception, which is usually stored in the CPU's program counter (PC). When a signal is sent to a user program, the instruction address itself is not directly passed through the data structure used to store detailed information about the signal in the Linux system. However, the user program can obtain the instruction address in other ways. For example, in the signal processing function, the current context information can be obtained through the structure used to save the context information of the user thread, such as the ucontext_t structure, which contains the value of the program counter (PC).

[0047] If a system call for handling signals, such as the sigaction system call, is used to register a signal handling function, and a flag is enabled to specify whether the signal handling function receives detailed information about the signal, such as the SA_SIGINFO flag in the sigaction system call, then the signal handling function receives a parameter containing context information from which the instruction address where the exception occurred can be extracted.

[0048] When the CPU detects an exception, the execution of the current program is suspended, and the operating system kernel saves the CPU context when the exception occurs, such as register status, program counter (PC), etc. Further, the kernel calls the corresponding exception handler according to the exception type. The kernel usually returns the instruction address where the exception occurs (that is, the value of the program counter PC) to the user program so that the user program can debug or process it.

[0049] When an exception occurs, the corresponding TB basic block can be found according to the target instruction address that triggered the exception. Specifically, the operating system kernel first returns the target instruction address that triggered the exception, which is the virtual address of the guest, and then converts the guest virtual address to the host virtual address, which is usually completed by the memory management module in the binary translation system. The binary translation system maintains a TB cache to store the translated TB basic blocks. Through the host virtual address, the corresponding TB basic block can be found in the TB cache.

[0050] For example, suppose a guest program is running in a binary translation system. When the guest program executes an illegal instruction, the CPU triggers an exception. At this time, the operating system kernel saves the context and returns the address of the exception instruction (such as 0x4000). The binary translation system converts the virtual address 0x4000 of the guest to the virtual address of the host; the TB basic block containing 0x4000 is searched in the TB cache. Assume that the starting address of the TB basic block found is 0x3FF0 and the ending address is 0x4010. The instructions in the TB basic block are analyzed, and the illegal instructions are found and repaired. In this way, exceptions can be efficiently handled in a virtualized environment and the correct execution of the guest program can be ensured.

[0051] In an embodiment of the present invention, based on a register delay calculation algorithm, the offset values ​​of each instruction between the first instruction in the basic block corresponding to the target instruction that triggers the exception and the target position can be calculated, and the offset values ​​corresponding to each instruction between the first instruction of the basic block and the target position can be accumulated to obtain the target offset value corresponding to the target register.

[0052] Finally, the target offset value is used to modify the value of the target register corresponding to the target instruction that triggered the exception. For example, the register value and the target offset value are added to obtain the value of the target register, such as: the optimization of the sp register, here is sp=sp+register optimization operation in set A.

[0053] In an embodiment of the present invention, the process of determining the offset value of each instruction in the basic block according to the register delay calculation algorithm can be described by Table 1, as shown in Table 1: Table 1

[0054] As shown in Table 1, taking the source program including x86 instructions and the target program including RISC-V instructions as an example, the table contains the instruction sequence in x86: poprbx; poprbp; popr12; ret; This instruction sequence usually appears at the end of the function and is used to restore the previously saved register values ​​before the function returns. First, the value of the rbx register is restored from the stack. Then, the value of the rbp register is restored from the stack, which usually means that the stack frame of the current function will be destroyed because rbp is the stack frame pointer. Next, the value of the r12 register is restored from the stack. Finally, the ret instruction is executed to pop the return address from the stack and jump to it, thereby returning to the caller.

[0055] The above x86 instruction sequence is translated into the RISC-V instruction sequence as follows: lw x10, 0 (x2) is used to indicate loading data from the top of the stack into register x10 (corresponding to rbx); addi x2, x2, 4 is used to indicate moving the stack pointer up by 4 bytes; lwx8, 0 (x2) is used to indicate loading data from the top of the stack into register x8 (corresponding to rbp); addi x2, x2, 4 is used to indicate moving the stack pointer up by 4 bytes; lw x12, 0 (x2) is used to indicate loading data from the top of the stack into register x12 (corresponding to r12); addi x2, x2, 4 is used to indicate moving the stack pointer up by 4 bytes; jr x1 is used to indicate returning to the address in the link register.

[0056] The instruction sequence after register delay calculation optimization is: lw x10, 0 (x2) is used to indicate loading data from the top of the stack to register x10; lw x8, 4 (x2) is used to indicate loading data from the top of the stack to register x8; lw x12, 8 (x2) is used to indicate loading data from the top of the stack to register x12; addi x2, x2, 12 is used to indicate moving the stack pointer up 12 bytes; jr x1 is used to indicate returning to the address in the link register.

[0057] For example, according to the register delay calculation algorithm, it can be determined that the offset value of the stack pointer sp of the three pop instructions is 4, that is, when reaching the ret instruction, the offset value of the stack pointer sp is 12, and the semantics of the ret instruction itself requires the stack pointer to be shifted, that is, sp+4, so the stack pointer sp+16 needs to be shifted in the ret instruction.

[0058] In the embodiment of the present invention, during the process of executing exception recovery, in the case of an exception, the source instruction and basic block corresponding to the target instruction that triggers the exception in the source program can be determined first, and the target position corresponding to the source instruction in the source program can be marked; then, the offset value corresponding to the target register can be determined according to the target position and the register delay calculation algorithm; the target register includes the registers corresponding to each instruction between the starting position of the basic block and the target position within the correction range of the register delay calculation algorithm; finally, the value of the target register can be corrected according to the offset value. Thus, in special cases such as the occurrence of exceptions and self-modifying codes, problems such as register value errors caused by register delay optimization in the binary translation process can be solved, and the efficiency of exception recovery can be improved.

[0059] Further, in the embodiment of the present invention, when determining the offset value corresponding to the target register according to the target position and the register delay calculation algorithm, the abnormality recovery method further includes steps 1021 to 1022: Step 1021: Determine the offset values ​​corresponding to the instructions between the first instruction of the basic block corresponding to the source instruction and the target position according to the target position and the register delay calculation algorithm.

[0060] Step 1022: Accumulate the offset values ​​corresponding to each instruction between the starting position of the basic block and the first source instruction to obtain the offset value of the first register corresponding to the first source instruction; the first source instruction is any instruction between the starting position of the basic block and the target position.

[0061] The basic block corresponding to the source instruction refers to the basic block to which the target instruction that triggers the exception belongs, which can be determined by the address of the target instruction that triggers the exception. For example, the corresponding TB basic block can be determined according to the address of the host instruction.

[0062] Exemplarily, starting from the first instruction (starting position) of the basic block and ending at the Nth instruction, each Guest instruction is scanned one by one, that is, all instructions between the first instruction of the basic block and the target position are traversed.

[0063] The offset value corresponding to each instruction can be determined by a register delay calculation algorithm.

[0064] The accumulation process refers to accumulating the offset values ​​corresponding to each instruction between the starting position of the basic block and the first source instruction.

[0065] Exemplarily, assuming that the offset value corresponding to the starting position of the basic block is A, the offset value corresponding to the second is B, ..., and the offset value corresponding to the first source instruction is X, then the offset values ​​corresponding to the instructions between the first instruction of the basic block and the first source instruction are added up, and the target offset value corresponding to the target register can be obtained as A+B+...+X.

[0066] The offset value of the first register corresponding to the first source instruction may be obtained by accumulating the offset values ​​corresponding to each instruction between the start position of the basic block and the first source instruction.

[0067] In an embodiment of the present invention, in the process of determining the target offset value, the binary translation system can first determine the basic block corresponding to the target instruction that triggers the exception, and then analyze and process each instruction between the first instruction of the basic block and the target position one by one through a register delay calculation algorithm to obtain the offset value corresponding to each instruction between the first instruction of the basic block and the target position; then accumulate the offset values ​​corresponding to each instruction, and then determine the target offset value corresponding to the target register.

[0068] Further, in the embodiment of the present invention, when determining the offset values ​​corresponding to the instructions between the first instruction of the basic block corresponding to the source instruction and the target position according to the target position and the register delay calculation algorithm, the exception recovery method further includes steps 10211 to 10212: Step 10211, determine whether there is a repair mark at the target position of the basic block; the repair mark is used to indicate that the register delay calculation algorithm has triggered the repair processing of the registers corresponding to each instruction between the first instruction of the basic block and the target position.

[0069] Step 10212: When there is no repair mark between the first instruction of the basic block and the target position, determine the offset value corresponding to each instruction between the first instruction of the basic block and the target position according to the register delay calculation algorithm.

[0070] The position of the current instruction contains a correction identifier for restoring a register delay calculation value, which means that the register delay calculation algorithm can restore the value of a register at any instruction in the middle of TB. For example, when there is a repair identifier in the current instruction, the register delay calculation value corresponding to the instruction can be restored based on the repair identifier.

[0071] In an embodiment of the present invention, in the process of determining the offset values ​​corresponding to each instruction between the first instruction of the basic block corresponding to the source instruction and the target position according to the target position and the register delay calculation algorithm, since the register delay calculation algorithm itself may also restore the value of a certain register at a certain instruction in the middle of the basic block, therefore, in the process of analyzing and processing each instruction between the first instruction of the basic block and the target position one by one, the binary translation system can also determine whether there is a repair mark at the target position of the basic block; in the case that there is no repair mark between the first instruction of the basic block and the target position, the binary translation system can determine the offset values ​​corresponding to each instruction between the first instruction of the basic block corresponding to the source instruction and the target position according to the register delay calculation algorithm.

[0072] Furthermore, the abnormality recovery method provided by the embodiment of the present invention may also include the following steps: Step 10213: When a repair mark exists between the first instruction of the basic block and the target position, the offset values ​​corresponding to the registers corresponding to the instructions between the first instruction of the basic block and the target position are cleared, and the next instruction of the target instruction is analyzed.

[0073] Exemplarily, when there is a repair marker between the first instruction of the basic block and the target position, the offset values ​​corresponding to the instructions stored in set A from the first instruction of the basic block to the instruction with the repair marker are cleared.

[0074] In an embodiment of the present invention, in the process of determining the offset values ​​corresponding to each instruction between the first instruction of the basic block corresponding to the source instruction and the target position according to the target position and the register delay calculation algorithm, since the register delay calculation algorithm itself may also restore the value of a certain register at a certain instruction in the middle of the basic block, in the process of analyzing and processing each instruction between the first instruction of the basic block and the target position one by one, the binary translation system can also determine whether there is a repair marker at the target position of the basic block; in the case where there is a repair marker between the first instruction of the basic block and the target position, the binary translation system can first clear the offset value corresponding to the repair marker position within the correction range of the register delay calculation algorithm; and then determine the offset values ​​corresponding to each instruction between the instruction with the repair marker and the target position according to the register delay calculation algorithm.

[0075] Further, in the embodiment of the present invention, when determining the offset values ​​corresponding to the instructions between the first instruction of the basic block corresponding to the source instruction and the target position according to the target position and the register delay calculation algorithm, the exception recovery method further includes steps 10214 to 10217: Step 10214: For the basic block corresponding to the target instruction that triggers the exception, determine the sequence number corresponding to each instruction in the basic block according to the arrangement order of the instructions in the basic block, and determine the target sequence number corresponding to the instruction in the target position.

[0076] Step 10215, determine whether the sequence number corresponding to the i-th instruction in the basic block is less than or equal to the target sequence number; the initial value of i is 1, and i is a positive integer.

[0077] Step 10216: When the sequence number corresponding to the ith instruction in the basic block is less than or equal to the target sequence number, determine the offset value corresponding to the ith instruction through the register delay calculation algorithm.

[0078] The arrangement order of instructions in a basic block refers to an instruction sequence, for example, the instruction sequence is inst a, inst b, inst c, ..., etc., which is not limited in the embodiments of the present invention.

[0079] Exemplarily, the sequence number corresponding to each instruction in the basic block refers to that the sequence number corresponding to inst a is 1, the sequence number corresponding to inst b is 2, the sequence number corresponding to inst c is 3, ..., which is not limited in the embodiments of the present invention.

[0080] The target serial number corresponding to the instruction in the target position refers to the target serial number corresponding to the target instruction that triggers the exception. For example, when the target instruction that triggers the exception is inst c, the target serial number corresponding to the target instruction that triggers the exception is 3, which is not limited in the embodiments of the present invention.

[0081] The sequence number corresponding to the ith instruction in the basic block refers to the sequence number determined by the arrangement order of the ith instruction in the basic block. For example, the sequence number corresponding to the ith instruction in the basic block may be 5 or 10.

[0082] The offset value corresponding to the i-th instruction can be determined through the register delay calculation algorithm.

[0083] Step 10217: When the sequence number corresponding to the i-th instruction in the basic block is greater than the target sequence number, it is determined that the offset values ​​corresponding to the target registers are all calculated.

[0084] In an embodiment of the present invention, in the process of determining the offset values ​​corresponding to each instruction between the first instruction of the basic block corresponding to the source instruction and the target position according to the target position and the register delay calculation algorithm, the binary translation system can first determine the sequence number corresponding to each instruction in the basic block, and determine the target sequence number corresponding to the instruction in the target position; and then determine the offset value corresponding to each instruction by comparing the sequence number corresponding to the i-th instruction in the basic block with the target sequence number; wherein, when the sequence number corresponding to the i-th instruction in the basic block is less than or equal to the target sequence number, the offset value corresponding to the i-th instruction can be determined by the register delay calculation algorithm; when the sequence number corresponding to the i-th instruction in the basic block is greater than the target sequence number, it is determined that the offset value corresponding to the target register is calculated.

[0085] Further, in the embodiment of the present invention, when the value of the target register is corrected according to the offset value, the abnormality recovery method further includes steps 1031 to 1033: Step 1031: Obtain register values ​​corresponding to each instruction between the start position and the target position of the basic block.

[0086] Step 1032: for a first register, add the register value and the offset value to obtain a corrected register value; the first register is any register in the target registers.

[0087] Step 1033: Replace the register value corresponding to the first register with the corrected register value.

[0088] Among them, in the process of correcting the value of the target register, the binary translation system can first obtain the register value corresponding to each instruction between the starting position of the basic block and the target position, and then for the first register, add the register value and the offset value to obtain the corrected register value; the first register is any register in the target register, and finally the register value corresponding to the first register is replaced by the corrected register value.

[0089] Exemplarily, for the first register, the process of adding the register value and the offset value to obtain the corrected register value refers to the process of adding the value of a register to the offset value stored in set A, for example: the optimization of the sp register, here is the register optimization operation of sp=sp+set A.

[0090] Exemplarily, replacing the register value corresponding to the first register with the modified register value refers to replacing the register value corresponding to the first register with sp+the register optimized value in the set A.

[0091] In an embodiment of the present invention, in the process of correcting the value of the target register according to the offset value, the binary translation system can add the register value and the offset value for the first register to obtain a corrected register value; and use the corrected register value to replace the register value corresponding to the first register.

[0092] Exemplarily, for the optimization of the sp register, the processing process of the binary translation system may be sp=sp+register optimization operations in set A.

[0093] Further, in the embodiment of the present invention, when an exception occurs, the source instruction and basic block corresponding to the target instruction triggering the exception in the source program are determined, and the target position corresponding to the source instruction in the source program is marked, and the exception recovery method further includes steps 1011 to 1013: Step 1011: When an exception occurs, determine the instruction address where the exception occurs.

[0094] Step 1012: Based on the instruction address, determine the basic block corresponding to the target instruction that triggers the exception.

[0095] Step 1013: Determine in the basic block the source instruction corresponding to the target instruction that triggers the exception in the source program based on the instruction address, and mark the target position corresponding to the source instruction in the source program.

[0096] Exemplarily, the target instruction address that triggers the exception may be the address of a host instruction.

[0097] The basic block corresponding to the target instruction that triggers the exception refers to the basic block to which the target instruction that triggers the exception belongs, which is determined according to the address of the host instruction.

[0098] Exemplarily, the source instruction corresponding to the target instruction that triggers the exception in the source program refers to the Guest instruction.

[0099] Exemplarily, marking the target position corresponding to the source instruction in the source program may be a process of marking the position sequence number to which the Guest instruction belongs.

[0100] In an embodiment of the present invention, in the event of an exception, in the process of determining the source instruction and basic block corresponding to the target instruction that triggers the exception in the source program, and marking the target position corresponding to the source instruction in the source program, the binary translation system can first determine the source instruction in the basic block that has the exception based on the address of the target instruction that triggers the exception, and finally mark the target position corresponding to the source instruction in the source program.

[0101] Another embodiment of the present invention, when an exception occurs, starts with the first instruction in TB and ends with the instruction where the exception occurs, and uses the algorithm of register delay calculation optimization to scan the instruction interval to obtain a delayed and uncalculated value of the register, and then corrects the register value at the time of the exception.

[0102] like Figure 6 As shown, Figure 6 A schematic diagram of a process for optimizing and restoring register delay calculation when an exception occurs provided by an embodiment of the present application is shown. As shown in the figure, when an exception occurs, the relevant TB is first obtained according to the instruction that triggers the exception, starting with the first instruction in the TB and ending with the instructions that cause the exception one by one, and processing the Guest instructions one by one, and finally obtaining the offset value of each register delay calculation at the time of the exception, and then correcting the register. The process of optimizing and restoring register delay calculation when an exception occurs specifically includes steps 301 to 308: Step 301: When exception handling occurs, determine the basic block corresponding to the target instruction that triggers the exception.

[0103] Get the exception TB based on the host instruction that triggered the exception.

[0104] When an exception occurs, the corresponding TB basic block is determined according to the address of the host instruction.

[0105] Step 302: Get the target instruction that triggers the exception, which is the instruction number in the basic block and mark it as N.

[0106] Get the guest instruction number in the TB of the host instruction that triggered the exception, and mark the number as N.

[0107] Step 303: Initialize the register delay calculation offset value set A to 0.

[0108] Initialize the register delay calculation offset value set to 0, assuming that the set is labeled A.

[0109] Step 304 : Start traversing from the first instruction in the basic block corresponding to the target instruction that triggers the exception.

[0110] Starting from the first instruction of the basic block and ending at the Nth instruction, scan each guest instruction one by one. The optimization algorithm itself may also restore the value of a register at an instruction in the middle of the TB.

[0111] Step 305: Determine whether the sequence number corresponding to the i-th instruction in the basic block is less than or equal to the sequence number of the instruction that triggers the exception.

[0112] If so, execute step 306 ; otherwise, execute step 307 .

[0113] Step 306: Call the optimization algorithm scanning instruction to obtain the corresponding offset values ​​of all register delay calculations.

[0114] Step 307: Restore the offset value corresponding to the target instruction that triggered the exception according to set A.

[0115] After scanning all instructions, the values ​​of all registers are restored according to the delay calculation offset values ​​corresponding to each register recorded in set A.

[0116] Step 308: Add the group of offset values ​​to set A.

[0117] It should be noted that the register delay calculation algorithm also includes: it can determine whether there is a repair mark in each instruction; the repair mark is used to indicate that the register delay calculation algorithm has triggered the repair processing of the registers corresponding to each instruction between the first instruction of the basic block and the target position, and the repair mark can be in any instruction between the first instruction of the basic block and the target position. If the repair mark exists, the value of the corresponding register in set A is cleared, and then the next instruction is scanned; otherwise, the register delay calculation offset value of the current instruction is calculated and accumulated into the corresponding register offset in set A.

[0118] The present invention aims at the problem that due to instruction optimization in a binary translation system, especially instruction optimization of register delay calculation, the optimization may cause register value errors in special cases such as exceptions and self-modifying codes. A scanning method is proposed. At the moment of the exception, the method starts with the first instruction in TB and ends with the instruction where the exception occurs. The algorithm of register delay calculation optimization itself is used to scan the instruction interval to obtain a value of a register that is delayed and not calculated, and then the register value at the moment of the exception is corrected.

[0119] The present invention provides a scanning algorithm for restoring the register scene when an exception occurs in a register delay calculation type optimization algorithm. The algorithm takes the basic block as the unit, and at the moment of the exception, starts with the first instruction in the TB and ends with the instruction where the exception occurs. The algorithm of the register delay calculation optimization itself is used to scan the instruction interval to obtain a value of a register that is delayed and not calculated, and then the register value at the moment of the exception is corrected.

[0120] In summary, the embodiment of the present invention provides an exception recovery method. In the process of executing exception recovery, in the case of an exception, the source instruction and basic block corresponding to the target instruction that triggers the exception in the source program can be determined first, and the target position corresponding to the source instruction in the source program can be marked; then, the offset value corresponding to the target register can be determined according to the target position and the register delay calculation algorithm; the target register includes the registers corresponding to each instruction between the starting position of the basic block and the target position within the correction range of the register delay calculation algorithm; finally, the value of the target register can be corrected according to the offset value. Therefore, in special cases such as the occurrence of exceptions and self-modifying codes, problems such as register value errors caused by register delay optimization in the binary translation process can be solved, and the efficiency of exception recovery can be improved.

[0121] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0122] Device Embodiment Reference Figure 7 , shows a structural block diagram of an abnormality recovery device of the present invention, which is applied to a binary translation system. The binary translation system is used to translate a source program in a client into a target program in a host. The abnormality recovery device 60 may specifically include: The determination unit 601 is used to determine the source instruction and basic block corresponding to the target instruction triggering the exception in the source program when an exception occurs, and mark the target position corresponding to the source instruction in the source program; determine the offset value corresponding to the target register according to the target position and the register delay calculation algorithm; the target register includes the registers corresponding to each instruction between the starting position of the basic block and the target position and within the correction range of the register delay calculation algorithm; The correction unit 602 is used to correct the value of the target register according to the offset value.

[0123] In an optional embodiment of the present invention, the determining unit is specifically configured to: Determine, according to the target position and the register delay calculation algorithm, the offset values ​​corresponding to the instructions between the first instruction of the basic block corresponding to the source instruction and the target position; The offset values ​​corresponding to the instructions between the starting position of the basic block and the first source instruction are accumulated to obtain the offset value of the first register corresponding to the first source instruction; the first source instruction is any instruction between the starting position of the basic block and the target position.

[0124] In an optional embodiment of the present invention, the determining unit is specifically configured to: Determine whether there is a repair mark at the target position of the basic block; the repair mark is used to indicate that the register delay calculation algorithm has triggered the repair processing of the registers corresponding to each instruction between the first instruction of the basic block and the target position; When there is no repair mark between the first instruction of the basic block and the target position, the offset value corresponding to each instruction between the first instruction of the basic block and the target position is determined according to the register delay calculation algorithm.

[0125] In an optional embodiment of the present invention, the determining unit is further configured to: In the case where the repair identifier exists between the first instruction of the basic block and the target position, the offset values ​​corresponding to the registers corresponding to the instructions between the first instruction of the basic block and the target position are cleared, and the next instruction of the target instruction is analyzed.

[0126] In an optional embodiment of the present invention, the determining unit is further configured to: For the basic block corresponding to the target instruction that triggers the exception, determine the sequence number corresponding to each instruction in the basic block according to the arrangement order of the instructions in the basic block, and determine the target sequence number corresponding to the instruction in the target position; Determine whether the sequence number corresponding to the i-th instruction in the basic block is less than or equal to the target sequence number; the initial value of i is 1, and i is a positive integer; When the sequence number corresponding to the i-th instruction in the basic block is less than or equal to the target sequence number, determining the offset value corresponding to the i-th instruction by using a register delay calculation algorithm; When the sequence number corresponding to the i-th instruction in the basic block is greater than the target sequence number, it is determined that the offset values ​​corresponding to the target registers are all calculated.

[0127] In an optional embodiment of the present invention, the correction unit is further used for: Get the register value corresponding to each instruction between the starting position and the target position of the basic block; For a first register, adding the register value and the offset value to obtain a corrected register value; the first register is any register in the target register; The register value corresponding to the first register is replaced by the modified register value.

[0128] In an optional embodiment of the present invention, the determining unit is further configured to: In the event of an exception, determining the instruction address where the exception occurred; Based on the instruction address, determining a basic block corresponding to the target instruction that triggers the exception; A source instruction corresponding to the target instruction triggering the exception in the source program is determined in the basic block based on the instruction address, and a target position corresponding to the source instruction in the source program is marked.

[0129] In summary, the embodiment of the present invention provides an exception recovery device, which can, in the process of executing exception recovery, first determine the source instruction and basic block corresponding to the target instruction that triggers the exception in the source program, and mark the target position corresponding to the source instruction in the source program; then determine the offset value corresponding to the target register according to the target position and the register delay calculation algorithm; the target register includes the registers corresponding to each instruction between the starting position of the basic block and the target position within the correction range of the register delay calculation algorithm; finally, the value of the target register can be corrected according to the offset value. Therefore, in special cases such as the occurrence of exceptions and self-modifying codes, problems such as register value errors caused by register delay optimization in the binary translation process can be solved, and the efficiency of exception recovery can be improved.

[0130] As for the abnormal recovery device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0131] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0132] An embodiment of the present invention provides an electronic device for exception recovery, the electronic device is applied to a binary translation system, the binary translation system is used to translate a source program in a client into a target program in a host, the electronic device includes a memory, and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors, wherein the one or more programs include instructions for performing the following operations: in the event of an exception, determining the source instruction and basic block corresponding to the target instruction triggering the exception in the source program, and marking the target position corresponding to the source instruction in the source program; determining the offset value corresponding to the target register according to the target position and a register delay calculation algorithm; the target register includes registers corresponding to each instruction between the starting position of the basic block and the target position and within the correction range of the register delay calculation algorithm; and correcting the value of the target register according to the offset value.

[0133] Figure 8 1 is a block diagram of an electronic device 300 for abnormal recovery according to an exemplary embodiment. For example, the electronic device 300 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0134] Reference Figure 8 , the electronic device 300 may include one or more of the following components: a processing component 302 , a memory 304 , a power component 306 , a multimedia component 308 , an audio component 310 , an input / output (I / O) interface 312 , a sensor component 314 , and a communication component 316 .

[0135] The processing component 302 generally controls the overall operation of the electronic device 300, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 302 may include one or more processors 320 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 302 may include one or more modules to facilitate the interaction between the processing component 302 and other components. For example, the processing component 302 may include a multimedia module to facilitate the interaction between the multimedia component 308 and the processing component 302.

[0136] The memory 304 is configured to store various types of data to support operations on the electronic device 300. Examples of such data include instructions for any application or method operating on the electronic device 300, contact data, phone book data, messages, pictures, videos, etc. The memory 304 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0137] The power supply component 306 provides power to the various components of the electronic device 300. The power supply component 306 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 300.

[0138] The multimedia component 308 includes a screen that provides an output interface between the electronic device 300 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 308 includes a front camera and / or a rear camera. When the electronic device 300 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0139] The audio component 310 is configured to output and / or input audio signals. For example, the audio component 310 includes a microphone (MIC), and when the electronic device 300 is in an operation mode, such as a call mode, a recording mode, and a voice information processing mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 304 or sent via the communication component 316. In some embodiments, the audio component 310 also includes a speaker for outputting audio signals.

[0140] I / O interface 312 provides an interface between processing component 302 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: home button, volume button, start button, and lock button.

[0141] The sensor assembly 314 includes one or more sensors for providing various aspects of status assessment for the electronic device 300. For example, the sensor assembly 314 can detect the open / closed state of the electronic device 300, the relative positioning of components, such as the display and keypad of the electronic device 300, and the sensor assembly 314 can also detect the position change of the electronic device 300 or a component of the electronic device 300, the presence or absence of user contact with the electronic device 300, the orientation or acceleration / deceleration of the electronic device 300, and the temperature change of the electronic device 300. The sensor assembly 314 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 314 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 314 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0142] The communication component 316 is configured to facilitate wired or wireless communication between the electronic device 300 and other devices. The electronic device 300 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 316 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 316 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency information processing (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0143] In an exemplary embodiment, the electronic device 300 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0144] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 304 including instructions, and the instructions can be executed by a processor 320 of an electronic device 300 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0145] A non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to perform Figure 2 The exception recovery method shown.

[0146] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0147] It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, devices or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0148] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram and the combination of the processes and / or blocks in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0149] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0150] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1The steps for the functions specified in one or more boxes.

[0151] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0152] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0153] The above is a detailed introduction to an abnormal recovery method, device and electronic device provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. An abnormality recovery method, characterized in that: Applied to a binary translation system, the binary translation system is used to translate a source program in a client into a target program in a host, the method comprising: In the event of an exception, determining a source instruction and a basic block corresponding to a target instruction triggering the exception in the source program, and marking a target position corresponding to the source instruction in the source program; Determine an offset value corresponding to a target register according to the target position and a register delay calculation algorithm; the target register includes registers corresponding to each instruction between the start position of the basic block and the target position and within a correction range of the register delay calculation algorithm; The value of the target register is modified according to the offset value.

2. The method according to claim 1, characterized in that Determining the offset value corresponding to the target register according to the target position and the register delay calculation algorithm includes: Determine, according to the target position and the register delay calculation algorithm, the offset values ​​corresponding to the instructions between the first instruction of the basic block corresponding to the source instruction and the target position; The offset values ​​corresponding to the instructions between the starting position of the basic block and the first source instruction are accumulated to obtain the offset value of the first register corresponding to the first source instruction; the first source instruction is any instruction between the starting position of the basic block and the target position.

3. The method according to claim 2, characterized in that The step of determining, according to the target position and the register delay calculation algorithm, offset values ​​corresponding to instructions between the first instruction of the basic block corresponding to the source instruction and the target position includes: Determine whether there is a repair mark at the target position of the basic block; the repair mark is used to indicate that the register delay calculation algorithm has triggered the repair processing of the registers corresponding to each instruction between the first instruction of the basic block and the target position; When there is no repair mark between the first instruction of the basic block and the target position, the offset value corresponding to each instruction between the first instruction of the basic block and the target position is determined according to the register delay calculation algorithm.

4. The method according to claim 3, characterized in that The method further comprises: In the case where the repair identifier exists between the first instruction of the basic block and the target position, the offset values ​​corresponding to the registers corresponding to the instructions between the first instruction of the basic block and the target position are cleared, and the next instruction of the target instruction is analyzed.

5. The method according to claim 2, characterized in that: The step of determining, according to the target position and the register delay calculation algorithm, offset values ​​corresponding to instructions between the first instruction of the basic block corresponding to the source instruction and the target position includes: For the basic block corresponding to the target instruction that triggers the exception, determine the sequence number corresponding to each instruction in the basic block according to the arrangement order of the instructions in the basic block, and determine the target sequence number corresponding to the instruction in the target position; Determine whether the sequence number corresponding to the i-th instruction in the basic block is less than or equal to the target sequence number; the initial value of i is 1, and i is a positive integer; When the sequence number corresponding to the i-th instruction in the basic block is less than or equal to the target sequence number, determining the offset value corresponding to the i-th instruction by using a register delay calculation algorithm; When the sequence number corresponding to the i-th instruction in the basic block is greater than the target sequence number, it is determined that the offset values ​​corresponding to the target registers are all calculated.

6. The method according to claim 1, characterized in that The step of modifying the value of the target register according to the offset value includes: Get the register value corresponding to each instruction between the starting position and the target position of the basic block; For a first register, adding the register value and the offset value to obtain a corrected register value; the first register is any register in the target register; The register value corresponding to the first register is replaced by the modified register value.

7. The method according to claim 1, characterized in that In the case of an exception, determining the source instruction and basic block corresponding to the target instruction triggering the exception in the source program, and marking the target position corresponding to the source instruction in the source program, includes: In the event of an exception, determining the instruction address where the exception occurred; Based on the instruction address, determining a basic block corresponding to the target instruction that triggers the exception; A source instruction corresponding to the target instruction triggering the exception in the source program is determined in the basic block based on the instruction address, and a target position corresponding to the source instruction in the source program is marked.

8. An abnormality recovery device, characterized in that: Applied to a binary translation system, the binary translation system is used to translate a source program in a client into a target program in a host, the device comprising: A determination unit is used to determine, in the event of an exception, a source instruction and a basic block corresponding to a target instruction triggering the exception in the source program, and mark a target position corresponding to the source instruction in the source program; determine an offset value corresponding to a target register according to the target position and a register delay calculation algorithm; the target register includes registers corresponding to each instruction between the start position of the basic block and the target position and within a correction range of the register delay calculation algorithm; The correction unit is used to correct the value of the target register according to the offset value.

9. The device according to claim 8, characterized in that The determining unit is specifically used for: Determine, according to the target position and the register delay calculation algorithm, the offset values ​​corresponding to the instructions between the first instruction of the basic block corresponding to the source instruction and the target position; The offset values ​​corresponding to the instructions between the starting position of the basic block and the first source instruction are accumulated to obtain the offset value of the first register corresponding to the first source instruction; the first source instruction is any instruction between the starting position of the basic block and the target position.

10. An electronic device, characterized in that: The electronic device comprises a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to execute the abnormality recovery method according to any one of claims 1 to 7 by one or more processors.

11. A readable storage medium, characterized in that: When the instructions in the storage medium are executed by a processor of an electronic device, the processor is enabled to execute the abnormality recovery method as described in any one of claims 1 to 7.

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