Distributed management method, device, system, equipment, and medium for upper half of interrupt

Abstract

The present disclosure provides a method, apparatus, system, device, and medium for distributed management of the upper half of interrupts. Among them, a processor runs a peripheral driver and a kernel thread for the lower half of interrupts; the peripheral driver allocates a memory area that can be directly read and written to the interrupt controller, assigns an interrupt flag to an external device, registers a processing function for the lower half of interrupts, and establishes a mapping relationship between the processing function for the lower half of interrupts and the interrupt flag. The interrupt controller receives an interrupt message sent by an external device, extracts the interrupt flag, and writes the interrupt flag and the position of a new cache tail pointer into a cache entry; the kernel thread for the lower half of interrupts determines whether there is an interrupt based on the position of the cache tail pointer and the position of the cache head pointer in the cache entry; in the case of an existing interrupt, queries the mapping relationship between the processing function for the lower half of interrupts and the interrupt flag based on the interrupt flag, determines the target processing function for the lower half of interrupts, and uses the target processing function for the lower half of interrupts to handle the interrupt.

Description

Technical Field

[0001] The present disclosure relates to the field of interrupt handling, and discloses a distributed management method, device, system, equipment, and medium for the upper half of an interrupt. Background Art

[0002] During the interrupt handling process, in order to improve the responsiveness and performance of the system, the interrupt handling process is usually divided into the top half and the bottom half; the upper half of the interrupt and the lower half of the interrupt are two important stages in the interrupt handling process. They work together through cooperation and division of labor to achieve efficient handling of interrupt events.

[0003] Currently, in the interrupt handling solution, both the upper half and the lower half of the interrupt need to be completed in the processor, which causes the occupation of processor resources, is not conducive to the improvement of interrupt handling efficiency, and has weak processing ability for concentrated interrupt outbreaks. Summary of the Invention

[0004] The present disclosure provides at least a distributed management method, device, system, equipment, and medium for the upper half of an interrupt to improve interrupt handling efficiency and solve the problem of processor resource occupation.

[0005] According to one aspect of the present disclosure, a distributed management method for the upper half of an interrupt is provided, including:

[0006] A processor runs a peripheral driver program and a kernel thread for the lower half of the interrupt; wherein, the peripheral driver program is used to allocate a directly readable and writable memory area to an interrupt controller, allocate an interrupt flag for an external device, the interrupt flag is used to uniquely identify the corresponding external device, and register a processing function for the lower half of the interrupt, establish a mapping relationship between the processing function for the lower half of the interrupt and the interrupt flag, and store the mapping relationship in a relationship table;

[0007] The interrupt controller receives an interrupt message sent by an external device, wherein the interrupt message includes an interrupt flag of the external device; wherein, the interrupt controller includes an upper half processing module and a tail pointer counter; the tail pointer counter is used to store the position of the cache tail pointer;

[0008] The interrupt controller uses the upper half processing module to extract the interrupt flag in the interrupt message, determines a new cache tail pointer position according to the cache tail pointer position, and writes the interrupt flag and the new cache tail pointer position into a cache entry in the directly readable and writable memory area;

[0009] The bottom half kernel thread of the interrupt obtains the cache header pointer position of the directly readable and writable memory area, and obtains cache entries from the directly readable and writable memory area according to the cache header pointer position; reads the cache tail pointer position in the cache entries, and determines whether there is an interrupt according to the cache header pointer position and the cache tail pointer position; in the case of the existence of an interrupt, reads the interrupt flag in the cache entries, queries the relationship table based on the extracted interrupt flag, determines the target bottom half interrupt handling function, and uses the target bottom half interrupt handling function to perform interrupt handling.

[0010] In a possible implementation manner, after determining the new cache tail pointer position according to the cache tail pointer position, the upper half interrupt processing module is further configured to update the cache tail pointer position to the new cache tail pointer position.

[0011] In a possible implementation manner, the bottom half kernel thread of the interrupt stores the cache header pointer position of the directly readable and writable memory area.

[0012] In a possible implementation manner, an interrupt flag and a directly readable and writable memory area mapping table are stored in the interrupt controller;

[0013] Before writing the interrupt flag and the new cache tail pointer position into the cache entry of the directly readable and writable memory area, it further includes:

[0014] The upper half interrupt processing module combines the interrupt flag, queries the interrupt flag and directly readable and writable memory area mapping table, and locates the directly readable and writable memory area.

[0015] In a possible implementation manner, the determining whether there is an interrupt according to the cache header pointer position and the cache tail pointer position includes:

[0016] In the case where the cache header pointer position is different from the cache tail pointer position, it is determined that there is an interrupt to be processed.

[0017] In a possible implementation manner, the obtaining the cache header pointer position of the directly readable and writable memory area includes:

[0018] Obtain the cache header pointer position of the directly readable and writable memory area from the header pointer counter of the processor.

[0019] According to another aspect of the present disclosure, there is provided an upper half distributed management device for interrupts, including a processor, an interrupt controller, and a directly readable and writable memory area;

[0020] The processor is used to run the peripheral driver and the bottom half kernel thread of the interrupt; wherein, the peripheral driver is used to allocate a directly readable and writable memory area to the interrupt controller, allocate an interrupt flag for the external device, the interrupt flag is used to uniquely identify the corresponding external device, and register a bottom half interrupt handling function, establish a mapping relationship between the bottom half interrupt handling function and the interrupt flag, and store the mapping relationship in a relationship table;

[0021] The interrupt controller is used to receive an interrupt message sent by an external device, wherein the interrupt message includes the interrupt flag of the external device; wherein, the interrupt controller includes an upper half interrupt handling module and a tail pointer counter; the tail pointer counter is used to store the position of the cache tail pointer; and, use the upper half interrupt handling module to extract the interrupt flag in the interrupt message, determine the new cache tail pointer position according to the cache tail pointer position, and write the interrupt flag and the new cache tail pointer position into the cache entry of the directly readable and writable memory area;

[0022] The bottom half kernel thread in the processor is used to obtain the position of the cache head pointer of the directly readable and writable memory area, and obtain a cache entry from the directly readable and writable memory area according to the cache head pointer position; read the cache tail pointer position in the cache entry, and judge whether there is an interrupt according to the cache head pointer position and the cache tail pointer position; in the case of an existing interrupt, read the interrupt flag in the cache entry, and query the relationship table based on the extracted interrupt flag to determine the target bottom half interrupt handling function, and use the target bottom half interrupt handling function to perform interrupt processing.

[0023] According to another aspect of the present disclosure, there is provided a distributed management system for the upper half of an interrupt, including:

[0024] The processor described in any one of the above;

[0025] The interrupt controller described in any one of the above;

[0026] The directly readable and writable memory area described in any one of the above;

[0027] An external device for sending an interrupt message to the interrupt controller.

[0028] According to another aspect of the present disclosure, there is provided an electronic device, including a memory, a processor, and a computer program stored on the memory, and the processor implements the method described in any one of the above when executing the computer program.

[0029] According to another aspect of the present disclosure, there is provided a computer-readable storage medium having a computer program stored therein, and when the computer program is executed by a processor, the method described in any one of the above is implemented.

[0030] In the method, apparatus, system, device, and medium for distributed management of the upper half of an interrupt in the present disclosure, a processor runs a peripheral driver and a kernel thread for the lower half of the interrupt; wherein, the peripheral driver is used to allocate a directly readable and writable memory area to an interrupt controller, allocate an interrupt flag for an external device, the interrupt flag is used to uniquely identify the corresponding external device, and register a processing function for the lower half of the interrupt, establish a mapping relationship between the processing function for the lower half of the interrupt and the interrupt flag, and store the mapping relationship in a relationship table. The interrupt controller receives an interrupt message sent by an external device, wherein the interrupt message includes the interrupt flag of the external device; wherein, the interrupt controller includes an upper half processing module for the interrupt and a tail pointer counter; the tail pointer counter is used to store the position of the cache tail pointer. The interrupt controller uses the upper half processing module for the interrupt to extract the interrupt flag in the interrupt message, determines a new cache tail pointer position according to the position of the cache tail pointer, and writes the interrupt flag and the new cache tail pointer position into a cache entry in the directly readable and writable memory area. The kernel thread for the lower half of the interrupt obtains the position of the cache head pointer in the directly readable and writable memory area, and obtains a cache entry from the directly readable and writable memory area according to the position of the cache head pointer; reads the position of the cache tail pointer in the cache entry, and determines whether there is an interrupt according to the position of the cache head pointer and the position of the cache tail pointer; in the case of an existing interrupt, reads the interrupt flag in the cache entry, queries the relationship table based on the extracted interrupt flag, determines a target processing function for the lower half of the interrupt, and uses the target processing function for the lower half of the interrupt to perform interrupt processing. The technical solution of the present disclosure unloads the processing operation of the upper half of the interrupt of the processor by using the interrupt controller, not only reduces the data processing pressure of the processor, but also can improve the interrupt processing efficiency, can quickly process the intensively burst interrupts, and effectively improves the interrupt processing ability and scenario adaptation ability.

[0031] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings are used to better understand the solution and do not constitute a limitation to the present disclosure. Among them:

[0033] Figure 1 is a flowchart of the method for distributed management of the upper half of an interrupt according to an embodiment of the present disclosure;

[0034] Figure 2 is a schematic structural diagram of the upper half of the interrupt distributed management system according to an embodiment of the present disclosure;

[0035] Figure 3 is a schematic diagram of a cache entry according to an embodiment of the present disclosure;

[0036] Figure 4 is a schematic structural diagram of the upper half of the interrupt distributed management device according to an embodiment of the present disclosure;

[0037] Figure 5 is a schematic structural diagram of an electronic device according to the present disclosure. Detailed implementation manners

[0038] The following describes exemplary embodiments of the present disclosure with reference to the accompanying drawings. Various details of the embodiments of the present disclosure are included to facilitate understanding, and they should be considered merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, descriptions of well-known functions and structures are omitted for clarity and conciseness.

[0039] In view of the problems of low interrupt handling efficiency and serious occupation of processor resources in the current interrupt handling solution, the present disclosure provides a distributed management method, apparatus, system, device, and medium for the upper half of interrupts. In the present disclosure, a processor runs a peripheral driver and a kernel thread for the lower half of interrupts; wherein, the peripheral driver is used to allocate a directly readable and writable memory area to an interrupt controller, allocate an interrupt flag for an external device, the interrupt flag is used to uniquely identify the corresponding external device, and register a processing function for the lower half of interrupts, establish a mapping relationship between the processing function for the lower half of interrupts and the interrupt flag, and store the mapping relationship in a relationship table. The interrupt controller receives an interrupt message sent by an external device, wherein the interrupt message includes the interrupt flag of the external device; wherein, the interrupt controller includes an upper half processing module for interrupts and a tail pointer counter; the tail pointer counter is used to store the position of the cache tail pointer. The interrupt controller uses the upper half processing module for interrupts to extract the interrupt flag in the interrupt message, determines a new cache tail pointer position according to the cache tail pointer position, and writes the interrupt flag and the new cache tail pointer position into a cache entry in the directly readable and writable memory area. The kernel thread for the lower half of interrupts obtains the position of the cache head pointer in the directly readable and writable memory area, and obtains a cache entry from the directly readable and writable memory area according to the cache head pointer position; reads the cache tail pointer position in the cache entry, and determines whether there is an interrupt according to the cache head pointer position and the cache tail pointer position; in the case of an existing interrupt, reads the interrupt flag in the cache entry, and queries the relationship table based on the extracted interrupt flag to determine a target processing function for the lower half of interrupts, and uses the target processing function for the lower half of interrupts to perform interrupt handling. The technical solution of the present disclosure unloads the processing operation of the upper half of interrupts of the processor by using the interrupt controller, not only reduces the data processing pressure of the processor, but also can improve the interrupt handling efficiency, can quickly process the interrupts that occur intensively, and effectively improves the interrupt handling ability and scenario adaptation ability.

[0040] The technical solution of the present disclosure will be described below through specific embodiments.

[0041] As Figure 1 shown, it is a flowchart of the distributed management method for the upper half of interrupts in this embodiment. The execution subject of this embodiment is a computing device or component with data processing capabilities. Specifically, the method of this embodiment may include the following steps:

[0042] S110. The processor runs the peripheral driver and the bottom half kernel thread of the interrupt; wherein, the peripheral driver is used to allocate a directly readable and writable memory area to the interrupt controller, allocate an interrupt flag for the external device, the interrupt flag is used to uniquely identify the corresponding external device, and register a bottom half interrupt handling function, establish a mapping relationship between the bottom half interrupt handling function and the interrupt flag, and store the mapping relationship in a relationship table.

[0043] The above directly readable and writable memory area is namely Direct Memory Access (DMA). Here, the interrupt controller corresponds to the DMA. After the processor finishes the allocation, the interrupt controller can directly perform read and write operations in the DMA.

[0044] The interrupt flag is used for the program running in the processor to distinguish the interrupt source, that is, to distinguish the external device that generates the interrupt.

[0045] After the processor allocates an interrupt flag for the external device, it can send the interrupt flag to the corresponding external device through the communication component.

[0046] S120. The interrupt controller receives the interrupt message sent by the external device, wherein, the interrupt message includes the interrupt flag of the external device; wherein, the interrupt controller includes an upper half interrupt handling module and a tail pointer counter; the tail pointer counter is used to store the position of the cache tail pointer.

[0047] After determining the new cache tail pointer position according to the cache tail pointer position, the upper half interrupt handling module is further used to update the cache tail pointer position to the new cache tail pointer position, that is, update the value of the tail pointer counter.

[0048] S130. The interrupt controller uses the upper half interrupt handling module to extract the interrupt flag in the interrupt message, determines the new cache tail pointer position according to the cache tail pointer position, and writes the interrupt flag and the new cache tail pointer position into the cache entry of the directly readable and writable memory area.

[0049] In some embodiments, the bottom half kernel thread of the interrupt stores the position of the cache head pointer of the directly readable and writable memory area.

[0050] In some embodiments, the bottom half kernel thread of the interrupt can obtain the position of the cache head pointer of the directly readable and writable memory area from the head pointer counter of the processor.

[0051] S140. The bottom half kernel thread of the interrupt obtains the cache header pointer position of the directly readable and writable memory area, and obtains a cache entry from the directly readable and writable memory area according to the cache header pointer position; reads the cache tail pointer position in the cache entry, and judges whether there is an interrupt according to the cache header pointer position and the cache tail pointer position; in the case of an existing interrupt, reads the interrupt flag in the cache entry, queries the relationship table based on the extracted interrupt flag, determines the target bottom half interrupt handling function, and uses the target bottom half interrupt handling function to perform interrupt processing.

[0052] In some embodiments, an interrupt flag and a directly readable and writable memory area mapping table are stored in the interrupt controller. In this case, before writing the interrupt flag and the new cache tail pointer position into the cache entry of the directly readable and writable memory area, the following steps need to be further executed:

[0053] The upper half interrupt processing module combines the interrupt flag and queries the interrupt flag and directly readable and writable memory area mapping table to locate the directly readable and writable memory area.

[0054] In some embodiments, the judgment of whether there is an interrupt according to the cache header pointer position and the cache tail pointer position can be specifically implemented by the following steps:

[0055] In the case where the cache header pointer position is different from the cache tail pointer position, it is determined that there is an interrupt to be processed; in the case where the cache header pointer position is the same as the cache tail pointer position, it is determined that there is no interrupt to be processed.

[0056] In some embodiments, as Figure 2 shown, in the upper half distributed management scheme of the interrupt, the processor CPU runs the peripheral driver program and the bottom half kernel thread Bottom Half. The peripheral driver program mainly completes the initialization of the external device and only focuses on the work related to the interrupt. The specific initialization tasks are as follows:

[0057] 1. Initialize the external device interrupt related configuration, allocate an interrupt flag for the external device, and the interrupt flag is globally unique and is used for the program for interrupt processing to distinguish the interrupt source.

[0058] 2. Allocate a memory area (i.e., the above-mentioned directly readable and writable memory area) that can be DMA (Direct Memory Access) to the interrupt controller for the interrupt controller to write the interrupt message into the memory area.

[0059] 3. Register the bottom half handler function, establish the mapping relationship between the bottom half handler function and the interrupt flag, and subsequently use it for the bottom half kernel thread to call the registered bottom half handler function for interrupt handling.

[0060] The external device sends an interrupt message to the interrupt controller, and the interrupt message includes the interrupt flag of the interrupt device.

[0061] The interrupt controller includes a top half processing module Top Half and a mapping table of interrupt flags and DMA-capable memory regions.

[0062] The interrupt controller is used to perform the following operations:

[0063] 1. After receiving the interrupt message sent by the external device, the top half processing module Top Half queries the mapping table of interrupt flags and DMA-capable memory regions through the interrupt flag carried in the external device interrupt message to find the corresponding DMA-capable memory.

[0064] 2. The top half processing module Top Half allocates a memory buffer for the interrupt flag and the Buffertail count (i.e., the new cache tail pointer position) through DMA writing to the driver.

[0065] 3. After the top half processing module Top Half completes the DMA write to the memory buffer (i.e., writes the interrupt flag and the new cache tail pointer position to the allocated memory buffer), it updates the Buffertail count, that is, updates it to the new cache tail pointer position.

[0066] Bottom Half is a task running on the operating system and can be scheduled and executed by the kernel task scheduling mechanism. Its main operations are as follows:

[0067] 1. Record the Bufferhead count (i.e., the cache head pointer position), and read the cache entry Entry in the DMA-capable memory region according to the recorded Bufferhead count.

[0068] 2. Compare the recorded Buffer head count with the Buffertail count to determine whether there is an interrupt. If there is an interrupt, obtain the interrupt flag from the Entry.

[0069] 3. Query the relationship table between the interrupt flag and the bottom half handler function, find the corresponding bottom half handler function, and use the queried bottom half handler function for interrupt handling.

[0070] Such as Figure 3As shown, the composition of the cache entry Entry includes the interrupt flag of the external device, the Buffer tail count in the interrupt controller (i.e., the cache tail pointer position), and other messages; the other messages can be customized according to specific application scenarios and are not limited in this disclosure.

[0071] Based on the same inventive concept, this disclosure provides a distributed management device for the upper half of interrupts. The steps executed by the components of this device are the same as or similar to those of the above method, so the similar parts will not be elaborated. As Figure 4 shown, the distributed management device for the upper half of interrupts in this embodiment includes a processor 410, an interrupt controller 420, and a directly readable and writable memory area 430.

[0072] The processor 410 is used to run the peripheral driver and the kernel thread of the lower half of the interrupt; wherein, the peripheral driver is used to allocate a directly readable and writable memory area to the interrupt controller, allocate an interrupt flag for the external device, the interrupt flag is used to uniquely identify the corresponding external device, and register the processing function of the lower half of the interrupt, establish a mapping relationship between the processing function of the lower half of the interrupt and the interrupt flag, and store the mapping relationship in the relationship table.

[0073] The interrupt controller 420 is used to receive the interrupt message sent by the external device, wherein the interrupt message includes the interrupt flag of the external device; wherein, the interrupt controller includes an upper half of interrupt processing module and a tail pointer counter; the tail pointer counter is used to store the cache tail pointer position; and use the upper half of interrupt processing module to extract the interrupt flag in the interrupt message, determine the new cache tail pointer position according to the cache tail pointer position, and write the interrupt flag and the new cache tail pointer position into the cache entry of the directly readable and writable memory area.

[0074] The kernel thread of the lower half of the interrupt in the processor 410 is used to obtain the cache head pointer position of the directly readable and writable memory area, and obtain the cache entry from the directly readable and writable memory area according to the cache head pointer position; read the cache tail pointer position in the cache entry, and judge whether there is an interrupt according to the cache head pointer position and the cache tail pointer position; in the case of an existing interrupt, read the interrupt flag in the cache entry, and query the relationship table based on the extracted interrupt flag to determine the target processing function of the lower half of the interrupt, and use the target processing function of the lower half of the interrupt to perform interrupt processing.

[0075] Based on the same inventive concept, this disclosure provides a distributed management system for the upper half of interrupts. The steps executed by the components of this system are the same as or similar to those of the above method, so the similar parts will not be elaborated. Specifically, the distributed management system for the upper half of interrupts includes:

[0076] The processor of any of the above embodiments; the interrupt controller of any of the above embodiments; the directly readable and writable memory area of any of the above embodiments; and an external device for sending an interrupt message to the interrupt controller.

[0077] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a computer-readable storage medium.

[0078] Figure 5 A schematic block diagram of an example electronic device 500 that can be used to implement the embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as, a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, a personal digital processor, a cellular phone, a smart phone, a wearable device, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely exemplary and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0079] As Figure 5 shown, the device 500 includes a computing unit 510 that can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 520 or a computer program loaded from a storage unit 580 into a random access memory (RAM) 530. In the RAM 530, various programs and data required for the operation of the device 500 can also be stored. The computing unit 510, the ROM 520, and the RAM 530 are connected to each other through a bus 540. An input / output (I / O) interface 550 is also connected to the bus 540.

[0080] A plurality of components in the device 500 are connected to the I / O interface 550, including: an input unit 560, such as a keyboard, a mouse, etc.; an output unit 570, such as various types of displays, speakers, etc.; a storage unit 580, such as a magnetic disk, an optical disk, etc.; and a communication unit 590, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 590 allows the device 500 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0081] The computing unit 510 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 510 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 510 executes the various methods and processes described above. For example, in some embodiments, any of the above methods can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 580. In some embodiments, part or all of the computer program can be loaded and / or installed onto the device 500 via the ROM 520 and / or the communication unit 590. When the computer program is loaded into the RAM 530 and executed by the computing unit 510, one or more steps of any of the methods described above can be executed. Alternatively, in other embodiments, the computing unit 510 can be configured to execute any of the methods described above in any other suitable manner (e.g., by means of firmware).

[0082] Various embodiments of the systems and techniques described above in this document can be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special-purpose or general-purpose programmable processor that receives data and instructions from a storage system, at least one input device, and at least one output device, and transmits the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0083] The program code for implementing the methods of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to the processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the program codes are executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code can be executed entirely on the machine, partially on the machine, as an independent software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0084] In the context of this disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0085] For purposes of providing an interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can also be used to provide for interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic, speech, or tactile input).

[0086] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0087] A computer system can include a client and a server. The client and the server are generally remote from each other and typically interact through a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, a server of a distributed system, or a server incorporating a blockchain.

[0088] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired results of the technical solution disclosed in this disclosure can be achieved, and no limitation is imposed herein.

[0089] The above specific embodiments do not constitute a limitation on the protection scope of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub - combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the protection scope of this disclosure.

Claims

1. A distributed management method for the upper half of interrupts, characterized in that, including: The processor runs the peripheral driver and the bottom half kernel thread of the interrupt; wherein, the peripheral driver is used to allocate a directly readable and writable memory area to the interrupt controller, allocate an interrupt flag for the external device, the interrupt flag is used to uniquely identify the corresponding external device, and register the bottom half interrupt handling function, establish a mapping relationship between the bottom half interrupt handling function and the interrupt flag, and store the mapping relationship in a relationship table; The interrupt controller receives an interrupt message sent by an external device, wherein the interrupt message includes the interrupt flag of the external device; wherein, the interrupt controller includes an upper half interrupt handling module and a tail pointer counter; the tail pointer counter is used to store the position of the cache tail pointer; The interrupt controller uses the upper half interrupt handling module to extract the interrupt flag in the interrupt message, determines a new cache tail pointer position according to the cache tail pointer position, and writes the interrupt flag and the new cache tail pointer position into the cache entry of the directly readable and writable memory area; The bottom half kernel thread of the interrupt obtains the cache head pointer position of the directly readable and writable memory area, and obtains a cache entry from the directly readable and writable memory area according to the cache head pointer position; reads the cache tail pointer position in the cache entry, and determines whether there is an interrupt according to the cache head pointer position and the cache tail pointer position; in the case of an existing interrupt, reads the interrupt flag in the cache entry, queries the relationship table based on the extracted interrupt flag, determines the target bottom half interrupt handling function, and uses the target bottom half interrupt handling function to handle the interrupt.

2. The method according to claim 1, wherein After determining the new cache tail pointer position according to the cache tail pointer position, the upper half interrupt handling module is further used to update the cache tail pointer position to the new cache tail pointer position.

3. The method according to claim 1, wherein The bottom half kernel thread of the interrupt stores the cache head pointer position of the directly readable and writable memory area.

4. The method according to claim 1, wherein An interrupt flag and directly readable and writable memory area mapping table is stored in the interrupt controller; Before writing the interrupt flag and the new cache tail pointer position into the cache entry of the directly readable and writable memory area, it further includes: The upper half interrupt handling module combines the interrupt flag, queries the interrupt flag and directly readable and writable memory area mapping table, and locates the directly readable and writable memory area.

5. The method according to claim 1, characterized in that, Determining whether there is an interrupt according to the cache head pointer position and the cache tail pointer position includes: In the case where the cache head pointer position is different from the cache tail pointer position, it is determined that there is an interrupt to be processed.

6. The method according to claim 1, wherein Obtaining the cache head pointer position of the directly readable and writable memory area includes: Obtaining the cache head pointer position of the directly readable and writable memory area from the head pointer counter of the processor.

7. A distributed management device for the upper half of an interrupt, characterized in that, including a processor, an interrupt controller, and a directly readable and writable memory area; The processor is used to run the peripheral driver and the bottom half kernel thread of the interrupt; wherein, the peripheral driver is used to allocate a directly readable and writable memory area to the interrupt controller, allocate an interrupt flag for the external device, the interrupt flag is used to uniquely identify the corresponding external device, and register the bottom half interrupt handling function, establish a mapping relationship between the bottom half interrupt handling function and the interrupt flag, and store the mapping relationship in the relationship table; The interrupt controller is used to receive the interrupt message sent by the external device, wherein the interrupt message includes the interrupt flag of the external device; wherein, the interrupt controller includes an upper half interrupt handling module and a tail pointer counter; the tail pointer counter is used to store the position of the cache tail pointer; and, use the upper half interrupt handling module to extract the interrupt flag in the interrupt message, determine the new cache tail pointer position according to the cache tail pointer position, and write the interrupt flag and the new cache tail pointer position into the cache entry of the directly readable and writable memory area; The bottom half kernel thread in the processor is used to obtain the position of the cache head pointer of the directly readable and writable memory area, and obtain the cache entry from the directly readable and writable memory area according to the cache head pointer position; read the cache tail pointer position in the cache entry, and judge whether there is an interrupt according to the cache head pointer position and the cache tail pointer position; in the case of an interrupt, read the interrupt flag in the cache entry, query the relationship table based on the extracted interrupt flag, determine the target bottom half interrupt handling function, and use the target bottom half interrupt handling function to perform interrupt processing.

8. A distributed management system for the upper half of interrupts, characterized in that, Comprising: The processor according to any one of claims 1 to 6; The interrupt controller according to any one of claims 1 to 6; The directly readable and writable memory area according to any one of claims 1 to 6; An external device for sending an interrupt message to the interrupt controller.

9. An electronic device, comprising a memory, a processor, and a computer program stored on the memory, wherein the processor implements the method according to any one of claims 1-6 when executing the computer program.

10. A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, and the computer program implements the method according to any one of claims 1-6 when executed by the processor.

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