A method for prefetch configuration optimization of a shared prefetcher within a plurality of core groups

Abstract

The application discloses a prefetch configuration optimization method of a plurality of core groups sharing a prefetcher, characterized by sampling performance characteristic data, obtaining a prefetch benefit ratio and a secondary cache miss rate of each application under different prefetch configurations, scheduling all the applications based on the secondary cache miss rate and the prefetch benefit ratio, obtaining an application group running in each core group, sampling core performance characteristic data, obtaining a core group prefetch benefit ratio and a memory bandwidth occupancy improvement value of each core group under different prefetch configurations, comparing the core group prefetch benefit ratios of each core group under different prefetch configurations, configuring the core group prefetch benefit ratio of each core group with the highest core group prefetch benefit ratio corresponding to the prefetch configuration, and monitoring the memory bandwidth in real time according to the memory bandwidth occupancy improvement value and optimizing the prefetch configuration of the prefetcher in the core group.

Description

TECHNICAL FIELD

[0001] The present application relates to a pre-fetch configuration optimization method of a pre-fetcher, in particular to a pre-fetch configuration optimization method of a shared pre-fetcher in multiple core groups. BACKGROUND

[0002] Data prefetching is a method that can effectively improve system performance. With the development of computer hardware and software, the speed of the processor has grown much faster than the improvement of memory speed. In order to bridge this gap, data prefetching technology is widely used in modern computer systems. Data prefetching reduces memory access latency by loading data into cache in advance before the processor actually needs it. This process is usually based on the prefetcher's prediction of the program's access pattern, and the data that may be needed is loaded into the cache from the main memory or other low-speed storage devices in advance. This technology can significantly improve the utilization of the processor and the overall system performance, and reduce the time for the processor to wait for data. Therefore, optimizing the prefetch configuration of the prefetcher is crucial to improving the performance of the system. However, in the multi-core processor environment, this task is challenging. An overly aggressive prefetch configuration can lead to memory bandwidth contention and cache pollution, reducing system performance. While an overly conservative prefetch configuration may not be able to load data into the cache in time. To solve these problems, current research focuses on dynamically selecting the optimal prefetch configuration for the prefetcher at runtime, using heuristic strategies or machine learning techniques to dynamically adjust according to the performance characteristics of the application.

[0003] Current prefetch configuration optimization methods for prefetchers mainly target processor architectures with core-exclusive two-level cache prefetchers, i.e., each core has exclusive access to level one and level two caches, and multiple cores share a level three cache. In this architecture, each level two cache is equipped with a corresponding group of level two cache prefetchers, which contain multiple prefetchers that can load data into the cache in advance according to different access patterns. By adjusting the parameters of these level two cache prefetcher groups, the data prefetching in the corresponding level two cache can be optimized, and the performance of the corresponding core can be improved.

[0004] However, the above optimization scheme is not applicable to the architecture in which multiple core groups share a second-level cache and a prefetcher, each core group including multiple processor cores, a first-level cache with the same number of processor cores, a second-level cache, and a second-level cache prefetcher, and multiple core groups sharing a third-level cache. In the design of such a processor architecture, each core group shares a second-level cache prefetcher, and a prefetcher serves all processor cores in a core group but only serves one processor core at any time. Therefore, adjusting the prefetch configuration of the second-level cache prefetcher in such a processor architecture will affect the data prefetching and performance of all processor cores in the entire core group. For example, when a prefetch-beneficial application and a prefetch-harmful application run on different processor cores in the same core group, if the prefetch aggressiveness parameter is increased according to the characteristics of the prefetch-beneficial application, the performance of the prefetch-harmful application will be severely degraded. In addition, even if all applications are beneficial to prefetching, blind adjustment of the prefetch aggressiveness parameter will also cause waste of shared resources such as memory bandwidth due to different prefetch benefits. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a prefetch configuration optimization method for a shared prefetcher in multiple core groups, which not only optimizes the prefetch configuration of the prefetcher but also improves the overall performance of the system.

[0006] The technical solution adopted by the present application to solve the above technical problem is a prefetch configuration optimization method for a shared prefetcher in multiple core groups, comprising the following steps:

[0007] Step 1: Sampling the performance characteristic data of applications distributed on all processor cores in each core group under different prefetch configurations during runtime, and obtaining the prefetch benefit ratio and second-level cache miss rate of each application under different prefetch configurations according to the performance characteristic data;

[0008] Step 2: Scheduling all applications based on the second-level cache miss rate and the prefetch benefit ratio to obtain an application group running in each core group;

[0009] Step 3: Sampling the core performance characteristic data of all processor cores in each core group under different prefetch configurations during runtime, and obtaining the core group prefetch benefit ratio and memory bandwidth occupancy improvement value of each core group under different prefetch configurations according to the core performance characteristic data;

[0010] Step 4: Comparing the core group prefetch benefit ratio of each core group under different prefetch configurations, and configuring the prefetch configuration corresponding to the highest core group prefetch benefit ratio for each core group;

[0011] Step 5, real-time monitoring of the memory bandwidth according to the memory bandwidth occupation promotion value, and optimizing the prefetch configuration of the prefetcher in the core group;

[0012] Step 6, repeating step 5, when the number of times of executing step 5 exceeds the preset fixed number of times, returning to execute step 1.

[0013] Compared with the prior art, the application has the advantages that the performance characteristic data of the application distributed on all processor cores in each core group under different prefetch configurations is sampled, the prefetch benefit ratio and the secondary cache miss rate of each application under different prefetch configurations are obtained according to the performance characteristic data, the secondary cache miss rate and the prefetch benefit ratio are used to schedule all applications, the application group running in each core group is obtained, the prefetch benefit of the applications in the core group is ensured to be similar, the situation that some applications have a serious performance decline after the prefetch configuration is adjusted according to the average prefetch benefit of the core group when there is a large difference in the prefetch benefit of the applications in the subsequent core group is avoided, in addition, the secondary cache contention problem in the core group is relieved by scheduling according to the secondary cache miss rate of the application; the core performance characteristic data of all processor cores in each core group under different prefetch configurations is sampled, the core group prefetch benefit ratio and the memory bandwidth occupation promotion value of each core group under different prefetch configurations are obtained according to the core performance characteristic data, the prefetch configuration of the secondary cache prefetcher of the core group is dynamically optimized according to the core group prefetch benefit ratio and the system memory bandwidth occupation, and the overall performance of the system is improved.

[0014] Further, the prefetch configuration includes closing prefetch, conservative prefetch and aggressive prefetch.

[0015] Further, the specific operation process of step 1 is as follows:

[0016] Step 1-1, sampling the performance characteristic data of the application distributed on all processor cores in each core group under different prefetch configurations by the performance monitoring unit of the processor, wherein the performance characteristic data includes the number of cycles in the sampling period, the number of executed instructions, the number of secondary cache hits, the number of secondary cache misses and the memory bandwidth usage;

[0017] Step 1-2, calculating the prefetch benefit ratio and the secondary cache miss rate of each application under different prefetch configurations according to the number of cycles, the number of executed instructions, the number of secondary cache hits, the number of secondary cache misses and the memory bandwidth usage:

[0018] The prefetch benefit ratio when the prefetch configuration is config is denoted as P2B_ratio config , wherein, IPC_ratio config represents the performance improvement ratio when the prefetch configuration is config, IPC config represents the number of instructions per cycle of the core when the prefetch configuration is config, IPC prefetch_off represents the number of instructions per cycle of the core when the prefetch configuration is off-prefetch, the number of instructions per cycle is the ratio of the number of executed instructions to the number of cycles, config represents the type of prefetch configuration, bandwidth_ratio config represents the bandwidth occupancy improvement ratio when the prefetch configuration is config, bandwidth config represents the memory bandwidth usage of the core when the prefetch configuration is config, bandwidth prefetch_off represents the memory bandwidth usage of the core when the prefetch configuration is off-prefetch.

[0019] L2_miss_ratio wherein, L2cache miss represents the number of secondary cache misses, and L2cache hit represents the number of secondary cache hits.

[0020] Further, the specific operation process of step ② is as follows:

[0021] Step ②-1, according to the secondary cache miss rate of each application program under different prefetch configurations, the average secondary cache miss rate of each application program is obtained, and all application programs are sorted in ascending order according to the average secondary cache miss rate of each application program, to obtain the sorted application programs;

[0022] Step ②-2, according to the prefetch benefit ratio of each application program under different prefetch configurations, the average prefetch benefit ratio of each application program is obtained, and the sorted application programs are grouped based on the number of core groups, and the application programs in each group are sorted in ascending order according to the average prefetch benefit ratio of each application program, to obtain group application programs, wherein M represents the total number of application programs, and N represents the total number of core groups, represents the upward rounding;

[0023] Step 2-3, the application programs with the same rank in each application program grouping are evenly scheduled to different processor cores in the same core group, to obtain the application program groups running in each core group. The average level 2 cache miss rate is used as an index for measuring the interference degree of the application programs on the shared level 2 cache. By grouping the application programs and distributing the application programs in the same cache grouping to different core groups, the average level 2 cache miss rate between the core groups is ensured to be close, and the unbalanced interference in the shared cache is effectively reduced. According to the sorting of the average prefetch revenue ratio of the application programs, the application programs with the same average prefetch revenue ratio rank are distributed to the same core group, so that the application programs in the same core group have close average prefetch revenue ratios, thereby enhancing the effect of subsequent prefetch configuration optimization and avoiding the problems of low overall prefetch revenue and overall waste of resources.

[0024] Further, the specific operation process of step 3 is as follows:

[0025] Step 3-1, the performance monitoring unit of the processor samples the core performance characteristic data of all processor cores in each core group under different prefetch configurations during runtime, and the core performance characteristic data includes the number of cycles, the number of executed instructions, the number of level 2 cache hits, the number of level 2 cache misses, and the memory bandwidth usage amount in the sampling period;

[0026] Step 3-2, based on the number of cycles, the number of executed instructions, the number of level 2 cache hits, the number of level 2 cache misses, and the memory bandwidth usage amount, the core group prefetch revenue ratio and the memory bandwidth occupancy improvement value of each core group under different prefetch configurations are calculated;

[0027] The core group prefetch revenue ratio when the prefetch configuration is config is denoted as GP2B_ratio config , Wherein, IPC_group_ratio conig represents the core group performance improvement ratio when the prefetch configuration is config, C represents the total number of cores in a core group, represents the performance improvement ratio of the kth core in the core group when the prefetch configuration is config, config represents the type of prefetch configuration, bandwidth_group_ratio config represents the core group bandwidth occupancy improvement ratio when the prefetch configuration is config, group_bandwidth config represents the memory bandwidth usage amount of all cores in the core group when the prefetch configuration is config, is the memory bandwidth usage amount of all cores in the core group when the prefetch configuration is turned off;

[0028] Let the memory bandwidth occupancy improvement value when prefetch is configured as config be bandwidth_change config , bandwidth_change config = group_bandwidth config - group_bandwidth prefetch_off , wherein group_bandwidth config represents the total bandwidth usage of the core group when prefetch is configured as config, and group_bandwidth prefetch_off represents the total bandwidth usage of the core group when prefetch is configured as off. By using the geometric mean to process the average performance improvement of the core group, and calculating the ratio of the average performance improvement to the total bandwidth occupancy improvement, the benefits of prefetch configuration are effectively revealed, overcoming the problem that simply using the average of the bandwidth occupancy improvement rates of all cores may lead to inaccurate memory occupancy evaluation in the case of different core bandwidth occupancy levels, and also solving the problem that when directly using core performance characteristic data, the performance improvement rate of different per-cycle instruction levels of application programs cannot be fully reflected, so that the benefits of prefetch configuration of different application programs in a multi-core environment can be more accurately evaluated and optimized.

[0029] Further, in steps ①-1 and ③-1, the sampling period is 100 ms.

[0030] Further, the specific operation process of step ⑤ is as follows:

[0031] Step ⑤-1, after waiting for a preset time interval, it is judged whether the memory bandwidth usage exceeds a preset first threshold value, if yes, step ⑤-2 is executed; if no, step ⑤-3 is executed.

[0032] Step ⑤-2, from the multiple core groups with low prefetch benefit ratio and with prefetch function not turned off, select the core group corresponding to the maximum memory bandwidth occupancy improvement value, if the prefetch aggressiveness parameter of the prefetcher in the core group has not been reduced to the minimum, reduce the prefetch aggressiveness parameter of the prefetcher in the core group, if the prefetch aggressiveness parameter of the prefetcher in the core group has been reduced to the minimum, set the prefetch configuration of the prefetcher in the core group to off, and execute step ⑤-1.

[0033] Step ⑤-3, it is judged whether the memory bandwidth usage is lower than a preset second threshold value, if yes, step ⑤-4 is executed; if no, it is ended.

[0034] Step ⑤-4, from the plurality of core groups with higher prefetch revenue ratio and the prefetch aggressiveness parameter not reaching the highest, select the core group corresponding to the minimum memory bandwidth occupation promotion value, if the prefetch configuration of the prefetcher in the core group is set to closed prefetch, set the prefetch configuration of the prefetcher in the core group to conservative prefetch, if the prefetch configuration of the prefetcher in the core group is not closed prefetch, promote the prefetch aggressiveness parameter of the prefetcher in the core group, and execute step ⑤-1. The average prefetch revenue ratio of each core group and the influence of prefetch on bandwidth occupation are comprehensively considered, when the system bandwidth usage is low, the prefetch aggressiveness parameter of the core group with higher prefetch revenue ratio and smaller influence on bandwidth is preferentially improved, compared with comprehensively improving the prefetch aggressiveness parameter of all core groups, this strategy can more effectively improve the core performance, and meanwhile, the system performance instability and memory delay increase caused by too high bandwidth occupation are avoided; on the contrary, when the system bandwidth usage is high, by reducing the prefetch aggressiveness parameter of the core group with lower prefetch revenue ratio and greater influence on bandwidth, the performance decline possibly caused by reducing the prefetch aggressiveness parameter can be reduced as much as possible while reducing the bandwidth occupation, so that the best balance between bandwidth usage and core performance is realized.

[0035] Further, in step ⑤-1, the preset time interval is 200-500 ms, and the preset first threshold is 75%; in step ⑤-2, the prefetch aggressiveness parameter of 25% of the prefetchers in the core group is reduced; in step ⑤-3, the preset second threshold is 40%; and in step ⑤-4, the prefetch aggressiveness parameter of 25% of the prefetchers in the core group is promoted.

[0036] Further, in step ⑥, the preset fixed number of times is 20 times. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 The processor architecture of the application is shown in the figure;

[0038] Figure 2 The overall flowchart of the application is shown in the figure;

[0039] Figure 3 The specific operation flowchart of step ② of the application is shown in the figure. DETAILED DESCRIPTION

[0040] The application will be further described in detail below with reference to the embodiments of the accompanying drawings.

[0041] A prefetch configuration optimization method for a plurality of core groups sharing prefetchers, as shown in the figure Figure 1As shown, the processor architecture applicable to the present application includes a memory, a three-level cache and a plurality of core groups, each core group including a plurality of processor cores, a first-level cache with the same number of processor cores, a second-level cache and a second-level cache prefetcher, such as Figure 2 As shown, the specific prefetch configuration optimization method includes the following steps:

[0042] Step 1, sample the performance characteristic data of the application programs distributed in all processor cores in each core group under different prefetch configurations, and obtain the prefetch benefit ratio and the second-level cache miss rate of each application program under different prefetch configurations according to the performance characteristic data; the prefetch configuration includes turning off prefetch, conservative prefetch and aggressive prefetch, which respectively represent that the prefetch parameter is not turned on, the prefetcher aggressiveness parameter is the lowest value, and the prefetcher aggressiveness parameter is the highest value; the prefetcher aggressiveness parameter is determined by the configurable parameters of the processor, including the prefetch distance, the prefetch depth, the external queue threshold and other parameters; taking the Intel Atom core group as an example, the prefetcher aggressiveness parameter includes the prefetch distance (Distance) and the external queue threshold (External Queue Threshold) ;

[0043] The specific operation process of step 1 is as follows:

[0044] Step 1-1, sample the performance characteristic data of the application programs distributed in all processor cores in each core group under different prefetch configurations by the performance monitoring unit of the processor, the performance characteristic data including the number of cycles, the number of executed instructions, the number of second-level cache hits, the number of second-level cache misses and the memory bandwidth usage in the sampling period; the sampling period is 100 ms;

[0045] Step 1-2, calculate the prefetch benefit ratio and the second-level cache miss rate of each application program under different prefetch configurations according to the number of cycles, the number of executed instructions, the number of second-level cache hits, the number of second-level cache misses and the memory bandwidth usage:

[0046] The prefetch benefit ratio when the prefetch configuration is config is denoted as P2B_ratio config , Wherein, IPC_ratio config represents the performance improvement ratio when the prefetch configuration is config, IPC config represents the number of instructions per cycle of the core when the prefetch configuration is config, and IPC prefetch_offThis indicates the number of instructions per cycle for the core when prefetching is disabled. Instructions per cycle is the ratio of the number of instructions executed to the number of cycles. `config` indicates the type of prefetch configuration, and `bandwidth_ratio`... config This indicates the bandwidth usage increase ratio when the prefetch configuration is set to config. bandwidth config This indicates the core's memory bandwidth usage when the prefetch configuration is set to config. prefetch_off This indicates the core's memory bandwidth usage when prefetching is configured to be disabled;

[0047] When the prefetch configuration is set to config, the second-level cache miss rate is denoted as L2_miss_ratio. Where L2cache miss represents the number of times the second-level cache is missed, and L2cache hit represents the number of times the second-level cache is hit;

[0048] Step 2: Schedule all applications based on the second-level cache miss rate and prefetch benefit ratio to obtain the application groups running in each core group;

[0049] like Figure 3 As shown, the specific operation process of step ② is as follows:

[0050] Step ②-1: Based on the L2 cache miss rate of each application under different prefetch configurations, obtain the average L2 cache miss rate of each application. Sort all applications in ascending order based on the average L2 cache miss rate of each application to obtain the sorted applications.

[0051] Step ②-2: Based on the prefetch revenue ratio of each application under different prefetch configurations, obtain the average prefetch revenue ratio of each application. Group the sorted applications according to the number of core groups, and within each group, sort the applications by their average prefetch revenue ratio from smallest to largest. The application groups are defined as follows: M represents the total number of applications, and N represents the total number of core groups. Indicates rounding up;

[0052] Step ②-3: Evenly schedule applications with the same ranking in each application group to different processor cores in the same core group to obtain the application group running in each core group.

[0053] Step 3, sampling the core performance characteristic data of all processor cores in each core group under different prefetch configurations, and obtaining the core group prefetch benefit ratio and memory bandwidth occupancy improvement value of each core group under different prefetch configurations according to the core performance characteristic data;

[0054] The specific operation process of step 3 is as follows:

[0055] Step 3-1, sampling the core performance characteristic data of all processor cores in each core group under different prefetch configurations by the performance monitoring unit of the processor, wherein the core performance characteristic data includes the number of cycles, the number of executed instructions, the number of second-level cache hits, the number of second-level cache misses, and the memory bandwidth usage in the sampling period; the sampling period is 100 ms;

[0056] Step 3-2, based on the number of cycles, the number of executed instructions, the number of second-level cache hits, the number of second-level cache misses, and the memory bandwidth usage, the core group prefetch benefit ratio and the memory bandwidth occupancy improvement value of each core group under different prefetch configurations are calculated;

[0057] The core group prefetch benefit ratio when the prefetch configuration is config is denoted as GP2B_ratio config , Wherein, IPC_group_ratio conig represents the core group performance improvement ratio when the prefetch configuration is config, C represents the total number of cores in a core group, represents the performance improvement ratio of the kth core in the core group when the prefetch configuration is config, config represents the type of prefetch configuration, bandwidth_group_ratio config represents the core group bandwidth occupancy improvement ratio when the prefetch configuration is config, group_bandwidth config represents the memory bandwidth usage of all cores in the core group when the prefetch configuration is config, is the memory bandwidth usage of all cores in the core group when the prefetch configuration is turned off;

[0058] The memory bandwidth occupancy improvement value when the prefetch configuration is config is denoted as bandwidth_change config , bandwidth_change config = group_bandwidth config - group_bandwidth prefetch_off , wherein, group_bandwidthconfig group_bandwidth represents the total bandwidth usage of the core group when the prefetch configuration is config prefetch_off group_bandwidth represents the total bandwidth usage of the core group when the prefetch configuration is off

[0059] Step 4, compare the core group prefetch benefit ratio of each core group under different prefetch configurations, and configure the prefetch configuration corresponding to the highest core group prefetch benefit ratio for each core group;

[0060] Step 5, real-time monitoring of memory bandwidth according to memory bandwidth occupancy improvement value, and optimizing the prefetch configuration of the prefetcher in the core group;

[0061] The specific operation process of step 5 is as follows:

[0062] Step 5-1, wait for a preset time interval, and then judge whether the memory bandwidth usage exceeds a preset first threshold value, if yes, execute step 5-2; if not, execute step 5-3; wherein the preset time interval is 200-500 ms, and the preset first threshold value is 75%;

[0063] Step 5-2, select the core group corresponding to the maximum memory bandwidth occupancy improvement value from the multiple core groups with lower core group prefetch benefit ratio and non-closed prefetch function, if the prefetch aggressiveness parameter of the prefetcher in the core group has not been reduced to the minimum, reduce the prefetch aggressiveness parameter of the prefetcher in the core group by 25%, if the prefetch aggressiveness parameter of the prefetcher in the core group has been reduced to the minimum, set the prefetch configuration of the prefetcher in the core group to closed prefetch, and execute step 5-1;

[0064] Step 5-3, judge whether the memory bandwidth usage is lower than a preset second threshold value, if yes, execute step 5-4; if not, end; wherein the preset second threshold value is 40%;

[0065] Step 5-4, select the core group corresponding to the minimum memory bandwidth occupancy improvement value from the multiple core groups with higher core group prefetch benefit ratio and non-maximum prefetch aggressiveness parameter, if the prefetch configuration of the prefetcher in the core group is closed prefetch, set the prefetch configuration of the prefetcher in the core group to conservative prefetch, if the prefetch configuration of the prefetcher in the core group is not closed prefetch, improve the prefetch aggressiveness parameter of the prefetcher in the core group by 25%, and execute step 5-1;

[0066] Step 6, repeat step 5, when the number of times of executing step 5 exceeds a preset fixed number of times, return to execute step 1, wherein the preset fixed number of times is 20.

Claims

1. A method for prefetch configuration optimization of a shared prefetcher within a plurality of core groups, the method comprising: The method comprises the following steps: Step 1: Sampling performance characteristic data of application programs running in different prefetch configurations on all processor cores in each core group, and obtaining a prefetch benefit ratio and a secondary cache miss rate of each application program in different prefetch configurations according to the performance characteristic data; Step 2: scheduling all application programs based on the secondary cache miss rate and the prefetch benefit ratio to obtain an application program group running in each core group; The specific operation process of step 2 is as follows: Step 2-1: obtaining an average secondary cache miss rate of each application program according to the secondary cache miss rate of each application program in different prefetch configurations, and sorting all application programs according to the average secondary cache miss rate from small to large to obtain sorted application programs; Step 2-2, according to the pre-fetch benefit ratio of each application program under different pre-fetch configurations, obtaining the average pre-fetch benefit ratio of each application program, grouping the sorted application programs based on the number of core groups, and sorting each application program in the group from small to large according to the average pre-fetch benefit ratio of each application program, obtaining Grouping the application programs, wherein M represents the total number of application programs, N represents the total number of core groups, represents rounding up; Step 2-3: uniformly scheduling application programs with the same ranking in each application program group to different processor cores in the same core group to obtain an application program group running in each core group; Step 3: sampling core performance characteristic data of all processor cores in different prefetch configurations running in time, and obtaining a core group prefetch benefit ratio and a memory bandwidth occupancy improvement value of each core group in different prefetch configurations according to the core performance characteristic data; Step 4: comparing the core group prefetch benefit ratio of each core group in different prefetch configurations, and configuring the prefetch configuration corresponding to the highest core group prefetch benefit ratio for each core group; Step 5: monitoring the memory bandwidth in real time according to the memory bandwidth occupancy improvement value, and optimizing the prefetch configuration of the prefetcher in the core group; The specific operation process of step 5 is as follows: Step 5-1: waiting for a preset time interval, and then judging whether the memory bandwidth usage exceeds a preset first threshold value, if yes, executing step 5-2; if no, executing step 5-3; Step 5-2: selecting a core group corresponding to the maximum memory bandwidth occupancy improvement value from multiple core groups with a lower core group prefetch benefit ratio and a prefetch function not closed, if the prefetch aggressiveness parameter of the prefetcher in the core group has not been reduced to the minimum, reducing the prefetch aggressiveness parameter of the prefetcher in the core group, if the prefetch aggressiveness parameter of the prefetcher in the core group has been reduced to the minimum, setting the prefetch configuration of the prefetcher in the core group to closed prefetch, and executing step 5-1; Step 5-3: judging whether the memory bandwidth usage is lower than a preset second threshold value, if yes, executing step 5-4; if no, ending; Step 5-4: selecting a core group corresponding to the minimum memory bandwidth occupancy improvement value from multiple core groups with a higher core group prefetch benefit ratio and a prefetch aggressiveness parameter not reaching the maximum, if the prefetch configuration of the prefetcher in the core group is closed prefetch, setting the prefetch configuration of the prefetcher in the core group to conservative prefetch, if the prefetch configuration of the prefetcher in the core group is not closed prefetch, improving the prefetch aggressiveness parameter of the prefetcher in the core group, and executing step 5-1; Step 6: repeatedly executing step 5, and returning to execute step 1 when the number of times of executing step 5 exceeds a preset fixed number.

2. The method of claim 1, wherein The prefetch configurations include closing prefetch, conservative prefetch and aggressive prefetch.

3. The method of claim 2, wherein The specific operation process of step ① is as follows: Step ①-1, the performance monitoring unit of the processor samples the runtime performance characteristic data of the application program distributed on all processor cores in each core group under different prefetch configurations, and the performance characteristic data includes the number of cycles, the number of executed instructions, the number of second cache hits, the number of second cache misses and the memory bandwidth usage in the sampling period; Step ①-2, the prefetch benefit ratio and the second cache miss rate of each application program under different prefetch configurations are calculated according to the number of cycles, the number of executed instructions, the number of second cache hits, the number of second cache misses and the memory bandwidth usage; P2B_ratio config , IPC_ratio config represents a performance improvement ratio when the prefetch configuration is config, IPC config represents the number of instructions per cycle of the core when the prefetch configuration is config, prefetch_off represents the number of instructions per cycle of the core when the prefetch configuration is off, the number of instructions per cycle is the ratio of the number of executed instructions to the number of cycles, config represents the type of prefetch configuration, bandwidth_ratio config represents a bandwidth occupation improvement ratio when the prefetch configuration is config, bandwidth config represents the memory bandwidth usage of the core when the prefetch configuration is config, prefetch_off represents the memory bandwidth usage of the core when the prefetch configuration is off; The pre-fetch is configured as config, and the secondary cache miss rate is recorded as L2 miss ratio, Wherein, L2 cache miss represents the number of secondary cache misses, and L2 cache hit represents the number of secondary cache hits.

4. The method of claim 3, wherein The specific operation process of step ③ is as follows: Step ③-1, the performance monitoring unit of the processor samples the runtime core performance characteristic data of all processor cores in each core group under different prefetch configurations, and the core performance characteristic data includes the number of cycles, the number of executed instructions, the number of second cache hits, the number of second cache misses and the memory bandwidth usage in the sampling period; Step ③-2, based on the number of cycles, the number of executed instructions, the number of second cache hits, the number of second cache misses and the memory bandwidth usage, the core group prefetch benefit ratio and the memory bandwidth occupancy improvement value of each core group under different prefetch configurations are calculated; GP2B_ratio config , wherein, IPC_group_ratio config represents the performance improvement ratio of a core group when the prefetch is configured as config, C represents the total number of cores in a core group, represents the performance improvement ratio of the kth core in a core group when the prefetch is configured as config, config represents the type of prefetch configuration, bandwidth_group_ratio config represents the bandwidth occupation improvement ratio of a core group when the prefetch is configured as config, group_bandwidth config represents the memory bandwidth usage of all cores in a core group when the prefetch is configured as config, represents the memory bandwidth usage of all cores in a core group when the prefetch is configured as no prefetch. Let the memory bandwidth occupancy improvement value when prefetch is configured as config be bandwidth_change config , bandwidth_change config = group_bandwidth config - group_bandwidth prefetch_off , wherein group_bandwidth config represents the total bandwidth usage of the core group when prefetch is configured as config, and group_bandwidth prefetch_off represents the total bandwidth usage of the core group when prefetch is configured as off.

5. The method of claim 3 or 4, wherein In step ①-1 and step ③-1, the sampling period is 100 ms.

6. The method of claim 1, wherein In step ⑤-1, the preset time interval is 200-500 ms, and the preset first threshold is 75%; in step ⑤-2, the prefetch aggressiveness parameter of 25% of the prefetchers in the core group is reduced; in step ⑤-3, the preset second threshold is 40%; in step ⑤-4, the prefetch aggressiveness parameter of 25% of the prefetchers in the core group is increased.

7. The method of claim 1, wherein In step ⑥, the preset fixed number of times is 20 times. In step ⑥, the preset fixed number of times is 20 times.

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