Multi-bit in-memory computing array structure and electronic equipment

Abstract

The invention discloses a multi-bit in-memory computing array structure and electronic equipment. The structure comprises a plurality of voltage-controlled delay circuits which are arranged in a rectangular shape. Each voltage-controlled delay circuit is provided with an input end, an output end, a voltage-controlled end and at least one control end. When the control end signal is 0, the reference signal generates a first delay through the corresponding input end and output end. And when the control end signal is 1, the reference signal generates delay 2 through the corresponding input end and output end. The second time delay is the sum of the first time delay and the delay adjustment amount, and the delay adjustment amount is in linear positive correlation with the corresponding voltage control end signal. And the in-memory calculation array structure represents a multiply-accumulate calculation result of a plurality of bit input values and a plurality of bit weight values through a delay adjustment amount generated by combining a plurality of columns of voltage-controlled delay circuits in a row form. According to the method, multiplication and accumulation in-memory calculation of multi-bit input and multi-bit weight is realized, and relatively high system-level reasoning precision and efficiency can be provided.

Description

Technical Field

[0001] The present invention relates to a computing array structure in the technical field of integrated circuit design, in particular to a multi-bit in-memory computing array structure, and also to an electronic device. Background Art

[0002] In traditional computing architecture, data needs to be moved repeatedly between memory and processor, resulting in the "memory wall" problem, which limits computing speed and energy efficiency. Computing In Memory (CIM) breaks the von Neuma architecture of traditional computers and embeds computing circuits into memory, integrating storage and computing, thereby greatly reducing data migration and memory access consumption.

[0003] Current non-volatile in-memory computing technology solutions support binary neural networks (BNNs) or binary weight networks (BWNs), which reduce storage requirements to a certain extent and improve energy efficiency. However, BNNs and BWNs are only suitable for simple networks, which usually only support single-bit input and weight multiplication and multiply and accumulate (MAC) in-memory computing. Therefore, when applied to complex applications, they can only provide limited system-level reasoning accuracy, which limits the further development of AI technology. Summary of the invention

[0004] In order to solve the technical problem that the existing in-memory computing array structure only supports in-memory computing of single-bit input and weight multiplication and can only provide limited system-level reasoning accuracy, the present invention provides a multi-bit in-memory computing array structure and electronic device.

[0005] The present invention is implemented by the following technical solution: a multi-bit in-memory computing array structure, comprising: A plurality of voltage-controlled delay circuits are arranged in a rectangular shape, wherein a column corresponds to a row of bit input values, and a row corresponds to a column of bit weight values; each voltage-controlled delay circuit has an input end, an output end, a voltage-controlled end, and at least one control end; in each row, the output end of each voltage-controlled delay circuit is connected to the input end of the next column; the same control end of each column is connected and receives the corresponding bit weight value, and the voltage-controlled end of each row is connected and receives the corresponding bit input value; when the control end signal is 0, the reference signal generates a delay of one through the corresponding input end and output end; when the control end signal is 1, the reference signal generates a delay of two through the corresponding input end and output end; the delay of two is the sum of the delay of one and a delay adjustment amount, and the delay adjustment amount is linearly positively correlated with the corresponding voltage-controlled end signal; The delay adjustment amounts of the multiple columns of voltage-controlled delay circuits are accumulated to represent the multiplication and accumulation calculation results of the multiple bit input values ​​and the multiple bit weight values.

[0006] The present invention characterizes the calculation result by using the rising edge delay adjustment amount of the reference signal. Since the rising edge delay adjustment amount can be accumulated, when it is necessary to realize the multiplication and accumulation calculation of multi-bit input and multi-bit weight, it is only necessary to combine the multi-column multi-bit data in-memory calculation array in the form of rows, and use the signal output by each voltage-controlled delay circuit in the previous column as the input of the corresponding voltage-controlled delay circuit in the next column, so that the bit calculation result in the previous column can be passed to the calculation result of the corresponding bit in the next column. The number of columns of the voltage-controlled delay circuit determines the maximum number of accumulation items that can be performed by the structure, and also determines the number of multi-bit multiplication and accumulation groups that can be performed simultaneously by the structure. The calculation array structure can provide greater system-level reasoning accuracy and efficiency, and solves the problem that the current non-volatile in-memory calculation circuit usually only supports single-bit input and weight multiplication and accumulation in-memory calculation, and can only provide limited system-level reasoning accuracy.

[0007] As a further improvement of the above scheme, the computing array structure also includes a storage array; each voltage-controlled delay circuit includes a high-order voltage-controlled delay unit and a low-order voltage-controlled delay unit; each voltage-controlled delay unit has the input end, the output end, the voltage-controlled end, and two control ends with opposite signals: control end 1 and control end 2; in each column, the output end of the high-order voltage-controlled delay unit is connected to the input end of the high-order voltage-controlled delay unit in the next column, and the output end of the low-order voltage-controlled delay unit is connected to the input end of the low-order voltage-controlled delay unit in the next column; in each voltage-controlled delay circuit, the control end 1 of the high-order voltage-controlled delay unit is connected to the control end 1 of the low-order voltage-controlled delay unit, and the control end 2 of the high-order voltage-controlled delay unit is connected to the control end 2 of the low-order voltage-controlled delay unit; the control end 1 of each row of the voltage-controlled delay circuit is connected to the local bit line LBL of the storage array, and the control end 2 is connected to the local bit line LBLB; The calculation array structure implements multiplication and accumulation calculation in the following way: (1) The sum of four times the delay adjustment amount generated by the high-order voltage-controlled delay unit in each column and the delay adjustment amount generated by the low-order voltage-controlled delay unit is taken as the total adjustment amount; (2) taking the number of unit adjustment amounts contained in the total adjustment amount as the multiplication and accumulation result of the multiple bit input values ​​and the single bit weight value; (3) using multiple rows of voltage-controlled delay circuits corresponding to multiple bit weight values, adding multiple total adjustment amounts according to the weight ratio to obtain a multiplication result of multiple bit input values ​​and multiple bit weight values; (4) The total adjustment amount generated by combining multiple rows of voltage-controlled delay circuits in column form represents the multiplication and accumulation calculation results of multiple bit input values ​​and multiple bit weight values.

[0008] Furthermore, each voltage-controlled delay unit includes: An input control circuit, used for generating an input voltage analog quantity of the voltage control terminal according to signals of the control terminal 1 and the control terminal 2; A trigger circuit connected to the input control circuit and configured to output a delay adjustment amount of a reference signal pulse width according to an input terminal signal; An inverter circuit is connected to the trigger circuit, is used for shaping the waveform output by the trigger circuit, and has the output end.

[0009] Further, the trigger circuit includes NMOS tubes N1~N3 and PMOS tube P1; the gate of N1 is connected to the reference signal, the source is grounded, and the drain is connected to node X1; the gate of N2 is connected to the reference signal, the source is connected to node X1, and the drain is connected to node X2; the gate of N3 is connected to node X2, the source is connected to node X1, and the drain is connected to node X3; the gate of P1 is connected to the reference signal, the source is connected to node X2, and the drain is connected to the power supply VDD; the gates of N1, N2, and P1 serve as the input terminals; The input control circuit includes NMOS transistors N4 and N5; the gate of N4 serves as the control terminal 1 and is connected to the local bit line LBL, the source is connected to the node X3, and the drain serves as the voltage control terminal; the gate of N5 serves as the control terminal 2 and is connected to the local bit line LBLB, the source is grounded, and the drain is connected to the node X3; The inverter circuit includes an NMOS tube N6 and a PMOS tube P2; the gate of N6 is connected to the node X2, the source is grounded, and the drain is used as the output terminal; the gate of P2 is connected to the node X2, the source is used as the output terminal, and the drain is connected to the power supply VDD.

[0010] Furthermore, the in-memory computing array structure also includes: A quantization module, which is used to convert the pulse width of the reference signal output by the last column of arbitrary voltage-controlled delay circuits from a time analog quantity into a binary digital signal; A digital shift adder module is used to amplify the quantization result of the high-bit voltage-controlled delay unit by four times and add it to the quantization result of the low-bit voltage-controlled delay unit to obtain the multiplication result of the single-bit input value and the single-bit weight value, and to weight the multiplication results of different bits according to the weights to obtain the multiplication and accumulation calculation results of the multi-bit input value and the multi-bit weight value.

[0011] As a further improvement of the above solution, the reference signal is a rectangular wave reference signal; when the control end 1 signal is 0 and the control end 2 signal is 1, the delay 1 is a fixed value t 0 , is not affected by the voltage at the voltage control terminal; when the signal at the control terminal 1 is 1 and the signal at the control terminal 2 is 0, the delay 2 is t 0 +kΔt; Among them, k is the binary value of the voltage-controlled end signal, Δt is the unit adjustment amount, which represents the minimum adjustment amount of the voltage-controlled delay circuit to the reference signal; the calculation array structure calculates the multiplication and accumulation results of multiple bit input values ​​and multiple bit weight values ​​through the number of unit adjustment amounts Δt contained in the delay adjustment amount.

[0012] Furthermore, the number of the bit input values ​​and the number of the bit weight values ​​are both four; and the in-memory calculation array structure further includes: An input signal column channel module is used to divide the four-bit input values ​​into a high-order two-bit signal and a low-order two-bit signal, and respectively control the output voltage of the input column channel one of the high-order voltage-controlled delay unit and the input column channel two of the low-order voltage-controlled delay unit, and the output voltage value is determined by the corresponding two-bit signal.

[0013] As a further improvement of the above solution, the in-memory computing array structure further includes: A storage array includes a plurality of storage cells arranged in a rectangular shape, which are used to store a plurality of bit weight values ​​and support switching between a standard read / write mode and a multi-bit multiplication-accumulation calculation mode; in the multi-bit multiplication-accumulation calculation mode, the calculation array structure realizes multiplication-accumulation calculation of a plurality of bit input values ​​and a plurality of bit weight values; a first storage node and a second storage node of each storage cell are respectively connected to a local bit line LBL and a local bit line LBLB.

[0014] Furthermore, the in-memory computing array structure also includes: A local read / write module is used to transmit read / write signals through a horizontal word line HWL and a global bit line GBL / GBLB in a standard read / write mode to complete the read / write operations on the storage unit; the local read / write module includes NMOS tubes N7 and N8; the gate of N7 is connected to the horizontal word line HWL, the drain is connected to a local bit line LBL, and the source is connected to the global bit line GBL; the gate of N8 is connected to the horizontal word line HWL, the drain is connected to a local bit line LBLB, and the source is connected to the global bit line GBLB; when the horizontal word line HWL and the word line WL of the n-th row storage unit are turned on, the write signal is first transmitted to the local bit line LBL / LBLB through the global bit line GBL / GBLB, and then the data is written into the n-th row storage unit, where n is an arbitrary number of rows of storage units.

[0015] The present invention also provides an electronic device, which includes a memory and a processor; the memory includes the multi-bit in-memory computing array structure described in any one of the above items.

[0016] Compared with the existing in-memory computing array structure and electronic device, the multi-bit in-memory computing array structure and electronic device of the present invention have the following beneficial effects: The multi-bit in-memory calculation array structure characterizes the calculation result by using the rising edge delay adjustment amount of the reference signal. Since the rising edge delay adjustment amount can be accumulated, when it is necessary to realize the multi-bit input and multi-bit weight multi-addition calculation, it is only necessary to combine the multi-column multi-bit data in-memory calculation array in the form of rows, and use the signal output by each voltage-controlled delay circuit in the previous column as the input of the corresponding voltage-controlled delay circuit in the next column, so that the bit calculation result in the previous column can be passed to the calculation result of the corresponding bit in the next column. The number of columns of the voltage-controlled delay circuit determines the maximum number of accumulation items that can be performed by the structure, and also determines the number of multi-bit multiplication and accumulation groups that can be performed simultaneously by the structure. The calculation array structure can provide greater system-level reasoning accuracy and efficiency, and solves the problem that the current non-volatile in-memory calculation circuit usually only supports single-bit input and weight multiplication and accumulation in-memory calculation, and can only provide limited system-level reasoning accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of the structure of a multi-bit in-memory computing array structure according to Embodiment 1 of the present invention; Figure 2 for Figure 1 A schematic diagram of the structure of the storage array and the local read-write module of the multi-bit in-memory computing array structure; Figure 3 for Figure 1 A circuit diagram of a voltage-controlled delay unit of a multi-bit in-memory computing array structure; Figure 4 for Figure 3 Symbol diagram of the voltage-controlled delay unit in; Figure 5 for Figure 1 A framework diagram of a storage array, a local read / write module, and a voltage-controlled delay circuit in a multi-bit in-memory computing array structure; Figure 6 Schematic diagram of calculation of four-bit input and four-bit weight in Embodiment 1 of the present invention; Figure 7 This is a simulation diagram when the input values ​​are 0V, 0.17V, 0.32V, 0.47V and the delay adjustment amount is 6p in Example 1 of the present invention; Figure 8 This is a simulation diagram of Example 1 of the present invention when the input values ​​are 0V, 0.175V, 0.338V, 0.576V and the delay adjustment amounts are different; Fig. 9 This is a simulation diagram when INPUT = 503ps, t0 = 26ps, and Δt = 6ps in Example 1 of the present invention; Fig.10 It is the first Monte Carlo simulation diagram for different delay adjustment amounts in Example 1 of the present invention; Fig.11 It is a second Monte Carlo simulation diagram for different delay adjustment amounts in Example 1 of the present invention; Fig.12 The third Monte Carlo simulation diagram for different delay adjustment amounts in Example 1 of the present invention; Fig.13 This is the fourth Monte Carlo simulation diagram for different delay adjustment amounts in Example 1 of the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0019] Example 1 See also Figures 1 to 5 This embodiment provides a multi-bit in-memory computing array structure, the core structure of which is a plurality of voltage-controlled delay circuits. In this embodiment, the in-memory computing array structure also includes a storage array, a quantization module, a digital shift adder module, an input signal column channel module, and a local read-write module. In some other embodiments, the in-memory computing array structure may also include other modules or circuits, which may be configured according to actual needs.

[0020] Multiple voltage-controlled delay circuits are arranged in a rectangular shape, that is, the voltage-controlled delay circuits are arranged in a matrix array, which is similar to a storage array. The columns of the matrix array correspond to a row of bit input values, and the rows correspond to a column of bit weight values. That is, the multiple voltage-controlled delay circuits in each column correspond to multiple bit input values, and the multiple voltage-controlled delay circuits in each row correspond to multiple bit weight values. Each voltage-controlled delay circuit has an input end, an output end, a voltage-controlled end, and at least one control end. In each row, the output end of each voltage-controlled delay circuit is connected to the input end of the next column. The same control end of each column is connected and receives the corresponding bit weight value, and the voltage-controlled end of each row is connected and receives the corresponding bit input value. When the control end signal is 0, the reference signal generates a delay of one through the corresponding input end and output end. When the control end signal is 1, the reference signal generates a delay of two through the corresponding input end and output end. Delay two is the sum of delay one and a delay adjustment amount, and the delay adjustment amount is linearly positively correlated with the corresponding voltage-controlled end signal. The in-memory computing array structure represents the multiplication and accumulation calculation results of multiple bit input values ​​and multiple bit weight values ​​by accumulating the delay adjustment amounts of multiple columns of voltage-controlled delay circuits.

[0021] Please continue reading Figure 2The storage array includes a plurality of storage units arranged in a rectangular shape and is used to store a plurality of bit weight values. The storage array can be set to a plurality of groups, each group being used to store a bit weight value. In this embodiment, the storage unit is preferably a 6T-SRAM, and the storage array is used to switch between a standard read-write mode and a multi-bit multiplication-accumulation calculation mode. In the multi-bit multiplication-accumulation calculation mode, the in-memory calculation array structure realizes the multiplication-accumulation calculation of a plurality of bit input values ​​and a plurality of bit weight values. The first storage node and the second storage node of the storage unit are connected to the local bit lines LBL and LBLB, respectively.

[0022] In some embodiments including this embodiment, the reference signal is a rectangular wave reference signal. When the control terminal 1 signal is 0 and the control terminal 2 signal is 1, the delay 1 is not affected by the voltage value of the voltage control terminal and is defined as t 0 When the control terminal 1 signal is 1 and the control terminal 2 signal is 0, when the voltage control terminal signal is 00, the delay time 2 is t 0 +0Δt, when the voltage control end signal is 01, the delay time is t 0 +1Δt, when the voltage control end signal is 10, the delay time is t 0 +2Δt, when the voltage control end signal is 11, the delay time is t 0 +3Δt. Δt is defined as a unit adjustment amount, which is the minimum adjustment amount of the voltage-controlled delay circuit to the reference signal. The in-memory calculation array structure calculates the multiplication and accumulation calculation results of multiple bit input values ​​and multiple bit weight values ​​by the number of delay adjustment amounts containing the unit adjustment amount.

[0023] Please continue reading Figure 3 , Figure 4 as well as Figure 5 In this embodiment, each voltage-controlled delay circuit includes two voltage-controlled delay units, and the two voltage-controlled delay units are respectively a high-order voltage-controlled delay unit and a low-order voltage-controlled delay unit. Each voltage-controlled delay unit has an input terminal IN, an output terminal OUT, a voltage-controlled terminal (Vin, A for the high-order voltage-controlled delay unit and B for the low-order voltage-controlled delay unit), and two control terminals with opposite signals: control terminal 1 C and control terminal 2 CB. The delay adjustment amount of the voltage-controlled delay unit is determined by the storage weight and the voltage value of the input signal, and the multiplication calculation of 2-bit input and 1-bit weight can be realized. In the multi-bit in-memory calculation mode, multiple voltage-controlled delay units delay the rising edge of the input rectangular wave reference signal, and the voltage-controlled delay units are connected in series step by step, which can realize the multiplication and accumulation calculation of multi-bit input and multi-bit weight.

[0024] The output end OUT of each high-order voltage-controlled delay unit is connected to the input end IN of the high-order voltage-controlled delay unit in the next column, and the control end of the high-order voltage-controlled delay unit is only connected to the control end of the low-order voltage-controlled delay unit, and is not connected to the control end of the high-order voltage-controlled delay unit in the next row. The output end OUT of each low-order voltage-controlled delay unit is connected to the input end IN of the low-order voltage-controlled delay unit in the next column, and the low-order voltage-controlled delay unit is only connected to the control end of the high-order voltage-controlled delay unit, and is not connected to the control end of the low-order voltage-controlled delay unit in the next row. In each voltage-controlled delay circuit, the control end 1C of the high-order voltage-controlled delay unit is connected to the control end 1C of the low-order voltage-controlled delay unit, and the control end 2CB of the high-order voltage-controlled delay unit is connected to the control end 2CB of the low-order voltage-controlled delay unit. The control end 1 of each row of voltage-controlled delay circuits is connected to the local bit line LBL of the storage array, and the control end 2 is connected to the local bit line LBLB of the storage array. The amount of delay adjustment of the reference signal rising edge by the high-order voltage-controlled delay unit and the amount of delay adjustment of the reference signal rising edge by the low-order voltage-controlled delay circuit are the multiplication results of the corresponding 2-bit input and 1-bit weight.

[0025] The calculation array structure of this embodiment implements multiplication and accumulation calculation in the following manner: (1) The sum of four times the delay adjustment amount generated by the high-order voltage-controlled delay unit in each column and the delay adjustment amount generated by the low-order voltage-controlled delay unit is taken as the total adjustment amount; (2) taking the number of unit adjustment amounts contained in the total adjustment amount as the multiplication and accumulation result of the multiple bit input values ​​and the single bit weight value; (3) using multiple rows of voltage-controlled delay circuits corresponding to multiple bit weight values, adding multiple total adjustment amounts according to the weight ratio to obtain a multiplication result of multiple bit input values ​​and multiple bit weight values; (4) The total adjustment amount generated by combining multiple rows of voltage-controlled delay circuits in column form represents the multiplication and accumulation calculation results of multiple bit input values ​​and multiple bit weight values.

[0026] Here, each column can realize the multiplication calculation of multi-bit input and multi-bit weight. The operation realized by different columns is the multiplication calculation of another group of multi-bit input and multi-bit weight value. The multiplication and accumulation result of multi-bit input and multi-bit weight value is realized by cascading multiple columns. The voltage-controlled input voltage of the voltage-controlled delay circuit in the same column is the same, both A and B, but the input control C and CB of the voltage-controlled delay unit in the same column are not the same, which are the data weights of the corresponding bits. This means that the final output of different groups of voltage-controlled delay units is used to characterize the multiplication calculation result of the data input and data weight of the corresponding bit. The sum of the four times adjustment of the time of the rising edge of the reference signal of the high-order voltage-controlled delay unit and the time adjustment of the rising edge of the reference signal of the low-order voltage-controlled delay circuit contains the amount of Δt, which is the multiplication calculation result of the bit input and the weight. The Δt in the above text is the unit adjustment, that is, the minimum adjustment of the voltage-controlled delay circuit to the reference signal.

[0027] As a design method, each voltage-controlled delay unit in this embodiment includes an input control circuit, a trigger circuit and an inverter circuit. In other embodiments, the structure of the voltage-controlled delay unit can be adaptively adjusted. The input control circuit is used to generate an analog value of the input voltage of the voltage-controlled end, and has a control end C, a control end CB and a voltage-controlled end Vin. The trigger circuit is connected to the input control circuit, used to output the delay adjustment amount of the reference signal pulse width, and has an input end IN. The inverter circuit is connected to the trigger circuit, used to shape the waveform output by the trigger circuit, and has an output end OUT. C and CB are connected to LBL and LBLB of the storage array, the output of the input control circuit is connected to the trigger circuit, the output of the trigger circuit is connected to the input of the inverter, the input of the trigger circuit is a rectangular wave reference signal IN, and the output port of the inverter is the output port OUT of the voltage-controlled delay circuit.

[0028] The trigger circuit is a Schmitt trigger circuit, which includes NMOS tubes N1~N3 and PMOS tube P1. The gate of N1 is connected to the reference signal, the source is grounded, and the drain is connected to node X1; the gate of N2 is connected to the reference signal, the source is connected to node X1, and the drain is connected to node X2. The gate of N3 is connected to node X2, the source is connected to node X1, and the drain is connected to node X3. The gate of P1 is connected to the reference signal, the source is connected to node X2, and the drain is connected to the power supply VDD. Among them, the gates of N1, N2, and P1 serve as input terminals.

[0029] The input control circuit includes NMOS transistors N4 and N5. The gate of N4 serves as the control terminal 1 and is connected to the local bit line LBL, the source is connected to the node X3, and the drain serves as the voltage control terminal. The gate of N5 serves as the control terminal 2 and is connected to the local bit line LBLB, the source is grounded, and the drain is connected to the node X3. When the input control C is 0, the voltage-controlled delay circuit delays the time of the rising edge of the reference signal by t 0; When the input control C is 1, the voltage-controlled delay circuit delays the rising edge of the reference signal by t 0 The rising edge time of the reference signal is adjusted based on the above, and the adjustment strategy is: the delay time of the rising edge of the reference signal is linearly positively correlated with the voltage-controlled input Vin.

[0030] The inverter circuit includes an NMOS tube N6 and a PMOS tube P2. The gate of N6 is connected to the node X2, the source is grounded, and the drain is used as the output terminal. The gate of P2 is connected to the node X2, the source is used as the output terminal, and the drain is connected to the power supply VDD. That is, the drain of N6 is connected to the source of P2 and serves as the output terminal OUT.

[0031] The functions of the voltage-controlled delay unit are as follows: When C = 0 and CB = 1 (the inverse signal of C), the delay of the voltage-controlled delay circuit is not affected by the voltage value of the voltage-controlled port. After the rectangular wave is delayed by the voltage-controlled delay circuit, the delay of the rising edge is t 0 .

[0032] When C = 1 and CB = 0, there are the following situations: V in = V 00 When the rising edge delay is t 0 +0Δt, V in = V 01 When the rising edge delay is t 0 +1Δt, V in = V 10 When the rising edge delay is t 0 +2Δt, V in = V 11 When the rising edge delay is t 0 +3Δt.

[0033] That is, when the control terminal 1 signal is 0 and the control terminal 2 signal is 1, the delay 1 is a fixed value t 0 , which is not affected by the voltage at the voltage control terminal. When the signal at the control terminal 1 is 1 and the signal at the control terminal 2 is 0, the delay 2 is t 0 +kΔt. k is the binary value of the voltage-controlled terminal signal, Δt is the unit adjustment amount, and represents the minimum adjustment amount of the voltage-controlled delay circuit to the reference signal. The calculation array structure of this embodiment calculates the multiplication and accumulation calculation results of multiple bit input values ​​and multiple bit weight values ​​by delaying the number of unit adjustment amounts Δt contained in the adjustment amount.

[0034] Table 1 Function table of voltage-controlled delay unit

[0035] The quantization module is used to convert the pulse width of the reference signal output by any voltage-controlled delay circuit in the last column from a time analog quantity to a binary digital signal. The quantization module quantizes the pulse width of the reference signal output by any voltage-controlled delay circuit in the last column, and converts the pulse width from a time analog quantity to a binary digital signal. In this embodiment, the quantization module is a TDC quantization module, and the time-to-digital converter quantizes the rising edge delay time output by the last column of the array, converts the time quantity into a binary code, and the quantized data can be a multi-bit input and a multi-bit weighted multiplication and accumulation result of 32 columns (which can be changed as needed).

[0036] The digital shift adder module is used to amplify the quantization result of the high-bit voltage-controlled delay unit by four times and add it to the quantization result of the low-bit voltage-controlled delay unit to obtain the multiplication result of the single-bit input value and the single-bit weight value, and weightedly sum the multiplication results of different bits according to the weight value to obtain the multiplication and accumulation calculation result of the multi-bit input value and the multi-bit weight value. It is used to amplify the quantization result of the high-bit voltage-controlled delay unit by four times and add it to the quantization result of the corresponding low-bit voltage-controlled delay unit to obtain the multiplication calculation result of the corresponding bit input and weight. The digital shift adder module is also used to weightedly sum the multiplication calculation results of different bit inputs and weights according to the bit relationship to obtain the multiplication and accumulation calculation result of the multi-bit input value and the multi-bit weight value.

[0037] The local read-write module is used to transmit read-write signals through the horizontal word line HWL and the global bit line GBL / GBLB in the standard read-write mode to complete the read-write operation of the storage unit. The local read-write module includes the seventh NMOS tube N7 and the eighth NMOS tube N8. The gate of the seventh NMOS tube N7 is connected to the horizontal word line HWL, the drain is connected to the local bit line LBL, and the source is connected to the global bit line GBL. The gate of the eighth NMOS tube N8 is connected to the horizontal word line HWL, the drain is connected to the local bit line LBLB, and the source is connected to the global bit line GBLB. When the horizontal word line HWL and the word line WL of the n-th row storage unit are turned on, the write signal is first transmitted to the local bit line LBL / LBLB through the global bit line GBL / GBLB, and then the data is written into the n-th row storage unit, where n is an arbitrary number of rows of storage units.

[0038] This embodiment is used as an example to illustrate that the number of bit input values ​​and bit weight values ​​are both four, that is, a four-bit input IN is implemented. 3 IN 2 IN 1 IN 0 and a four-bit weight W 3 W 2 W 1 W 0The four groups of voltage-controlled delay units correspond to four bits respectively. Therefore, the four groups of voltage-controlled delay units can obtain the multiplication calculation results of the four-bit data input and the data weight, and then add the multiplication calculation results from the high bit to the low bit according to the weight ratio of 8 / 4 / 2 / 1 to obtain the four-bit input IN 3 IN 2 IN 1 IN 0 and a four-bit weight W 3 W 2 W 1 W 0 The multiplication result of .

[0039] The input signal column channel module is used to convert the four-bit input value IN 3 IN 2 IN 1 IN 0 Divided into high two-bit signal IN 3 IN 2 and the low two-bit signal IN 1 IN 0 , high two-bit signal IN 3 IN 2 and the low two-bit signal IN 1 IN 0 The output voltages of the input column channel 1 connected to the high-order voltage-controlled delay unit and the input column channel 2 connected to the low-order voltage-controlled delay unit are controlled respectively, and the voltage values ​​are determined by the corresponding two-bit signals.

[0040] See also Figure 6-13 , this embodiment can realize four-bit input IN 3 IN 2 IN 1 IN 0 and a four-bit weight W 3 W 2 W 1 W 0 The core is to characterize the calculation result by the rising edge delay adjustment of the reference signal. Since the rising edge delay adjustment can be accumulated, when a four-bit input IN is required 3 IN 2 IN 1 IN 0 and a four-bit weight W 3 W 2 W 1 W 0When performing multiplication and accumulation calculations, it is only necessary to combine multiple rows of multi-bit data in-memory calculation arrays in the form of columns, and use the signals output by each voltage-controlled delay circuit in the previous column as the input of the corresponding voltage-controlled delay circuit in the next column. The correspondence here means that they all correspond to the same bit and are all high-order delay circuits or low-order delay circuits. For example, there is a correspondence between the high-order delay circuit corresponding to the second bit in the previous column and the high-order delay circuit corresponding to the second bit in the next column. The calculation result of the bit in the previous column can then be passed to the calculation result of the corresponding bit in the next column. The multi-bit data in-memory calculation array provided in this embodiment supports the formation of a multi-bit data in-memory calculation array structure in a combined form to realize a four-bit input IN 3 IN 2 IN 1 IN 0 and a four-bit weight W 3 W 2 W 1 W 0 The multiplication and accumulation calculation can provide greater system-level reasoning accuracy and efficiency, solving the problem that the current non-volatile in-memory computing circuits usually only support in-memory multiplication and accumulation calculations of single-bit input and weight, and can only provide limited system-level reasoning accuracy.

[0041] exist Figure 8 In the example, VIN is 0, 175mv, 338mv, and 576mv, and the corresponding delays are 26p, 32p, 38p, and 44p. Fig. 9 In the example, INPUT = 503ps, t0 = 26ps, Δt = 6ps, OUT7 = 649ps OUT6 = 637ps, OUT5 =625ps, OUT4 = 637ps, OUT3 = 643ps, OUT2 = 643ps OUT1 = 631ps, OUT0 = 631ps, then: [(649-503)-4t0] / Δt=7; [(637-503)-4t0] / Δt=5; [(625-503)-4t0] / Δt=3; [(637-503)-4t0] / Δt=5; [(643-503)-4t0] / Δt=5 4t0-] / Δt=6; [(643-503)-4t0] / Δt=6; [(631-503)-4t0] / Δt=4; [(631-503)-4t0] / Δt=4. exist Figure 10-13 In the analysis, the stds were 2p, 2.5p, 3.1p, and 4.2p respectively. Monte Carlo ran about 100 times, and the fluctuation was less than 5ps, which was very small.

[0042] Exemplarily, the control inputs of the four voltage-controlled delay units corresponding to the same bit in the four columns are 1, 0, 1, and 1 respectively, and the input voltages of the four voltage-controlled delay units are as follows: A1 = V 11 , A2 = V 10 , A3 = V 00 , A4 = V 01 The theoretical quantization result of TDC is 3×1+2×0+0×1+1×1=4. Among them, after the first voltage-controlled delay circuit, the rising edge of the rectangular wave is delayed by t 0 + 3Δt; After the second voltage-controlled delay circuit, the rising edge of the rectangular wave is delayed by t 0 + 0Δt; after the third voltage-controlled delay circuit, the rising edge of the rectangular wave is delayed by t 0 + 0Δt; After the fourth voltage-controlled delay circuit, the rising edge of the rectangular wave is delayed by t 0 +Δt, the total delay is 4t 0 + 4Δt.

[0043] Simply convert the last column of rectangular wave rising delay into a binary number (the number of unit pulse delay adjustment Δt it contains), and then subtract the binary number set according to the initial rectangular wave rising edge time from the binary number to obtain the four columns of 2bit×1bit multiplication and accumulation results in the above example.

[0044] In the present embodiment, the multi-bit multiplication and accumulation process of the multi-bit data in-memory calculation array structure is explained, which illustrates that the multiplication calculation result in the previous column can be accumulated to the multiplication calculation result in the next column. Further, in the multi-bit data in-memory calculation array structure, the number of columns of the multi-bit data in-memory calculation array determines the maximum number of accumulation items that can be performed by the structure, and the number of rows of the multi-bit data in-memory calculation array determines the number of groups of four-bit multiplication and accumulation that can be performed simultaneously by the structure. For example, in the present embodiment, there are 4 multi-bit data in-memory calculation arrays in each column, indicating that 4 groups of multi-bit ratio multiplication and accumulation calculations can be performed in parallel, and the multi-bit data in-memory calculation array has a total of 32 columns, indicating that a maximum of 32 multi-bit ratio multiplication calculation results can be accumulated.

[0045] Compared with the existing in-memory computing array structure, the multi-bit in-memory computing array structure and electronic device of this embodiment have the following beneficial effects: The multi-bit in-memory calculation array structure characterizes the calculation result by using the rising edge delay adjustment amount of the reference signal. Since the rising edge delay adjustment amount can be accumulated, when it is necessary to realize the multi-bit input and multi-bit weight multi-addition calculation, it is only necessary to combine the multi-column multi-bit data in-memory calculation array in the form of rows, and use the signal output by each voltage-controlled delay circuit in the previous column as the input of the corresponding voltage-controlled delay circuit in the next column, so that the bit calculation result in the previous column can be passed to the calculation result of the corresponding bit in the next column. The number of columns of the voltage-controlled delay circuit determines the maximum number of accumulation items that can be performed by the structure, and also determines the number of multi-bit multiplication and accumulation groups that can be performed simultaneously by the structure. The calculation array structure can provide greater system-level reasoning accuracy and efficiency, and solves the problem that the current non-volatile in-memory calculation circuit usually only supports single-bit input and weight multiplication and accumulation in-memory calculation, and can only provide limited system-level reasoning accuracy.

[0046] Example 2 This embodiment provides a static random access memory (SRAM), which adopts the multi-bit in-memory calculation array structure in Example 1 to implement multi-bit input and multi-bit weight multiplication and accumulation calculation, and can implement four-bit input and four-bit weight multiplication and accumulation calculation.

[0047] Based on the multi-bit in-memory computing array structure in Example 1, the SRAM in-memory computing of this embodiment directly completes the multiplication and accumulation operations in the storage unit, reducing data movement and significantly reducing power consumption. SRAM can process the multiplication and accumulation operations of multiple inputs and weights at the same time, greatly improving computing efficiency, and is particularly suitable for application scenarios that require high throughput. The read and write speed of SRAM is much higher than that of DRAM and flash memory, and can achieve low-latency multiplication and accumulation calculations, which is suitable for applications with high real-time requirements, such as edge computing and Internet of Things devices. SRAM can be integrated with other computing units (such as CPU, GPU) on the same chip to form an efficient storage and computing architecture.

[0048] The SRAM of this embodiment is suitable for artificial intelligence and machine learning. The reasoning and training process of neural networks involves a large number of multiplication and accumulation operations, and SRAM in-memory computing can significantly accelerate these operations and improve overall performance. Multi-bit input and weights enable SRAM to support everything from simple linear models to complex deep neural networks. The in-memory computing of the SRAM of this embodiment reduces the complex interface between memory and processor in traditional computing architectures and simplifies system design. SRAM can reduce the overall cost and power consumption of the system by reducing data movement and simplifying the architecture.

[0049] Example 3 This embodiment provides an electronic device, which includes a memory and a processor. Among them, the memory includes a multi-bit in-memory computing array structure of embodiment 1. Compared with existing electronic devices, this electronic device can significantly improve computing efficiency, reduce power consumption, and support high-precision computing. It has broad application prospects in the fields of artificial intelligence, edge computing, etc. Although it faces some technical challenges, its advantages make it an important technical direction for in-memory computing.

[0050] Example 4 This embodiment provides a computer device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor. The memory is the static random access memory in the second embodiment.

[0051] The computer device can take various forms, including embedded chips or modules, or general-purpose data processing devices, such as smart terminals that can execute programs, tablet computers, laptop computers, desktop computers, rack servers, blade servers, tower servers or cabinet servers (including independent servers, or server clusters consisting of multiple servers), etc.

[0052] The computer device of this embodiment includes at least but is not limited to: a memory and a processor that can be connected to each other through a system bus. The memory (i.e., a readable storage medium) includes a flash memory, a hard disk, a multimedia card, a card-type memory (e.g., an SD or DX memory, etc.), a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, an optical disk, etc. In some embodiments, the memory may be an internal storage unit of a computer device, such as a hard disk or a memory of the computer device.

[0053] The processor may be a central processing unit (CPU), a graphics processing unit (GPU), a controller, a microcontroller, a microprocessor, or other data processing chips in some embodiments. The processor is generally used to control the overall operation of a computer device. In this embodiment, the processor is used to run program codes stored in a memory or process data.

[0054] Example 5 The present embodiment provides an artificial intelligence chip, which includes the multi-bit in-memory computing array structure in Embodiment 1, which has a standard read-write mode and a multi-bit multiplication-accumulation computing mode. In the standard read-write mode, the read and write operations of the data in the storage array can be realized. In the multi-bit multiplication-accumulation computing mode, the chip can realize the multiplication and accumulation of multiple bit input values ​​and multiple bit weight values. In this way, the chip can efficiently process artificial intelligence tasks, is not prone to problems of excessive energy consumption and delay, avoids the occurrence of a "storage wall", and greatly reduces data migration and memory access consumption. The artificial intelligence chip of this embodiment has multi-bit input (IN) and output (OUT) multiplication and accumulation, which is conducive to promoting the realization of artificial intelligence chips with high reasoning accuracy.

[0055] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-bit in-memory computing array structure, characterized in that: It includes: A plurality of voltage-controlled delay circuits are arranged in a rectangular shape, wherein a column corresponds to a row of bit input values, and a row corresponds to a column of bit weight values; each voltage-controlled delay circuit has an input terminal, an output terminal, a voltage-controlled terminal, and at least one control terminal; in each row, the output terminal of each voltage-controlled delay circuit is connected to the input terminal of the next column; The same control end of each column is connected and receives the corresponding bit weight value, and the voltage control end of each row is connected and receives the corresponding bit input value; when the control end signal is 0, the reference signal generates a delay of one through the corresponding input end and output end; when the control end signal is 1, the reference signal generates a delay of two through the corresponding input end and output end; the delay of two is the sum of the delay of one and the delay adjustment amount, and the delay adjustment amount is linearly positively correlated with the corresponding voltage control end signal; The delay adjustment amounts of the multiple columns of voltage-controlled delay circuits are accumulated to represent the multiplication and accumulation calculation results of the multiple bit input values ​​and the multiple bit weight values.

2. The multi-bit in-memory computing array structure according to claim 1, characterized in that: The computing array structure also includes a storage array; each voltage-controlled delay circuit includes a high-order voltage-controlled delay unit and a low-order voltage-controlled delay unit; each voltage-controlled delay unit has the input end, the output end, the voltage-controlled end, and two control ends with opposite signals: control end 1 and control end 2; in each column, the output end of the high-order voltage-controlled delay unit is connected to the input end of the high-order voltage-controlled delay unit in the next column, and the output end of the low-order voltage-controlled delay unit is connected to the input end of the low-order voltage-controlled delay unit in the next column; in each voltage-controlled delay circuit, the control end 1 of the high-order voltage-controlled delay unit is connected to the control end 1 of the low-order voltage-controlled delay unit, and the control end 2 of the high-order voltage-controlled delay unit is connected to the control end 2 of the low-order voltage-controlled delay unit; the control end 1 of each row of the voltage-controlled delay circuit is connected to the local bit line LBL of the storage array, and the control end 2 is connected to the local bit line LBLB; The calculation array structure implements multiplication and accumulation calculation in the following way: (1) The sum of four times the delay adjustment amount generated by the high-order voltage-controlled delay unit in each column and the delay adjustment amount generated by the low-order voltage-controlled delay unit is taken as the total adjustment amount; (2) taking the number of unit adjustment amounts contained in the total adjustment amount as the multiplication and accumulation result of the multiple bit input values ​​and the single bit weight value; (3) using multiple rows of voltage-controlled delay circuits corresponding to multiple bit weight values, adding multiple total adjustment amounts according to the weight ratio to obtain a multiplication result of multiple bit input values ​​and multiple bit weight values; (4) The total adjustment amount generated by combining multiple rows of voltage-controlled delay circuits in column form represents the multiplication and accumulation calculation results of multiple bit input values ​​and multiple bit weight values.

3. The multi-bit in-memory computing array structure as claimed in claim 2, characterized in that: Each voltage-controlled delay unit includes: An input control circuit, used for generating an input voltage analog quantity of the voltage control terminal according to signals of the control terminal 1 and the control terminal 2; A trigger circuit connected to the input control circuit and configured to output a delay adjustment amount of a reference signal pulse width according to an input terminal signal; An inverter circuit is connected to the trigger circuit, is used for shaping the waveform output by the trigger circuit, and has the output end.

4. The multi-bit in-memory computing array structure according to claim 3, characterized in that: The trigger circuit includes NMOS tubes N1-N3 and PMOS tube P1; the gate of N1 is connected to the reference signal, the source is grounded, and the drain is connected to node X1; the gate of N2 is connected to the reference signal, the source is connected to node X1, and the drain is connected to node X2; the gate of N3 is connected to node X2, the source is connected to node X1, and the drain is connected to node X3; the gate of P1 is connected to the reference signal, the source is connected to node X2, and the drain is connected to the power supply VDD; the gates of N1, N2, and P1 serve as the input terminals; The input control circuit includes NMOS transistors N4 and N5; the gate of N4 serves as the control terminal 1 and is connected to the local bit line LBL, the source is connected to the node X3, and the drain serves as the voltage control terminal; the gate of N5 serves as the control terminal 2 and is connected to the local bit line LBLB, the source is grounded, and the drain is connected to the node X3; The inverter circuit includes an NMOS tube N6 and a PMOS tube P2; the gate of N6 is connected to the node X2, the source is grounded, and the drain is used as the output terminal; the gate of P2 is connected to the node X2, the source is used as the output terminal, and the drain is connected to the power supply VDD.

5. The multi-bit in-memory computing array structure according to claim 2, characterized in that: The in-memory computing array structure also includes: A quantization module, which is used to convert the pulse width of the reference signal output by the last column of arbitrary voltage-controlled delay circuits from a time analog quantity into a binary digital signal; A digital shift adder module is used to amplify the quantization result of the high-bit voltage-controlled delay unit by four times and add it to the quantization result of the low-bit voltage-controlled delay unit to obtain the multiplication result of the single-bit input value and the single-bit weight value, and to weight the multiplication results of different bits according to the weights to obtain the multiplication and accumulation calculation results of the multi-bit input value and the multi-bit weight value.

6. The multi-bit in-memory computing array structure according to claim 2, characterized in that: The reference signal is a rectangular wave reference signal; when the control terminal 1 signal is 0 and the control terminal 2 signal is 1, the delay 1 is a fixed value t0 and is not affected by the voltage of the voltage control terminal; when the control terminal 1 signal is 1 and the control terminal 2 signal is 0, the delay 2 is t0 +kΔt; Among them, k is the binary value of the voltage-controlled end signal, Δt is the unit adjustment amount, which represents the minimum adjustment amount of the voltage-controlled delay circuit to the reference signal; the calculation array structure calculates the multiplication and accumulation results of multiple bit input values ​​and multiple bit weight values ​​through the number of unit adjustment amounts Δt contained in the delay adjustment amount.

7. The multi-bit in-memory computing array structure according to claim 2, characterized in that: The number of the bit input values ​​and the number of the bit weight values ​​are both four; The in-memory computing array structure also includes: An input signal column channel module is used to divide the four-bit input values ​​into a high-order two-bit signal and a low-order two-bit signal, and respectively control the output voltage of the input column channel one of the high-order voltage-controlled delay unit and the input column channel two of the low-order voltage-controlled delay unit, and the output voltage value is determined by the corresponding two-bit signal.

8. The multi-bit in-memory computing array structure according to claim 1, characterized in that: The in-memory computing array structure also includes: A storage array includes a plurality of storage cells arranged in a rectangular shape, which are used to store a plurality of bit weight values ​​and support switching between a standard read / write mode and a multi-bit multiplication-accumulation calculation mode; in the multi-bit multiplication-accumulation calculation mode, the calculation array structure realizes multiplication-accumulation calculation of a plurality of bit input values ​​and a plurality of bit weight values; a first storage node and a second storage node of each storage cell are respectively connected to a local bit line LBL and a local bit line LBLB.

9. The multi-bit in-memory computing array structure according to claim 8, characterized in that: The in-memory computing array structure also includes: A local read / write module is used to transmit read / write signals through a horizontal word line HWL and a global bit line GBL / GBLB in a standard read / write mode to complete the read / write operations on the storage unit; the local read / write module includes NMOS tubes N7 and N8; the gate of N7 is connected to the horizontal word line HWL, the drain is connected to a local bit line LBL, and the source is connected to the global bit line GBL; the gate of N8 is connected to the horizontal word line HWL, the drain is connected to a local bit line LBLB, and the source is connected to the global bit line GBLB; when the horizontal word line HWL and the word line WL of the n-th row storage unit are turned on, the write signal is first transmitted to the local bit line LBL / LBLB through the global bit line GBL / GBLB, and then the data is written into the n-th row storage unit, where n is an arbitrary number of rows of storage units.

10. An electronic device comprising a memory and a processor; characterized in that: The memory includes a multi-bit in-memory computing array structure as described in any one of claims 1-9.

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