A simulation simplification method for a reflow soldering packaging process

Abstract

The present invention provides a simulation simplification method for a reflow soldering packaging process, comprising the following steps: obtaining parameters of multiple components in a packaging structure and establishing a geometric model corresponding to each component; establishing an equivalent geometric model corresponding to each component; demarcating an equivalent region according to the density in the equivalent geometric model, thermally equivalenting parts within the equivalent region and generating an equivalent material model corresponding to the equivalent geometric model; establishing an equivalent simplified geometric model according to the equivalent geometric model and the corresponding equivalent material model; and establishing a simulation model according to multiple equivalent simplified geometric models. The present invention solves the problems of low simulation efficiency and large resource consumption existing in the simulation method for the reflow soldering packaging process in the prior art.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic packaging technology, and particularly to a method for simulating and simplifying a reflow soldering packaging process. Background Art

[0002] In the current field of electronic packaging, with the continuous increase in the integration degree of integrated circuits, the 2.5D packaging technology has been widely used due to its unique advantages. However, as a key step in the 2.5D packaging, the quality prediction of the reflow soldering process faces many challenges.

[0003] Traditional methods for predicting the quality of the reflow soldering process mainly rely on experience and actual process experiments. However, with the increasing complexity of the packaging structure and the sharp rise in scale, the accuracy and completeness of this method are gradually not guaranteed. Many uncertain factors in the experimental process and the limitation of experimental costs make it difficult to comprehensively and accurately predict the quality of the reflow soldering process.

[0004] To overcome this problem, a method based on finite element simulation has emerged. This method can perform numerical simulation of the entire process of the reflow soldering process, thereby providing a relatively accurate simulation prediction. However, with the continuous increase in the packaging scale and complexity, the simulation time and resource consumption also increase. For a 2.5D packaging with a complex structure and large scale, relying on detailed modeling to achieve reflow soldering process simulation will consume a large amount of time and computing resources, and it is difficult to integrate into the fast-paced process line iteration. At the same time, this also increases the cost of computing resources, which has an adverse impact on the production efficiency of enterprises.

[0005] In addition, the existing methods for simplifying the reflow soldering of models and materials in 2.5D packaging are not complete. Most methods only optimize the simulation process flow and do not involve the simplification and equivalence of detailed models. This results in the need to process a large amount of detailed information during the simulation, reducing the simulation efficiency. In addition, in the existing equivalent methods, the metal wiring layer of the redistribution layer on the interposer is generally simply equivalent to a copper plate, while ignoring the PI (Polyimide) dielectric material between the wirings. Although this simplification method reduces the complexity of the model, it will also cause deviations in stress simulation and warpage simulation compared with the actual process results, affecting the accuracy of the simulation.

[0006] All in all, the simulation methods for the reflow soldering packaging process in the prior art have the problems of low simulation efficiency and large resource consumption. Summary of the Invention

[0007] The purpose of the present invention is to provide a method for simulating and simplifying a reflow soldering packaging process to solve the problems of low simulation efficiency and large resource consumption in the simulation methods for the reflow soldering packaging process in the prior art.

[0008] To achieve the above object of the present invention, an embodiment of the present invention provides a simulation simplification method for a reflow soldering packaging process, which includes the following steps:

[0009] Obtain the parameters of multiple components in the packaging structure and establish a geometric model corresponding to each component;

[0010] Establish an equivalent geometric model corresponding to each component;

[0011] Define an equivalent region according to the density in the equivalent geometric model, thermally equivalent the parts within the equivalent region, and generate an equivalent material model corresponding to the equivalent geometric model;

[0012] Establish an equivalent simplified geometric model based on the equivalent geometric model and the corresponding equivalent material model;

[0013] Establish a simulation model based on multiple equivalent simplified geometric models.

[0014] As a further improvement of an embodiment of the present invention, in the process of "obtaining the parameters of multiple components in the packaging structure and establishing a geometric model corresponding to each component", the geometric model is established by Space Claim software.

[0015] As a further improvement of an embodiment of the present invention, the multiple components include: EMC encapsulant, chip, ABF substrate, solder joint, silicon interposer, and redistribution layer.

[0016] As a further improvement of an embodiment of the present invention, the process of establishing an equivalent geometric model corresponding to each component specifically includes:

[0017] When establishing an equivalent geometric model corresponding to the silicon interposer, ignore the barrier layer on the sidewall of the through-silicon via, equivalent the through-silicon via to a single copper conductor structure, and divide the silicon interposer into regions according to the through-silicon via density.

[0018] As a further improvement of an embodiment of the present invention, the process of establishing an equivalent geometric model corresponding to each component further includes:

[0019] When establishing an equivalent geometric model corresponding to the redistribution layer, divide the equivalent region based on the layout information according to the wiring density, and each region includes metal wires and filling media.

[0020] As a further improvement of an embodiment of the present invention, the solder joints include C2 solder joints and C4 solder joints, the chips include a main control chip, an HBM chip, and a dummy layer chip, and the process of establishing an equivalent geometric model corresponding to each component further includes:

[0021] When establishing an equivalent geometric model corresponding to the C2 solder joints and C4 solder joints, the C2 solder joint array and the C4 solder joint array are respectively equivalent to a hexahedron cubic block model. Among them, the C2 solder joints connect the main control chip, the HBM chip, the dummy layer chip and the silicon interposer, and the C4 solder joints connect the silicon interposer and the ABF substrate.

[0022] As a further improvement of an embodiment of the present invention, wherein the specific method of material thermal equivalence includes:

[0023] When performing material thermal equivalence on the silicon interposer, the through-silicon vias and the surrounding silicon materials are regarded as an integral component. Based on the elastic mechanics method, the longitudinal Young's modulus, the transverse Young's modulus, the longitudinal Poisson's ratio, the transverse Poisson's ratio and the thermal expansion coefficient are calculated. Then, material thermal equivalence is performed according to the foregoing parameters.

[0024] As a further improvement of an embodiment of the present invention, wherein the specific method of material thermal equivalence includes:

[0025] When performing material thermal equivalence on the redistribution layer, according to the volume ratio of the metal wire and the dielectric material, an orthotropic composite material model is used to calculate the equivalent elastic modulus, Poisson's ratio and thermal expansion coefficient. Then, material thermal equivalence is performed according to the foregoing parameters.

[0026] As a further improvement of an embodiment of the present invention, wherein the specific method of material thermal equivalence includes:

[0027] When performing material thermal equivalence on the solder joints, based on the volume fraction of the solder joints and the filling material, the equivalent Young's modulus, Poisson's ratio and thermal expansion coefficient are calculated by the linear weighting method. Then, material thermal equivalence is performed according to the foregoing parameters.

[0028] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0029] The simulation model established by the thermal parameters determined by determining the equivalent material region through density can meet the calculation accuracy of reflow soldering and reduce the resource occupation of the model. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a flowchart of a simulation simplification method for a reflow soldering packaging process provided by an embodiment of the present invention;

[0031] Figure 2 It is a schematic diagram of the simplified geometric model partition of the interposer in an embodiment of the present invention;

[0032] Figure 3 It is a schematic diagram of the simplified geometric model partition of the small solder joints in an embodiment of the present invention;

[0033] Figure 4It is a comparison diagram of the warpage simulation results between the simulation model (b) based on the equivalent simplified geometric model and the detailed modeling model (a) in an embodiment of the present invention. Detailed implementation manners

[0034] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the drawings and in combination with the embodiments.

[0035] It should be pointed out that unless otherwise specified, all technical and scientific terms used in this application have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs.

[0036] In the present invention, unless otherwise stated, the orientation words such as "upper, lower, top, bottom" are usually in the direction shown in the drawings, or in the vertical, perpendicular or gravitational direction of the component itself; similarly, for the convenience of understanding and description, "inner, outer" refer to the inner and outer of the contour of each component itself, but the above orientation words do not limit the present invention.

[0037] In order to solve the problems of low simulation efficiency and large resource consumption in the simulation method of the reflow soldering packaging process in the prior art. The present invention provides a simulation simplification method for the reflow soldering packaging process.

[0038] The present invention will be further described in detail below with reference to the drawings and specific embodiments. Embodiment

[0039] As Figure 1 shown, a simulation simplification method for the reflow soldering packaging process provided by an embodiment of the present invention includes the following steps:

[0040] S1: Obtain the parameters of multiple components in the packaging structure and establish a geometric model corresponding to each component;

[0041] S2: Establish an equivalent geometric model corresponding to each component;

[0042] S3: Define an equivalent region according to the density in the equivalent geometric model, perform material thermal equivalence on the part within the equivalent region, and generate an equivalent material model corresponding to the equivalent geometric model;

[0043] S4: Establish an equivalent simplified geometric model according to the equivalent geometric model and the corresponding equivalent material model;

[0044] S5: Establish a simulation model according to multiple equivalent simplified geometric models.

[0045] In this embodiment, the reflow package is a 2.5D package, an advanced heterogeneous integration technology that lies between traditional 2D planar packaging and 3D stacked packaging. Its core feature is the use of silicon interposers to achieve high-density interconnection of multiple chips (such as logic chips and memory chips), while utilizing through-silicon vias (TSVs) and redistribution layers (RDLs) to optimize signal transmission efficiency and power consumption.

[0046] It should be noted that in this invention, the "geometric model" is the physical model of an object in space, also known as the original model. The "equivalent geometric model" considers only the density partitioning within the geometric model. The "equivalent material model" performs material equivalence within this partitioned area.

[0047] In the present invention, the basic principle of the simulation simplification method of the reflow soldering packaging process is: first, a packaging structure is selected, which usually includes multiple components, and the parameters of the multiple components in the packaging structure are analyzed. The purpose of analyzing the parameters is to establish a geometric model of each component; then, an equivalent geometric model corresponding to each component is established, and the equivalent geometric model of each component is the division of the density of the component on its geometric model; then, equivalent areas are delineated according to the density in the equivalent geometric model, and different equivalent areas are divided into different densities; the part within each equivalent area is subjected to material thermal equivalence and an equivalent material model corresponding to the equivalent geometric model is generated; then, an equivalent simplified geometric model is established based on the equivalent geometric model and the corresponding equivalent material model; finally, a simulation model is established based on multiple equivalent simplified geometric models.

[0048] Establishment of equivalent geometric model:

[0049] To create an equivalent simplified geometric model of each component in the 2.5D package structure, the SpaceClaim software in Ansys Workbench is first used to perform 3D modeling of the 2.5D package structure to be simulated based on the layout information. Layout information refers to the physical layout data generated during the chip and package design phase, describing the precise geometry, spatial position, material properties, and connectivity of each component in the package structure.

[0050] The components selected for the geometry model creation include: EMC molding compound, chips (including the main control chip, dummy layer chip, and HBM chip), ABF substrate, solder balls (C2 and C4 solder joints), silicon interposer, and redistribution layer. Name the created geometry model for easy reference in subsequent operations.

[0051] In the process of establishing the equivalent geometric model, the following situations are included:

[0052] 1) For the through-silicon vias (TSVs) in the interposer, since the thickness of the sidewall barrier layer (silicon dioxide) is much larger than the silicon material and the surrounded copper fill in terms of size difference, this component is ignored in the modeling of the material equivalent model and the equivalent geometric model, and the TSV is treated as a single copper conductor. The silicon interposer is divided into regions according to the TSV density, and then the material equivalent treatment is carried out for each divided region;

[0053] 2) For the redistribution layer, the redistribution layer (RDL) in the 2.5D package is a key component on the interposer and is used to achieve high-density electrical interconnection between the chip and the substrate. The RDL is composed of multiple layers of metal wires and dielectric materials, and a fine wiring network is formed through photolithography and electroplating processes. Due to the complexity of the wiring, the wiring layer is generally equivalent to a single-layer metal. In this example, to ensure the accuracy of the simulation, according to the layout information, the metal wirings with different densities are divided into the same region (including metal and filled resin dielectric), and then the material equivalent is carried out for each region;

[0054] 3) For the C2 and C4 solder ball arrays (BGAs) located above and below the interposer, since the purpose of the reflow soldering process is to form solder joints, no volume equivalent and equivalent geometric model region division are carried out for the solder joints. However, due to the complex structure of the 2.5D package in this example and the inclusion of tens of thousands of solder balls of different sizes, directly establishing a completely detailed model according to the layout will greatly increase the mesh division density and complexity of the finite element simulation. Although it can accurately characterize the stress and deformation of the solder joints in the actual process, it cannot balance the computational resources and time costs. Therefore, in this embodiment, the solder joint structure is equivalent to a hexahedron cubic block model, and the parts it connects are: the main control chip - interposer, HBM - interposer, dummy layer - interposer, interposer - ABF substrate.

[0055] Establishment of the equivalent material model and the equivalent simplified geometric model of each component of the package structure:

[0056] 1) For the material equivalent of the silicon interposer, the mechanical analysis method of the characteristics of composite materials is adopted. The through-silicon vias (copper) and the surrounding silicon material are regarded as an overall component equivalent material model. This overall equivalent material model is regarded as an isotropic material, and the equivalent Young's modulus and Poisson's ratio of the divided regions are obtained through the method of elasticity. According to the analysis method of elasticity, the equivalent longitudinal Young's modulus E V is:

[0057] ;

[0058] Among them, E Cu and E Si are the elastic moduli of copper and silicon respectively, v Cu and v Si are the Poisson's ratios of copper and silicon respectively, V Cu and V Si are the volume ratios of copper and silicon respectively.

[0059] The equivalent transverse Young's modulus E l is:

[0060] ;

[0061] Among them:

[0062] ;

[0063] ;

[0064] ;

[0065] .

[0066] The equivalent longitudinal Poisson's ratio v 12 is:

[0067] .

[0068] The equivalent transverse Poisson's ratio v 23 is:

[0069] .

[0070] The equivalent shear modulus is:

[0071] .

[0072] The longitudinal equivalent thermal expansion coefficient α1 is:

[0073] .

[0074] The transverse equivalent thermal expansion coefficient α2 is:

[0075] .

[0076] Based on the parameters obtained from the above calculations, the thermal equivalence of the silicon interposer material can be carried out and an equivalent material model can be established. Then, based on the equivalent material model of the interposer and the equivalent geometric model established previously, a simplified geometric model of the interposer can be established.

[0077] A schematic diagram of the partition of the simplified geometric model of the interposer can be referred to Figure 2 as shown.

[0078] 2) For the equivalence of the redistribution layer, since the redistribution layer consists of copper transmission lines and the PI surrounding them, the redistribution layer cannot be equivalent to a single metal or dielectric. In this embodiment, the representative volume fraction equivalence method is adopted to perform the equivalence of this layer, and the equivalent mechanical properties of the composite material with orthotropic characteristics are obtained. The equivalent formula based on the composite material theory is expressed as follows:

[0079] ;

[0080] ;

[0081] ;

[0082] ;

[0083] ;

[0084] ;

[0085] Among them, V m and V f respectively represent the volume percentages of PID and copper; E m , v m and α m respectively represent the elastic modulus, Poisson's ratio and coefficient of thermal expansion (CTE) of PID; the symbols E1, v 12 and α1 respectively represent the equivalent elastic modulus, Poisson's ratio and coefficient of thermal expansion of the RDL (redistribution layer) in the thickness direction; while E2, v 23 and α2 represent the equivalent elastic modulus, Poisson's ratio and coefficient of thermal expansion of the RDL in the plane direction. E f1 , ν 12 and α f1 are respectively the elastic modulus, Poisson's ratio and coefficient of thermal expansion of the copper wire in the direction perpendicular to the upper surface of the RDL; while E f2 , ν 23 and α f2 represent the elastic modulus, Poisson's ratio and coefficient of thermal expansion of the copper wire in the transverse direction. Compared with the volume percentage method, the representative volume method considered in this example can obtain more accurate substitute mechanical properties.

[0086] Based on the parameters obtained from the above calculations, the thermal equivalence of the material of the redistribution layer can be performed and an equivalent material model can be established. Then, according to the equivalent material model of the redistribution layer and the equivalent geometric model established previously, a simplified geometric model of the redistribution layer can be established.

[0087] 3) For the equivalence of the solder joint layer, since the interposer and the chips (main control chip, HBM, dummy chip) are bonded through small solder joints (C2 bumps), their volume and proportion in the underfill layer are relatively small. According to process experience, the peak solder joint stress and stress concentration points are mainly concentrated in the area near the chip edge. Therefore, a reasonable equivalence method is used to equivalently transform the specified area inside the chip into a uniform material layer, while the solder joints in the area near the chip edge are still modeled using a simplified six-sided cube. For the large solder joints (C4 bumps) under the interposer, due to their large volume and relatively sparse distribution, they are also modeled using a simplified six-sided cube without equivalent transformation into a uniform material layer. The method for equivalently transforming the small solder joint into a uniform material layer in this embodiment is as follows:

[0088] The equivalent Young's modulus (E) of the small solder joint fill layer is expressed as:

[0089] ;

[0090] where E f and c f are the Young's modulus and volume fraction of the small solder joint respectively; E m and c m are the Young's modulus and volume fraction of the filler in the small solder joint fill layer respectively;

[0091] The equivalent Poisson's ratio (v) of the small solder joint fill layer is expressed as:

[0092] ;

[0093] where K f and v f are the bulk modulus and Poisson's ratio of the small solder joint respectively, and K m and v m are the bulk modulus and Poisson's ratio of the filler in the small solder joint fill layer respectively;

[0094] The equivalent coefficient of thermal expansion (α) of the small solder joint fill layer is expressed as:

[0095] ;

[0096] where α f and α m are the coefficients of thermal expansion of the small solder joint and the filler in the small solder joint fill layer respectively.

[0097] Based on the parameters calculated above, the thermal material equivalence of the large and small solder joints can be carried out to establish an equivalent material model. Then, based on the equivalent material models of the large and small solder joints and the previously established equivalent geometric model, a simplified geometric model of the large and small solder joints can be established.

[0098] Data Output and Analysis Processing:

[0099] 1) When creating an equivalent model, the regions will be divided according to density. The regional division of the interposer layer is as shown in Figure 2 and the regional division of the small solder joints on the interposer layer is as shown in Figure 3 .

[0100] 2) After defining the equivalent regions according to density, the thermal parameters of the materials in the equivalent regions are equivalent. According to the material equivalent methods for the interposer layer, the redistribution layer, and the small solder joint regions mentioned above, the equivalent Young's modulus, Poisson's ratio, and coefficient of thermal expansion of each region are obtained. Taking the TSV equivalence of the interposer layer as an example, the above equivalent method is used for regional material equivalence. Since the TSV density is the same in each region, all sub-blocks are equivalent to the same material. The equivalent material results and the thermal parameter properties of the original materials are shown in Table 1 below:

[0101] Table 1 Thermal Parameter Coefficients Equivalent for Each Region

[0102]

[0103] It can be seen from this that since the volume fraction of copper is very small and silicon dioxide is ignored, after material equivalence, the material parameters of the copper-silicon material are very close.

[0104] 3) Perform steady-state thermal simulation and stress warpage simulation of the reflow soldering process on the detailed model of BGA in the 2.5D package that has undergone material equivalence simplification and geometric model simplification. The boundary conditions are set the same as those of the equivalent model. The warpage of the solder joints of the two models is as shown in Figure 4 . (a) is the reflow soldering simulation warpage distribution map after detailed modeling of the 2.5D package structure, and (b) is the simulation warpage distribution map of the package structure after replacing it with the equivalent simplified model mentioned in this embodiment. By comparison, it can be seen that the warpage distribution trends before and after equivalence are the same, and the maximum warpage range is concentrated at the junction of the main control chip and the HBM chip. Through the comparison of the stress equivalence situation and the warpage situation, it can be directly seen that the effect of the equivalent model is good. Therefore, the error between the simulation model results determined by the thermal parameters determined by the density to determine the equivalent material region and the thermal parameters of the detailed structure meets the requirements, fully meets the calculation accuracy of reflow soldering, and greatly simplifies the detailed model.

[0105] In summary, the embodiments of the present invention achieve the following technical effects:

[0106] The simulation model established by the thermal parameters determined by the density to determine the equivalent material region can meet the calculation accuracy of reflow soldering and reduce the resource occupation of the model.

[0107] Obviously, the embodiments described above are only some of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative efforts shall fall within the protection scope of the present invention.

[0108] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly dictates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they specify the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0109] It should be noted that the terms "first", "second", etc. in the description and claims of the present application and the above drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order different from those illustrated or described herein.

[0110] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A simplified simulation method for a reflow soldering packaging process, characterized in that: The following steps are involved: Obtaining parameters of multiple components in a package structure and establishing a geometric model corresponding to each component; Establish an equivalent geometric model corresponding to each component; Delineating an equivalent region according to the density in the equivalent geometric model, performing material thermal equivalence on the parts within the equivalent region, and generating an equivalent material model corresponding to the equivalent geometric model; Establish an equivalent simplified geometric model based on the equivalent geometric model and the corresponding equivalent material model; Establish a simulation model based on multiple equivalent simplified geometric models; The process of establishing an equivalent geometric model corresponding to each component specifically includes: When establishing an equivalent geometric model corresponding to the silicon interposer, the TSV sidewall barrier layer is ignored, the TSV is equivalent to a single copper conductor structure, and the silicon interposer is divided into regions according to the TSV density; When establishing an equivalent geometric model corresponding to the redistribution layer, the equivalent regions are divided according to the wiring density based on the layout information, and each region contains metal conductors and filling media; When establishing an equivalent geometric model corresponding to the solder joint, the solder joint array is equivalent to a hexahedral cubic block model.

2. The simulation simplification method for the reflow soldering packaging process according to claim 1, characterized in that: In the process of "obtaining the parameters of multiple components in the package structure and establishing a geometric model corresponding to each component", the geometric model is established using Space Claim software.

3. The simulation simplification method of the reflow soldering packaging process according to claim 2, characterized in that: The multiple components include: EMC plastic packaging material, chip, ABF substrate, solder joints, silicon interposer, and redistribution layer.

4. The simulation simplification method for the reflow soldering packaging process according to claim 3, characterized in that: The solder joints include C2 solder joints and C4 solder joints, the chips include a main control chip, an HBM chip, and a dummy layer chip, and the process of establishing an equivalent geometric model corresponding to each component further includes: When establishing the equivalent geometric models corresponding to the C2 solder joints and the C4 solder joints, the C2 solder joint and the C4 solder joint arrays are respectively equivalent to hexahedral cubic block models, where the C2 solder joints connect the main control chip, HBM chip, dummy layer chip and silicon interposer, and the C4 solder joints connect the silicon interposer and the ABF substrate.

5. The simulation simplification method for reflow soldering packaging process according to claim 1, characterized in that: The specific method of thermal equivalence of the materials includes: When performing material thermal equivalence on the silicon interposer, the through-silicon via and the surrounding silicon material are regarded as an integral component. The longitudinal Young's modulus, transverse Young's modulus, longitudinal Poisson's ratio, transverse Poisson's ratio and thermal expansion coefficient are calculated based on the elastic mechanics method. Then, the material thermal equivalence is performed based on the above parameters.

6. The simulation simplification method for reflow soldering packaging process according to claim 1, characterized in that: The specific method of thermal equivalence of the materials includes: When performing material thermal equivalence on the redistribution layer, the equivalent elastic modulus, Poisson's ratio and thermal expansion coefficient are calculated using an orthotropic composite material model based on the volume ratio of the metal conductor and the dielectric material. Then, the material thermal equivalence is performed based on the aforementioned parameters.

7. The simulation simplification method for reflow soldering packaging process according to claim 1, characterized in that: The specific method of thermal equivalence of the materials includes: When performing material thermal equivalence on solder joints, the equivalent Young's modulus, Poisson's ratio, and thermal expansion coefficient are calculated using a linear weighted method based on the volume fraction of the solder joint and the filler material. Then, material thermal equivalence is performed based on the aforementioned parameters.

Images