Circuit diagram analysis method for automatically generating analog circuit netlist

Abstract

The invention discloses a circuit diagram analysis method for automatically generating an analog circuit netlist, and the method comprises the steps: carrying out the recognition of an input to-be-processed circuit diagram through a target detection model, and outputting the type and position of each component in the circuit diagram; removing components from the circuit diagram to be processed to obtain a circuit diagram without components; a representative template picture of each component is called, the matching degree of the template picture and the identified component area is calculated, and the pin function and the position coordinate of each identified component are determined; identifying connecting line segments in the circuit diagram without components by adopting a connected domain detection method, and judging to obtain a really connected circuit network in the circuit diagram in combination with connecting points; and matching the pin ports of the components with the circuit network endpoints one by one, generating a netlist file of the circuit diagram to be processed, and checking and outputting the netlist file. According to the method, circuit schematic diagrams of different styles can be processed, and the accuracy of circuit netlist conversion is remarkably improved.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic design automation (EDA), and in particular relates to a circuit diagram parsing method for automatically generating an analog circuit netlist. Background Art

[0002] As the core of electronic design, the circuit diagram directly shows the layout of components in the circuit and their connection relationship, while the netlist converts the circuit diagram into a standardized data format that can be processed by subsequent EDA tools. In modern electronic design, the accuracy of the netlist is crucial to multiple links such as design optimization, simulation analysis, layout and routing, and fault diagnosis. An accurate netlist can provide real component parameters and connection relationships for circuit simulation, allowing engineers to discover problems in the design in advance, thereby avoiding expensive physical experiments and debugging. With the netlist, designers can use automated layout and routing tools to design circuit boards to ensure that the circuit design matches the actual production process. The netlist is also used for subsequent electrical rule checking (ERC) and design rule checking (DRC) to help designers ensure that the electrical performance and physical layout of the circuit meet the design specifications and reduce potential manufacturing defects. Furthermore, the automatic generation of the netlist can improve design efficiency, reduce errors and inconsistencies caused by manual operations, and make design work more efficient and reliable. In summary, the conversion of circuit diagram to netlist is not only a key step in the electronic design process, but also provides strong support for subsequent simulation, layout and routing, optimization, and debugging tasks, thereby greatly improving the accuracy and efficiency of the design and having important practical application value.

[0003] In traditional methods, designers usually need to manually draw circuit schematics and define the connection relationships and parameters of components according to the requirements of simulation software. This process is cumbersome and error-prone, especially in complex circuit designs, where manually generated netlists often cause errors due to inconsistencies or omissions, which increases debugging time and reduces design efficiency.

[0004] In the existing design process, designers usually need to manually draw the schematic diagram of the circuit in the simulation software and further define the connection relationship and parameters of the components. This process is not only cumbersome, but also prone to additional debugging and modification work due to input errors. In the design of complex analog circuits, there are many types of components and complex connection relationships. These manually generated netlists are prone to omissions or logical errors, which seriously affect the design efficiency and the accuracy of the simulation results. In addition, different simulation software have different requirements for netlist formats, which forces designers to draw circuit diagrams separately for each software. This incompatibility not only greatly increases the workload of designers, but also causes duplication of work and unnecessary computing overhead.

[0005] At present, there are some tools that can assist in generating netlists. These tools can improve the convenience of netlist generation to a certain extent, but there are still many limitations. Most tools are based on a graphical interface and rely on users to manually adjust the layout and connection of components. They cannot directly process hand-drawn or existing analog circuit diagram images. At the same time, traditional methods do not provide sufficient support for complex circuits, especially when it comes to circuits involving active devices such as amplifiers and transistors, the degree of automation is low. For large-scale unstructured analog circuit diagram data, the processing capabilities of existing methods are also significantly insufficient. This not only restricts the further development of automated design, but also leads to a large amount of potential data value not being fully explored and utilized.

[0006] The invention with the publication number CN114417778B discloses a method for obtaining a circuit netlist by means of node electrical characteristics, obtaining the electrical characteristics of each pin on the circuit board under test in advance; randomly selecting a pin in the empty pin set, comparing the electrical characteristics with all other pins in the empty pin set, determining the pins of the same type whose electrical characteristic error is less than a specified preset value, and constructing a node netlist based on the pins of the same type; performing a connection test on the pins in the node netlist, eliminating the pins that are not actually connected according to the test results, and obtaining the actual netlist of the node; deleting all the pins of the node from the empty pin set; randomly selecting a pin in the remaining empty pin set to start obtaining the next node netlist, repeating this process until the empty pin set is empty, and obtaining the netlist of the entire circuit board. However, the invention mainly introduces the pin electrical characteristics as constraints to shorten the generation time of the circuit netlist, but still cannot solve the problem of generating electric meter files for complex circuits or large-scale unstructured analog circuit diagram data.

[0007] The invention with publication number CN102323964B discloses a method for processing digital circuit netlist data, including: extracting netlist data from a planar circuit diagram; the netlist data includes attribute information of each component and attribute information of each wire net in the planar circuit diagram; the attribute information of the component includes: component identification, component type; the attribute information of the wire net includes wire net identification; according to the correspondence between the component type and the standard component type, each component type in the netlist data is replaced with the standard component type corresponding to the component type. The invention can simplify the planar circuit diagram while keeping the logical function unchanged by processing the netlist data; it does not involve the problem of generating electric meter files for complex circuits or large-scale unstructured analog circuit diagram data.

[0008] Therefore, developing an intelligent tool to realize the automatic conversion of analog circuit diagrams to netlists has important technical value and application prospects. Summary of the invention

[0009] The present invention discloses a circuit diagram parsing method for automatically generating an analog circuit netlist, which can solve the problems of low efficiency and poor robustness in identifying circuit diagram line segments using a combination of Hough transform and OCR, as well as complexity and low accuracy in using logic to judge component pin ports in the existing analog circuit diagram to circuit netlist conversion technology, and effectively improves the accuracy of generating a circuit netlist.

[0010] A circuit diagram parsing method for automatically generating an analog circuit netlist, the method comprising the following steps:

[0011] S1, annotate the original circuit diagram, clarify the category of each component in the circuit diagram and its position in the image, and generate a training data set;

[0012] S2, training the neural network model using the training data set to construct a target detection model; the target detection model recognizes the input circuit diagram to be processed and outputs the type and position of each component in the circuit diagram;

[0013] S3, based on the result recognized by the target detection model, removing components from the circuit diagram to be processed to obtain a circuit diagram without components;

[0014] S4, retrieve a representative template image of each component, calculate the matching degree between the template image and the identified component area, and determine the pin function and position coordinates of each identified component;

[0015] S5, using a connected domain detection method to identify the connecting line segments in the circuit diagram without components, and combining the connection points to determine the truly connected circuit network in the circuit diagram;

[0016] S6, matching the pin ports of each component with the circuit network endpoints one by one, generating a netlist file of the circuit diagram to be processed, and verifying and outputting the netlist file.

[0017] Step S1 further comprises the following steps:

[0018] Label the original circuit diagram, clarify the category of each component in the circuit diagram and its position in the image, and generate the initial data set;

[0019] Enhance the initial dataset by cropping, scaling, and rotating it;

[0020] The data in the enhanced initial dataset is adjusted to the standard format required by the target detection model to generate a training dataset.

[0021] As a preferred example, in step S2, a YOLOv11 neural network model is trained using a training data set to construct a target detection model, and the output result of the target detection model includes the category of each component and the coordinates of the corresponding bounding box.

[0022] Step S3 further includes the following steps:

[0023] According to the coordinates of the bounding box output by the target detection model, the corresponding area is extracted and filled or deleted, and the components contained in the circuit diagram are removed to obtain a circuit diagram without components.

[0024] Step S4 further includes the following steps:

[0025] S41, taking any recognized component image as a target area, selecting a representative component template image according to the component type of the circuit schematic, and marking the pin position of the component in the template image;

[0026] S42, gradually rotate the template image, mirror and scale the template image at the same time, and use the normalized correlation coefficient cv2.TM_CCOEFF_NORMED in the computer image processing software library opencv to evaluate the similarity between the template image and the target area with different template transformation parameters:

[0027]

[0028] Where R(x,y) represents the matching degree between the template image T and the target area I at the position (x,y), T′(x′,y′) represents the pixel value of the template image T at the position (x′,y′), and I′(x+x′,y+y′) represents the pixel value of the target area I at the position (x+x′,y+y′); the template transformation parameters include the rotation angle, mirror state and scaling factor;

[0029] S43, using the cv2.minMaxLoc function in opencv to find the template image corresponding to the best match and record the template transformation parameters with the highest match; combining the predefined port coordinates in the component template image and the template transformation parameters, calculating the pin port positions corresponding to the components in the target area;

[0030] S44, repeating steps S41 to S43 until the pin port function and coordinates of each identified component are determined.

[0031] As a preferred example, in step S42, the rotation interval angle is set according to the symmetry of the components.

[0032] As a preferred example, in step S41, for components with irregular shapes or markings, multiple component template images with different initial rotation angles and scaling ratios are set and selected, corresponding to various placement methods of the components.

[0033] Step S5 further comprises:

[0034] Through breadth-first traversal, all connected domains in the circuit diagram without components are identified, and combined with the connection point judgment algorithm, the network with intersections but not actually connected in the circuit diagram is corrected, and the valid connection points in the circuit are identified to ensure that only truly connected circuit networks are classified with the same number. According to the identification results, the corresponding circuit network digital number is modified, and finally a unique number is generated for all unconnected circuit networks; at the same time, the endpoint coordinates of each circuit network are recorded and marked with the digital number of the circuit network to which it belongs.

[0035] Step S6 further comprises:

[0036] Calculate the Euclidean distance between the pin of each component in the circuit diagram and the circuit network endpoint, match the component pin with the circuit network endpoint closest to establish the circuit connection relationship; the calculation formula of the Euclidean distance is:

[0037]

[0038] Where d is the Euclidean distance between two points, (x1, y1) and (x2, y2) are the coordinates of the component pins and the circuit network endpoints respectively;

[0039] Convert the established circuit connection relationship into the circuit netlist file, and verify the integrity and accuracy of the netlist file.

[0040] As a preferred example, in step S6, it is checked whether the netlist file covers all components and their pins in the circuit diagram and the connectivity of the circuit network is confirmed to determine whether the netlist file is complete and accurate.

[0041] The beneficial effects of the present invention are:

[0042] First, the circuit diagram parsing method of the present invention for automatically generating an analog circuit netlist can directly parse an existing circuit diagram, automatically identify the components and their connection relationships therein, generate a netlist file that meets the requirements, and minimize human intervention in the process, thereby providing new support for complex analog circuit design and simulation, and effectively helping electronic design automation develop in a more efficient and intelligent direction.

[0043] Second, the circuit diagram analysis method for automatically generating analog circuit netlists of the present invention can not only accurately identify the types of circuit components and the functions of component pins, but also accurately distinguish and mark circuit networks. The overall algorithm is highly adaptable and can handle circuit schematics of different styles, significantly improving the accuracy of circuit netlist conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A flow chart of a circuit diagram analysis method for automatically generating a simulation circuit netlist according to the present invention;

[0045] Figure 2 This is a flow chart of template matching for multiple angles and multiple templates in the present invention. DETAILED DESCRIPTION

[0046] The following examples will enable those skilled in the art to more fully understand the present invention, but are not intended to limit the present invention in any way.

[0047] The present invention discloses a circuit diagram analysis method for automatically generating an analog circuit netlist, the method comprising the following steps:

[0048] S1, annotate the original circuit diagram, clarify the category of each component in the circuit diagram and its position in the image, and generate a training data set;

[0049] S2, training the neural network model using the training data set to construct a target detection model; the target detection model recognizes the input circuit diagram to be processed and outputs the type and position of each component in the circuit diagram;

[0050] S3, based on the result recognized by the target detection model, removing components from the circuit diagram to be processed to obtain a circuit diagram without components;

[0051] S4, retrieve a representative template image of each component, calculate the matching degree between the template image and the identified component area, and determine the pin function and position coordinates of each identified component;

[0052] S5, using a connected domain detection method to identify the connecting line segments in the circuit diagram without components, and combining the connection points to determine the truly connected circuit network in the circuit diagram;

[0053] S6, matching the pin ports of each component with the circuit network endpoints one by one, generating a netlist file of the circuit diagram to be processed, and verifying and outputting the netlist file.

[0054] like Figure 1 As shown, the circuit diagram analysis method of this embodiment specifically includes the following steps:

[0055] Step S1: Build and train a target detection model.

[0056] This embodiment uses the YOLOv11 neural network model to build a target detection model. In order to train the YOLOv11 neural network model to achieve accurate recognition of components in the circuit diagram, a large number of original circuit diagrams are first annotated one by one to clarify the category of each component and its position in the image. In order to further improve the robustness and adaptability of the model, this embodiment introduces a variety of data enhancement techniques, such as cropping, scaling, rotation and other operations, to expand the diversity of the data set. In addition, brightness adjustment and noise addition are also performed to simulate complex image scenes. After data cleaning and enhancement, these labeled data are converted into the standard format required for YOLOv11 neural network model training, a standardized data set is generated, and it is input into the YOLOv11 neural network model for training. By optimizing training hyperparameters, such as learning rate, batch size, etc., the recognition accuracy of the model is further improved. Finally, the fully trained target detection model is evaluated and verified to ensure that its performance meets the needs of practical applications.

[0057] Step S2: Use the trained YOLOv11 neural network model to identify components in the circuit diagram and obtain the type and location information of each component in the circuit diagram. The output results of the YOLOv11 target detection model include the category of each component, the coordinates of the bounding box, etc., where the component types include common analog circuit components such as resistors, capacitors, diodes, transistors, MOS tubes, and op amps. By parsing these output results, the location information of all components in the circuit diagram can be obtained, thereby locating the position and type of each component in the circuit diagram.

[0058] Step S3, based on the result of YOLOv11 neural network model recognition, the component area in the circuit diagram can be removed by image processing technology to generate an image containing only the circuit network connection relationship. According to the bounding box output by the YOLOv11 neural network model, the corresponding area is extracted and filled or deleted, and finally a circuit diagram with components removed is obtained. The image processed in this way can provide the required image data for subsequent circuit network connection relationship identification and processing, help identify the lines and nodes in the circuit, and further generate a circuit netlist.

[0059] Step S4: Use the multi-angle template matching algorithm to mark the pin functions of components. The overall process is as follows: Figure 2As shown. First, take any identified component image as the target area, select a representative component template image according to the component type of the circuit schematic, and accurately mark the position of each component pin in the template image. On this basis, a multi-angle matching template algorithm is used to match the component template image with the highest similarity and identify the component pins. Specifically, the template is gradually rotated and mirrored to improve the robustness of the matching. In addition, the template image is scaled to adapt to components of different sizes in the circuit diagram. During the matching process, the normalized correlation coefficient cv2.TM_CCOEFF_NORMED in the computer image processing software library opencv can be used to evaluate the similarity between the template and the target area, and the matching degree between the two is calculated. The formula for the normalized correlation coefficient is as follows:

[0060]

[0061] Where R(x,y) represents the matching degree between template T and target area I at position (x,y), T′(x′,y′) represents the pixel value of template T; I′(x+x′,y+y′) represents the pixel value of target area I at position (x+x′,y+y′).

[0062] In order to improve the robustness of the algorithm, the template image will be gradually rotated and mirrored to ensure that it can match components at different angles and orientations in the circuit diagram. The rotation process is usually carried out step by step from 0° to 360°, and the rotation interval can be simplified according to the symmetry of the components. For example, for components with strong symmetry, such as capacitors and resistors, it is sufficient to rotate 90° each time, instead of rotating every degree, which can significantly improve the operating efficiency of the algorithm. In order to further improve the matching accuracy, the template image is also mirrored horizontally during the rotation process. This is because in the circuit diagram, the components may be mirrored and flipped. Mirroring can enhance the adaptability of the algorithm and ensure that components in different directions can be recognized.

[0063] For example, for components with special shapes or irregular markings, multiple templates are designed, corresponding to the possible typical placement of these components. Each template corresponds to a different initial angle and scaling ratio to ensure that the template can match components of various placements in the circuit diagram.

[0064] In all matching attempts, the best matching position is found through the cv2.minMaxLoc function in OpenCV, and the template transformation parameters with the highest matching degree are recorded. According to the template type, rotation angle and mirror state of the matching result, combined with the predefined port coordinates in the template, the corresponding port position in the target image is accurately calculated.

[0065] Based on the above method, the identified components in the circuit diagram are matched one by one to determine the pin function and coordinates of each component.

[0066] Step S5: Using a connected domain detection algorithm, all connected domains in the circuit diagram without circuit components are identified through breadth-first traversal, and combined with a connection point judgment algorithm, some networks in the circuit diagram that have intersections but are actually disconnected are corrected, valid connection points in the circuit are identified, and the corresponding circuit network numbers are modified to ensure accurate identification of all circuit connections and avoid missed judgments and misjudgments. Finally, a unique circuit network number is generated for each disconnected line segment.

[0067] Step S6: Establish a circuit connection relationship based on the identified circuit connection points and component ports. Specifically, the Euclidean distance formula is used to calculate the distance between the pin and the connection point, and the pin coordinates of each component in the circuit diagram are matched with the circuit network. The distance calculation formula is as follows:

[0068]

[0069] Where d is the Euclidean distance between two points, (x1, y1) and (x2, y2) are the coordinates of the component pins and the circuit network endpoints, respectively.

[0070] Match the nearest component pins with the circuit network endpoints, convert all recorded circuit connection relationships into a circuit netlist format file that meets the requirements, and verify the integrity and accuracy of the circuit netlist. Check whether the netlist covers all components and their pins in the circuit diagram and confirm the connectivity of the circuit network to avoid missed judgments or misjudgments; after passing the verification, generate the final netlist file.

[0071] In summary, the circuit diagram parsing method based on multi-angle template matching and connected domain detection algorithm involved in this embodiment has the following advantages compared to the prior art: by utilizing the powerful image recognition capability of multi-angle template matching, it is possible to more accurately identify components and their pin functions in the circuit diagram, and adapt to components of different placement angles and sizes. At the same time, the connected domain detection algorithm combined with the connection point judgment technology can effectively identify the effective connection relationship in the circuit, avoiding misjudgment and missed judgment. Finally, by generating a unique number for each circuit network, the network connection relationship in the circuit diagram is accurately recorded, thereby generating a circuit netlist. This method ensures the accurate identification of circuit connections and provides reliable data support for subsequent circuit design, simulation and optimization.

[0072] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. A circuit diagram analysis method for automatically generating an analog circuit netlist, characterized in that: The method comprises the following steps: S1, annotate the original circuit diagram, clarify the category of each component in the circuit diagram and its position in the image, and generate a training data set; S2, training the neural network model using the training data set to construct a target detection model; the target detection model recognizes the input circuit diagram to be processed and outputs the type and position of each component in the circuit diagram; S3, based on the result recognized by the target detection model, removing components from the circuit diagram to be processed to obtain a circuit diagram without components; S4, retrieve a representative template image of each component, calculate the matching degree between the template image and the identified component area, and determine the pin function and position coordinates of each identified component; S5, using a connected domain detection method to identify the connecting line segments in the circuit diagram without components, and combining the connection points to determine the truly connected circuit network in the circuit diagram; S6, matching the pin ports of each component with the circuit network endpoints one by one, generating a netlist file of the circuit diagram to be processed, and verifying and outputting the netlist file.

2. The circuit diagram analysis method for automatically generating a simulation circuit netlist according to claim 1, characterized in that: Step S1 further comprises the following steps: Label the original circuit diagram, clarify the category of each component in the circuit diagram and its position in the image, and generate the initial data set; Enhance the initial dataset by cropping, scaling, and rotating it; The data in the enhanced initial dataset is adjusted to the standard format required by the target detection model to generate a training dataset.

3. The circuit diagram analysis method for automatically generating a simulation circuit netlist according to claim 1, characterized in that: In step S2, the YOLOv11 neural network model is trained using the training data set to construct a target detection model. The output result of the target detection model includes the category of each component and the coordinates of the corresponding bounding box.

4. The circuit diagram analysis method for automatically generating a simulation circuit netlist according to claim 1, characterized in that: Step S3 further includes the following steps: According to the coordinates of the bounding box output by the target detection model, the corresponding area is extracted and filled or deleted, and the components contained in the circuit diagram are removed to obtain a circuit diagram without components.

5. The circuit diagram analysis method for automatically generating an analog circuit netlist according to claim 1, characterized in that: Step S4 further includes the following steps: S41, taking any recognized component image as a target area, selecting a representative component template image according to the component type of the circuit schematic, and marking the pin position of the component in the template image; S42, gradually rotate the template image, mirror and scale the template image at the same time, and use the normalized correlation coefficient cv2.TM_CCOEFF_NORMED in the computer image processing software library opencv to evaluate the similarity between the template image and the target area with different template transformation parameters: Where R(x,y) represents the matching degree between the template image T and the target area I at the position (x,y), T′(x′,y′) represents the pixel value of the template image T at the position (x′,y′), and I′(x+x′,y+y′) represents the pixel value of the target area I at the position (x+x′,y+y′); the template transformation parameters include the rotation angle, mirror state and scaling factor; S43, using the cv2.minMaxLoc function in opencv to find the template image corresponding to the best match and record the template transformation parameters with the highest match; combining the predefined port coordinates in the component template image and the template transformation parameters, calculating the pin port positions corresponding to the components in the target area; S44, repeating steps S41 to S43 until the pin port function and coordinates of each identified component are determined.

6. The circuit diagram analysis method for automatically generating a simulation circuit netlist according to claim 5, characterized in that: In step S42, the rotation interval angle is set according to the symmetry of the components.

7. The circuit diagram analysis method for automatically generating a simulation circuit netlist according to claim 5, characterized in that: In step S41, for components with irregular shapes or markings, multiple component template images with different initial rotation angles and scaling ratios are set and selected, corresponding to multiple placement methods of the components.

8. The circuit diagram analysis method for automatically generating a simulation circuit netlist according to claim 1, characterized in that: Step S5 further comprises: Through breadth-first traversal, all connected domains in the circuit diagram without components are identified, and combined with the connection point judgment algorithm, the network with intersections but not actually connected in the circuit diagram is corrected, the valid connection points in the circuit are identified, and the truly connected circuit networks are classified with the same number. According to the identification results, the corresponding circuit network digital number is modified, and finally a unique number is generated for all unconnected circuit networks; the endpoint coordinates of each circuit network are recorded and marked with the digital number of the circuit network to which it belongs.

9. The circuit diagram analysis method for automatically generating a simulation circuit netlist according to claim 1, characterized in that: Step S6 further comprises: Calculate the Euclidean distance between the pin of each component in the circuit diagram and the circuit network endpoint, match the component pin with the circuit network endpoint closest to establish the circuit connection relationship; the calculation formula of the Euclidean distance is: Where d is the Euclidean distance between two points, (x1, y1) and (x2, y2) are the coordinates of the component pins and the circuit network endpoints respectively; Convert the established circuit connection relationship into the circuit netlist file, and verify the integrity and accuracy of the netlist file.

10. The circuit diagram analysis method for automatically generating a simulation circuit netlist according to claim 1, characterized in that: In step S6, it is checked whether the netlist file covers all components and their pins in the circuit diagram and the connectivity of the circuit network is confirmed to determine whether the netlist file is complete and accurate.

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