Critical path delay optimization method and system based on logic depth driving graph division

Abstract

The invention discloses a critical path delay optimization method and system based on logic depth driving graph division. The method comprises the following steps: 1) obtaining a logic netlist of an integrated circuit; 2) constructing a critical path logic cone based on the logic netlist; 3) screening out a sub-circuit with an optimization value from the logic cone through a logic depth driving graph division method; 4) simplifying the sub-circuit with the optimization value through a sub-graph logic reconstruction method to obtain a reconstruction logic unit with better time delay; 5) screening the reconstruction logic units corresponding to the sub-graphs of which the reuse rates are greater than a preset value, and replacing the reconstruction logic units into the initial logic netlist to obtain an optimized logic netlist; 6) carrying out equivalence test on the initial logic netlist and the optimized logic netlist, and 7) carrying out delay evaluation on the logic netlist passing the equivalence test, and if the evaluation is passed, obtaining a final reconstruction logic unit and logic netlist. The method has the advantages of low cost, effective reduction of key path delay and the like.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of microprocessor design, and in particular to a critical path delay optimization method and system based on logic depth drive graph partitioning. Background Art

[0002] Vigorously promoting independent research, design and manufacturing of high-performance microprocessors is a key measure to enhance the competitiveness of the integrated circuit (IC) industry and effectively reduce external dependence. It is of great significance to scientific and technological progress, economic development, national defense security and other aspects. At present, large-scale complex microprocessor design is usually implemented through semi-custom design methods based on commercial standard cell libraries using electronic design automation (EDA) tools. This design method can greatly shorten the complex IC design process and accelerate the time to market, but it often fails to achieve the optimal circuit configuration. Especially under the constraint of higher main frequency, there are still a large number of critical paths with timing violations in the logic netlist obtained under the harsh constraints of commercial EDA tools. When the critical path delay exceeds the set clock cycle constraint, the design main frequency of the microprocessor will be reduced, thereby limiting the further improvement of its performance. The critical path delay is a key factor that restricts the performance and main frequency improvement of the microprocessor, and directly determines the maximum operating frequency and data processing rate of the processor. Therefore, optimizing the critical path delay is of great significance in the design of high-performance microprocessors.

[0003] Critical path delay optimization is a multifaceted, multi-level complex process involving multiple links in microprocessor design. After the optimization is completed in the design stage by applying pipeline insertion, retiming, logic replication, logic optimization and other methods, there may still be room for further optimization of the design. Since the front-end design and optimization iterations require a lot of resources, the iteration cost is high and the number of iterations is limited, so the back-end optimization technology is used to effectively reduce the delay of the critical path without changing the original design. It is an important means to improve performance at a limited cost. The current back-end optimization is usually performed for a specific design and may not be suitable for subsequent design iterations or expansions, which limits the scalability and reusability of the design. In addition, the optimization at this stage is limited by the standard cell library and often cannot achieve the optimal circuit configuration. Summary of the invention

[0004] In view of the technical problems existing in the prior art, the present invention provides a critical path delay optimization method and system based on logic depth drive graph partitioning, which can effectively reduce the critical path delay.

[0005] In order to solve the above technical problems, the technical solution proposed by the present invention is: A critical path delay optimization method based on logic depth drive graph partitioning comprises the following steps: 1) Obtain the logic netlist, given standard cell library and timing constraints in the integrated circuit semi-custom design process; 2) Analyze the characteristics of the critical path in the logic netlist and construct the critical path logic cone based on the given standard cell library and timing constraints; 3) Screen out sub-circuits with optimization value from the critical path logic cone through the logic depth driven graph partitioning method; 4) Simplify the sub-circuit with optimization value through the sub-graph logic reconstruction method to obtain the reconstructed logic unit with better delay; 5) Filter the reconstructed logic units corresponding to the subgraphs whose reuse rate is greater than the preset value and replace them into the initial logic netlist to obtain the optimized logic netlist; 6) Perform an equivalence test on the initial logic netlist and the optimized logic netlist; if they pass the equivalence test, proceed to the next step; 7) Perform delay evaluation on the logic netlist that passes the equivalence test. If the evaluation passes, the final reconstructed logic unit and optimized logic netlist are obtained.

[0006] Preferably, in step 2), the direction of constructing the critical path logic cone is exactly opposite to the signal transmission direction; first, the end point of the critical path is obtained from the logic netlist; then, the end point is gradually traced back to the output port of the timing unit and stopped. In this process, the module hierarchy and the internal connections of the module are not retained, only the standard unit and its port information, as well as the logical relationship between them are retained; by identifying the driving nodes corresponding to all input ports of the node, all standard units from the end point of the critical path to the timing unit and their connection relationship can be obtained in turn; in the constructed logic cone, each obtained standard unit is regarded as a node; wherein the timing unit is a trigger, static random access memory or IP in the process library, and its output is defined as the starting point of the logic cone.

[0007] Preferably, in step 2), in the critical path logic cone, the logic depth of the standard unit corresponding to the node is used as its weight, stored in the form of a weighted directed acyclic graph, and visualized; each node contains one or more logic gates, and the logic depth of the node is the number of logic gates on the longest path from the input to the output of the node.

[0008] Preferably, the specific steps of step 3) are: Initialize the subgraph structure: treat each node in the logic cone as an independent minimum subgraph and calculate the logic depth of each subgraph; the logic depth of a subgraph is the logic depth of the longest path from the input port to the output port of the subgraph; Search for all possible subgraph pairs that can be merged; the subgraph pairs that can be merged must satisfy the following conditions: the merged graph meets the port number constraint, and the logical depth of the merged new graph is greater than the logical depth of the subgraph before merging. Calculate the logical depth increment: For each pair of subgraphs, calculate the logical depth increment after merging; the larger the logical depth increment, the greater the merging benefit; if the logical depth increment is less than or equal to 0, it means that this merging method is not desirable; the logical depth increment is the difference between the logical depth of the new graph after merging and the average logical depth of the subgraph pair before merging; Select the best merge: For all identified subgraph pairs that may be merged, find the subgraph pair with the largest logical depth increment after merging, and merge them to obtain a new subgraph; use the new subgraph to replace the merged subgraph and update the subgraph structure; The merging operation is iterated until there are no more merged subgraph pairs, and the final partitioning result is obtained.

[0009] Preferably, the specific steps of step 4) are: Identify ports: Identify the input ports and output ports of the subgraph to ensure that the port configuration of the reconstruction unit is consistent with the subgraph; Logic simplification: Implement two-level logic simplification for each output port of the subgraph; specifically, identify and merge the implied terms to find the minimum set of prime implied terms, and then obtain the minimum SOP expression of the circuit, implement two-level logic simplification to reduce the logic level of the circuit; Negation logic extraction: Based on the two-level logic simplification, all the negation logic is extracted and simplified upward, and finally a new optimized reconstructed logic unit is obtained.

[0010] Preferably, in step 5), the specific steps of screening the reconstruction logic units corresponding to the subgraphs whose reuse rates are greater than a preset value are: First, the nodes in the logic cone are topologically sorted into a linear sequence of logical precedence; Then, based on the sorting results, matching is performed in sequence in the form of a graph, and the parts with the same graph structure as the subgraph are matched in the logic cone; units with the same functions are represented by nodes in the same form, and the lines between the nodes represent the connection between the units, and the arrows are used to indicate the data flow direction, while the buffer unit is directly represented in the form of a line instead of a node; The reuse rate of each sub-graph is counted and sorted in turn, and the sub-graph with a reuse rate greater than a preset value is selected to obtain the corresponding reconstruction logic unit.

[0011] Preferably, the specific process of the equivalence test in step 6) is: Taking the initial logic netlist as the reference model, and under the premise that other irrelevant conditions remain the same, verify the equivalence of the initial logic netlist and the optimized logic netlist. When the logical functions corresponding to the two netlists are equivalent, it is proved that the optimized logic cone is equivalent to the original logic cone, and the equivalence test passes.

[0012] Preferably, in step 7), when performing delay evaluation on the logic netlist that has passed the equivalence check, a quantitative analysis is performed using the change in logic depth on the critical path before and after optimization as a key indicator for evaluation.

[0013] Preferably, the specific process of quantitatively analyzing the change in logic depth on the critical path before and after optimization as the key indicator of evaluation is as follows: Divide the logical cone G into k non-overlapping subgraphs G1, G2, . . . , Gk; where k is a positive integer; Select subgraphs with larger logic depths for logic reconstruction, and use the reconstructed subgraphs to replace the original subgraphs in the logic cone G. Finally, the logic cone G is optimized to a new logic cone G′, and the logic depth corresponding to G′ is h(G′); The optimization effect is evaluated by calculating the change in the graph logic depth before and after optimization; the evaluation function is defined as: ∆h=h(G)-h(G'); When the logic depth of the logic cone after optimization is less than the logic depth of the logic cone before optimization, that is, the ∆h value is greater than 0, the evaluation passes.

[0014] The present invention also discloses a critical path delay optimization system based on logic depth driven graph partitioning, comprising an interconnected memory and a processor, wherein a computer program is stored on the memory, and when the computer program is run by the processor, the steps of the method described above are executed.

[0015] Compared with the prior art, the advantages of the present invention are: The critical path delay optimization method based on logic depth driven graph partitioning of the present invention deeply analyzes the characteristics of the critical path in the microprocessor logic netlist, accurately identifies the sub-circuit structure with optimization value from the logic netlist of the IC semi-custom design process through the logic depth driven graph partitioning method, and optimizes the identified complex circuit structure by logic reconstruction to obtain a reconstruction unit with better delay. By fully custom designing a small number of reconstruction units and replacing them in the logic netlist, the logic depth and the number of units on the critical path are optimized under the premise of consistent logic functions. Under the premise of ensuring consistent logic functions, the critical path delay is effectively reduced, so as to achieve improved microprocessor performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1A flowchart of a critical path delay optimization method based on logic depth drive graph partitioning provided in an embodiment of the present invention.

[0017] Figure 2 A flowchart of a logic depth driven critical path graph partitioning method provided in an embodiment of the present invention.

[0018] Figure 3 A flowchart of a subgraph logic reconstruction method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments.

[0020] like Figure 1 As shown, the critical path delay optimization method based on logic depth drive graph partitioning of an embodiment of the present invention includes the steps of: 1) Obtain the logic netlist, given standard cell library and timing constraints in the semi-custom design process of integrated circuit (IC); 2) Analyze the characteristics of the critical path in the logic netlist and construct the critical path logic cone based on the given standard cell library and timing constraints; 3) Screen out sub-circuits with optimization value from the critical path logic cone through the logic depth driven graph partitioning method; 4) Simplify the sub-circuit with optimization value through the sub-graph logic reconstruction method to obtain the reconstructed logic unit with better delay; 5) Filter the reconstructed logic units corresponding to the subgraphs whose reuse rate is greater than the preset value and replace them into the initial logic netlist to obtain the optimized logic netlist; 6) Perform an equivalence test on the initial logic netlist and the optimized logic netlist; if they pass the equivalence test, proceed to the next step; 7) Perform delay evaluation on the logic netlist that passes the equivalence test. If the evaluation passes, the final reconstructed logic unit and optimized logic netlist are obtained.

[0021] In step 1), IC semi-custom design completes the circuit design by using pre-designed standard cells. In the logic synthesis step, an optimized gate-level netlist is generated based on the optimized Boolean description, the characteristics of the standard cell library, and the set constraints. Under the constraints of higher main frequency, there are still a large number of critical paths with timing violations in the logic netlist obtained under the strict constraints of commercial EDA tools. The logic netlist in the IC semi-custom design process, as well as the corresponding commercial standard cell library and the given timing constraints are obtained for subsequent optimization processing.

[0022] In step 2), the necessary design information is extracted from the library file corresponding to the selected standard cell library and the netlist file corresponding to the selected design; the characteristics of the critical path in the logic netlist are analyzed, and the critical path and its associated parts in the netlist are abstracted into a critical path logic cone, without retaining the module hierarchy and the internal connections of the module, only the standard cell and its port information, and the logical relationship between them. In the constructed logic cone, each standard cell is regarded as a node; a weight system is introduced, and the logic depth of the standard cell corresponding to the node is used as its weight, and it is stored in the form of a weighted directed acyclic graph (DAG); finally, the constructed critical path logic cone is visualized.

[0023] In step 3), the critical path characteristics of the circuit are accurately analyzed based on the critical path logic cone, and the sub-circuit with optimization value is identified by graph partitioning the critical path, and the critical path partitioning problem is modeled as a directed graph partition selection problem. The logic depth-driven critical path graph partitioning method uses the logic depth as the partitioning basis, iteratively selects the partition with the largest logic depth increment, and accurately identifies the sub-circuit with greater optimization value.

[0024] In step 4), first identify and record the port information of the sub-circuit with optimization value to ensure that the port configuration of the reconstructed unit is consistent with the original circuit; then use two-level logic simplification to reduce the logic level of the circuit; at the same time, consider the complementary characteristics of CMOS circuits and extract the inversion logic upward; finally, obtain a reconstructed logic unit with delay optimization.

[0025] In step 5), the identified subcircuits with optimization value are matched in the netlist, and the reuse of the subcircuits in the netlist is quantified; the reuse rate of each subgraph is counted in turn and sorted accordingly; some subgraphs with higher reuse rates are selected according to different design requirements, and their corresponding reconstructed logic units are obtained; and the reconstructed logic units are used to replace the corresponding structures in the netlist.

[0026] In step 6), the initial logic netlist and the logic netlist after the logic optimization are used for equivalence test, and the initial logic netlist is used as the reference model to verify the equivalence of the logic before and after reconstruction. When the logic functions corresponding to the two netlists are equivalent, it proves that the optimized design is equivalent to the original design, and verifies the accuracy of the matching and replacement operations; if the logic functions corresponding to the two netlists are not equivalent, it proves that the matching and replacement operations are incorrect, and replacement and verification must be performed again until the equivalence test passes.

[0027] In step 7), the delay of the standard cell and the line delay between cells are not fixed values, but an interval, which is difficult to directly quantify and analyze. The present invention uses the logic depth on the critical path as the key indicator to measure the circuit delay, establishes an evaluation model, and evaluates the delay optimization effect by comparing the changes in the logic depth on the critical path before and after optimization.

[0028] The critical path delay optimization method based on logic depth driven graph partitioning of the present invention first constructs a critical path logic cone based on a logic netlist in an IC semi-custom design process in combination with a given standard cell library and timing constraints, thereby converting the originally complex netlist critical path problem into a directed graph problem that is more intuitive and easy to handle; secondly, the critical path logic cone is directly partitioned using logic depth as a partitioning driver, and the critical path partitioning problem is modeled as a directed graph partitioning selection problem to identify sub-circuits with greater optimization value; then, the identified complex logic circuit is reconstructed by sub-graph logic, and the logic depth of the design is reduced upward by using two-level logic simplification and negation logic to obtain a delay optimized reconstruction unit; a small number of general reconstruction units are selected for matching and replacement in the designed netlist to achieve critical path delay optimization; finally, a model is established to evaluate the optimization effect, and the circuit delay is measured by the logic depth on the critical path, and the change in the critical path logic depth before and after optimization is used as a key indicator for evaluating the delay optimization effect.

[0029] The present invention deeply analyzes the characteristics of the critical path in the logic netlist of the microprocessor, and accurately identifies the sub-circuit structure with optimization value from the logic netlist of the IC semi-custom design process through a logic depth-driven graph partitioning method, and optimizes the identified complex circuit structure using logic reconstruction to obtain a reconstruction unit with better delay. By fully custom designing a small number of reconstruction units and replacing them in the logic netlist, the logic depth and the number of units on the critical path are optimized under the premise of consistent logic functions. Under the premise of ensuring consistent logic functions, the critical path delay is effectively reduced, so as to achieve improved microprocessor performance.

[0030] The logic depth-driven critical path graph partitioning method of the present invention models the critical path partitioning problem as a directed acyclic graph partitioning selection problem, takes the logic depth as the partitioning basis, and performs graph partitioning on the critical path logic cone to more accurately identify sub-circuits with greater optimization value, thereby providing options for circuit reconstruction optimization.

[0031] The subgraph logic reconstruction method of the present invention uses two-level logic simplification and negation logic upward extraction to simplify the identified complex logic circuits with optimization value, reduces the delay by reducing the logic depth and the number of logic gates in the circuit, and finally obtains a reconstruction unit with optimized delay.

[0032] The present invention is based on the implementation of the logic netlist in the IC semi-custom design process, giving full play to the respective advantages of semi-custom design and full-custom design, and can be easily embedded in the conventional IC design logic synthesis process, and provides an effective means for optimizing the critical path delay at a limited cost.

[0033] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0034] like Figure 1 As shown, the critical path delay optimization method based on logic depth drive graph partitioning provided by the embodiment of the present invention includes the following steps: 1) Obtain the logic netlist, given standard cell library and timing constraints in the IC semi-custom design process; 2) In-depth analysis of the characteristics of the critical path in the logic netlist, combined with the given standard cell library and timing constraints, construct the critical path logic cone and store it in the form of a weighted directed acyclic graph; 3) Configure reasonable partitioning constraints, use logic depth as the partitioning driver, and use the graph partitioning method to screen out a number of sub-circuits with optimization value from the logic cone; 4) The logic of each sub-circuit generated by the division is reconstructed through two-level logic simplification and negation logic extraction. By reducing the logic depth of the sub-graph, a reconstructed logic unit with better delay is obtained; 5) Comprehensively consider multiple factors such as reuse rate and optimization value, select a small number of reconstructed logic units, and replace them in the initial logic netlist; 6) Use the initial logic netlist as a reference model to verify the equivalence of the logic before and after reconstruction; if the equivalence test passes, proceed to the next step, otherwise return to step 5); 7) Using the delay evaluation model, the change in the critical path logic depth before and after optimization is used as the key indicator to evaluate the delay optimization effect. The delay evaluation is performed on the logically equivalent reconstructed logic to determine whether the optimization goal is met. If so, a batch of reconstructed logic units with customized value and the optimized logic netlist are obtained; if not, jump to step 3).

[0035] In practical applications, the method of the present invention can be used to perform multiple cycles of optimization on the logic netlist when necessary to reduce the critical path delay as much as possible.

[0036] Specifically, step 1) includes: obtaining a logic netlist and corresponding critical path information in the IC semi-custom design process; obtaining a standard cell library corresponding to the logic netlist, and extracting basic information such as ports and logic functions of each standard cell; and obtaining given timing constraints.

[0037] In step 2), the specific process of constructing the critical path logic cone based on the logic netlist includes: In order to solve the problems of complex netlist information and difficulty in processing cross-level modules, and enhance the readability and optimization efficiency of the netlist, the present invention uses an abstract processing method to construct a critical path logic cone based on a given logic netlist. By introducing a new data structure, redundant information such as the hierarchical relationship and connection details between modules is ignored, and only the connection relationship between each standard unit is retained while maintaining the accuracy of the circuit design, so as to improve the efficiency of subsequent optimization processing.

[0038] The present invention abstracts the critical path and its associated parts in the netlist into a weighted directed acyclic graph, so that the originally complex netlist critical path problem is transformed into a directed graph problem that is more intuitive and easy to handle, providing a new perspective and method for circuit design optimization. The weighted directed acyclic graph DAG is used to represent the circuit structure of the critical path and its associated parts in the netlist, the vertices represent the instances of the standard units in the circuit, the directed edges between the vertices represent the connection relationship between the units, and the direction of the arrow represents the direction of signal transmission between the units.

[0039] The direction of constructing the critical path logic cone of the present invention is exactly opposite to the direction of signal transmission. First, the end points of the critical path are obtained from the netlist; then, the output ports of the timing units are gradually traced back from these end points to stop. In this process, the module hierarchy and the internal connections of the modules are not retained, only the standard units and their port information, as well as the logical relationship between them are retained. By identifying the driving nodes corresponding to all input ports of the nodes, all standard units from the end point of the critical path to the timing unit and their connection relationships can be obtained in turn. In the constructed logic cone, each obtained standard unit is regarded as a node. The timing unit can be a trigger, a static random access memory (SRAM) or an IP in the process library, and its output is defined as the starting point of the logic cone.

[0040] The present invention introduces a weight system in the abstracted logic cone, that is, the logic depth of the node is used as its weight. Each node contains one or more logic gates. The logic depth of the node is the number of logic gates on the longest path from the input to the output of the node, which is the key factor determining the node delay.

[0041] In step 3), the critical path logic cone is divided into graphs under certain constraints to identify sub-circuits with optimization value. This is a dynamic process that requires multiple iterations, and each iteration may involve the reconstruction of different sub-circuits. The method of logic depth-driven critical path graph division provided by the present invention initially regards each node in the logic cone as a minimum sub-graph, and then gradually merges those sub-graph pairs that can produce the maximum delay optimization value after merging until the final division result is obtained. In the present invention, logic depth is used as a key indicator to judge the quality of sub-graph division, and the optimal division is iteratively selected. The purpose is to make the logic depth inside the sub-graph as large as possible after division, which means that the optimization value of the sub-graph is also greater.

[0042] Specifically, Figure 2 As shown, the key path logic cone diagram division driven by logic depth in step 3) is as follows: Initialize the subgraph structure. Treat each node in the logic cone as an independent minimum subgraph and calculate the logic depth of each subgraph. The logic depth of a subgraph is the logic depth of the longest path from the input port to the output port of the subgraph.

[0043] Search for all possible subgraph pairs that can be merged. In the present invention, considering the impact of the number of ports of a unit on its design cost, physical size, layout and wiring, delay and power consumption of the unit, based on the empirical data of back-end designers, the present invention constrains the number of input ports of the divided subgraph to not exceed 8, and the number of output ports to not exceed 2. Therefore, the subgraph pairs that can be merged must meet the following requirements: the merged graph meets the port number constraint, and the logical depth of the merged new graph is greater than the logical depth of the subgraph before merging.

[0044] Calculate the logical depth increment IncD (Incremental Depth). In the present invention, the logical depth increment is the difference between the logical depth of the new graph after merging and the average logical depth of the subgraph pair before merging, and the logical depth increment is used as an evaluation indicator of the merge operation. For each pair of subgraphs, calculate the logical depth increment after merging; the larger the logical depth increment, the greater the merging benefit; if the logical depth increment is less than or equal to 0, it means that this merging method is not desirable.

[0045] Select the best merge. For all subgraph pairs that can be merged, find the subgraph pair with the largest logical depth increment after merging, and merge them to get a new subgraph. Use the new subgraph to replace the merged subgraph and update the subgraph structure.

[0046] The merging operation is iterated until there are no more subgraph pairs that can be further merged, and the final partitioning result is obtained.

[0047] like Figure 3As shown, in step 4), the sub-circuit with optimization value obtained by graph partitioning is logically reconstructed to obtain a delay-optimized reconstruction unit. The specific process is as follows: Identify ports: Identify the input and output ports of the subgraph to ensure that the port configuration of the reconstruction unit is consistent with the subgraph.

[0048] Logical simplification: Two-level logical simplification is implemented for each output port of the subgraph. Specifically, the present invention finds the minimum set of prime implied terms by identifying and merging implied terms, and then obtains the minimum SOP (Sum of Products, a basic concept in Boolean algebra) expression of the circuit, and implements two-level logical simplification to reduce the logical level of the circuit.

[0049] Negation logic extraction: Based on the two-level logic simplification, all the negation logic is extracted and simplified upward, and finally a new optimized reconstructed logic unit will be obtained.

[0050] In step 5), in practical applications, it is difficult to reconstruct all sub-circuits with optimization value to obtain new reconstructed logic units through sub-graph logic reconstruction. In order to achieve higher optimization benefits, the present invention carefully selects a small number of reconstructed logic units with higher optimization benefits, so that better optimization effects can be obtained by reconstructing and replacing a small number of units, thereby improving the benefits of delay optimization.

[0051] Specifically, the sub-circuits with optimization value are matched in the netlist. Specifically, the nodes in the logic cone are topologically sorted first, and they are arranged into a linear sequence of logical preorders to ensure that the driver unit of each unit is placed before it; then, based on the sorting results, matching is performed in sequence in the form of a graph, and the parts with the same graph structure as the subgraph are matched in the logic cone. Among them, the units with the same functions are represented by nodes of the same form, and the lines between the nodes represent the connection between the units. Arrows are used to indicate the data flow, and the buffer units are directly represented in the form of lines rather than nodes. The reuse rate of each subgraph is counted in turn, and sorted accordingly. The subgraphs with higher reuse rates are selected to obtain the corresponding reconstructed logic units. Finally, the reconstructed logic units are used to replace the corresponding structures in the netlist to obtain the optimized logic netlist.

[0052] In step 6), the specific process of equivalence test is as follows: The initial logic netlist and the optimized logic netlist are used for equivalence testing. The initial logic netlist is used as a reference model. Under the premise that other irrelevant conditions remain consistent, the equivalence of the logic before and after optimization is verified. When the logical functions corresponding to the two netlists are equivalent, it is proved that the optimized logic cone is equivalent to the original logic cone.

[0053] In step 7), an evaluation model is used to evaluate the key path delay optimization effect. The specific evaluation method is as follows: The delay between basic units is not a fixed value, but a range. The performance evaluation is completed using the evaluation model, with the change in logic depth on the critical path before and after optimization as the key indicator for quantitative analysis.

[0054] Specifically, divide the logic cone G into k (k is a positive integer) non-overlapping subgraphs G1, G2, . . . , Gk; Select subgraphs with larger logic depths for logical reconstruction, and use the reconstructed subgraphs to replace the original subgraphs in the logic cone G. Finally, the logic cone G is optimized into a new logic cone G′, and the logic depth corresponding to G′ is h(G′).

[0055] The optimization effect is evaluated by calculating the change in the graph logic depth before and after optimization; the evaluation function is defined as: ∆h=h(G)-h(G'); In the present invention, the critical path delay optimization method for logic depth driven graph partitioning is provided to satisfy that the logic depth of the logic cone after optimization is less than the logic depth of the logic cone before optimization, that is, the ∆h value is greater than 0.

[0056] The present invention re-optimizes the circuit designed by the EDA tool, which can effectively reduce the logic depth on the critical path, thereby providing an effective means for optimizing the critical path delay at a limited cost, and at the same time provides an option for designing new logic units. A batch of new units can be obtained by performing full-custom design on the logic reconstruction unit, and finally a new full-custom unit library is generated.

[0057] The present invention also provides a critical path delay optimization system based on logic depth drive graph partitioning, comprising an interconnected memory and a processor, wherein a computer program is stored on the memory, and the computer program executes the steps of the above method when executed by the processor. The optimization system of the present invention corresponds to the above optimization method and also has the advantages described in the above optimization method.

[0058] The present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by hardware related to computer program instructions. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above-mentioned method embodiment can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. Computer-readable storage media include: any entity or device that can carry computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. The memory is used to store computer programs and / or modules. The processor implements various functions by running or executing computer programs and / or modules stored in the memory, and calling data stored in the memory. The memory may include a high-speed random access memory and may also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0059] The above is a detailed introduction to the method for optimizing the critical path delay of the logic depth driver graph partitioning provided by the present invention. The present invention illustrates the principles and implementation methods of the present invention through specific examples. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A critical path delay optimization method based on logic depth drive graph partitioning, characterized in that: Includes steps: 1) Obtain the logic netlist, given standard cell library and timing constraints in the integrated circuit semi-custom design process; 2) Analyze the characteristics of the critical path in the logic netlist and construct the critical path logic cone based on the given standard cell library and timing constraints; 3) Screen out sub-circuits with optimization value from the critical path logic cone through the logic depth driven graph partitioning method; 4) Simplify the sub-circuit with optimization value through the sub-graph logic reconstruction method to obtain the reconstructed logic unit with better delay; 5) Filter the reconstructed logic units corresponding to the subgraphs whose reuse rate is greater than the preset value and replace them into the initial logic netlist to obtain the optimized logic netlist; 6) Perform equivalence check on the initial logic netlist and the optimized logic netlist; If the equivalence test is passed, proceed to the next step; 7) Perform delay evaluation on the logic netlist that passes the equivalence test. If the evaluation passes, the final reconstructed logic unit and optimized logic netlist are obtained.

2. The critical path delay optimization method based on logic depth drive graph partitioning according to claim 1 is characterized in that: In step 2), the direction of constructing the critical path logic cone is exactly opposite to the signal transmission direction; first, the end point of the critical path is obtained from the logic netlist; then, the end point is gradually traced back to the output port of the timing unit and stopped. In this process, the module hierarchy and the internal connections of the module are not retained, only the standard unit and its port information, as well as the logical relationship between them are retained; by identifying the driving nodes corresponding to all the input ports of the node, all the standard units from the end point of the critical path to the timing unit and their connection relationships can be obtained in turn; in the constructed logic cone, each obtained standard unit is regarded as a node; the timing unit is a trigger, static random access memory or IP in the process library, and its output is defined as the starting point of the logic cone.

3. The critical path delay optimization method based on logic depth drive graph partitioning according to claim 2 is characterized in that: In step 2), in the critical path logic cone, the logic depth of the standard cell corresponding to the node is used as its weight, stored in the form of a weighted directed acyclic graph, and visualized; each node contains one or more logic gates, and the logic depth of the node is the number of logic gates on the longest path from the input to the output of the node.

4. The critical path delay optimization method based on logic depth drive graph partitioning according to claim 1, 2 or 3, characterized in that: The specific steps of step 3) are: Initialize the subgraph structure: treat each node in the logic cone as an independent minimum subgraph and calculate the logic depth of each subgraph; the logic depth of a subgraph is the logic depth of the longest path from the input port to the output port of the subgraph; Search for all possible subgraph pairs that can be merged; the subgraph pairs that can be merged must satisfy the following conditions: the merged graph meets the port number constraint, and the logical depth of the merged new graph is greater than the logical depth of the subgraph before merging. Calculate the logical depth increment: For each pair of subgraphs, calculate the logical depth increment after merging; The larger the logical depth increment, the greater the merging benefit; if the logical depth increment is less than or equal to 0, it means that this merging method is not desirable; the logical depth increment is the difference between the logical depth of the new graph after merging and the average logical depth of the subgraph before merging; Select the best merge: For all the identified subgraph pairs that may be merged, find the subgraph pair with the largest logical depth increment after merging, and merge them to obtain a new subgraph; Use the new subgraph to replace the merged subgraph and update the subgraph structure; The merging operation is iterated until there are no more merged subgraph pairs, and the final partitioning result is obtained.

5. The critical path delay optimization method based on logic depth drive graph partitioning according to claim 4 is characterized in that: The specific steps of step 4) are: Identify ports: Identify the input ports and output ports of the subgraph to ensure that the port configuration of the reconstruction unit is consistent with the subgraph; Logic simplification: Implement two-level logic simplification for each output port of the subgraph; specifically, identify and merge the implied terms to find the minimum set of prime implied terms, and then obtain the minimum SOP expression of the circuit, implement two-level logic simplification to reduce the logic level of the circuit; Negation logic extraction: Based on the two-level logic simplification, all the negation logic is extracted and simplified upward, and finally a new optimized reconstructed logic unit is obtained.

6. The critical path delay optimization method based on logic depth drive graph partitioning according to claim 5 is characterized in that: In step 5), the specific steps of screening the reconstruction logic units corresponding to the subgraphs whose reuse rate is greater than the preset value are: First, the nodes in the logic cone are topologically sorted into a linear sequence of logical precedence; Then, based on the sorting results, matching is performed in sequence in the form of a graph, and the parts with the same graph structure as the subgraph are matched in the logic cone; units with the same functions are represented by nodes in the same form, and the lines between the nodes represent the connection between the units, and the arrows are used to indicate the data flow direction, while the buffer unit is directly represented in the form of a line instead of a node; The reuse rate of each sub-graph is counted and sorted in turn, and the sub-graph with a reuse rate greater than a preset value is selected to obtain the corresponding reconstruction logic unit.

7. The critical path delay optimization method based on logic depth drive graph partitioning according to claim 1, 2 or 3, characterized in that: The specific process of the equivalence test in step 6) is: Taking the initial logic netlist as the reference model, and under the premise that other irrelevant conditions remain the same, verify the equivalence of the initial logic netlist and the optimized logic netlist. When the logical functions corresponding to the two netlists are equivalent, it is proved that the optimized logic cone is equivalent to the original logic cone, and the equivalence test passes.

8. The critical path delay optimization method based on logic depth drive graph partitioning according to claim 1, 2 or 3, characterized in that: In step 7), when performing delay evaluation on the logic netlist that has passed the equivalence check, the change in logic depth on the critical path before and after optimization is used as a key indicator for evaluation and quantitative analysis is performed.

9. The critical path delay optimization method based on logic depth drive graph partitioning according to claim 8 is characterized in that: The specific process of quantitative analysis using the change in logic depth on the critical path before and after optimization as the key indicator for evaluation is as follows: Divide the logical cone G into k non-overlapping subgraphs G1, G2, . . . , Gk; where k is a positive integer; Select subgraphs with larger logic depths for logic reconstruction, and use the reconstructed subgraphs to replace the original subgraphs in the logic cone G. Finally, the logic cone G is optimized to a new logic cone G′, and the logic depth corresponding to G′ is h(G′); The optimization effect is evaluated by calculating the change in the graph logic depth before and after optimization; the evaluation function is defined as: ∆h=h(G)-h(G'); When the logic depth of the logic cone after optimization is less than the logic depth of the logic cone before optimization, that is, the ∆h value is greater than 0, the evaluation passes.

10. A critical path delay optimization system based on logic depth drive graph partitioning, comprising a memory and a processor connected to each other, wherein a computer program is stored in the memory, characterized in that: When the computer program is executed by a processor, the computer program performs the steps of the method according to any one of claims 1 to 9.

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