Chip design hold time violation automatic correction method, system, medium and product

Abstract

The present invention discloses a method, system, medium and product for automatically correcting hold time violations in chip design. The method includes calculating the ratio between the setup time margin and the absolute value of the hold time violation value for the endpoint pin of the timing path of the hold time violation in the chip design, and selecting different insertion points to insert a delay unit or a buffer unit based on whether the ratio is greater than a preset value K; then completing a hold time violation correction, and then detecting and reporting whether there are still timing paths with hold time violations. If there are, repeating the above process until all hold time violation paths in the design are repaired. The present invention aims to realize the automated correction of hold time violations in chip design, to make up for the deficiency of existing engineering renovation tools that can only automatically repair hold time violations with sufficient setup time margin at the endpoint of the timing path, and to automatically and efficiently repair various hold time violations with sufficient and insufficient setup time margins, so that the chip design can achieve the purpose of timing convergence as soon as possible.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit physical design, and in particular to a chip design hold time violation automatic correction method, system, medium and product. Background Art

[0002] Static timing analysis (STA) is a crucial step in integrated circuit physical design, used to verify that chip designs meet timing requirements. A timing verification method that doesn't rely on test vectors, STA analyzes all timing paths in a circuit, calculates signal propagation delays along these paths, and checks whether signal setup and hold times meet constraint requirements.

[0003] Setup time refers to the minimum time that input data must remain stable before a clock edge (rising or falling) arrives. Setup slack refers to the difference between the actual setup time and the required setup time. When the actual setup time is greater than the required setup time, the setup slack is positive, indicating that timing requirements are met; conversely, a negative setup slack indicates that timing requirements are not met and a setup time violation has occurred. Hold time refers to the minimum time that input data must remain stable after a clock edge (rising or falling) is triggered. A hold time violation occurs when the data arrival time is less than the required hold time.

[0004] In chip design, if setup violations remain unfixed, the final manufactured chip will not achieve the expected operating frequency; if hold violations remain unfixed, the final chip will not function properly. Therefore, before the final chip tape-out, all setup and hold violations must be fixed. In particular, hold violations should be fixed with higher priority than setup violations. Currently, hold violation repair typically uses a combination of engineering overhaul tools (ECO tools) within electronic design automation tools and manual repair. The ECO tools repair the majority of hold violations, while the remaining minor violations rely on the experience of physical design engineers to repair them one by one. This can result in low repair efficiency, impacting design convergence time. Summary of the Invention

[0005] Technical problem to be solved by the present invention: In response to the above-mentioned problems in the prior art, a method, system, medium and product for automatically correcting hold time violations in chip design are provided. The present invention aims to obtain hold time violation points in static timing analysis, automatically analyze and determine the number of delay units or buffer units to be inserted to repair hold time violations and the positions of insertion points, and automatically and efficiently repair hold time violations in the design.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A method for automatically correcting a chip design hold time violation comprises the following steps:

[0008] S1, obtain the endpoint pins of the timing path with hold time violation from the static timing analysis report of the chip design and put them into the list;

[0009] S2, traverse and select an endpoint pin from the list, obtain the hold time violation value hold_slack of the endpoint pin and the setup time margin setup_slack of the point; calculate the ratio between the setup time margin setup_slack and the absolute value hold_slack_abs of the hold time violation value hold_slack;

[0010] S3, determining whether the ratio is greater than a preset value K. If so, the end pin is used as the insertion point and the process goes to step S5; otherwise, the process goes to step S4;

[0011] S4, obtain all fan-in pins with hold time violations in the destination pin, traverse to obtain the setup time margin passing through each fan-in pin, and select the pin with the largest positive setup time margin as the insertion point, and jump to step S5;

[0012] S5, determining the type and number of delay units or buffer units to be inserted at the insertion point according to the hold time violation value hold_slack, obtaining the physical position coordinates of the insertion point, inserting a corresponding number of delay units or buffer units at the physical position coordinates, and jumping to step S6;

[0013] S6, determine whether the traversal of the timing path endpoint list has been completed. If not, jump to step S2; otherwise, jump to step S7;

[0014] S7, first complete the hold time violation correction for the chip design, then check whether there are still timing paths with hold time violations in the chip design. If so, jump to step S1, otherwise it is determined that all timing paths with hold time violations in the chip design have been repaired, end and exit.

[0015] Optionally, obtaining the hold time violation value hold_slack of the endpoint pin and the setup time margin setup_slack of the point in step S2 refers to obtaining them in a static timing analysis tool.

[0016] Optionally, step S4 includes:

[0017] S4.1, put all fan-in pins to the destination pin into a list all_fanin_pins;

[0018] S4.2, traverse and obtain the hold time margin from each fan-in pin to the destination pin in the list all_fanin_pins, and put the fan-in pins with negative hold time margin into a list hold_fanin_pins;

[0019] S4.3, traverse and obtain the setup time margin of each fan-in pin in the list hold_fanin_pins, and select a fan-in pin with a positive and largest setup time margin as the insertion point.

[0020] Optionally, step S5 includes:

[0021] S5.1, determine whether the absolute value of the hold time violation value hold_slack of the endpoint pin, hold_slack_abs, is greater than the preset maximum delay unit delay value D. If so, jump to step S5.2; otherwise, jump to step S5.3;

[0022] S5.2, calculate the ratio between the absolute value hold_slack of the hold time violation value hold_slack of the endpoint pin and the preset maximum delay unit delay value D, and round it down to obtain the number N of inserted maximum delay units. Then calculate the remaining value hold_slack_left of the hold time violation after inserting N maximum delay units, and jump to step S5.4;

[0023] S5.3, determining the type of delay unit or buffer unit to be inserted based on the absolute value hold_slack_abs of the hold time violation value hold_slack of the endpoint pin, obtaining the physical location coordinates of the current pin, and inserting a delay unit or buffer unit of the determined type at the physical location coordinates;

[0024] S5.4, determine the type of delay unit or buffer unit to be inserted based on the hold_slack_left value of the remaining hold time violation after inserting N maximum delay units, obtain the physical position coordinates of the current pin, insert N maximum delay units and 1 other type of delay unit or buffer unit at the physical position coordinates, the maximum delay unit refers to the delay unit with the largest delay value among multiple delay units and the preset maximum delay unit delay value D, and the other type of delay unit refers to the delay unit other than the maximum delay unit among the multiple delay units.

[0025] Optionally, the calculation function expression of the remaining value hold_slack_left of the hold time violation after inserting N maximum delay units in step S5.2 is:

[0026] hold_slack_left=hold_slack_abs- N×D;

[0027] Wherein, hold_slack_abs is the absolute value of the hold time violation value hold_slack of the endpoint pin, N is the number of inserted maximum delay units, and D is the preset maximum delay unit delay value.

[0028] Optionally, completing one hold time violation correction for the chip design in step S7 refers to performing a cell position legalization operation and a local routing operation in a placement and routing tool to complete one hold time violation correction for the chip design.

[0029] Optionally, detecting whether the chip design still has a timing path with a hold time violation in step S7 refers to detecting the chip design in a static timing tool to determine whether the chip design still has a timing path with a hold time violation.

[0030] In addition, the present invention also provides a chip design hold time violation automatic correction system, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the chip design hold time violation automatic correction method.

[0031] In addition, the present invention also provides a computer-readable storage medium, which stores a computer program or instruction. The computer program or instruction is programmed or configured to execute the chip design hold time violation automatic correction method through a processor.

[0032] In addition, the present invention also provides a computer program product, including a computer program or instructions, which is programmed or configured to execute the chip design hold time violation automatic correction method through a processor.

[0033] Compared with the prior art, the present invention mainly has the following advantages: the method of the present invention includes calculating the ratio between the setup time margin and the absolute value of the hold time violation value for the endpoint pin of the timing path of the hold time violation in the chip design, and selecting different insertion points to insert delay units or buffer units according to whether the ratio is greater than a preset value K; then completing a hold time violation correction, and then detecting and reporting whether there are still timing paths with hold time violations. If there are, repeating the above process until all hold time violation paths in the design are repaired. The present invention automatically analyzes and determines the number of delay units or buffer units to be inserted and the position of the insertion points to repair the hold time violation, automatically and efficiently repairing the hold time violations in the design, making up for the deficiency of existing engineering renovation tools that can only automatically repair hold time violations with sufficient setup time margin at the endpoint of the timing path, and effectively solving the problem of low efficiency in manual repair of hold time violations. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Schematic diagram of the basic process of the method of the embodiment of the present invention.

[0035] Figure 2 This is a flow chart of obtaining fan-in pins with sufficient setup time margin in step S4 of the method according to an embodiment of the present invention.

[0036] Figure 3 A schematic diagram of establishing fan-in pins with sufficient time margin in an embodiment of the present invention.

[0037] Figure 4 Schematic diagram of the process of step S5 in an embodiment of the present invention.

[0038] Figure 5 This is a schematic diagram illustrating an example of inserting a delay unit and a buffer unit in a method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0039] like Figure 1 As shown, the chip design hold time violation automatic correction method of this embodiment includes the following steps:

[0040] S1, obtain the endpoint pins of the timing path with hold time violation from the static timing analysis report of the chip design and put them into the list;

[0041] S2, traverse and select an endpoint pin from the list, obtain the hold time violation value hold_slack of the endpoint pin and the setup time margin setup_slack of the point; calculate the ratio between the setup time margin setup_slack and the absolute value hold_slack_abs of the hold time violation value hold_slack;

[0042] S3, determining whether the ratio is greater than a preset value K. If so, the end pin is used as the insertion point and the process goes to step S5; otherwise, the process goes to step S4;

[0043] S4, obtain all fan-in pins with hold time violations in the destination pin, traverse to obtain the setup time margin passing through each fan-in pin, and select the pin with the largest positive setup time margin as the insertion point, and jump to step S5;

[0044] S5, determining the type and number of delay units or buffer units to be inserted at the insertion point according to the hold time violation value hold_slack, obtaining the physical position coordinates of the insertion point, inserting a corresponding number of delay units or buffer units at the physical position coordinates, and jumping to step S6;

[0045] S6, determine whether the traversal of the timing path endpoint list has been completed. If not, jump to step S2; otherwise, jump to step S7;

[0046] S7, first complete the hold time violation correction for the chip design, then check whether there are still timing paths with hold time violations in the chip design. If so, jump to step S1, otherwise it is determined that all timing paths with hold time violations in the chip design have been repaired, end and exit.

[0047] As an optional implementation manner, obtaining the hold time violation value hold_slack of the endpoint pin and the setup time margin setup_slack of the point in step S2 refers to obtaining them in a static timing analysis tool.

[0048] like Figure 2 As shown, step S4 includes:

[0049] S4.1, put all fan-in pins to the destination pin into a list all_fanin_pins;

[0050] S4.2, traverse and obtain the hold time margin from each fan-in pin to the destination pin in the list all_fanin_pins, and put the fan-in pins with negative hold time margin into a list hold_fanin_pins;

[0051] S4.3, traverse and obtain the setup time margin of each fan-in pin in the list hold_fanin_pins, and select a fan-in pin with a positive and largest setup time margin as the insertion point.

[0052] Figure 3 This is a schematic diagram of fan-in pins with sufficient time margin in this embodiment. Figure 3As shown, there are three fan-in pins to the D input terminal of the timing path endpoint flip-flop FF2: the B terminal of the two-input AND gate AND2, the A terminal of the three-input OR gate, and the I terminal of the inverter INV. The static timing analysis tool shows that the hold time margins from these three fan-in pins to the D terminal of the endpoint FF2 are all negative, and the setup time margin from the B terminal of the two-input AND gate AND2 is the largest. Therefore, the B terminal pin of the two-input AND gate AND2 is selected as the fan-in pin of the buffer unit or delay unit to be inserted.

[0053] like Figure 4 As shown, step S5 includes:

[0054] S5.1, determine whether the absolute value of the hold time violation value hold_slack of the endpoint pin, hold_slack_abs, is greater than the preset maximum delay unit delay value D. If so, jump to step S5.2; otherwise, jump to step S5.3;

[0055] S5.2, calculate the ratio between the absolute value hold_slack of the hold time violation value hold_slack of the endpoint pin and the preset maximum delay unit delay value D, and round it down to obtain the number N of inserted maximum delay units. Then calculate the remaining value hold_slack_left of the hold time violation after inserting N maximum delay units, and jump to step S5.4;

[0056] S5.3, determining the type of delay unit or buffer unit to be inserted based on the absolute value hold_slack_abs of the hold time violation value hold_slack of the endpoint pin, obtaining the physical location coordinates of the current pin, and inserting a delay unit or buffer unit of the determined type at the physical location coordinates;

[0057] S5.4, determine the type of delay unit or buffer unit to be inserted based on the hold_slack_left value of the remaining hold time violation after inserting N maximum delay units, obtain the physical position coordinates of the current pin, insert N maximum delay units and 1 other type of delay unit or buffer unit at the physical position coordinates, the maximum delay unit refers to the delay unit with the largest delay value among multiple delay units and the preset maximum delay unit delay value D, and the other type of delay unit refers to the delay unit other than the maximum delay unit among the multiple delay units.

[0058] As an optional implementation, in step S5.2 of this embodiment, the calculation function expression of the remaining value hold_slack_left of the hold time violation after inserting N maximum delay units is:

[0059] hold_slack_left=hold_slack_abs-N×D;

[0060] Wherein, hold_slack_abs is the absolute value of the hold time violation value hold_slack of the endpoint pin, N is the number of inserted maximum delay units, and D is the preset maximum delay unit delay value.

[0061] Figure 5 This is a schematic diagram showing an example of inserting a delay unit and a buffer unit in the method of this embodiment. Figure 5 As shown in the figure, assume the absolute value of the hold time violation from terminal A of the three-input OR gate OR3 to terminal D of the endpoint FF2 is 210ps. The delays of the three delay units DLY1, DLY2, and DLY4 are 25ps, 50ps, and 100ps, respectively. This means the delay D of the largest delay unit DLY4 is 100ps, and the delay of the buffer unit BUF1 is 10ps. Because the absolute value of the hold time violation on the current pin is greater than the delay of the largest delay unit, calculation shows that two largest delay units DLY4 need to be inserted into terminal A of the three-input OR gate OR3. The remaining hold time violation value, hold_slack_left, is 10ps. Therefore, inserting another buffer unit BUF1 into terminal A can correct the hold time violation.

[0062] As an optional implementation, in step S7 of this embodiment, completing one hold time violation correction for the chip design refers to performing a cell position legalization operation and a local routing operation in a placement and routing tool to complete one hold time violation correction for the chip design.

[0063] As an optional implementation, in step S7 of this embodiment, detecting whether the chip design still has a timing path with a hold time violation refers to detecting the chip design in a static timing tool to determine whether the chip design still has a timing path with a hold time violation.

[0064] In summary, the method for automatically correcting hold time violations in chip design of this embodiment includes obtaining the endpoint pins of the timing path with hold time violations from the static timing analysis report and putting them into a list; traversing and selecting a timing path endpoint pin from the list, obtaining the hold time violation value of the point and the setup time margin of the point; calculating the ratio between the setup time margin and the absolute value of the hold time violation value, if the ratio is greater than a preset value K (the value is determined empirically according to different processes), determining the type and number of delay units or buffer units to be inserted according to the hold time violation value, obtaining the physical position coordinates of the point, and inserting the corresponding number of delay units or buffer units at the physical position; if the ratio is less than K, obtaining the hold time violation value in the endpoint pin. All fan-in pins with hold time violation are traversed to obtain the setup time margin passing through each fan-in pin, and the one with the positive and largest setup time margin among all fan-in pins is selected. The type and number of delay units or buffer units to be inserted are determined according to the hold time violation value, and the physical position coordinates of the fan-in pin are obtained. The corresponding number of delay units or buffer units are inserted at the physical position; the system traverses until the list of terminal pins of all timing paths is empty; the unit position legalization operation and local routing operation are performed in the placement and routing tool to complete the hold time violation correction. Then, the static timing analysis tool is used to detect and report whether there are still timing paths with hold time violation. If there are, the above process is repeated until all hold time violation paths in the design are fixed. The method for automatically correcting hold time violations in chip design of this embodiment obtains hold time violation points in static timing analysis, automatically analyzes and determines the number of delay units or buffer units to be inserted to repair the hold time violation and the positions of the insertion points, and automatically and efficiently repairs the hold time violations existing in the design. The method for automatically correcting hold time violations in chip design of this embodiment makes up for the deficiency that existing engineering renovation tools can only automatically repair hold time violations with sufficient time margin at the end point of the timing path, and effectively solves the problem of low efficiency in manually repairing hold time violations.

[0065] In addition, this embodiment also provides a chip design hold time violation automatic correction system, including a microprocessor and a memory connected to each other, and the microprocessor is programmed or configured to execute the chip design hold time violation automatic correction method.

[0066] In addition, this embodiment also provides a computer-readable storage medium, which stores a computer program or instruction. The computer program or instruction is programmed or configured to execute the chip design hold time violation automatic correction method through a processor.

[0067] In addition, this embodiment also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the chip design hold time violation automatic correction method through a processor.

[0068] Those skilled in the art should understand that the technical solution that the present invention can provide can be in the form of a method, a system, or a computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment that combines software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the functions in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including the instruction device, which implements the function specified in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0069] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A method for automatically correcting chip design hold time violations, characterized in that: The steps include: S1, obtain the endpoint pins of the timing path with hold time violation from the static timing analysis report of the chip design and put them into the list; S2, traverse and select an endpoint pin from the list, obtain the hold time violation value hold_slack of the endpoint pin and the setup time margin setup_slack of the point; calculate the ratio between the setup time margin setup_slack and the absolute value hold_slack_abs of the hold time violation value hold_slack; S3, determining whether the ratio is greater than a preset value K. If so, the end pin is used as the insertion point and the process goes to step S5; otherwise, the process goes to step S4; S4, obtain all fan-in pins with hold time violations in the destination pin, traverse to obtain the setup time margin passing through each fan-in pin, and select the pin with the largest positive setup time margin as the insertion point, and jump to step S5; S5, determining the type and number of delay units or buffer units to be inserted at the insertion point according to the hold time violation value hold_slack, obtaining the physical position coordinates of the insertion point, inserting a corresponding number of delay units or buffer units at the physical position coordinates, and jumping to step S6; S6, determine whether the traversal of the timing path endpoint list has been completed, if not, jump to step S2; Otherwise, jump to step S7; S7, first complete the hold time violation correction for the chip design, then check whether there are still timing paths with hold time violations in the chip design. If so, jump to step S1, otherwise it is determined that all timing paths with hold time violations in the chip design have been repaired, end and exit.

2. The chip design hold time violation automatic correction method according to claim 1, characterized in that: In step S2 , obtaining the hold time violation value hold_slack of the endpoint pin and the setup time margin setup_slack of the point refers to obtaining them in a static timing analysis tool.

3. The chip design hold time violation automatic correction method according to claim 1, characterized in that: Step S4 includes: S4.1, put all fan-in pins to the destination pin into a list all_fanin_pins; S4.2, traverse and obtain the hold time margin from each fan-in pin to the destination pin in the list all_fanin_pins, and put the fan-in pins with negative hold time margin into a list hold_fanin_pins; S4.3, traverse to obtain the setup time margin of each fan-in pin in the list hold_fanin_pins, and select the fan-in pin with the largest positive setup time margin as the insertion point.

4. The chip design hold time violation automatic correction method according to claim 1, characterized in that: Step S5 includes: S5.1, determine whether the absolute value of the hold time violation value hold_slack of the endpoint pin, hold_slack_abs, is greater than the preset maximum delay unit delay value D. If so, jump to step S5.2; otherwise, jump to step S5.3; S5.2, calculate the ratio between the absolute value hold_slack of the hold time violation value hold_slack of the endpoint pin and the preset maximum delay unit delay value D, and round it down to obtain the number N of inserted maximum delay units. Then calculate the remaining value hold_slack_left of the hold time violation after inserting N maximum delay units, and jump to step S5.4; S5.3, determining the type of delay unit or buffer unit to be inserted based on the absolute value hold_slack_abs of the hold time violation value hold_slack of the endpoint pin, obtaining the physical location coordinates of the current pin, and inserting a delay unit or buffer unit of the determined type at the physical location coordinates; S5.4, determine the type of delay unit or buffer unit to be inserted based on the hold_slack_left value of the remaining hold time violation after inserting N maximum delay units, obtain the physical position coordinates of the current pin, insert N maximum delay units and 1 other type of delay unit or buffer unit at the physical position coordinates, the maximum delay unit refers to the delay unit with the largest delay value among the multiple delay units and the preset maximum delay unit delay value D, and the other type of delay unit refers to the delay unit other than the maximum delay unit among the multiple delay units.

5. The chip design hold time violation automatic correction method according to claim 4, characterized in that: The calculation function expression of the remaining value hold_slack_left of the hold time violation after inserting N maximum delay units in step S5.2 is: hold_slack_left=hold_slack_abs- N×D; Wherein, hold_slack_abs is the absolute value of the hold time violation value hold_slack of the endpoint pin, N is the number of inserted maximum delay units, and D is the preset maximum delay unit delay value.

6. The chip design hold time violation automatic correction method according to claim 1, characterized in that: The step S7 of completing one hold time violation correction for the chip design refers to executing a cell position legalization operation and a local routing operation in a placement and routing tool to complete one hold time violation correction for the chip design.

7. The chip design hold time violation automatic correction method according to claim 1, characterized in that: Detecting whether the chip design still has a timing path with a hold time violation in step S7 refers to detecting the chip design in a static timing tool to determine whether the chip design still has a timing path with a hold time violation.

8. A chip design hold time violation automatic correction system, comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor is programmed or configured to execute the chip design hold time violation automatic correction method according to any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program or instruction stored therein, characterized in that: The computer program or instruction is programmed or configured to execute the chip design hold time violation automatic correction method according to any one of claims 1 to 7 through a processor.

10. A computer program product comprising a computer program or instructions, characterized in that The computer program or instruction is programmed or configured to execute the chip design hold time violation automatic correction method according to any one of claims 1 to 7 through a processor.

Images