Display panel and driving method thereof

Abstract

The invention provides a display panel and a driving method thereof, and belongs to the technical field of display. The display panel comprises a plurality of display unit sets which are sequentially arranged in the row direction. The display unit set comprises a plurality of first display units located in different display unit columns and a plurality of second display units located in different display unit columns; the display panel is also provided with a first data line and a second data line corresponding to the display unit set; each first display unit of the display unit set is electrically connected with the first data wire, and each second display unit of the display unit set is electrically connected with the corresponding second data wire. The display panel can reduce power consumption.

Description

Technical Field

[0001] The present disclosure relates to the technical field of pixel data line layout, and in particular to a display panel and a driving method thereof. Background Art

[0002] In the Pentile pixel arrangement, the red sub-pixels and the blue sub-pixels share a data line. The voltage on the data line needs to be refreshed once in each odd and even row, and it cyclically jumps between L255 and L0, thereby generating additional power consumption.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a display panel and a driving method thereof to reduce the power consumption of the display panel.

[0005] According to one aspect of the present disclosure, a display panel is provided, comprising a plurality of display unit sets sequentially arranged along a row direction; the display unit sets comprise a plurality of first display units located in different display unit columns and a plurality of second display units located in different display unit columns;

[0006] The display panel is also provided with a first data line and a second data line corresponding to the display unit set; each first display unit of the display unit set is electrically connected to the first data line, and each second display unit of the display unit set is electrically connected to the corresponding second data line.

[0007] According to one embodiment of the present disclosure, the display unit set includes a first display unit column arranged adjacent to the first data routing line and a second display unit column arranged adjacent to the second data routing line; the first display unit column includes first display units and second display units arranged alternately in sequence along the column direction; the second display unit column includes second display units and first display units arranged alternately in sequence along the column direction.

[0008] According to an embodiment of the present disclosure, in the same display unit row, the first display units and the second display units are alternately arranged.

[0009] According to one embodiment of the present disclosure, the display unit set includes a first display unit column, a third display unit column, a second display unit column and a fourth display unit column arranged in sequence along the row direction; the third display unit column and the fourth display unit column each include a plurality of third display units arranged in sequence along the column direction.

[0010] According to an embodiment of the present disclosure, in the same display unit row, each row of sub-pixels includes a first display unit, a second display unit and two third display units.

[0011] According to an embodiment of the present disclosure, the display panel is further provided with a third data routing line and a fourth data routing line corresponding to the display unit set;

[0012] Each third display unit in the third display unit column is electrically connected to a third data line, and each third display unit in the fourth display unit column is electrically connected to a fourth data line.

[0013] According to an embodiment of the present disclosure, the third data wiring is disposed adjacent to the first data wiring and is located between each pixel driving circuit of the first display unit column and each pixel driving circuit of the third display unit column;

[0014] The fourth data wiring is disposed adjacent to the second data wiring and is located between each pixel driving circuit of the second display unit column and each pixel driving circuit of the fourth display unit column.

[0015] According to an embodiment of the present disclosure, the display panel is provided with a first adapter wire and a second adapter wire;

[0016] The second display unit located in the first display unit column is electrically connected to the second data wiring through the second adapter wire;

[0017] The first display unit located in the second display unit column is electrically connected to the first data wiring through the first adapter wire.

[0018] According to an embodiment of the present disclosure, the display panel includes a base substrate, a driving circuit layer and a pixel layer which are stacked in sequence; the driving circuit layer includes a transistor layer, a first source-drain metal layer, a transfer metal layer and a second source-drain metal layer which are stacked in sequence; each transistor of the pixel driving circuit of the display unit is arranged in the transistor layer; the sub-pixel of the display unit is arranged in the pixel electrode layer;

[0019] The second source-drain metal layer is provided with the first data wiring and the second data wiring;

[0020] The transfer metal layer is provided with a first transfer metal structure, a first transfer wire and a second transfer wire; wherein:

[0021] The data voltage input terminal of the pixel driving circuit of the first display unit adjacent to the first data wiring is electrically connected to the first transfer metal structure corresponding to the first display unit through a via hole; the first transfer metal structure is electrically connected to the first data wiring through a via hole;

[0022] The data voltage input terminal of the pixel driving circuit of the second display unit adjacent to the second data wiring is electrically connected to the first transfer metal structure corresponding to the second display unit through a via hole, and the first transfer metal structure is electrically connected to the second data wiring through a via hole;

[0023] The data voltage input terminal of the pixel driving circuit of the first display unit adjacent to the second data wiring is electrically connected to the first end of the first adapter wire through a via hole, and the second end of the first adapter wire is electrically connected to the first data wiring through a via hole;

[0024] The data voltage input terminal of the pixel driving circuit of the second display unit adjacent to the first data wiring is electrically connected to the first end of the second adapter wire through a via hole, and the second end of the second adapter wire is electrically connected to the second data wiring through a via hole.

[0025] According to an embodiment of the present disclosure, the shape of the first end of the second patch cord is the same as the shape of the first patch metal structure; the second end of the second patch cord is adjacent to and insulated from the first end of the first patch cord;

[0026] The shape of the first end of the first transition wire is the same as that of the first transition metal structure; the second end of the first transition wire is adjacent to and insulated from the first end of the second transition wire.

[0027] According to an embodiment of the present disclosure, the second source-drain metal layer further includes a driving voltage wiring;

[0028] A first avoidance gap is formed on a side of the driving voltage wiring close to the first data wiring; the orthographic projection of the second end of the first adapter wire on the plane where the display panel is located is located within the orthographic projection of the first avoidance gap on the plane where the display panel is located;

[0029] A second avoidance gap is formed on one side of the driving voltage wiring close to the second data wiring; the orthographic projection of the second end of the second adapter wire on the plane where the display panel is located is located within the orthographic projection of the second avoidance gap on the plane where the display panel is located.

[0030] According to an embodiment of the present disclosure, the first data wiring has a first side branch portion that penetrates into the first avoidance gap, and the first side branch portion is electrically connected to the second end of the first adapter wire through a via;

[0031] The second data wiring has a second side branch portion extending deep into the second avoidance gap, and the second side branch portion is electrically connected to the second end of the second adapter wire through a via.

[0032] According to another aspect of the present disclosure, there is provided a method for driving a display panel, comprising: driving each display unit row by row;

[0033] When driving any display unit row, the driving voltage required by the first display unit of the display unit set is loaded onto the first data line corresponding to the display unit set, and the driving voltage required by the second display unit of the display unit set is loaded onto the second data line corresponding to the display unit set.

[0034] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0036] Figure 1 It is a structural schematic diagram of a display panel in the related art.

[0037] Figure 2 It is a schematic diagram of the structure of a display panel in one embodiment of the present disclosure.

[0038] Figure 3 FIG. 1 is a schematic diagram of a cross-sectional structure of a display panel in one embodiment of the present disclosure.

[0039] Figure 4 FIG. 4 is an equivalent circuit diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0040] Figure 5 It is a schematic diagram of the stacked structure of a polysilicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer, a third gate layer, and a first source-drain metal layer in a circuit layout region of an embodiment of the present disclosure.

[0041] Figure 6 It is a schematic diagram of the local structure of a metal light-shielding layer in one embodiment of the present disclosure.

[0042] Figure 7 It is a schematic diagram of the local structure of a polysilicon semiconductor layer in one embodiment of the present disclosure.

[0043] Figure 8 It is a schematic diagram of the local structure of the first gate layer in one embodiment of the present disclosure.

[0044] Fig. 9 FIG. 1 is a schematic diagram of a partial structure of a second gate layer in one embodiment of the present disclosure.

[0045] Fig.10 It is a schematic diagram of the local structure of a metal oxide semiconductor layer in one embodiment of the present disclosure.

[0046] Fig.11 It is a schematic diagram of the local structure of the third gate layer in one embodiment of the present disclosure.

[0047] Fig.12 It is a schematic diagram of the local structure of the first source-drain metal layer in one embodiment of the present disclosure.

[0048] Fig.13 It is a schematic diagram of the stacked structure of a second gate layer, a metal oxide semiconductor layer, a third gate layer and a first source-drain metal layer in one embodiment of the present disclosure.

[0049] Fig.14 It is a schematic diagram of the local structure of the transfer metal layer in one embodiment of the present disclosure.

[0050] Fig.15 It is a schematic diagram of the local structure of the second source-drain metal layer in one embodiment of the present disclosure.

[0051] Fig.16 It is a schematic diagram of the stacked structure of a transfer metal layer and a second source-drain metal layer in one embodiment of the present disclosure.

[0052] Fig.17 It is a schematic diagram of the stacked structure of a transfer metal layer, a second source-drain metal layer, and a pixel layer in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0054] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0055] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0056] In the present disclosure, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. The channel region refers to the region where the current mainly flows. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source" and the "drain" are sometimes interchanged. Therefore, in this specification, "source" and "drain" are relative concepts that can be interchanged.

[0057] In the present disclosure, when describing the overlapping arrangement of structure A and structure B, it means that structure A and structure B are arranged in different film layers, and there is an overlapping part between the orthographic projection of structure A on the substrate and the orthographic projection of structure B on the substrate.

[0058] In the present disclosure, the overlapping portion of structure C and structure D refers to a specific portion C1 in structure C; the orthographic projection of the specific portion C1 on the substrate is the overlapping portion of the orthographic projection of structure C on the substrate and the orthographic projection of structure D on the substrate.

[0059] In the present disclosure, the structure layer E is located on the side of the structure layer F away from the base substrate, which can be understood as the structure layer E is formed on the side of the structure layer F away from the base substrate. When the structure layer F is a patterned structure, part of the structure layer E may also be located at the same physical height of the structure layer E or lower than the physical height of the structure layer E, wherein the base substrate is a height reference.

[0060] Figure 1FIG. 1 is a schematic diagram of a display panel structure in the related art. Figure 1 In the related art, the display panel has display unit columns and data lines DL corresponding to the display unit columns. Among them, each pixel driving circuit PDC of the display unit column is electrically connected to the data line DL corresponding to the display unit column. Some of the display unit columns have display units DU of different colors, and these display units DU of different colors are driven by the same data line DL. For example, at least one display unit column includes red display units and blue display units that are alternately arranged; the voltage on the data line must be refreshed once for each odd row and even row, and it cyclically jumps between grayscale Lmax and grayscale L0, resulting in additional power consumption. Among them, grayscale Lmax is the maximum value of the grayscale of the display panel, for example, 255 grayscales.

[0061] The present disclosure provides a display panel PNL, see Figure 2 The display panel PNL includes a display area AA and a peripheral area BB located at least on one side of the display area AA. In the display area AA, the display panel PNL is provided with display units DU (eg Figure 2 The first display unit DU1, the second display unit DU2, and the third display unit DU3 in the display unit DU include sub-pixels PIX (e.g. Figure 2 The display panel PNL includes a first sub-pixel PIX1, a second sub-pixel PIX2, and a third sub-pixel PIX3) and a pixel driving circuit PDC for driving the sub-pixels PIX. The display panel PNL does not have a display unit DU in the peripheral area BB, or the display unit DU is not used for displaying images. The display panel PNL has a plurality of scanning lines ( Figure 2 (not shown), each scan line is arranged in one-to-one correspondence with each display unit row HDU. The pixel driving circuit PDC of each display unit DU of the display unit row is electrically connected to the corresponding scan line. The display panel PNL is also provided with a plurality of data lines DL extending along the column direction DV in the display area AA. Each data line DL is arranged in one-to-one correspondence with each display unit column VDU. The pixel driving circuit PDC of each display unit DU is connected to a scan line and a data line DL. When a scan signal is loaded on the scan line, the driving voltage loaded on the data line DL can be written into the pixel driving circuit PDC, so that the pixel driving circuit PDC can control the brightness of the sub-pixel PIX according to the written driving voltage.

[0062] The display panel PNL includes a plurality of display unit sets DUS ( Figure 2 only one example is given in ); see Figure 2, the display unit set DUS includes a plurality of first display units DU1 located in different display unit columns VDU and a plurality of second display units DU2 located in different display unit columns VDU. The display panel PNL is also provided with a first data line DL1 and a second data line DL2 corresponding to the display unit set DUS. Each first display unit DU1 of the display unit set DUS is electrically connected to the first data line DL1, and each second display unit DU2 of the display unit set DUS is electrically connected to the corresponding second data line DL2. In this way, the first data line DL1 can be used to load and control the data voltage of each first display unit DU1, and the second data line DL2 can be used to load and control the data voltage of each second display unit DU2, thereby avoiding the extra power consumption generated by the same data line controlling the first display unit DU1 and the second display unit DU2 at the same time, and reducing the power consumption of the display panel.

[0063] It can be understood that the voltage signal on the first data line DL1 is written into the pixel driving circuit PDC of each first display unit DU1 in sequence according to the preset control timing, and the voltage signal on the second data line DL2 is written into the pixel driving circuit PDC of each second display unit DU2 in sequence according to the preset control timing, and the corresponding sub-pixel PIX is controlled by the pixel driving circuit PDC.

[0064] In one embodiment of the present disclosure, Figure 2 As shown, the display unit set DUS includes a first display unit column VDU1, a third display unit column VDU3A, a second display unit column VDU2, and a fourth display unit column VDU3B arranged in sequence along the row direction DH. The first display unit column VDU1 is arranged adjacent to the first data line DL1, and the second display unit column VDU2 is arranged adjacent to the second data line DL2. In an example, the first display unit column VDU1 includes a first display unit DU1 and a second display unit DU2 arranged alternately in sequence along DV; the second display unit column VDU2 includes a second display unit DU2 and a first display unit DU1 arranged alternately in sequence along DV. The second display unit DU2 in the first display unit column VDU1 is electrically connected to the second data line DL2, and the first display unit DU1 in the second display unit column VDU2 is electrically connected to the first data line DL1. In this way, under the premise of keeping the existing pixel arrangement unchanged, the first data line DL1 controls the first display unit DU1, and the second data line DL2 controls the second display unit DU2 in a display unit set DUS.

[0065] In one embodiment of the present disclosure, the display panel PNL is further provided with a third data line DL3A and a fourth data line DL3B corresponding to the display unit set DUS. The third display unit column VDU3A is arranged adjacent to the third data line DL3A, and the fourth display unit column VDU3B is arranged adjacent to the fourth data line DL3B. The third display unit column VDU3A and the fourth display unit column VDU3B each include a plurality of third display units DU3 arranged in sequence along DV. Each third display unit DU3 of the third display unit column VDU3A is electrically connected to the third data line DL3A, and each third display unit DU3 of the fourth display unit column VDU3B is electrically connected to the fourth data line DL3B.

[0066] In one embodiment of the present disclosure, in the display unit set DUS, the same display unit row includes one first display unit DU1, one second display unit DU2 and two third display units DU3. In the same display unit row, the first display unit DU1 and the second display unit DU2 are alternately arranged. For example, Figure 2 As shown, the sub-pixels of the first display unit row in the display unit set DUS are the first display unit DU1, the third display unit DU3, the second display unit DU2, and the third display unit DU3, respectively; the sub-pixels of the adjacent second display unit row are the second display unit DU2, the third display unit DU3, the first display unit DU1, and the third display unit DU3, respectively.

[0067] In one embodiment of the present disclosure, the third data routing DL3A and the first data routing DL1 are arranged adjacent to each other, and the third data routing DL3A and the first data routing DL1 are both located between each pixel driving circuit PDC of the first display unit column VDU1 and each pixel driving circuit PDC of the third display unit column VDU3A; the fourth data routing DL3B and the second data routing DL2 are arranged adjacent to each other, and the fourth data routing DL3B and the second data routing DL2 are both located between each pixel driving circuit PDC of the second display unit column VDU2 and each pixel driving circuit PDC of the fourth display unit column VDU3B.

[0068] In one embodiment of the present disclosure, see Figure 2The display panel PNL is provided with a first adapter wire TRL1 and a second adapter wire TRL2; the second display unit DU2 located in the first display unit column VDU1 is electrically connected to the second data line DL2 through the second adapter wire TRL2; the first display unit DU1 located in the second display unit column VDU2 is electrically connected to the first data line DL1 through the first adapter wire TRL1. In this way, by bridging the first adapter wire TRL1 and the second adapter wire TRL2, on the basis of the original pixel arrangement, the same data line DL only needs to control the display unit DU of one color, and the power consumption of the display panel is reduced without affecting the existing pixel arrangement.

[0069] In one embodiment of the present disclosure, the first display unit DU1 includes a pixel driving circuit PDC and a first sub-pixel PIX1 driven by the pixel driving circuit PDC; the second display unit DU2 includes a pixel driving circuit PDC and a second sub-pixel PIX2 driven by the pixel driving circuit PDC; the third display unit DU3 includes a pixel driving circuit PDC and a third sub-pixel PIX3 driven by the pixel driving circuit PDC. The colors of the first sub-pixel PIX1, the second sub-pixel PIX2 and the third sub-pixel PIX3 are different; further, the sizes of the first sub-pixel PIX1, the second sub-pixel PIX2 and the third sub-pixel PIX3 are different.

[0070] In one example, the sizes of the first sub-pixel PIX1 , the second sub-pixel PIX2 , and the third sub-pixel PIX3 decrease in sequence.

[0071] In an example, the first sub-pixel PIX1 is a blue sub-pixel; the second sub-pixel PIX2 is a red sub-pixel; and the third sub-pixel PIX3 is a green sub-pixel.

[0072] Figure 3 The cross-sectional structure diagram of a display panel in the embodiment of the present disclosure is illustrated. The display panel includes a base substrate BP, a driving circuit layer FA and a pixel layer FB which are stacked in sequence.

[0073] The substrate substrate BP may be a substrate substrate BP of an inorganic material, or may be a substrate substrate BP of an organic material. For example, in one embodiment of the present disclosure, the material of the substrate substrate BP may be a glass material such as soda-lime glass, quartz glass, sapphire glass, or may be a metal material such as stainless steel, aluminum, nickel, etc. In another embodiment of the present disclosure, the material of the substrate substrate BP may be polymethylmethacrylate (PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) or a combination thereof. In another embodiment of the present disclosure, the substrate substrate BP may also be a flexible substrate substrate BP, for example, the material of the substrate substrate BP may be polyimide (PI). The substrate BP may also be a composite of multiple layers of materials. For example, in one embodiment of the present disclosure, the substrate BP may include a bottom film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer stacked in sequence.

[0074] As an example, in Figure 3 In the embodiment, the material of the base substrate BP is polyimide, so that the display panel is a flexible display panel. Figure 3 The display panel can be first formed on a support substrate SBP, and the support substrate SBP can be peeled off after the preparation is completed. In this way, during the process, the support substrate SBP can provide support for the display panel.

[0075] The driving circuit layer FA is provided with a pixel driving circuit PDC for driving sub-pixels. The driving circuit layer FA includes a transistor layer, and each transistor of the pixel driving circuit PDC of the display unit DU is provided in the transistor layer. In the driving circuit layer FA, any pixel driving circuit PDC may include a transistor and a storage capacitor. Figure 3In the example, the driving circuit layer may be provided with a polysilicon semiconductor layer SEMI1 and a metal oxide semiconductor layer SEMI2, so that the transistors in the driving circuit layer may include metal oxide transistors and polysilicon transistors (e.g., low-temperature polysilicon transistors) at the same time. Furthermore, these transistors may be thin film transistors. Of course, in other embodiments of the present disclosure, the polysilicon transistors may also be amorphous silicon transistors; accordingly, the polysilicon semiconductor layer SEMI1 of the driving circuit layer may be replaced by an amorphous silicon semiconductor layer.

[0076] In one embodiment of the present disclosure, the polysilicon transistor may be a top-gate thin film transistor, a bottom-gate thin film transistor or a dual-gate thin film transistor, whichever is more effective in controlling the transistor. The metal oxide transistor is a dual-gate thin film transistor, that is, the channel region of the transistor is sandwiched between the top gate (the gate on the side away from the substrate) and the bottom gate (the gate on the side close to the substrate); in this way, the bottom gate can block light from the substrate side, preventing light from irradiating the channel region of the transistor and causing abnormal operation of the transistor.

[0077] In some embodiments of the present disclosure, the gate of the polysilicon transistor can be arranged in the same layer as a gate of the metal oxide transistor, for example, the gate of the polysilicon transistor and the bottom gate of the metal oxide transistor are arranged in the same gate layer. In other embodiments, the gate of the polysilicon transistor and the top gate and the bottom gate of the metal oxide transistor can be arranged in different gate layers respectively.

[0078] As an example, see Figure 3 , the driving circuit layer includes a polysilicon semiconductor layer SEMI1, a first gate insulating layer GI1, a first gate layer GT1, a second buffer layer Buff2, a second gate layer GT2, a second gate insulating layer GI2, a metal oxide semiconductor layer SEMI2, a third gate insulating layer GI3, and a third gate layer GT3, which are sequentially stacked on one side of the substrate BP. Among them, the polysilicon semiconductor layer SEMI1 is provided with an active area of ​​a polysilicon transistor, and the first gate layer GT1 is provided with a gate of a polysilicon transistor. The metal oxide semiconductor layer SEMI2 is provided with an active area of ​​a metal oxide transistor; the second gate layer GT2 is provided with a bottom gate of a metal oxide transistor; and the third gate layer GT3 is provided with a top gate of a metal oxide transistor. In the present disclosure, the active area of ​​the transistor includes a channel area of ​​the transistor and a source and a drain located on both sides of the channel area; wherein the channel area maintains semiconductor characteristics, and the source and the drain are conductorized.

[0079] In one example, the display panel further has control wirings for applying control signals to the gates of the transistors. These control wirings may extend substantially along the row direction and be electrically connected to the gates of the driven transistors.

[0080] In the embodiment of the present disclosure, the driving circuit layer also includes a metal layer, which is located on the side of each gate layer and semiconductor layer away from the substrate BP. The metal layer is provided with a data line DL for loading a data voltage Data and a driving voltage line VDDL for loading a driving voltage VDD; the data line DL is used to load the data voltage Data to the pixel driving circuit PDC, so that the pixel driving circuit PDC controls the brightness of the sub-pixel according to the voltage value of the data voltage Data. Figure 3 In the example, the metal layer is three layers, including a first source-drain metal layer SD1, a transfer metal layer DRL, and a second source-drain metal layer SD2 that are stacked. An interlayer dielectric layer ILD is arranged on the surface of the first source-drain metal layer SD1 close to the substrate BP, a first planarization layer PLN1 is arranged between the first source-drain metal layer SD1 and the transfer metal layer DRL, a second planarization layer PLN2 is arranged between the transfer metal layer DRL and the second source-drain metal layer SD2, and a third planarization layer PLN3 is arranged on the side of the second source-drain metal layer SD2 away from the substrate BP.

[0081] Optionally, the driving circuit layer FA may further include a first buffer layer Buff1 disposed between the substrate BP and the semiconductor layer, and the semiconductor layer and the gate layer are all located on a side of the first buffer layer Buff1 away from the substrate BP. The material of the first buffer layer Buff1 may be an inorganic insulating material such as silicon oxide or silicon nitride. The first buffer layer Buff1 may be a single inorganic material layer or a plurality of stacked inorganic material layers.

[0082] Optionally, the driving circuit layer FA may also include a metal shading layer LS located between the first buffer layer Buff1 and the substrate BP, and the metal shading layer LS may shield at least part of the channel region of the transistor. Furthermore, in some embodiments, the metal shading layer LS may be electrically connected to the metal layer through a via, so that the metal shading layer LS may transmit signals, shield signals or perform other functions as needed. For example, the metal shading layer LS may be loaded with a common electrode voltage so that the metal shading layer LS can achieve the function of signal shielding. For another example, a portion of the metal shading layer LS is patterned into a conductive wire so that the conductive wire located in the metal shading layer LS can be used to transmit signals, such as transmitting touch signals.

[0083] Optionally, an inorganic barrier layer Barr may be provided between the metal light shielding layer LS and the first buffer layer Buff1 to prevent the material in the base substrate BP from penetrating into the driving circuit layer.

[0084] The pixel layer FB is provided with light-emitting elements distributed in an array, and each light-emitting element emits light under the control of a pixel driving circuit. These light-emitting elements can be used as sub-pixels of an embodiment of the present disclosure. In the present disclosure, the light-emitting element may be an organic light-emitting diode (OLED), a micro light-emitting diode (Micro LED), a quantum dot-organic light-emitting diode (QD-OLED), a quantum dot light-emitting diode (QLED) or other types of light-emitting elements. Exemplarily, as follows, taking the light-emitting element as an organic light-emitting diode as an example, a feasible structure of the pixel layer is exemplarily introduced.

[0085] In this example, the pixel layer FB can be arranged on the side of the driving circuit layer FA away from the base substrate BP, which may include a pixel electrode layer ANL, a pixel definition layer PDL, a support column layer PS, an organic light-emitting functional layer EL and a common electrode layer COML stacked in sequence. Among them, the pixel electrode layer ANL has a plurality of pixel electrodes in the display area of ​​the display panel; the pixel definition layer PDL has a plurality of through pixel openings arranged one by one corresponding to the plurality of pixel electrodes in the display area, and any pixel opening exposes at least a portion of the corresponding pixel electrode. The support column layer PS includes a plurality of support columns in the display area, and the support columns are located on the surface of the pixel definition layer PDL away from the base substrate BP so as to support the fine metal mask (FineMetal Mask, FMM) in the evaporation process. The organic light-emitting functional layer EL at least covers the pixel electrode exposed by the pixel definition layer PDL. Among them, the organic light-emitting functional layer EL may include an organic electroluminescent material layer, and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer and an electron injection layer. Each film layer of the organic light-emitting functional layer EL can be prepared by an evaporation process, and a fine metal mask or an open mask can be used to define the pattern of each film layer during evaporation. The common electrode layer COML can cover the organic light-emitting functional layer EL in the display area. In this way, the pixel electrode, the common electrode layer COML and the organic light-emitting functional layer EL located between the pixel electrode and the common electrode layer COML form an organic electroluminescent diode, and any organic electroluminescent diode can be used as a sub-pixel of the display panel. In this embodiment, see Fig.17 The sub-pixel PIX may include sub-pixels PIX of multiple different colors, for example, a red sub-pixel R for emitting red light, a blue sub-pixel B for emitting blue light, and a green sub-pixel G for emitting green light.

[0086] In some embodiments, the pixel layer FB may further include a light extraction layer located on a side of the common electrode layer COML away from the substrate BP to enhance the light extraction efficiency of the organic light emitting diode.

[0087] Optionally, the display panel may further include a thin film encapsulation layer TFE. The thin film encapsulation layer TFE is disposed on the surface of the pixel layer FB away from the base substrate BP, and may include an inorganic encapsulation layer and an organic encapsulation layer alternately stacked. Among them, the inorganic encapsulation layer can effectively block external moisture and oxygen, and prevent water and oxygen from invading the organic light-emitting functional layer EL and causing material degradation. Optionally, the edge of the inorganic encapsulation layer may be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce the stress between the inorganic encapsulation layers. Among them, the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the side of the pixel layer FB away from the base substrate BP.

[0088] In one embodiment of the present disclosure, the pixel driving circuit PDC includes a storage capacitor Cst and a plurality of transistors, wherein a portion of the transistors may be polysilicon transistors and another portion may be metal oxide transistors.

[0089] Figure 4 A pixel driving circuit PDC is provided as an example. Figure 4 , the exemplary pixel driving circuit PDC includes transistors such as a storage capacitor Cst, a threshold compensation transistor T2, a driving transistor T3, a capacitor reset transistor T1, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6 and a pixel electrode reset transistor T7. Among them, the threshold compensation transistor T2 is a metal oxide transistor, which is used to compensate the threshold voltage of the driving transistor T3 in response to the threshold compensation signal GN1. The driving transistor T3 is a polysilicon transistor, which can generate a driving current under the control of the first node N1. It can be understood that in other examples of the present disclosure, the pixel driving circuit PDC may also include other transistors or a storage capacitor Cst, or may have fewer transistors; the electrical connection relationship between the transistors and the loaded signals and the timing of the loaded signals may also be the same as Figure 3 The pixel driving circuit PDC shown in the example is different.

[0090] As follows, Figure 4 Taking the exemplary pixel driving circuit PDC as an example, the structure, principle and effect of the display panel according to the embodiment of the present disclosure are further introduced and illustrated.

[0091] exist Figure 4In the example pixel driving circuit PDC, the first electrode plate of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode plate of the storage capacitor Cst is used to load the driving voltage VDD. In this way, the voltage loaded on the second electrode plate of the storage capacitor Cst is stable. In some other embodiments of the present disclosure, the second electrode plate of the storage capacitor Cst can be loaded with other power supply voltages, such as the same common voltage as the common electrode layer. Of course, in other embodiments of the present disclosure, the voltage of the second electrode plate of the storage capacitor may not be constant, for example, the drain of the capacitor reset transistor and the drain of the data write transistor are electrically connected to the second electrode plate of the storage capacitor; the capacitor reset transistor is used to reset the voltage of the second electrode plate of the storage capacitor, and the data write transistor is used to load the data voltage to the second electrode plate of the storage capacitor; through coupling, the voltage of the first node can be adjusted as the voltage of the second electrode plate of the storage capacitor is adjusted.

[0092] exist Figure 4 In the exemplary pixel driving circuit PDC, the pixel driving circuit PDC further includes a first light-emitting control transistor T5 and a second light-emitting control transistor T6, the source of the first light-emitting control transistor T5 is used to load the driving voltage VDD, for example, electrically connected to the data routing DL for loading the driving voltage VDD. The drain of the first light-emitting control transistor T5 is electrically connected to the third node N3. The source of the second light-emitting control transistor T6 is electrically connected to the second node N2, and the drain of the second light-emitting control transistor T6 is electrically connected to the fourth node N4, and the fourth node N4 is also electrically connected to the pixel electrode of the sub-pixel. The gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6 are used to load the light-emitting control signal EM, for example, electrically connected to the light-emitting control routing EML for loading the light-emitting control signal EM. When the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on in response to the light-emitting control signal EM, the driving current generated by the driving transistor T3 can flow to the sub-pixel, thereby driving the sub-pixel to emit light. Further, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 can be polysilicon transistors. Of course, in other embodiments of the present disclosure, the pixel driving circuit PDC may include only one of the first light emission control transistor T5 and the second light emission control transistor T6.

[0093] exist Figure 4In the example pixel driving circuit PDC, the pixel driving circuit PDC also includes a capacitor reset transistor T1 and a data write transistor T4. The source of the capacitor reset transistor T1 is used to load the first initialization voltage Vinit1, and the drain of the capacitor reset transistor T1 is electrically connected to the first node N1; the capacitor reset transistor T1 is used to load the first initialization voltage Vinit1 to the first node N1 in response to the capacitor reset signal GN2, so as to reset the first node N1. In this example, the capacitor reset transistor T1 is a metal oxide semiconductor transistor; in other examples of the present disclosure, the capacitor reset transistor T1 can also be a polysilicon transistor. The data write transistor T4 is a polysilicon transistor. The source of the data write transistor T4 is used to load the data voltage Data, for example, electrically connected to the data line DL for loading the data voltage Data; the drain of the data write transistor T4 is electrically connected to the third node N3; the data write transistor T4 is used to load the data voltage Data to the third node N3 in response to the data scan signal GP.

[0094] exist Figure 4 In the example pixel driving circuit PDC, the pixel driving circuit PDC also includes a pixel electrode reset transistor T7, which is a polysilicon transistor; the source of the pixel electrode reset transistor T7 is used to load the second initialization voltage Vinit2, for example, electrically connected to the second initialization voltage wiring Vinit2L used to load the second initialization voltage Vinit2. The drain of the pixel electrode reset transistor T7 is electrically connected to the fourth node N4, and the pixel electrode reset transistor T7 is used to load the second initialization voltage Vinit2 to the fourth node N4 in response to the pixel electrode reset signal RP, thereby resetting the pixel electrode of the sub-pixel. Of course, in other embodiments of the present disclosure, the pixel driving circuit PDC may not include the pixel electrode reset transistor T7, or the pixel electrode reset transistor T7 may be a metal oxide thin film transistor.

[0095] exist Figure 4 In the example pixel driving circuit PDC, the first initialization voltage Vinit1 loaded by the source of the capacitor reset transistor T1 and the second initialization voltage Vinit2 loaded by the source of the pixel electrode reset transistor T7 can be different voltage signals, for example, they can be voltage signals from different wirings (the voltages can be the same). In other examples of the present disclosure, the first initialization voltage Vinit1 loaded by the source of the capacitor reset transistor T1 and the second initialization voltage Vinit2 loaded by the source of the pixel electrode reset transistor T7 can also be the same signal, for example, a signal from the same wiring.

[0096] In the display panel of the present disclosure, Figure 4The pixel driving circuit PDC shown can work in sequence according to the following timing. In the capacitor reset stage, the gate of the capacitor reset transistor T1 is loaded with the capacitor reset signal GN2 and turned on, so that the first node N1 is reset to the first initialization voltage Vinit1. At this time, under the control of the first node N1, the driving transistor T3 is turned on. The threshold compensation transistor T2, the first light emission control transistor T5, the second light emission control transistor T6, the data writing transistor T4, and the pixel electrode reset transistor T7 remain turned off.

[0097] In the data writing stage, the gate of the data writing transistor T4 is loaded with the data scanning signal GP so that the data writing transistor T4 is turned on, so that the data voltage Data is written to the third node N3; the gate of the threshold compensation transistor T2 is loaded with the threshold compensation signal GN1 so that the threshold compensation transistor T2 is turned on. The capacitor reset transistor T1, the first light emitting control transistor T5, and the second light emitting control transistor T6 remain cut off. In this way, the third node N3 can charge the first node N1 so that the voltage of the first node N1 is pulled up until the first node N1 is pulled up to make the driving transistor T3 cut off. In this way, the data voltage Data and the threshold voltage of the driving transistor T3 are written into the first node N1, and the voltage of the first node N1 is VData+Vth3, Vth3 is the threshold voltage of the driving transistor T3, and VData is the voltage value of the data voltage Data. In this way, in the data writing stage, data writing and threshold compensation of the driving transistor T3 are realized at the same time.

[0098] In the pixel electrode reset stage, the gate of the pixel electrode reset transistor T7 is loaded with the pixel electrode reset signal RP, so that the pixel electrode reset transistor T7 is turned on, and then the second initialization voltage Vinit2 is loaded to the fourth node N4. In some embodiments, the pixel electrode reset signal RP of the pixel driving circuit PDC of the previous row and the data scanning signal GP of the pixel driving circuit PDC of the next row are the same signal, so that when the pixel driving circuit PDC of the previous row is in the pixel electrode reset stage, the pixel driving circuit PDC of the next row is in the data writing stage. Of course, in other examples of the present disclosure, the pixel electrode reset signal RP and the data scanning signal GP of the pixel driving circuit PDC of the same row can be the same signal, and the pixel electrode reset stage and the data writing stage of the pixel driving circuit PDC of this row are the same stage, that is, the data writing transistor T4 and the pixel electrode reset transistor T7 are synchronously turned on or off.

[0099] In the light emitting stage, the gate of the first light emitting control transistor T5 and the gate of the second light emitting control transistor T6 are loaded with the light emitting control signal EM, so that the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on. In this way, the driving voltage VDD is loaded to the third node N3, and the second node N2 is electrically connected to the sub-pixel; the driving transistor T3 outputs the driving current under the control of the first node N1, thereby driving the sub-pixel to emit light.

[0100] It is understandable that the pixel driving circuit PDC of 7T1C (7 transistors and 1 storage capacitor) in the above example of the present disclosure is only one of the exemplary pixel driving circuits PDC of the display panel of the present disclosure, rather than a specific limitation of the pixel driving circuit PDC used in the display panel of the present disclosure. In other embodiments of the present disclosure, the pixel driving circuit PDC may include more or fewer transistors, for example, 8 transistors, 9 transistors, etc., and one or more of the transistors illustrated in the above 7T1C may also be set as a plurality of sub-transistors connected in series in sequence. In other embodiments of the present disclosure, the pixel driving circuit PDC may include more storage capacitors Cst, for example, two or three storage capacitors.

[0101] In the display panel disclosed in the present invention, the pixel driving circuit PDC can reduce the leakage of the first node N1 by setting the threshold compensation transistor T2 as a metal oxide transistor, thereby improving the voltage holding capability of the pixel driving circuit PDC, reducing the flicker risk of the display panel under low-frequency driving and reducing the power consumption of the display panel.

[0102] As follows, the specific layout of the pixel driving circuit PDC of the above-mentioned 7T1C example in the display panel is introduced and explained in conjunction with the accompanying drawings. It can be understood that the 7T1C exampled in the embodiments of the present disclosure can also be presented in other layout modes, and the display panel of the present disclosure can also adopt other pixel driving circuits PDC. When other pixel driving circuit PDC structures are adopted, the layout mode of the pixel driving circuit PDC in the display panel of the present disclosure can be adjusted accordingly.

[0103] See also Figure 3In the display panel of this example, the driving circuit layer FA includes a metal light shielding layer LS, an inorganic barrier layer Barr, a first buffer layer Buff1, a polysilicon semiconductor layer SEMI1, a first gate insulating layer GI1, a first gate layer GT1, a second buffer layer Buff2, a second gate layer GT2, a second gate insulating layer GI2, a metal oxide semiconductor layer SEMI2, a third gate insulating layer GI3, a third gate layer GT3, an interlayer dielectric layer ILD, a first source-drain metal layer SD1, a first planarization layer PLN1, a transfer metal layer DRL, a second planarization layer PLN2, a second source-drain metal layer SD2, and a third planarization layer PLN3, which are sequentially stacked on one side of the substrate BP. It can be understood that in some other embodiments of the display panel disclosed in the present invention, the metal light shielding layer LS may not be provided.

[0104] In the display area AA, the main area where the pixel driving circuit PDC is arranged can be defined as the circuit layout area PDCA corresponding to the pixel driving circuit PDC. In this way, the main or most transistors and storage capacitors Cst of the pixel driving circuit PDC are arranged in the corresponding circuit layout area PDCA. Figure 5 , the circuit layout area PDCA can be a rectangle. In two adjacent rows of pixel driving circuits PDC, the pixel electrode reset transistor T7 of the upper row of pixel driving circuits PDC can be arranged in the circuit layout area PDCA corresponding to the next row of pixel driving circuits PDC. In other words, the capacitor reset transistor T1 to the second light emitting control transistor T6 and the storage capacitor Cst of the pixel driving circuit PDC are arranged in the circuit layout area PDCA corresponding to the pixel driving circuit PDC, and the pixel electrode reset transistor T7 of the pixel driving circuit PDC is arranged in the circuit layout area PDCA of the next row. In the example of the present disclosure, the layout of two adjacent pixel driving circuits PDC can be arranged in a mirror image. Of course, in other embodiments of the present disclosure, the layout of two adjacent pixel driving circuits PDC can also be the same instead of a mirror image.

[0105] Figure 6 FIG. 1 shows a partial structural diagram of a metal light shielding layer LS of a display panel according to an example of the present disclosure. Figure 6 In the circuit layout area PDCA, the metal light shielding layer LS has a metal light shielding portion LSP and a connecting line LSL; the metal light shielding portions LSP adjacent to each other in the same row and in the same column are connected by the connecting line LSL. In this way, the metal light shielding layer LS is in a grid shape, which can shield external signals and prevent signals outside the display panel from affecting the normal display of the display panel. The metal light shielding portion LSP needs to have a larger size to shield the light irradiating the channel region of the driving transistor T3 to ensure the stability of the characteristics of the driving transistor T3.

[0106] Figure 7A partial structural schematic diagram of a polycrystalline silicon semiconductor layer SEMI1 of a display panel according to an example of the present disclosure is shown. Figure 8 FIG. 1 is a schematic diagram showing a partial structure of the first gate layer GT1 of the display panel of the present disclosure. Figure 7 The polysilicon semiconductor layer SEMI1 has a polysilicon pattern corresponding to each pixel driving circuit PDC. The polysilicon pattern forms a channel region T3Act of a driving transistor T3 with semiconductor characteristics, a channel region T4Act of a data writing transistor T4, a channel region T5Act of a first light-emitting control transistor T5, a channel region T6Act of a second light-emitting control transistor T6, and a channel region T7Act of a pixel electrode reset transistor T7, as well as a first polysilicon strip PL1, a second polysilicon strip PL2, a third polysilicon strip PL3, a fourth polysilicon strip PL4, a fifth polysilicon strip PL5, and a sixth polysilicon strip PL6 that are conductorized. The first polysilicon strip PL1, the second polysilicon strip PL2, the third polysilicon strip PL3, the fourth polysilicon strip PL4, the fifth polysilicon strip PL5, and the sixth polysilicon strip PL6 can be conductorized after the first gate layer GT1 is patterned. See Figure 7 The first polysilicon strip PL1 is electrically connected to one end of the channel region T4Act of the data writing transistor T4 and serves as the source of the data writing transistor T4. The second polysilicon strip PL2 is electrically connected to the other end of the channel region T4Act of the data writing transistor T4, one end of the channel region T3Act of the driving transistor T3, and one end of the channel region T5Act of the first light emission control transistor T5 and serves as a part of the third node N3, and serves as the drain of the data writing transistor T4, the source of the driving transistor T3, and the drain of the first light emission control transistor T5. The third polysilicon strip PL3 is electrically connected to the other end of the channel region T5Act of the first light emission control transistor T5 and serves as the source of the first light emission control transistor T5. The fourth polysilicon strip PL4 is electrically connected to the other end of the channel region T3Act of the driving transistor T3 and one end of the channel region T6Act of the second light emission control transistor T6 and serves as a part of the second node N2, and serves as the drain of the driving transistor T3 and the source of the second light emission control transistor T6. The fifth polysilicon strip PL5 is electrically connected to the other end of the channel region T6Act of the second light emission control transistor T6 and one end of the channel region T7Act of the pixel electrode reset transistor T7 to serve as a part of the fourth node N4, and also serves as the drain of the second light emission control transistor T6 and the drain of the pixel electrode reset transistor T7. The sixth polysilicon strip PL6 is electrically connected to the other end of the channel region T7Act of the pixel electrode reset transistor T7 to serve as the source of the pixel electrode reset transistor T7. Figure 7The channel region T7Act of the pixel electrode reset transistor T7 of the polysilicon pattern corresponding to the pixel driving circuit PDC, a portion of the sixth polysilicon strip PL6 and the fifth polysilicon strip PL5 can be arranged in the circuit layout area PDCA corresponding to the next row of pixel driving circuits PDC; correspondingly, the channel region T7Act of the pixel electrode reset transistor T7 of the previous row of pixel driving circuits PDC, the sixth polysilicon strip PL6 and a portion of the fifth polysilicon strip PL5 are arranged in the circuit layout area PDCA corresponding to the pixel driving circuit PDC.

[0107] See also Figure 7 , the channel region T3Act of the driving transistor T3 is bent so that the channel region T3Act of the driving transistor T3 has a longer length, for example, a length of 15 to 25 microns. Further, the orthographic projection of the area where the channel region T3Act of the driving transistor T3 is distributed on the metal light shielding layer LS can be completely located within the metal light shielding portion LSP. In this way, the metal light shielding portion LSP can shield the channel region T3Act of the driving transistor T3. See Figure 5 and Figure 8 The first gate layer GT1 is provided with a first electrode plate CP1 of a storage capacitor Cst, and the first electrode plate CP1 of the storage capacitor Cst completely covers the channel region T3Act of the driving transistor T3; that is, the positive projection of the channel region T3Act of the driving transistor T3 on the first gate layer GT1 is located within the range of the first electrode plate CP1 of the storage capacitor Cst. In this way, the first electrode plate CP1 of the storage capacitor Cst can serve as the gate of the driving transistor T3.

[0108] See also Figure 7 , the channel region T4Act of the data writing transistor T4 of the next row pixel driving circuit PDC is arranged adjacent to the channel region T7Act of the pixel electrode reset transistor T7 of the previous row pixel driving circuit PDC. Figure 5 and Figure 8 The first gate layer GT1 is provided with a data scanning line GPL for loading a data scanning signal GP and extending substantially along the row direction. The data scanning line GPL overlaps with the channel region T4Act of the data writing transistor T4; the portion where the data scanning line GPL overlaps with the channel region T4Act of the data writing transistor T4 can be reused as the gate T4G of the data writing transistor T4. The data scanning line GPL also overlaps with the channel region T7Act of the pixel electrode reset transistor T7, so that the portion where the data scanning line GPL overlaps with the channel region T7Act of the pixel electrode reset transistor T7 can be reused as the gate of the pixel electrode reset transistor T7; the data scanning signal GP loaded on the data scanning line GPL can be used as the pixel electrode reset signal RP at the same time, so that the data scanning line GPL can be reused as the pixel electrode reset line RPL.

[0109] See also Figure 5 , Figure 7 and Figure 8 , the channel region T5Act of the first light emission control transistor T5 and the channel region T6Act of the second light emission control transistor T6 are arranged in the same row or substantially in the same row. The first gate layer GT1 is provided with a light emission control trace EML for loading the light emission control signal EM and extending substantially along the row direction. The light emission control trace EML overlaps with the channel region T5Act of the first light emission control transistor T5 and the channel region T6Act of the second light emission control transistor T6; the portion where the light emission control trace EML overlaps with the channel region T5Act of the first light emission control transistor T5 is reused as the gate of the first light emission control transistor T5, and the portion where the light emission control trace EML overlaps with the channel region T6Act of the second light emission control transistor T6 is reused as the gate of the second light emission control transistor T6.

[0110] Fig. 9 A schematic diagram of a partial structure of a second gate layer GT2 of a display panel according to an example of the present disclosure is shown. Fig.10 A schematic diagram of a partial structure of a metal oxide semiconductor layer SEMI2 of a display panel according to an example of the present disclosure is shown. Fig.11 A partial structural schematic diagram of the third gate layer GT3 of the display panel of the example of the present disclosure is shown.

[0111] See also Fig.10The metal oxide semiconductor layer SEMI2 has a metal oxide pattern corresponding to each pixel driving circuit PDC, and the metal oxide pattern of the pixel driving circuit PDC is completely located in the circuit layout area PDCA corresponding to the pixel driving circuit PDC. Among them, the metal oxide pattern of the pixel driving circuit PDC and the orthographic projection of the polysilicon pattern on the substrate BP do not overlap. The metal oxide pattern of the pixel driving circuit PDC includes a channel region T1Act of the capacitor reset transistor T1 and a channel region T2Act of the threshold compensation transistor T2 that maintain semiconductor characteristics, and a first metal oxide portion OL1, a second metal oxide portion OL2, and a third metal oxide portion OL3 that are conductorized. Among them, the first metal oxide portion OL1, the second metal oxide portion OL2, and the third metal oxide portion OL3 can be conductorized after the third gate layer GT3 is patterned. The second metal oxide portion OL2 is electrically connected to one end of the channel region T1Act of the capacitor reset transistor T1 and one end of the channel region T2Act of the threshold compensation transistor T2 to serve as a part of the first node N1, and also serves as the drain of the capacitor reset transistor T1 and the drain of the threshold compensation transistor T2. The first metal oxide portion OL1 is electrically connected to the other end of the channel region T1Act of the capacitor reset transistor T1 to serve as the source of the capacitor reset transistor T1; the third metal oxide portion OL3 is electrically connected to the other end of the channel region T2Act of the threshold compensation transistor T2 to serve as the source of the threshold compensation transistor T2.

[0112] See also Figure 5 and Fig.11 The third gate layer GT3 is provided with a capacitor reset top routing GN2UL and a threshold compensation top routing GN1UL extending substantially along the row direction. The capacitor reset top routing GN2UL is used to load the capacitor reset signal GN2, and has a channel definition portion GN2ULP of the capacitor reset top routing GN2UL overlapping with the channel region T1Act of the capacitor reset transistor T1. The portion where the channel definition portion GN2ULP of the capacitor reset top routing GN2UL overlaps with the channel region T1Act of the capacitor reset transistor T1 is reused as the top gate T1GU of the capacitor reset transistor T1, and is used to define the boundary of the channel region T1Act of the capacitor reset transistor T1 in its length direction. The threshold compensation top routing GN1UL is used to load the threshold compensation signal GN1, and has a channel defining portion GN1ULP of the threshold compensation top routing GN1UL that overlaps with the channel region T2Act of the threshold compensation transistor T2. The portion of the channel defining portion GN1ULP of the threshold compensation top routing GN1UL that overlaps with the channel region T2Act of the threshold compensation transistor T2 is reused as the top gate T2GU of the threshold compensation transistor T2, and is used to define the boundary of the channel region T2Act of the threshold compensation transistor T2 in the length direction.

[0113] See also Figure 5and Fig. 9 The second gate layer GT2 is provided with a capacitor reset bottom wiring GN2DL and a threshold compensation bottom wiring GN1DL extending substantially along the row direction, and a second electrode plate CP2 provided with storage capacitors Cst corresponding to each pixel driving circuit PDC. The capacitor reset bottom wiring GN2DL is used to load the capacitor reset signal GN2, and has an enlarged portion GN2DLP of the capacitor reset bottom wiring GN2DL overlapping with the channel region T1Act of the capacitor reset transistor T1, and the positive projection of the channel definition portion GN2ULP of the capacitor reset top wiring GN2UL on the second gate layer GT2 is completely located in the enlarged portion GN2DLP of the capacitor reset bottom wiring GN2DL, so that the positive projection of the channel region T1Act of the capacitor reset transistor T1 on the second gate layer GT2 is completely located in the enlarged portion GN2DLP of the capacitor reset bottom wiring GN2DL. In this way, the enlarged portion GN2DLP of the capacitor reset bottom wiring GN2DL can not only load the capacitor reset signal GN2 to the channel region T1Act of the capacitor reset transistor T1 to eliminate the floating body effect of the capacitor reset transistor T1, but also shield the light on the side of the substrate BP so that the channel region T1Act of the capacitor reset transistor T1 maintains stable performance. The threshold compensation bottom wiring GN1DL is used to load the threshold compensation signal GN1, and has an enlarged portion GN1DLP of the threshold compensation bottom wiring GN1DL overlapping with the channel region T2Act of the threshold compensation transistor T2, and the positive projection of the channel definition portion GN1ULP of the threshold compensation top wiring GN1UL on the second gate layer GT2 is completely located in the enlarged portion GN1DLP of the threshold compensation bottom wiring GN1DL, so that the positive projection of the channel region T2Act of the threshold compensation transistor T2 on the second gate layer GT2 is completely located in the enlarged portion GN1DLP of the threshold compensation bottom wiring GN1DL. In this way, the enlarged portion GN1DLP of the threshold compensation bottom wiring GN1DL can not only load the threshold compensation signal GN1 to the channel area T2Act of the threshold compensation transistor T2 to eliminate the floating body effect of the threshold compensation transistor T2, but also shield the light on the side of the substrate BP to keep the channel area T2Act of the threshold compensation transistor T2 stable.

[0114] See also Figure 5 and Figure 8 , Fig. 9 The second electrode plate CP2 of the storage capacitor Cst overlaps with the first electrode plate CP1 of the storage capacitor Cst to form the storage capacitor Cst. The second electrode plate CP2 of the storage capacitor Cst has a notch CP2G, and the notch CP2G exposes a portion of the first electrode plate CP1 of the storage capacitor Cst, so that the first electrode plate CP1 of the storage capacitor Cst can be connected to the first source-drain metal layer SD1 through a via located in the notch CP2G. Fig. 9The second gate layer GT2 may also be provided with a first initialization voltage trace Vinit1L for loading the first initialization voltage Vinit1, and the first initialization voltage trace Vinit1L extends substantially along the row direction. Further, the capacitor reset bottom trace GN2DL is located between the threshold compensation bottom trace GN1DL and the first initialization voltage trace Vinit1L.

[0115] Fig.12 A schematic diagram of the partial structure of the first source-drain metal layer SD1 of the display panel of the example of the present disclosure is shown. Fig.13 A partial structural diagram of a second gate layer GT2, a metal oxide semiconductor layer SEMI2, a third gate layer GT3, and a first source-drain metal layer SD1 of a display panel according to an example of the present disclosure is shown. Fig.14 A schematic diagram of a partial structure of a transfer metal layer DRL of a display panel according to an example of the present disclosure is shown.

[0116] See also Figure 5 , Fig.12 and Fig.13 In the circuit layout area PDCA, the first source-drain metal layer SD1 is provided with the first conductive structure ML1 to the sixth conductive structure ML6, and a second initialization voltage trace Vinit2L extending substantially along the row direction and used to load the second initialization voltage Vinit2 is provided. The second initialization voltage trace Vinit2L can be bent in the circuit layout area PDCA to avoid other conductive structures.

[0117] Fig.14 A schematic structural diagram showing a transfer metal layer DRL in a circuit layout area corresponding to eight local sub-pixels of a display panel according to an example of the present disclosure; Fig.15 A schematic structural diagram showing a second source-drain metal layer SD2 in a circuit layout area corresponding to eight local sub-pixels of a display panel according to an example of the present disclosure; Fig.16 A schematic diagram showing the structural coordination of a transfer metal layer DRL and a second source-drain metal layer SD2 in a circuit layout area corresponding to eight local sub-pixels of a display panel according to an example of the present disclosure.

[0118] like Figure 14 to Figure 16As shown, the second source-drain metal layer SD2 includes a data line DL and a driving voltage line VDDL, and a pixel transfer structure PA; the data line DL includes the first data line DL1, the second data line DL2, the third data line DL3A and the fourth data line DL3B. In the circuit layout diagram of each display unit DU, the transfer metal layer DRL is provided with a second transfer metal structure TRP2 and a third transfer metal structure TRP3. Among them, the second transfer metal structure TRP2 is electrically connected to the pixel transfer structure PA through a via hole, and is electrically connected to the output end of the pixel driving circuit through a via hole, for example, it is electrically connected to the sixth conductive structure ML6 located in the first source-drain metal layer through a via hole. The pixel transfer structure PA is electrically connected to the pixel electrode of the sub-pixel through a via hole. In this way, the driving current of the pixel driving circuit can be loaded to the sub-pixel through the sixth conductive structure ML6, the second transfer metal structure TRP2, and the pixel transfer structure PA. The third transfer metal structure TRP3 is electrically connected to the driving voltage line VDDL through a via, and provides a driving voltage to the pixel driving circuit through the via, for example, it is electrically connected to the second conductive structure ML2 located in the first source-drain metal layer SD1 through a via. In this way, the driving voltage of the driving voltage line VDDL is loaded to the pixel driving circuit through the third transfer metal structure TRP3 and the second conductive structure ML2.

[0119] For a display unit directly connected to an adjacent data line, a first transfer metal structure TRP1 is further provided in the transfer metal layer DRL in the circuit layout area of ​​the display unit. The first transfer metal structure TRP1 is electrically connected to the data line through a via, and a data voltage is loaded to the pixel driving circuit through the via, for example, it is electrically connected to the first conductive structure ML1 of the pixel driving circuit through the via.

[0120] The transfer metal layer DRL is also provided with a first transfer wire TRL1 and a second transfer wire TRL2. Among them, the second display unit DU2 located in the first display unit column VDU1 is electrically connected to the second data line DL2 through the second transfer wire TRL2. For example, the first conductive structure ML1 of the second display unit DU2 located in the first display unit column VDU1 is electrically connected to the first end TRL21 of the second transfer wire TRL2 through a via, and the second end TRL22 of the second transfer wire TRL2 is electrically connected to the second data line DL2 through a via. The first display unit DU1 located in the second display unit column VDU2 is electrically connected to the first data line DL1 through the first transfer wire TRL1. For example, the first conductive structure ML1 of the first display unit DU1 located in the second display unit column VDU2 is electrically connected to the first end TRL11 of the first transfer wire TRL1 through a via, and the second end TRL12 of the first transfer wire TRL1 is electrically connected to the first data line DL1 through a via.

[0121] For example, Fig.14 As shown, in the circuit layout area PDCA of the first display unit DU1 of the first display unit column VDU1, the circuit layout area PDCA of the second display unit DU2 of the second display unit column VDU2, the circuit layout area PDCA of the third display unit DU3 of the third display unit column VDU3A and the fourth display unit column VDU3B, the transfer metal layer DRL includes a first transfer metal structure TRP1, a second transfer metal structure TRP2 and a third transfer metal structure TRP3. In the circuit layout area PDCA corresponding to the pixel driving circuit PDC of the second display unit DU2 of the first display unit column VDU1, the transfer metal layer DRL includes a first end TRL21 of the second transfer line, a second end TRL12 of the first transfer line, a second transfer metal structure TRP2 and a third transfer metal structure TRP3. In the circuit layout area PDCA corresponding to the pixel driving circuit PDC of the first display unit DU1 of the second display unit column VDU2, the transfer metal layer DRL includes the second end TRL22 of the second transfer line, the first end TRL11 of the first transfer line, the second transfer metal structure TRP2 and the third transfer metal structure TRP3; wherein the second end TRL12 of the first transfer line is electrically connected to the first end TRL11 of the first transfer line through TRL1; the second end TRL22 of the second transfer line is electrically connected to the first end TRL21 of the second transfer line through TRL2.

[0122] In one example, the shape of the first end TRL21 of the second adapter wire is the same as the shape of the first adapter metal structure TRP1; the second end TRL22 of the second adapter wire is adjacent to and insulated from the first end TRL11 of the first adapter wire; the shape of the first end TRL11 of the first adapter wire is the same as the shape of the second adapter metal structure TRP2; the second end TRL12 of the first adapter wire is adjacent to and insulated from the first end TRL21 of the second adapter wire.

[0123] like Figure 7 , Fig.12 , Fig.13 , Fig.14 and Fig.15 As shown, the electrical conduction connection relationship between the data voltage and the driving voltage in the driving circuit layer FA in the first display unit DU1 adjacent to the first data line DL1, the second display unit DU2 adjacent to the second data line DL2, and the third display unit DU3 is described in detail as follows. Take the third display unit DU3 in the third display unit column VDU3A as an example.

[0124] The first conductive structure ML1 overlaps with the first polysilicon strip PL1 and is electrically connected through a via hole. The first conductive structure ML1 also overlaps with the first transfer metal structure TRP1 and is electrically connected through a via hole. The first transfer metal structure TRP1 overlaps with the third data line DL3A and is electrically connected through a via hole. In this way, the data voltage Data loaded on the data line DL can be loaded to the first polysilicon strip PL1 as the source of the data writing transistor T4 through the first transfer metal structure TRP1 and the first conductive structure ML1.

[0125] The second conductive structure ML2 overlaps with the third polysilicon strip PL3 and is electrically connected through a via hole, overlaps with the second electrode plate CP2 of the storage capacitor Cst and is electrically connected through a via hole, and also overlaps with the third transfer metal structure TRP3 and is electrically connected through a via hole, and the third transfer metal structure TRP3 overlaps with the driving voltage line VDDL and is electrically connected through a via hole. In this way, the driving voltage VDD loaded on the driving voltage line VDDL can be loaded to the second electrode plate CP2 of the storage capacitor Cst and the third polysilicon strip PL3 as the source of the first light-emitting control transistor T5 through the third transfer metal structure TRP3 and the second conductive structure ML2.

[0126] In one embodiment of the present disclosure, see Fig.12 , two adjacent second conductive structures ML2 are connected, so that two adjacent driving voltage lines VDDL are electrically connected through the second conductive structure ML2. In this way, the driving voltage VDD of the display panel in the display area AA is distributed in a grid, which can improve the signal uniformity of the driving voltage VDD, thereby avoiding the uneven display of the display panel due to the voltage drop or current unevenness of the driving voltage VDD.

[0127] See also Figure 5 , Fig.10 and Fig.12 The third conductive structure ML3 overlaps with the second metal oxide portion OL2 and is electrically connected through a via, and also overlaps with the first electrode plate CP1 of the storage capacitor Cst and is electrically connected through a via. The via between the third conductive structure ML3 and the first electrode plate CP1 of the storage capacitor Cst can pass through the gap CP2G. In this way, the second metal oxide portion OL2, which is the drain of the threshold compensation transistor T2, the drain of the capacitor reset transistor T1, and a part of the first node N1, is electrically connected to the second electrode plate CP2 of the storage capacitor Cst through the third conductive structure ML3.

[0128] The fourth conductive structure ML4 overlaps with the first initialization voltage trace Vinit1L and is electrically connected through a via, and overlaps with the first metal oxide portion OL1 and is electrically connected through a via. In this way, the first metal oxide portion OL1, which serves as the source of the capacitor reset transistor T1, is electrically connected to the first initialization voltage trace Vinit1L through the fourth conductive structure ML4, and the first initialization voltage Vinit1 loaded on the first initialization voltage trace Vinit1L can be loaded to the source of the capacitor reset transistor T1.

[0129] The fifth conductive structure ML5 overlaps and is electrically connected to the third metal oxide portion OL3, and also overlaps and is electrically connected to the fourth polysilicon strip PL4. In this way, the third metal oxide portion OL3, which is the source of the threshold compensation transistor T2, is electrically connected to the fourth polysilicon strip PL4, which is a drain of the driving transistor T3, a source of the second light emission control transistor T6, and a part of the second node N2, through the fifth conductive structure ML5.

[0130] The sixth conductive structure ML6 overlaps with the fifth polysilicon strip PL5 and is electrically connected through a via hole, and also overlaps with the second transfer metal structure TRP2 and is electrically connected through a via hole, and the second transfer metal structure TRP2 overlaps with the pixel transfer structure PA and is electrically connected through a via hole. In this way, the fifth polysilicon strip PL5, which is the drain of the second light-emitting control transistor T6, the drain of the pixel electrode reset transistor T7, and a part of the fourth node N4, is electrically connected to the pixel transfer structure PA through the sixth conductive structure ML6 and the third transfer metal structure TRP3, and the pixel transfer structure PA is used to be electrically connected to the pixel electrode of the sub-pixel, such as Fig.15 and Fig.16 shown.

[0131] In one embodiment of the present disclosure, see Figure 14 to Figure 16, the driving voltage line VDDL has a first avoidance gap on the side close to the first data line DL1; the orthographic projection of the second end TRL12 of the first adapter line TRL1 on the plane where the display panel PNL is located is located within the orthographic projection of the first avoidance gap on the plane where the display panel PNL is located. The driving voltage line VDDL has a second avoidance gap on the side close to the second data line DL2; the orthographic projection of the second end TRL22 of the second adapter line on the plane where the display panel PNL is located is located within the orthographic projection of the second avoidance gap on the plane where the display panel PNL is located. The first data line DL1 has a first side branch portion LBP1 that penetrates into the first avoidance gap, and the first side branch portion LBP1 is electrically connected to the second end TRL12 of the first adapter line TRL1 through a via. The second data line DL2 has a second side branch portion LBP2 that penetrates into the second avoidance gap, and the second side branch portion LBP2 is electrically connected to the second end TRL22 of the second adapter line through a via. In this way, the first conductive structure ML1 corresponding to the first display unit DU1 adjacent to the second data line DL2 is electrically connected to the first end TRL11 of the first adapter line TRL1 through a via, and the second end TRL12 of the first adapter line TRL1 is electrically connected to the first side branch portion LBP1 through a via, and the first side branch portion LBP1 is electrically connected to the first data line DL1.

[0132] In this way, the data voltage loaded on the first data line DL1 can be loaded to the first polysilicon strip PL1 of the source of the data write transistor T4 corresponding to the first display unit DU1 adjacent to the second data line DL2 through the first side branch portion LBP1, the second end TRL12 of the first transfer line TRL1, the first transfer line TRL1, the first end TRL11 of the first transfer line TRL1, and the first conductive structure ML1. Similarly, the first conductive structure ML1 corresponding to the second display unit DU2 adjacent to the first data line DL1 is electrically connected to the first end TRL21 of the second transfer line TRL2 through a via, the second end TRL22 of the second transfer line is electrically connected to the second side branch portion LBP2 through a via, and the second side branch portion LBP2 is electrically connected to the second data line DL2. In this way, the data voltage loaded on the second data line DL2 can be loaded to the first polysilicon strip PL1 of the source of the data writing transistor T4 corresponding to the second display unit DU2 adjacent to the first data line DL1 through the second side branch portion LBP2, the second end TRL22 of the second transfer line, the second transfer line TRL2, the first end TRL21 of the second transfer line TRL2, and the first conductive structure ML1. In this way, the cross-bridge connection between the second display unit DU2 adjacent to the first data line DL1 and the second data line DL2, and the cross-bridge connection between the first display unit DU1 adjacent to the second data line DL2 and the first data line DL1 are realized.

[0133] The disclosed embodiment also provides a method for driving a display panel PNL, the method comprising: driving each DU row by row; when driving any HDU, loading the driving voltage required by the first display unit DU1 of the display unit set DUS onto the first data line DL1 corresponding to the display unit set DUS, and loading the driving voltage required by the second display unit DU2 of the display unit set DUS onto the second data line DL2 corresponding to the display unit set DUS. This allows the data voltage loaded on the first data line DL1 to be written into the pixel driving circuit PDC of the first display unit DU1 of the display unit set DUS, and the data voltage loaded on the second data line DL2 to be written into the pixel driving circuit PDC of the second display unit DU2 of the display unit set DUS, thereby avoiding the additional energy consumption caused by the alternating control of the first display unit DU1 and the second display unit DU2 by the first data line DL1 and the second data line DL2.

[0134] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A display panel, characterized in that: The display unit comprises a plurality of display unit sets sequentially arranged along a row direction; the display unit set comprises a plurality of first display units located in different display unit columns and a plurality of second display units located in different display unit columns; The display panel is also provided with a first data line and a second data line corresponding to the display unit set; each first display unit of the display unit set is electrically connected to the first data line, and each second display unit of the display unit set is electrically connected to the corresponding second data line.

2. The display panel according to claim 1, characterized in that: The display unit set includes a first display unit column arranged adjacent to the first data routing line and a second display unit column arranged adjacent to the second data routing line; the first display unit column includes first display units and second display units arranged alternately in sequence along the column direction; the second display unit column includes second display units and first display units arranged alternately in sequence along the column direction.

3. The display panel according to claim 1, characterized in that: In the same display unit row, the first display units and the second display units are alternately arranged.

4. The display panel according to any one of claims 1 to 3, characterized in that: The display unit set includes a first display unit column, a third display unit column, a second display unit column and a fourth display unit column arranged in sequence along a row direction; the third display unit column and the fourth display unit column each include a plurality of third display units arranged in sequence along a column direction.

5. The display panel according to claim 4, characterized in that: In the same display unit row, each row of sub-pixels includes a first display unit, a second display unit and two third display units.

6. The display panel according to claim 4, characterized in that: The display panel is also provided with a third data routing line and a fourth data routing line corresponding to the display unit set; Each third display unit in the third display unit column is electrically connected to a third data line, and each third display unit in the fourth display unit column is electrically connected to a fourth data line.

7. The display panel according to claim 6, characterized in that: The third data wiring is disposed adjacent to the first data wiring and is located between each pixel driving circuit of the first display unit column and each pixel driving circuit of the third display unit column; The fourth data wiring is disposed adjacent to the second data wiring and is located between each pixel driving circuit of the second display unit column and each pixel driving circuit of the fourth display unit column.

8. The display panel according to claim 7, characterized in that: The display panel is provided with a first adapter wire and a second adapter wire; The second display unit located in the first display unit column is electrically connected to the second data wiring through the second adapter wire; The first display unit located in the second display unit column is electrically connected to the first data wiring through the first adapter wire.

9. The display panel according to claim 1, characterized in that: The display panel comprises a base substrate, a driving circuit layer and a pixel layer which are stacked in sequence; the driving circuit layer comprises a transistor layer, a first source-drain metal layer, a transfer metal layer and a second source-drain metal layer which are stacked in sequence; each transistor of the pixel driving circuit of the display unit is arranged in the transistor layer; and the sub-pixel of the display unit is arranged in the pixel electrode layer; The second source-drain metal layer is provided with the first data wiring and the second data wiring; The transfer metal layer is provided with a first transfer metal structure, a first transfer wire and a second transfer wire; wherein: The data voltage input terminal of the pixel driving circuit of the first display unit adjacent to the first data wiring is electrically connected to the first transfer metal structure corresponding to the first display unit through a via hole; the first transfer metal structure is electrically connected to the first data wiring through a via hole; The data voltage input terminal of the pixel driving circuit of the second display unit adjacent to the second data wiring is electrically connected to the first transfer metal structure corresponding to the second display unit through a via hole, and the first transfer metal structure is electrically connected to the second data wiring through a via hole; The data voltage input terminal of the pixel driving circuit of the first display unit adjacent to the second data wiring is electrically connected to the first end of the first adapter wire through a via hole, and the second end of the first adapter wire is electrically connected to the first data wiring through a via hole; The data voltage input terminal of the pixel driving circuit of the second display unit adjacent to the first data wiring is electrically connected to the first end of the second adapter wire through a via hole, and the second end of the second adapter wire is electrically connected to the second data wiring through a via hole.

10. The display panel according to claim 9, characterized in that: The shape of the first end of the second patch cord is the same as that of the first patch metal structure; the second end of the second patch cord is adjacent to and insulated from the first end of the first patch cord; The shape of the first end of the first transition wire is the same as that of the first transition metal structure; the second end of the first transition wire is adjacent to and insulated from the first end of the second transition wire.

11. The display panel according to claim 9, characterized in that: The second source-drain metal layer also includes a driving voltage wiring; A first avoidance gap is formed on a side of the driving voltage wiring close to the first data wiring; the orthographic projection of the second end of the first adapter wire on the plane where the display panel is located is located within the orthographic projection of the first avoidance gap on the plane where the display panel is located; A second avoidance gap is formed on one side of the driving voltage wiring close to the second data wiring; the orthographic projection of the second end of the second adapter wire on the plane where the display panel is located is located within the orthographic projection of the second avoidance gap on the plane where the display panel is located.

12. The display panel according to claim 11, characterized in that: The first data wiring has a first side branch portion extending deep into the first avoidance gap, and the first side branch portion is electrically connected to the second end of the first adapter wire through a via hole; The second data wiring has a second side branch portion extending deep into the second avoidance gap, and the second side branch portion is electrically connected to the second end of the second adapter wire through a via.

13. A method for driving a display panel according to any one of claims 1 to 12, characterized in that: include: Driving each display unit line by line; When driving any display unit row, the driving voltage required by the first display unit of the display unit set is loaded onto the first data line corresponding to the display unit set, and the driving voltage required by the second display unit of the display unit set is loaded onto the second data line corresponding to the display unit set.

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