Memory unit, memory array, memory, system-on-chip chip and electronic equipment

Abstract

According to the storage unit, the storage array, the memory, the system-on-chip chip and the electronic equipment provided by the invention, calculation is realized while the first data is stored, and the utilization rate of the first data can be greatly improved. The memory cell may include a memory circuit, a transfer gate circuit, and a logic gate circuit. The storage circuit can be used for storing data, the first control end and the second control end of the storage circuit are electrically connected with the first electrode wire, the first input and output end of the storage circuit is electrically connected with the second electrode wire, and the second input and output end of the storage circuit is electrically connected with the third electrode wire. The output end of the storage circuit is electrically connected with the input end of the transmission gate circuit, the control end of the transmission gate circuit is electrically connected with the fourth electrode wire, the output end of the transmission gate circuit is electrically connected with the first input end of the logic gate circuit, and the second input end of the logic gate circuit is used for receiving second data. The output end of the logic gate circuit serves as the output end of the storage unit.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and more specifically, to a storage unit, a storage array, a memory, a system-on-chip chip, and an electronic device. Background Art

[0002] With the rapid development of technologies such as artificial intelligence and the Internet of Things, the demand for high-computing power and high-energy-efficiency chips is becoming increasingly urgent. Chips can adopt a digital in-memory computing architecture. The digital in-memory computing architecture does not require a large amount of digital-to-analog conversion and analog-to-digital conversion, and can achieve full-precision calculations. Therefore, its calculation accuracy is relatively high.

[0003] The chip using the digital in-memory computing architecture provided by the related art may include two storage circuits and a logic gate circuit. One storage circuit is used to read data, and the other storage circuit is used to store data. In other words, data can be stored and calculated simultaneously through two storage circuits and logic gate circuits. It can be seen that the reading and writing of data are realized through different storage circuits, and only half of the data can be used for calculation in each cycle, and it is impossible to realize the simultaneous calculation of two storage circuits, and the utilization rate of data is low.

[0004] Therefore, there is an urgent need for a technical solution that can store and calculate data simultaneously and has a high data utilization rate. Summary of the invention

[0005] The present application provides a storage unit, a storage array, a memory, a system-on-chip chip and an electronic device, which can store first data and realize calculation at the same time, and can greatly improve the utilization rate of the first data.

[0006] In a first aspect, the present application provides a storage unit, which may include a storage circuit, a transmission gate circuit, and a logic gate circuit.

[0007] Among them, the storage circuit can be used to store the first data, the first control end and the second control end of the storage circuit can be electrically connected to the first electrode line, the first input and output ends of the storage circuit can be electrically connected to the second electrode line, the second input and output ends of the storage circuit can be electrically connected to the third electrode line, the output end of the storage circuit can be electrically connected to the input end of the transmission gate circuit, the control end of the transmission gate circuit can be electrically connected to the fourth electrode line, the output end of the transmission gate circuit can be electrically connected to the first input end of the logic gate circuit, the second input end of the logic gate circuit can be used to receive the second data, and the output end of the logic gate circuit serves as the output end of the storage unit.

[0008] The storage unit provided in the present application can store the first data through the storage circuit. The storage circuit can also output the first data to the transmission gate circuit, output the first data to the logic gate circuit through the transmission gate circuit, and implement logical operations of the first data and the second data through the logic gate circuit. Not only can the first data and the second data be stored and logically operated at the same time, but the utilization rate of the first data or the second data can also be greatly improved, thereby realizing high computing power and high energy efficiency of the storage unit.

[0009] In a possible implementation manner, the storage circuit may include a switch circuit and a storage sub-circuit.

[0010] The first input terminal of the switch circuit can be used as the first control terminal of the storage circuit, and the second input terminal of the switch circuit can be used as the second control terminal of the storage circuit. The first input and output terminals of the switch circuit can be used as the first input and output terminals of the storage circuit, and the second input and output terminals of the switch circuit can be used as the second input and output terminals of the storage circuit. The third input and output terminals of the switch circuit can be electrically connected to the first input and output terminals of the storage sub-circuit, and the fourth input and output terminals of the switch circuit can be electrically connected to the second input and output terminals of the storage sub-circuit. The output terminal of the storage sub-circuit can be used as the output terminal of the storage circuit.

[0011] Furthermore, the switch circuit may include a first switch tube and a second switch tube.

[0012] The control electrode of the first switch tube can be used as the first input end of the switch circuit, and the control electrode of the second switch tube can be used as the second input end of the switch circuit. The control electrodes of the first switch tube and the second switch tube (i.e., the first control end and the second control end of the storage circuit) can be electrically connected to the first word line (i.e., the first electrode line) for receiving the first control signal. In other words, the first switch tube and the second switch tube can both receive the first control signal from the first word line. The first electrode of the first switch tube (i.e., the first input and output end of the storage circuit) can be electrically connected to the first bit line (i.e., the second electrode line) for receiving the first data. In other words, the first switch tube can receive the first data from the first bit line. The first electrode of the second switch tube (i.e., the second input and output end of the storage circuit) can be electrically connected to the second bit line (i.e., the third electrode line) for receiving the third data. In other words, the second switch tube can receive the third data from the second bit line. The second electrode of the first switch tube can be used as the third input and output end of the switch circuit, and the second electrode of the second switch tube can be used as the fourth input and output end of the switch circuit.

[0013] The first data and the third data are both 1 or 0, and the first data and the third data are different. That is, the first data can be 1 or 0, and the third data can also be 1 or 0. When the first data is 1, the third data can be 0. Conversely, when the first data is 0, the third data can be 1.

[0014] It can be imagined that the switching circuit can be used: when the first control signal is at a high level, the first switch tube and the second switch tube can both be turned on, and the switching circuit can output the first data to the storage sub-circuit through the first switch tube, and can output the third data to the storage sub-circuit through the second switch tube.

[0015] In another possible implementation, the storage sub-circuit may include a third switch tube, a fourth switch tube, a fifth switch tube, and a sixth switch tube.

[0016] The first pole of each of the third switch tube and the fourth switch tube can be used to receive a first operating voltage (which can be represented by VDD), and the second pole of the third switch tube and the first pole of the fifth switch tube can be electrically connected to node A, and node A can be used as a first input and output terminal of the storage subcircuit. The control poles of each of the third switch tube and the fifth switch tube can be electrically connected to node B, the second pole of the fourth switch tube and the first pole of the sixth switch tube can be electrically connected to node C, and node B can be connected to node C, which can also be used as a second input and output terminal of the storage subcircuit. The control poles of each of the fourth switch tube and the sixth switch tube can be electrically connected to node D, and node A can be electrically connected to node D. The second poles of the fifth switch tube T5 and the sixth switch tube T can be used to receive a second operating voltage (which can be represented by VSS).

[0017] It can be imagined that the storage sub-circuit can be used for: when the first data is 1 and the third data is 0, the fourth switch tube can be controlled to be turned off and the sixth switch tube can be controlled to be turned on according to the first data, and the third switch tube can be controlled to be turned on and the fifth switch tube can be controlled to be turned off according to the third data, and the first data and the third data can be stored through the third switch tube, the fourth switch tube, the fifth switch tube and the sixth switch tube.

[0018] Alternatively, the storage subcircuit can be used for: when the first data is 0 and the third data is 1, the fourth switch tube can be controlled to be turned on and the sixth switch tube can be controlled to be turned off according to the first data, and the third switch tube can be controlled to be turned off and the fifth switch tube can be controlled to be turned on according to the third data, and the first data and the third data can be stored through the third switch tube, the fourth switch tube, the fifth switch tube and the sixth switch tube.

[0019] It can be seen that in both cases where the first data is 1 and the third data is 0 or the first data is 0 and the third data is 1, the storage of the first data and the third data can be achieved by turning on or off the third switch tube, the fourth switch tube, the fifth switch tube and the sixth switch tube.

[0020] Exemplarily, the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube and the sixth switch tube can all be metal-oxide-semiconductor field-effect transistors (MOSFET), which can be referred to as MOS tubes. Of course, the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube and the sixth switch tube can also be other types, which are not limited in this application.

[0021] Furthermore, the first switch tube, the second switch tube, the fifth switch tube and the sixth switch tube can be N-type metal oxide semiconductor field effect transistors (can be referred to as NMOS tubes), respectively. The third switch tube and the fourth switch tube can be P-type metal oxide semiconductor field effect transistors (can be referred to as PMOS tubes), respectively.

[0022] In yet another possible implementation, the transmission gate circuit may include a seventh switch tube and an eighth switch tube.

[0023] Optionally, the control electrodes of the seventh switch tube and the eighth switch tube can each serve as the control electrode of the transmission gate circuit. Among them, the control electrode of the seventh switch tube can be electrically connected to the second word line (i.e., the fourth electrode line) for receiving the second control signal. That is to say, the seventh switch tube can receive the second control signal from the second word line. The control electrode of the eighth switch tube can be electrically connected to the third word line (i.e., the fourth electrode line) for receiving the third control signal. That is to say, the eighth switch tube can receive the third control signal from the third word line. The first electrode of the seventh switch tube is electrically connected to the first electrode of the eighth switch tube, and can serve as the input end of the transmission gate circuit. The input end of the transmission gate circuit can be electrically connected to node A or node C. The second electrode of the seventh switch tube can be electrically connected to the second electrode of the eighth switch tube, and can serve as the output end of the logic gate circuit.

[0024] Wherein, the second control signal and the third control signal can both be high level or low level, and the second control signal and the third control signal are different. That is to say, the second control signal can be high level or low level, and the third control signal can also be high level or low level. When the second control signal is high level, the third control signal can be low level. Conversely, when the second control signal is low level, the third control signal can be high level.

[0025] It is conceivable that the transmission gate circuit can be used to control the seventh switch tube and the eighth switch tube to be turned off (which can be understood as the transmission gate circuit is turned off) according to the second control signal and the third control signal, thereby preventing the first data and the third data from being output to the logic gate circuit. It is conceivable that when the second control signal is at a high level and the third control signal is at a low level, the seventh switch tube and the eighth switch tube can both be turned off, and the seventh switch tube and the eighth switch tube play a role in preventing the first data and the third data from being output to the logic gate circuit.

[0026] Alternatively, the transmission gate circuit can be used to: control the seventh switch tube and the eighth switch tube to be turned on (which can be understood as the transmission gate circuit is turned on) according to the second control signal and the third control signal, and output the first data or the third data to the logic gate circuit. It can be imagined that when the second control signal is at a low level and the third control signal is at a high level, the seventh switch tube and the eighth switch tube can both be turned on, and the seventh switch tube and the eighth switch tube play the role of outputting the first data or the third data.

[0027] It can be understood that, whether the seventh switch tube and the eighth switch tube are turned on or off, the storage unit can store the first data and the third data through the storage sub-circuit, and also realize the logic operation of the second data and the first data / third data through the logic gate circuit. It can be imagined that when the seventh switch tube and the eighth switch tube are turned off, the first data or the third data used by the logic gate circuit for the logic operation can be the first data or the third data on the connection line between the transmission gate circuit and the logic gate circuit.

[0028] It can also be understood that when the seventh switch tube and the eighth switch tube are both turned off, the storage unit and the logic gate circuit work independently, and the first data and the third data can be stored or output through the storage unit, and the logic operation can be realized through the logic gate circuit. After the first data and the third data are stored, the seventh switch tube and the eighth switch tube are both turned on, that is, the transmission gate circuit is opened, and the first data and the third data can be refreshed.

[0029] Exemplarily, the seventh switch tube may be a PMOS tube, and the eighth switch tube may be an NMOS tube. Alternatively, the seventh switch tube may be an NMOS tube, and the eighth switch tube may be a PMOS tube.

[0030] Therefore, it can be understood that the transmission gate circuit can be a CMOS transmission gate, which can include a PMOS transistor and an NMOS transistor connected in parallel. Of course, the transmission gate circuit can also be other structures, which are not limited in this application.

[0031] In an example, the first electrodes of the seventh switch tube and the eighth switch tube can be connected to the node A, and the logic gate circuit can be an AND gate. The logic operation can be implemented through the AND gate to output the logic operation result.

[0032] In another example, the first electrodes of the seventh switch tube and the eighth switch tube can be connected to the node C, and the logic gate circuit can be a NOR gate. The logic operation can be implemented through the NOR gate to output the logic operation result.

[0033] It can be understood that, during the process of performing logical operations, the logic gate circuit can simultaneously realize the storage of the first data and the third data in the storage unit, that is, realize the updating of the first data and the third data, so that all the data stored in the storage unit can meet the refresh requirements of the first data and the third data while performing logical operations, thereby maximizing the time utilization of the first data and the third data in the process of logical operations and the storage space utilization of the storage unit.

[0034] In a second aspect, the present application provides a storage array, which may include M first electrode lines (which may be first word lines), M fourth electrode lines (which may be second word lines and third word lines), M input lines, N second electrode lines (which may be first bit lines), N third electrode lines (which may be second bit lines), and M×N storage cells provided by the above first aspect and possible implementations thereof. Among them, storage cells located in the same row may share the first electrode line, the fourth electrode line, and the input line. Storage cells located in the same column may share the second electrode line and the third electrode line.

[0035] The storage array provided in the present application can receive a first control signal through a first electrode line, receive a second control signal and a third control signal through a fourth electrode line, and can also receive first data through a second electrode line and third data through a third electrode line, and finally implement the storage of the first data and the third data through M×N storage units, and can also implement logical operations on the second data and the first data, or logical operations on the second data and the third data.

[0036] Furthermore, the storage array may further include a summing unit. Some or all of the M×N storage units are connected to the summing unit.

[0037] It is conceivable that the summing unit may be one or more. In the case where there is one summing unit, all storage units may be connected to the summing unit. In the case where there are multiple summing units, the M×N storage units may be divided into multiple parts. Each part may include one or more storage units. Each part may be connected to one summing unit.

[0038] Optionally, the summing unit may be used to sum the logic operation results output by the logic gate circuit in each storage unit.

[0039] Exemplarily, the summing unit may be an addition tree, etc., which is not limited in the present application.

[0040] In a third aspect, the present application provides a memory, which may include a control unit, a first decoder, a second decoder, and a storage array provided by the above-mentioned second aspect and possible implementations thereof.

[0041] Optionally, the control unit can be used to: output M-way second data to each storage unit in the storage array according to the calculation clock signal, and output M-way second control signals and M-way third control signals to each storage unit. In other words, the output of M-way second data, M-way second control signals and M-way third control signals by the control unit needs to be controlled by the calculation clock signal.

[0042] The control unit can also be used to: output a read / write clock signal and the first address information of each storage unit to the first decoder, and output a fourth control signal, the read / write clock signal and the second address information of each storage unit to the second decoder. The fourth control signal can be used to instruct the memory to perform a read operation or a write operation.

[0043] The first decoder can be used to decode the first address information according to the read / write clock signal, and output M first control signals to the corresponding storage units according to the obtained first decoding result.

[0044] The second decoder can be used to decode the second address information according to the read / write clock signal and the fourth control signal, and output one channel of first data and one channel of third data to the corresponding storage unit according to the fourth data and the obtained second decoding result.

[0045] In the memory provided by the present application, the control unit can not only output M-way second data, M-way second control signals and M-way third control signals to the storage unit, but also output the read-write clock signal, the first address information, the fourth control signal and the second address information, and then the first decoder can decode the first address information and output the M-way first control signal, and the second decoder can decode the second address information and output the N-way first data and N-way third data. Since the storage unit can realize the logical operation of the first data and the third data while storing them, the memory provided by the present application can also realize the simultaneous storage and logical operation of the first data and the third data, thereby realizing the high computing power and high energy efficiency of the memory.

[0046] Since the storage and logical operations of the first data and the third data are all completed in the storage unit, the memory provided in the present application can be called a computing in memory (CIM) memory, which can be referred to as a CIM memory for short.

[0047] In a possible implementation, the control unit may include a first controller and a second controller. The second controller, the first decoder, and the second decoder are all connected to the first controller.

[0048] The first controller is used to: output a calculation clock signal and a second control signal to the second controller, obtain the first address information and the second address information, and output a read / write clock signal and the first address information to the first decoder, and output a read / write clock signal, the second address information and a fourth control signal to the second decoder.

[0049] The second controller is used to: divide the second control signal from the first controller into M second control signals and output them one-to-one to the M second word lines in the storage array. The second controller can also be used to invert the second control signal to obtain a third control signal, and divide the third control signal into M third control signals and output them one-to-one to the M third word lines in the storage array.

[0050] The second controller can also be used to: output M-way second data one-to-one to the logic gate circuit in each storage unit according to the calculation clock signal, or invert the M-way first input data according to the calculation clock signal to obtain M-way second data and output them one-to-one to each logic gate circuit.

[0051] Since the second controller is controlled by the first controller and the second controller can output M channels of second data, the first controller can be called a master controller and the second controller can be called an input controller.

[0052] Furthermore, the memory may further include an amplifier, and the amplifier may be connected to the first controller, and the amplifier may also be connected to the second decoder.

[0053] The second decoder can also be used to: select at least one first data from the multiple first data corresponding to the second decoder and output it to the amplifier according to the read-write clock signal, the fourth control signal and the second decoding result, and select at least one third data from the multiple third data corresponding to the second decoder and output it to the amplifier.

[0054] The first controller can also be used to: output a read / write clock signal to the amplifier. It can be seen that the first controller not only outputs the read / write clock signal to the first decoder and the second decoder, but also outputs the read / write clock signal to the amplifier.

[0055] The amplifier can be used to: amplify and output the difference between the first data and the third data according to the read / write clock signal, that is, obtain and output the weight data of the memory.

[0056] Exemplarily, the operating modes of the memory may include a read-write mode, a storage calculation mode, a calculation mode, and a retention mode.

[0057] Among them, the read-write mode can be used to instruct the memory to perform a read operation or a write operation, that is, the memory only performs reading and writing. The storage calculation mode can be used to instruct the memory to perform storage operations and calculation operations at the same time, that is, the memory performs storage and logical operations at the same time. The calculation mode can be used to instruct the memory to perform calculation operations, that is, the memory only performs calculation operations. The retention mode can be used to instruct the memory to retain the first data and the third data, that is, the memory does not perform storage operations or calculation operations.

[0058] In one possible implementation, when the memory is in a read-write mode, the memory can be used to: control the second control signal to a high level through a second controller to close each transmission gate circuit in the storage array, write the first data and the third data through each storage unit, and amplify and output the difference between the first data and the third data through an amplifier.

[0059] In another possible implementation, when the memory is in a storage calculation mode, the memory can be used to: control the second control signal to a high level through a second controller to close each transmission gate circuit in the storage array, write the first data and the third data through the storage unit, and amplify and output the difference between the first data and the third data through the amplifier; the memory can also be used to output the result of the logic operation through each storage unit.

[0060] It can be seen that when the memory is in the read-write mode or the storage calculation mode, the second control signal is at a high level and each transmission gate circuit is closed. In the read-write mode, the memory can not only store the first data and the third data, but also amplify and output the difference between the first data and the third data. In the storage calculation mode, the memory can not only store the first data and the third data, but also amplify and output the difference between the first data and the third data, but also output the result of the logic operation.

[0061] In another possible implementation, when the memory is in a calculation mode, the memory can be used to: control the second control signal to a low level through a second controller, so that each transmission gate circuit in the storage array is opened, and the logic operation result is output through each storage unit.

[0062] In another possible implementation, when the memory is in the hold mode, the memory can be used to: control the second control signal to a low level through the second controller, so that each transmission gate circuit in the storage array is opened, and the first data and the third data are stored through each storage unit.

[0063] It can be seen that when the memory is in the calculation mode or the holding mode, the second control signal is at a low level and each transmission gate circuit is open. In the calculation mode, the memory is used to output the logic operation result, and in the holding mode, the memory is used to hold and store the first data and the third data.

[0064] In a fourth aspect, the present application provides a circuit layout of a memory cell, which may include a substrate, an N-well region, an active region, a gate layer, and a metal layer, wherein the active region may include a first active region and a second active region.

[0065] Optionally, the substrate and the N-well region may be stacked along the first direction. The first active region may be arranged on the substrate along the first direction, and the second active region may be arranged on the N-well region along the first direction. The gate layer may be arranged on the active region along the first direction, and the metal layer may be arranged on the active region or the gate layer along the first direction.

[0066] The circuit layout provided in the present application can form multiple switching tubes through the substrate, N-well region, active region, gate layer and metal layer, and the storage circuit, transmission gate circuit and logic gate circuit in the storage unit are constituted by the multiple switching tubes, thereby not only being able to simultaneously store and perform logical operations on the first data and the second data, but also being able to greatly improve the utilization rate of the first data or the second data, thereby achieving high computing power and high energy efficiency of the storage unit.

[0067] In a possible implementation manner, the first active region may include a first active sub-region and a second active sub-region, and the second active region may include a third active sub-region and a fourth active sub-region.

[0068] Optionally, the first active sub-region, the third active sub-region, the fourth active sub-region and the second active sub-region may be arranged in parallel in sequence along the second direction. The second direction may be perpendicular to the first direction. It is understandable that the first active sub-region, the third active sub-region, the fourth active sub-region and the second active sub-region may serve as the source or drain of the switch tube.

[0069] In another possible implementation, the gate layer may include a first gate sublayer, a second gate sublayer, a third gate sublayer, a fourth gate sublayer, a fifth gate sublayer, a sixth gate sublayer, a seventh gate sublayer, and an eighth gate sublayer arranged along a third direction. The third direction may be perpendicular to the first direction, and the third direction may be perpendicular to the second direction. That is, the first direction, the second direction, and the third direction are perpendicular to each other.

[0070] Optionally, the first gate sublayer, the fourth gate sublayer, the fifth gate sublayer and the eighth gate sublayer are sequentially arranged in parallel along the third direction.

[0071] The first active sub-region, the third active sub-region and the fourth active sub-region may be stacked and connected to the first gate sub-layer, respectively. The third active sub-region, the fourth active sub-region and the second active sub-region may be stacked and connected to the fourth gate sub-layer, respectively. The fourth active sub-region and the second active sub-region may be stacked and connected to the fifth gate sub-layer, respectively. The fourth active sub-region and the second active sub-region may be stacked and connected to the eighth gate sub-layer, respectively.

[0072] The second gate sublayer may be located in the extension direction of the first gate sublayer, and the second gate sublayer may be stacked and connected to the second active sub-region. The third gate sublayer may be located in the extension direction of the fourth gate sublayer, and the third gate sublayer may be stacked and connected to the first active sub-region. The sixth gate sublayer and the seventh gate sublayer may both be located in the extension direction of the eighth gate sublayer; wherein the sixth gate sublayer may be stacked and connected to the first active sub-region, and the seventh gate sublayer may be stacked and connected to the third active sub-region.

[0073] In another possible implementation, the metal layer may include a first metal layer and a second metal layer. The first metal layer may be arranged along a third direction, and the second metal layer may be arranged along a second direction. That is, the arrangement direction of the first metal layer is perpendicular to the arrangement direction of the second metal layer.

[0074] In an example, the first metal layer may include a first metal sub-layer, a second metal sub-layer, a third metal sub-layer, a fourth metal sub-layer, a fifth metal sub-layer, and a sixth metal sub-layer.

[0075] The first metal sublayer, the third metal sublayer and the fifth metal sublayer can be arranged in parallel in sequence along the second direction, the second metal sublayer, the fourth metal sublayer and the sixth metal sublayer can be arranged in parallel in sequence along the second direction, the second metal sublayer can be located in the extension direction of the first metal sublayer, the fourth metal sublayer can be located in the extension direction of the third metal sublayer, and the sixth metal sublayer can be located in the extension direction of the fifth metal sublayer.

[0076] Furthermore, the first metal sublayer and the second metal sublayer can be located between the first gate sublayer and the fourth gate sublayer, the first active sub-region and the third active sub-region can be stacked and connected to the first metal sublayer, respectively, and the fourth active sub-region and the second active sub-region can be stacked and connected to the second metal sublayer, respectively.

[0077] The third metal sublayer may be located between the fourth gate sublayer and the seventh gate sublayer, and the first active sub-region and the third active sub-region may be stacked and connected to the third metal sublayer, respectively.

[0078] The fourth metal sublayer may be located between the fifth gate sublayer and the eighth gate sublayer, and the second active sub-region and the fourth metal sublayer may be stacked and connected.

[0079] The fifth metal sublayer may be located on a side of the seventh gate sublayer away from the third metal sublayer in the second direction, and the first active sub-region and the third active sub-region may be stacked and connected to the fifth metal sublayer, respectively.

[0080] The sixth metal sublayer may be located on a side of the eighth gate sublayer away from the fourth metal sublayer in the second direction, and the fourth active sub-region may be stacked and connected to the sixth metal sublayer.

[0081] In another example, the second metal layer may include a seventh metal sub-layer, an eighth metal sub-layer, a ninth metal sub-layer, and a tenth metal sub-layer;

[0082] The seventh metal sublayer may be stacked with the third active sub-region along the first direction, and the first metal sublayer, the fourth gate sublayer and the third metal sublayer may be stacked and connected with the seventh metal sublayer, respectively. The eighth gate sublayer and the fifth metal sublayer may be stacked and connected with the eighth metal sublayer, respectively. The ninth metal sublayer may be stacked with the fourth active sub-region along the first direction, and the first gate sublayer and the second metal sublayer may be stacked and connected with the ninth metal sublayer, respectively. The fourth metal sublayer, the eighth gate sublayer and the sixth metal sublayer may be stacked and connected with the tenth metal sublayer, respectively.

[0083] In a possible implementation, the first active sub-region may be provided with a first through hole and a second through hole. The first through hole may be located on a side of the first gate sublayer away from the first metal sublayer in the second direction, and is used to connect the first power line. The second through hole may be located between the third gate sublayer and the third metal sublayer, and is used to connect the second bit line.

[0084] The second active sub-region may be provided with a third through hole, a fourth through hole and a fifth through hole. The third through hole may be located on a side of the second gate sublayer away from the second metal sublayer in the second direction, and is used to connect the first bit line. The fourth through hole may be located between the fourth gate sublayer and the fifth gate sublayer, the fifth through hole may be located on a side of the eighth gate sublayer away from the fourth metal sublayer in the second direction, and both the fourth through hole and the fifth through hole may be used to connect the first power line.

[0085] The third active sub-region may be provided with a sixth through hole, and the fourth active sub-region may be provided with a seventh through hole. The sixth through hole may be located on a side of the first gate sub-layer away from the first metal sub-layer in the second direction, and the seventh through hole may be located between the fourth gate sub-layer and the fifth gate sub-layer, and both the sixth through hole and the seventh through hole may be used to connect the second power line.

[0086] The first power line can be used to provide the second operating voltage, and the second power line can be used to provide the first operating voltage.

[0087] In another possible implementation, the second gate sublayer may be provided with an eighth through hole, the third gate sublayer may be provided with a ninth through hole, and the eighth through hole and the ninth through hole may be used to connect the first word line.

[0088] The fifth gate sublayer may be provided with a tenth through hole, and the tenth through hole may be used to connect an input line, and the input line may be used to provide second data.

[0089] The sixth gate sublayer may be provided with an eleventh through hole, and the eleventh through hole may be used to connect the third word line.

[0090] The seventh gate sublayer may be provided with a twelfth through hole, and the twelfth through hole may be used to connect the second word line.

[0091] The fourth metal sub-layer may be provided with a thirteenth through hole, and the thirteenth through hole may be used to connect an output line, and the output line may be used to output a logic operation result of the storage unit.

[0092] In a fifth aspect, the present application provides a system on chip (SOC) chip, which may be referred to as a SOC chip. The SOC chip may include a processor and a memory provided by the third aspect and possible implementations thereof. The memory may be connected to the processor.

[0093] Exemplarily, the SOC chip may include one or more CIM memories, which is not limited in the present application. The one or more CIM memories may be connected to the processor via a bus.

[0094] Optionally, the SOC chip may further include a static random-access memory (SRAM) and the like, and the SRAM may also be connected to the processor via a bus.

[0095] In a sixth aspect, the present application provides an electronic device, which may include an off-chip memory chip and a SOC chip provided by the fifth aspect and possible implementations thereof. The off-chip memory chip may be connected to a processor in the SOC chip via a bus.

[0096] Exemplarily, the off-chip storage chip may include a non-volatile memory (NVM) and a dynamic random access memory (DRAM), etc., which is not limited in this application.

[0097] Furthermore, the NVM may be connected to the DRAM, and the DRAM may be connected to the processor in the SOC chip through a bus.

[0098] It should be understood that the second to sixth aspects of the present application are consistent with the technical solutions of the first aspect of the present application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0099] In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0100] Figure 1 is a schematic structural diagram of a storage unit 10 in an embodiment of the present application;

[0101] Figure 2 is another schematic structural diagram of the storage unit 10 in the embodiment of the present application;

[0102] Figure 3 is another schematic structural diagram of the storage unit 10 in the embodiment of the present application;

[0103] Figure 4 A schematic structural diagram of a circuit layout 20 of a storage unit 10 in an embodiment of the present application;

[0104] Figure 5 is a schematic structural diagram of a storage array 100 in an embodiment of the present application;

[0105] Figure 6 is another schematic structural diagram of the storage array 100 in an embodiment of the present application;

[0106] Figure 7 is a schematic structural diagram of the memory 1100 in an embodiment of the present application;

[0107] Figure 8 is another schematic structural diagram of the memory 1100 in an embodiment of the present application;

[0108] Fig. 9 is another schematic structural diagram of the memory 1100 in an embodiment of the present application;

[0109] Fig.10 is another schematic structural diagram of the memory 1100 in an embodiment of the present application;

[0110] Fig.11This is a timing diagram of the memory 1100 in the read-write mode according to the embodiment of the present application;

[0111] Fig.12 This is a timing diagram of the memory 1100 in the storage calculation mode according to the embodiment of the present application;

[0112] Fig.13 This is a timing diagram of the memory 1100 in the computing mode according to the embodiment of the present application;

[0113] Fig.14 1 is a timing diagram of the memory 1100 in the holding mode according to the embodiment of the present application;

[0114] Fig.15 A schematic structural diagram of a SOC chip 1000 in an embodiment of the present application;

[0115] Fig.16 1 is a schematic structural diagram of an electronic device 1000 in an embodiment of the present application. DETAILED DESCRIPTION

[0116] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0117] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0118] The terms "first", "second", etc. in the specification embodiments, claims, and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. The method, system, product, or device is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0119] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0120] With the rapid development of technologies such as artificial intelligence and the Internet of Things, the demand for high-computing power and high-energy-efficiency chips is becoming increasingly urgent. Chips can adopt the von Neumann architecture or the in-memory computing architecture. In the von Neumann architecture, data such as input data and weight data need to be stored in the memory, and then transmitted to the processor via the bus for logical operations, and the results of the logical operations are then transmitted to the memory via the bus. The limited number of read interfaces of the memory limits the number of logical operations per unit cycle, and the data transmission process not only generates energy consumption of the chip, but also limits the throughput of the processor. Compared with the von Neumann architecture, the in-memory computing architecture not only has storage and read and write functions, but also can support logical operations such as multiplication and addition in the memory, reducing the frequent interaction between the processor and the memory, reducing the amount of data transmission, and thus reducing the energy consumption of the chip. That is, the chip using the in-memory computing architecture has high computing power and high energy efficiency.

[0121] In-memory computing architectures can be divided into analog in-memory computing architectures and digital in-memory computing architectures. Among them, analog in-memory computing architectures usually require a large number of digital-to-analog conversions and analog-to-digital conversions, and the calculation accuracy is greatly affected by noise, voltage, temperature, etc., resulting in low calculation accuracy of analog in-memory computing architectures, usually less than 8 bits. Compared with analog in-memory computing architectures, digital in-memory computing architectures do not require a large number of digital-to-analog conversions and analog-to-digital conversions, and can achieve full-precision calculations. Therefore, the calculation accuracy of digital in-memory computing architectures is higher.

[0122] The chip using the digital in-memory computing architecture provided by the related art may include two storage circuits and a logic gate circuit. One of the storage circuits is used to read data (such as weight data), and the other storage circuit is used to write data (such as weight data). In other words, data can be read, written and calculated simultaneously through two storage circuits and logic gate circuits. It can be seen that the reading and writing of data are realized through different storage circuits, and only half of the data can be used for calculation in each cycle, and it is impossible to realize logical operations of two storage units at the same time. Therefore, the utilization rate of data is low.

[0123] In order to overcome the above shortcomings, the present application embodiment provides a storage unit, such as Figure 1 and Figure 2 shown. Figure 1 and Figure 2 In the embodiment, the storage unit 10 may include a storage circuit 1, a transmission gate circuit 2 and a logic gate circuit 3.

[0124] The storage circuit 1 is used to store the first data. The first control terminal (which may be the control electrode (i.e., gate) of the first switch tube T1) and the second control terminal (which may be the control electrode (i.e., gate) of the second switch tube T2) of the storage circuit 1 may be electrically connected to the first word line WL1 (i.e., the first electrode line). The first input / output terminal (which may be the first electrode (which may be the drain) of the first switch tube T1) of the storage circuit 1 may be electrically connected to the first bit line BL1 (i.e., the second electrode line). The second input / output terminal (which may be the first electrode (which may be the drain) of the second switch tube T2) of the storage circuit 1 may be electrically connected to the second bit line BL2 (i.e., the third electrode line). The output terminal (which may be the first electrode (which may be the drain) of the second switch tube T2) of the storage circuit 1 may be electrically connected to the second bit line BL2 (i.e., the third electrode line). Figure 1 The second electrode (which may be the source electrode) of the third switch tube T3 and the first electrode (which may be the drain electrode) of the fifth switch tube T5 shown in the figure may be Figure 2 The second electrode (which may be the source electrode) of the fourth switch tube T4 and the first electrode (which may be the drain electrode) of the sixth switch tube T6 shown in the figure may be electrically connected to the input end (which may be the first electrode (which may be the drain electrode) of the seventh switch tube T7 and the first electrode (which may be the drain electrode) of the eighth switch tube T8) of the transmission gate circuit 2, the control end (which may be the control electrode (i.e., the gate electrode) of the seventh switch tube T7 and the control electrode (i.e., the gate electrode) of the eighth switch tube T8) of the transmission gate circuit 2 may be electrically connected to the second word line WL2 and the third word line WL3 (i.e., the fourth electrode line), and the output end (which may be the second electrode (which may be the source electrode) of the seventh switch tube T7 and the second electrode (which may be the source electrode) of the eighth switch tube T8) of the transmission gate circuit 2 may be electrically connected to the first input end (which may be the gate electrode) of the logic gate circuit 3. Figure 1 The first input of the AND gate or Figure 2 The first input terminal of the NOR gate in the logic gate circuit 3 is electrically connected to the second input terminal of the logic gate circuit 3 (i.e. Figure 1The second input terminal IN of the AND gate or Figure 2 The second input terminal IN of the NOR gate can be used to receive the second data, and the output terminal of the logic gate circuit 3 (i.e. Figure 1 The output terminal OUT of the AND gate or Figure 2 The output terminal OUT of the NOR gate can be used as the output terminal of the storage unit 10.

[0125] Optionally, the first data may be weight data, etc., and the second data may be input data of the storage unit 10, hereinafter referred to as second input data. The embodiment of the present application is described by taking the first data as weight data as an example, hereinafter referred to as first weight data (which may be represented by W1).

[0126] The storage unit 10 provided in the embodiment of the present application can implement the storage of the first weight data W1 through the storage circuit 1. The storage circuit 1 can also output the first weight data W1 to the transmission gate circuit 2, output the first weight data W1 to the logic gate circuit 3 through the transmission gate circuit 2, and implement the logical operation of the first weight data W1 and the second input data through the logic gate circuit 3. Not only can the first weight data W1 and the second input data be stored and logically operated at the same time, but the utilization rate of the first weight data W1 can also be greatly improved, thereby realizing the high computing power and high energy efficiency of the storage unit 120.

[0127] like Figure 1 and Figure 2 As shown, the storage circuit 1 may include a switch circuit and a storage sub-circuit. The first input terminal of the switch circuit (which may be the control electrode of the first switch tube T1) may be used as the first control terminal of the storage circuit 1, and the second input terminal of the switch circuit 1 (which may be the control electrode of the second switch tube T2) may be used as the second control terminal of the storage circuit 1. The first input-output terminal of the switch circuit (which may be the first electrode of the first switch tube T1) may be used as the first input-output terminal of the storage circuit 1, the second input-output terminal of the switch circuit (which may be the first electrode of the second switch tube T1) may be used as the second input-output terminal of the storage circuit 1, the third input-output terminal of the switch circuit (which may be the second electrode of the first switch tube T1 (which may be the source electrode)) may be electrically connected to the first input-output terminal of the storage sub-circuit (which may be the second electrode of the third switch tube T3 and the first electrode of the fifth switch tube T5), and the fourth input-output terminal of the switch circuit (which may be the second electrode of the second switch tube T2 (which may be the source electrode)) may be electrically connected to the second input-output terminal of the storage sub-circuit (which may be the second electrode of the fourth switch tube T4 and the first electrode of the sixth switch tube T6). The output terminal of the storage sub-circuit (which may be Figure 1 The second electrode of the third switch tube T3 and the first electrode of the fifth switch tube T5 shown in the figure may be Figure 2The second electrode of the fourth switch tube T4 and the first electrode of the sixth switch tube T6 shown in the figure can be used as the output end of the storage circuit 1.

[0128] Further, refer to Figure 1 and Figure 2 The switch circuit may include a first switch tube T1 and a second switch tube T2. The storage sub-circuit may include a third switch tube T3, a fourth switch tube T4, a fifth switch tube T5 and a sixth switch tube T6.

[0129] In some embodiments, reference Figure 1 and Figure 2 , the control electrode of the first switch tube T1 can be used as the first input terminal of the switch circuit, and the control electrode of the second switch tube T2 can be used as the second input terminal of the switch circuit. The control electrodes of the first switch tube T1 and the second switch tube T2 can be electrically connected to the first word line WL1 for receiving the first control signal (which can be represented by CS1). That is, the first switch tube T1 and the second switch tube T2 can both receive the first control signal CS1 from the first word line WL1. The first electrode of the first switch tube T1 can be electrically connected to the first bit line BL1 for receiving the first weight data W1. That is, the first switch tube T1 can receive the first weight data W1 from the first bit line BL1. The first electrode of the second switch tube T2 can be connected to the second bit line BL2 for receiving the third data (which can be the weight data, hereinafter referred to as the third weight data, represented by W3). That is, the second switch tube T2 can receive the third weight data W3 from the second bit line BL2. The second electrode of the first switch tube T1 can be used as the third input and output terminal of the switch circuit, and the second electrode of the second switch tube can be used as the fourth input and output terminal of the switch circuit.

[0130] The first weight data W1 and the third weight data W3 are both 1 or 0, and the first weight data W1 and the third weight data W3 are different. That is, the first weight data W1 can be 1 or 0, and the third weight data W3 can also be 1 or 0. When the first weight data W1 is 1, the third weight data W3 can be 0. Conversely, when the first weight data W1 is 0, the third weight data W3 can be 1.

[0131] It can be imagined that the switching circuit can be used: when the first control signal CS1 is at a high level, the first switch tube T1 and the second switch tube T2 can both be turned on, and the switching circuit can transmit the first weight data W1 to the storage sub-circuit through the first switch tube T1, and can transmit the third weight data W3 to the storage sub-circuit through the second switch tube T2.

[0132] Exemplarily, the first switch tube T1 and the second switch tube T2 can both be N-type metal-oxide-semiconductor field-effect transistors (MOSFET), which can be referred to as NMOS tubes. Of course, the first switch tube T1 and the second switch tube T2 can also be other types, which are not limited in the embodiments of the present application.

[0133] In some other embodiments, in the storage sub-circuit, the first electrode of each of the third switch tube T3 and the fourth switch tube T4 can be used to receive the first working voltage (which can be represented by VDD), the second electrode of the third switch tube T3 and the first electrode of the fifth switch tube T5 can be electrically connected to node A, and node A can serve as the first input and output terminal of the storage sub-circuit. The control electrode of the third switch tube T3 and the control electrode of the fifth switch tube T5 can be electrically connected to node B, the second electrode of the fourth switch tube T4 and the first electrode of the sixth switch tube T6 can be electrically connected to node C, node B can be electrically connected to node C, and node C can also serve as the second input and output terminal of the storage sub-circuit. The control electrode of the fourth switch tube T4 and the control electrode of the sixth switch tube T6 can be electrically connected to node D, and node A can be electrically connected to node D. The second electrodes of the fifth switch tube and the sixth switch tube can be used to receive the second working voltage (which can be represented by VSS).

[0134] It can be understood that node A can be used as the output terminal of the storage sub-circuit, such as Figure 1 As shown, node A is electrically connected to the transmission gate circuit 2. Node C can also be used as the output end of the storage subcircuit, such as Figure 2 As shown, node C is electrically connected to the transmission gate circuit 2.

[0135] It can be imagined that the storage subcircuit can be used for: when the first weight data W1 is 1 and the third weight data W3 is 0, the fourth switch tube T4 can be controlled to be turned off and the sixth switch tube T6 can be controlled to be turned on according to the first weight data W1, and the third switch tube T3 can be controlled to be turned on and the fifth switch tube T5 can be controlled to be turned off according to the third weight data W3, and the first weight data W1 and the third weight data W3 are stored through the third switch tube T3, the fourth switch tube T4, the fifth switch tube T5 and the sixth switch tube T6.

[0136] Alternatively, the storage subcircuit can be used for: when the first weight data W1 is 0 and the third weight data W3 is 1, the fourth switch tube T4 can be controlled to be turned on and the sixth switch tube T6 can be controlled to be turned off according to the first weight data W1, and the third switch tube T3 can be controlled to be turned off and the fifth switch tube T5 can be controlled to be turned on according to the third weight data W3, and the first weight data W1 and the third weight data W3 can be stored through the third switch tube T3, the fourth switch tube T4, the fifth switch tube T5 and the sixth switch tube T6.

[0137] It can be seen that in both cases where the first weight data W1 is 1 and the third weight data W3 is 0 or where the first weight data W1 is 0 and the third weight data W3 is 1, the storage of the first weight data W1 and the third weight data W3 can be achieved by turning on or off the third switch tube T3, the fourth switch tube T4, the fifth switch tube T5 and the sixth switch tube T6.

[0138] Exemplarily, the third switch tube T3 and the fourth switch tube T4 may also be P-type metal-oxide-semiconductor field-effect transistors (MOSFET), which may be referred to as PMOS tubes. The fifth switch tube T5 and the sixth switch tube T6 may also be NMOS tubes. Of course, the third switch tube T3, the fourth switch tube T4, the fifth switch tube T5 and the sixth switch tube T6 may also be other types, which are not limited in the embodiments of the present application.

[0139] In one possible implementation, Figure 1 and Figure 2 As shown, the transmission gate circuit 2 may include a seventh switch tube T7 and an eighth switch tube T8.

[0140] Optionally, the control electrodes of the seventh switch tube T7 and the eighth switch tube T8 can each serve as the control electrode of the transmission gate circuit 2. The control electrode of the seventh switch tube T7 can be electrically connected to the second word line WL2 for receiving a second control signal (which can be represented by CS2). That is, the seventh switch tube T7 can receive the second control signal CS2 from the second word line WL2. The control electrode of the eighth switch tube T8 can be electrically connected to the third word line WL3 for receiving a third control signal (which can be represented by CS3). That is, the eighth switch tube T8 can receive the third control signal CS3 from the third word line WL3. The first electrode of the seventh switch tube T7 and the first electrode of the eighth switch tube T8 are electrically connected, and can serve as the input end of the transmission gate circuit 2. The first electrode of the seventh switch tube T7 and the first electrode of the eighth switch tube T8 can be electrically connected to node A, respectively, as shown in FIG. Figure 1 Alternatively, the first electrodes of the seventh switch tube T7 and the eighth switch tube T8 are electrically connected to the node C, as shown in FIG. Figure 2 The second electrode of the seventh switch tube T7 and the second electrode of the eighth switch tube T8 are electrically connected to serve as the output end of the transmission gate circuit 2 .

[0141] Among them, the second control signal CS2 and the third control signal CS3 are both high level or low level, and the second control signal CS2 and the third control signal CS3 are different. That is to say, the second control signal CS2 can be high level or low level, and the third control signal CS3 can also be high level or low level. When the second control signal CS2 is high level, the third control signal CS3 can be low level. Conversely, when the second control signal CS2 is low level, the third control signal CS3 can be high level. Figure 1 and Figure 2 As shown, an inverter may be provided between the second word line WL2 and the third word line WL3 to achieve the difference between the second control signal CS2 and the third control signal CS3.

[0142] It is conceivable that the transmission gate circuit 2 can be used to control the seventh switch tube T7 and the eighth switch tube T8 to be turned off (which can be understood as the transmission gate circuit 2 is turned off) according to the second control signal CS2 and the third control signal CS3, and prevent the first weight data W1 and the third weight data W3 from being output to the logic gate circuit 3. It is conceivable that when the second control signal CS2 is at a high level and the third control signal CS3 is at a low level, the seventh switch tube T7 and the eighth switch tube T8 can be turned off, and the seventh switch tube T7 and the eighth switch tube T8 play a role in preventing the first weight data W1 and the third weight data W3 from being output to the logic gate circuit 3.

[0143] Alternatively, the transmission gate circuit 2 can be used to: control the seventh switch tube T7 and the eighth switch tube T8 to be turned on (which can be understood as the transmission gate circuit 2 is turned on) according to the second control signal CS2 and the third control signal CS3, and output the first weight data W1 or the third weight data W3 to the logic gate circuit 3. It can be imagined that when the second control signal CS2 is at a low level and the third control signal CS3 is at a high level, the seventh switch tube T7 and the eighth switch tube T8 can be turned on, and the seventh switch tube T7 and the eighth switch tube T8 play the role of outputting the first weight data W1 or the third weight data W3.

[0144] It can be understood that, whether the seventh switch tube T7 and the eighth switch tube T8 are turned on or off, the storage unit 10 can store the first weight data W1 and the third weight data W3 through the storage subcircuit, and also realize the logic operation of the second data and the first weight data W1 / the third weight data W3 through the logic gate circuit 3. It can be imagined that when the seventh switch tube T7 and the eighth switch tube T8 are turned off, the first weight data W1 or the third weight data W3 used by the logic gate circuit 3 for the logic operation can be the first weight data W1 or the third weight data W3 on the connection line between the transmission gate circuit 2 and the logic gate circuit 3.

[0145] It can also be understood that when the seventh switch tube T7 and the eighth switch tube T8 are both turned off, the storage circuit 1 and the logic gate circuit 3 work independently, and the storage or transmission of the first weight data W1 and the third weight data W3 is realized through the storage circuit 1, and the logic operation is realized through the logic gate circuit 3. After the first weight data W1 and the third weight data W3 are stored, the seventh switch tube T7 and the eighth switch tube T8 are both turned on, that is, the transmission gate circuit 2 is opened, and the refresh of the first weight data W1 and the third weight data W3 can be completed.

[0146] For example, the seventh switch tube T7 may be a PMOS tube, and the eighth switch tube T8 may be an NMOS tube. Figure 1 and Figure 2 Alternatively, the seventh switch tube T7 may be an NMOS tube, and the eighth switch tube T8 may be a PMOS tube.

[0147] Therefore, it can be understood that the transmission gate circuit 2 can be a CMOS transmission gate, which can include a PMOS tube (i.e., the seventh switch tube T7) and an NMOS tube (i.e., the eighth switch tube T8) connected in parallel. Of course, the transmission gate circuit 2 can also be other structures, which are not limited in the embodiments of the present application.

[0148] In an example, the first electrodes of the seventh switch tube T7 and the eighth switch tube T8 may be electrically connected to the node A, and the logic gate circuit 3 may be an AND gate (AND), such as Figure 1 That is to say, when node A is used as the output terminal of the storage sub-circuit, the logic gate circuit 3 may be an AND gate, through which a logic operation can be implemented and a logic operation result can be output.

[0149] In another example, the first electrodes of the seventh switch tube T7 and the eighth switch tube T8 may be electrically connected to the node C, and the logic gate circuit 3 may be a NOR gate. Figure 2 That is to say, when the node C is used as the output terminal of the storage sub-circuit, the logic gate circuit 3 can be a NOR gate, through which a logic operation can be implemented and a logic operation result can be output.

[0150] Understandable, because Figure 1 The logic gate circuit 3 can be an AND gate. Figure 2 The logic gate circuit 3 can be a NOR gate. Therefore, the second input data of the AND gate is different from the second input data of the NOR gate, and it is necessary to satisfy that when the second input data of the AND gate is 1, the second input data of the NOR gate can be 0. Alternatively, when the second input data of the AND gate is 0, the second input data of the NOR gate can be 1. Figure 1 and Figure 2 IN is used in both.

[0151] It can also be understood that, during the process of performing logical operations, the logic gate circuit 3 can simultaneously realize the storage of the first weight data W1 and the third weight data W3 in the storage circuit 1, that is, realize the update of the first weight data W1 and the third weight data W3, thereby satisfying the refresh requirements of the first weight data W1 and the third weight data W3 while performing logical operations for all weight data stored in the storage circuit 1, thereby maximizing the time utilization of the first weight data W1 and the third weight data W3 in the process of logical operations and the storage space utilization of the storage unit 10.

[0152] In one possible implementation, Figure 2 The NOR gate may include a ninth switch tube T9, a tenth switch tube T10, an eleventh switch tube T11 and a twelfth switch tube T12. Figure 3 As shown. Among them, the control electrode of the ninth switch tube T9 and the control electrode of the eleventh switch tube T11 can be electrically connected as the second input terminal IN of the NOR gate, which is used to receive the second input data. The control electrode of the tenth switch tube T10 and the control electrode of the twelfth switch tube T12 can be electrically connected as the first input terminal of the NOR gate, which is used to receive the first weight data W1 or the third weight data W3. The first electrode (which can be the drain) of the ninth switch tube T9, the first electrode (which can be the drain) of the tenth switch tube T10 and the second electrode (which can be the source) of the twelfth switch tube are electrically connected as the output terminal OUT of the NOR gate. The second electrode (which can be the source) of the ninth switch tube T9 and the second electrode (which can be the source) of the tenth switch tube can both be used to receive the second working voltage VSS. The first electrode (which can be the drain) of the eleventh switch tube T11 can be used to receive the first working voltage VDD. The second electrode (which can be the source) of the eleventh switch tube T11 can be electrically connected to the first electrode (which can be the drain) of the twelfth switch tube T12.

[0153] Optionally, the ninth switch tube T9 and the tenth switch tube T10 may be NMOS tubes, and the eleventh switch tube T11 and the twelfth switch tube T12 may be PMOS tubes.

[0154] The present application also provides a circuit board diagram of a storage unit 10, such as Figure 4 As shown. The circuit board diagram 20 may include a substrate 11, an N-well region 12, an active region, a gate layer, and a metal layer. The active region may include a first active region (may include a first active sub-region 131 and a second active sub-region 132) and a second active region (may include a third active sub-region 133 and a fourth active sub-region 134).

[0155] Optionally, the substrate 11 and the N-well region 12 may be stacked along the first direction. The first active region may be disposed on the substrate 11 along the first direction, and the second active region may be disposed on the N-well region 12 along the first direction. That is, the first active sub-region 131 and the second active sub-region 132 may be disposed on the substrate 11 along the first direction, and the third active sub-region 133 and the fourth active sub-region 134 may be disposed on the N-well region 12 along the first direction. In other words, the first part of the sub-regions in the active region are directly disposed on the substrate 11, and the second part of the sub-regions may be disposed on the N-well region 12.

[0156] The gate layer may be disposed on the active region along the Z direction. Since the active region may include a first active region and a second active region, that is to say, for the gate layer, the gate layer may be disposed on the first active region and the second active region along the Z direction. The metal layer may be disposed on the active region or the gate layer along the Z direction. In the embodiment of the present application, the first direction may be described by taking the Z direction as an example.

[0157] The circuit layout 20 provided in the embodiment of the present application can form multiple switching tubes through the substrate 11, N-well region 12, active region, gate layer and metal layer, and the storage circuit 1, transmission gate circuit 2 and logic gate circuit 3 in the storage unit 10 are constituted by multiple switching tubes, thereby not only being able to simultaneously store and perform logical operations on the first weight data W1 and the second input data, but also being able to greatly improve the utilization rate of the first weight data W1 or the second input data, thereby achieving high computing power and high energy efficiency of the storage unit 10.

[0158] Optionally, refer to Figure 4 , the first active sub-region 131, the third active sub-region 133, the fourth active sub-region 134 and the second active sub-region 132 can be arranged in parallel in sequence along the second direction. The second direction can be perpendicular to the Z direction. In the embodiment of the present application, the second direction is taken as the Y direction as an example. It can be understood that the first active sub-region 131, the third active sub-region 133, the fourth active sub-region 134 and the second active sub-region 132 can be used as the source or drain of the switch tube.

[0159] In a possible implementation, the gate layer may include a first gate sublayer 141, a second gate sublayer 142, a third gate sublayer 143, a fourth gate sublayer 144, a fifth gate sublayer 145, a sixth gate sublayer 146, a seventh gate sublayer 147, and an eighth gate sublayer 148 arranged along a third direction. The third direction may be perpendicular to the first direction, and the third direction may be perpendicular to the second direction. In other words, the first direction, the second direction, and the third direction are mutually perpendicular. In the embodiment of the present application, the third direction is taken as the X direction as an example.

[0160] Optionally, refer to Figure 4The first gate sublayer 141 , the fourth gate sublayer 144 , the fifth gate sublayer 145 and the eighth gate sublayer 148 are sequentially arranged in parallel along the X direction.

[0161] Among them, the first active sub-region 131, the third active sub-region 133 and the fourth active sub-region 134 can be stacked and connected to the first gate sublayer 141 respectively (can be connected through a through hole). The third active sub-region 133, the fourth active sub-region 134 and the second active sub-region 132 can be stacked and connected to the fourth gate sublayer 142 respectively (can be connected through a through hole). The fourth active sub-region 134 and the second active sub-region 132 are stacked and connected to the fifth gate sublayer 145 respectively (can be connected through a through hole). The fourth active sub-region 134 and the second active sub-region 132 are stacked and connected to the eighth gate sublayer 148 respectively (can be connected through a through hole).

[0162] The second gate sublayer 142 may be located in the extension direction of the first gate sublayer 141, and the second gate sublayer 142 may be stacked and connected to the second active sub-region 132 (may be connected through a through hole). The third gate sublayer 143 may be located in the extension direction of the fourth gate sublayer 144, and the third gate sublayer 143 may be stacked and connected to the first active sub-region 131 (may be connected through a through hole). The sixth gate sublayer 146 and the seventh gate sublayer 147 may both be located in the extension direction of the eighth gate sublayer 148. Among them, the sixth gate sublayer 146 may be stacked and connected to the first active sub-region 131 (may be connected through a through hole), and the seventh gate sublayer 147 may be stacked and connected to the third active sub-region 133 (may be connected through a through hole).

[0163] It is conceivable that the first gate sublayer 141 , the second gate sublayer 142 , the third gate sublayer 143 , the fourth gate sublayer 144 , the fifth gate sublayer 145 , the sixth gate sublayer 146 , the seventh gate sublayer 147 and the eighth gate sublayer 148 can serve as gates of the switching tube.

[0164] In another possible implementation, the metal layer may include a first metal layer and a second metal layer. The first metal layer may be arranged along the X direction, and the second metal layer may be arranged along the Y direction. It can be seen that the first metal layer and the second metal layer are perpendicular.

[0165] In one example, continue to refer to Figure 4 , the first metal layer may include a first metal sub-layer 151 , a second metal sub-layer 152 , a third metal sub-layer 153 , a fourth metal sub-layer 154 , a fifth metal sub-layer 155 and a sixth metal sub-layer 156 .

[0166] The first metal sublayer 151, the third metal sublayer 153 and the fifth metal sublayer 155 can be arranged in parallel in sequence along the Y direction, the second metal sublayer 152, the fourth metal sublayer 154 and the sixth metal sublayer 156 can be arranged in parallel in sequence along the Y direction, the second metal sublayer 152 can be located in the extension direction of the first metal sublayer 151, the fourth metal sublayer 154 can be located in the extension direction of the third metal sublayer 153, and the sixth metal sublayer 156 can be located in the extension direction of the fifth metal sublayer 155.

[0167] Furthermore, the first metal sublayer 151 and the second metal sublayer 152 can be located between the first gate sublayer 141 and the fourth gate sublayer 144, the first active sub-region 131 and the third active sub-region 133 can be stacked and connected to the first metal sublayer 151 respectively (can be connected through through holes), and the fourth active sub-region 134 and the second active sub-region 132 can be stacked and connected to the second metal sublayer 152 respectively (can be connected through through holes).

[0168] The third metal sublayer 153 may be located between the fourth gate sublayer 144 and the seventh gate sublayer 147 , and the first active sub-region 131 and the third active sub-region 133 may be stacked and connected to the third metal sublayer 153 , respectively (may be connected through a through hole).

[0169] The fourth metal sublayer 154 may be located between the fifth gate sublayer 145 and the eighth gate sublayer 148 , and the second active sub-region 131 and the fourth metal sublayer 154 may be stacked and connected (may be connected through a through hole).

[0170] The fifth metal sublayer 155 may be located on one side of the seventh gate sublayer 147 away from the third metal sublayer 153 in the X direction, and the first active sub-region 131 and the third active sub-region 133 may be stacked and connected to the fifth metal sublayer 155 respectively (may be connected through a through hole).

[0171] The sixth metal sublayer 156 may be located on a side of the eighth gate sublayer 148 away from the fourth metal sublayer 154 in the X direction, and the fourth active sub-region 134 may be stacked and connected to the sixth metal sublayer 156 (may be connected through a through hole).

[0172] In another example, the second metal layer may include a seventh metal sub-layer 157 , an eighth metal sub-layer 158 , a ninth metal sub-layer 159 , and a tenth metal sub-layer 1510 .

[0173] Among them, the seventh metal sublayer 157 can be stacked with the third active sub-region 133 along the Z direction, and the first metal sublayer 151, the fourth gate sublayer 144 and the third metal sublayer 153 can be stacked and connected with the seventh metal sublayer 157 respectively (can be connected through a through hole). The eighth gate sublayer 148 and the fifth metal sublayer 155 can be stacked and connected with the eighth metal sublayer 158 respectively (can be connected through a through hole). The ninth metal sublayer 159 can be stacked with the fourth active sub-region 134 along the Z direction, and the first gate sublayer 141 and the second metal sublayer 152 can be stacked and connected with the ninth metal sublayer 159 respectively (can be connected through a through hole). The fourth metal sublayer 154, the eighth gate sublayer 148 and the sixth metal sublayer 156 can be stacked and connected with the tenth metal sublayer 1510 respectively (can be connected through a through hole).

[0174] It can be imagined that the connection between different switching tubes can be achieved through the first metal sublayer 151, the second metal sublayer 152, the third metal sublayer 153, the fourth metal sublayer 154, the fifth metal sublayer 155, the sixth metal sublayer 156, the seventh metal sublayer 157, the eighth metal sublayer 158, the ninth metal sublayer 159 and the tenth metal sublayer 1510, thereby forming a storage unit 10.

[0175] It is also conceivable that, in contrast Figures 1 to 4 , the second active sub-region 132 and the second gate sub-layer 142 can constitute a switch transistor T1. The first active sub-region 131 and the third gate sub-layer 143 can constitute a switch transistor T2, and the switch transistor T1 and the switch transistor T2 can constitute a switch circuit of the storage circuit 1. The fourth active sub-region 134 and the fourth gate sub-layer 144 can constitute a switch transistor T3, the third active sub-region 133 and the first gate sub-layer 141 can constitute a switch transistor T4, the second active sub-region 132 and the fourth gate sub-layer 144 can constitute a switch transistor T5, and the first active sub-region 131 and the first gate sub-layer 141 can constitute a switch transistor T6. Thus, the switch transistor T3, the switch transistor T4, the switch transistor T5 and the switch transistor T6 can constitute a storage sub-circuit of the storage circuit 2. The third active sub-region 133 and the seventh gate sub-layer 147 can constitute a switch transistor T7, and the first active sub-region 131 and the sixth gate sub-layer 146 can constitute a switch transistor T8. Thus, the switch tube T7 and the switch tube T8 can constitute a transmission gate circuit 2. The second active sub-region 132 and the fifth gate sub-layer 145 can constitute a switch tube T9. The second active sub-region 132 and the eighth gate sub-layer 148 can constitute a switch tube T10. The fourth active sub-region 134 and the fifth gate sub-layer 145 can constitute a switch tube T11. The fourth active sub-region 134 and the eighth gate sub-layer 148 can constitute a switch tube T12. Thus, the switch tubes T9, T10, T11 and T12 can constitute a NOR gate (i.e. Figure 4Logic gate circuit in 3).

[0176] In a possible implementation, the first active sub-region 131 may be provided with a first through hole 161 and a second through hole 162. The first through hole 161 may be located on a side of the first gate sublayer 141 away from the first metal sublayer 151 in the X direction, and is used to connect the first power line. The first power line may be used to provide a second operating voltage VSS. The second through hole 162 may be located between the third gate sublayer 143 and the third metal sublayer 153, and is used to connect the second bit line.

[0177] The second active sub-region 132 may be provided with a third through hole 163, a fourth through hole 164, and a fifth through hole 165. The third through hole 163 may be located at a side of the second gate sublayer 142 away from the second metal sublayer 152 in the X direction, and is used to connect the first bit line. The fourth through hole 164 may be located between the fourth gate sublayer 144 and the fifth gate sublayer 145. The fifth through hole 165 may be located at a side of the eighth gate sublayer 148 away from the fourth metal sublayer 154 in the X direction, and both the fourth through hole 164 and the fifth through hole 165 may be used to connect the first power line.

[0178] The third active sub-region 133 may be provided with a sixth through hole 166. The fourth active sub-region 134 may be provided with a seventh through hole 167. The sixth through hole 166 may be located on a side of the first gate sublayer 141 away from the first metal sublayer 151 in the X direction. The seventh through hole 167 may be located between the fourth gate sublayer 144 and the fifth gate sublayer 145. Both the sixth through hole 166 and the seventh through hole 167 may be used to connect a second power line. The second power line may be used to provide a first operating voltage VDD.

[0179] In another possible implementation, the second gate sublayer 142 may be provided with an eighth through hole 168. The third gate sublayer 143 may be provided with a ninth through hole 169. The eighth through hole 168 and the ninth through hole 169 may be used to connect the first word line.

[0180] The fifth gate sublayer 145 may be provided with a tenth through hole 1610. The tenth through hole 1610 may be used to connect an input line, and the input line may be used to provide second input data.

[0181] The sixth gate sublayer 146 may be provided with an eleventh through hole 1611 , and the eleventh through hole 1611 may be used to connect the third word line.

[0182] The seventh gate sublayer 147 may be provided with a twelfth through hole 1612 , and the twelfth through hole 1612 may be used to connect the second word line.

[0183] The fourth metal sub-layer 154 may be provided with a thirteenth through hole 1613 , and the thirteenth through hole 1613 may be used to connect an output line, and the output line may be used to output a logic operation result of the memory cell 10 .

[0184] The present application also provides a storage array, such as Figure 5 and Figure 6 The memory array 100 may include M first word lines (i.e., first electrode lines), M second word lines (i.e., fourth electrode lines), M third word lines (i.e., fourth electrode lines), M input lines, N first bit lines (i.e., second electrode lines), N second bit lines (i.e., third electrode lines), and M×N memory cells. Figure 5 In the storage unit, the logic gate circuit can use AND gate. Figure 6 In the storage unit, the logic gate circuit can use a NOR gate.

[0185] Among them, the M-way first word line may include a first word line WL11, a first word line WL12, ..., a first word line WL1M. The M-way second word line may include a second word line WL21, a second word line WL22, ..., a second word line WL2M. The M-way third word line may include a third word line WL31, a third word line WL32, ..., a third word line WL3M. The M-way input line may include an input line IN1, an input line IN2, ..., an input line INM.

[0186] The N first bit lines may include first bit line BL11, first bit line BL12, ..., first bit line BL1n, ..., first bit line BL1N. The N second bit lines may include second bit line BL21, second bit line BL22, ..., second bit line BL2n, ..., second bit line BL2N.

[0187] from Figure 5 and Figure 6 It can be seen that the memory cells in the same row can be connected to the same first word line, the same second word line, the same third word line and the same input line. That is, the memory cells in the same row can share the first word line WL1, the second word line WL2, the third word line WL3 and the input line IN. Similarly, the memory cells in the same column can be connected to the same first bit line and the same second bit line. That is, the memory cells in the same column can share the first bit line BL1 and the second bit line BL2.

[0188] The storage array 100 provided in the present application can receive the first control signal CS1 through the first word line, receive the second control signal CS2 through the second word line, and receive the third control signal CS3 through the third word line. It can also receive the first weight data W1 through the first bit line and the third weight data W3 through the second bit line. Finally, the storage of the first weight data W1 and the third weight data W3 is realized through M×N storage units. It can also realize the logical operation of the second input data and the first weight data W1, or the logical operation of the second input data and the third weight data W3.

[0189] In one possible implementation, Figure 5 and Figure 6 As shown, the memory array 100 may further include a summing unit. Some or all of the M×N memory cells are connected to the summing unit.

[0190] It is conceivable that the summing unit may be one or more. In the case where there is one summing unit, all storage units may be connected to the summing unit. Figure 5 In the case of summing unit 21 to summing unit 2H in the embodiment, M×N storage units can be divided into multiple parts. Each part can include one or more storage units. Each part can be connected to a summing unit. The embodiment of the present application is described by taking multiple summing units as an example.

[0191] Optionally, a summing unit (such as summing unit 21 ) may be used to sum the logic operation results output by the logic gate circuit 3 in each storage unit, obtain a summing result (which may be represented by ADD) and output it.

[0192] Exemplarily, the summing units 21 to 2H may be adder trees, etc., which is not limited in the embodiments of the present application.

[0193] In one example, the logic gate circuit in the storage unit 10 may be an AND gate, such as Figure 5 shown.

[0194] In another example, the logic gate circuit in the storage unit 10 may be a NOR gate, such as Figure 6 shown.

[0195] The present application embodiment provides a memory, such as Figure 7 and Figure 8 The memory 1100 may include a control unit 200 , a first decoder 300 (which may be called a row decoder), a plurality of second decoders (which may be called column decoders), and a memory array 100 .

[0196] Among them, the plurality of second decoders may include second decoders 401, ..., second decoder 40H. It is conceivable that the number of second decoders is equal to the number of summing units, and the plurality of second decoders correspond one-to-one to the plurality of summing units. Of course, the number of second decoders may be determined by the number of storage units. Therefore, the second decoder may also be one, which is not limited in the embodiments of the present application.

[0197] Optionally, the control unit 200 may be configured to: output M channels of second input data (i.e. Figure 7 and Figure 8 The input data transmitted on the input line IN1 to the input line INM) is sent to each memory cell in the memory array 100, and M second control signals CS2 (i.e. Figure 7 and Figure 8 The control signal transmitted on the second word line WL21 to the second word line WL2M) and the M-way third control signal CS3 (ie Figure 7 and Figure 8 The control signal transmitted on the third word line WL31 to the third word line WL3M) is given to each memory cell.

[0198] The control unit 200 may also be used to: output the read / write clock signal CLKW and the first address information IP1 of each storage unit to the first decoder 300, and output the fourth control signal (which may be represented by CS4), the read / write clock signal CLKW and the second address information IP2 of each storage unit to the second decoder 401 to the second decoder 40H. The first address information IP1 may be used to indicate the row address information of each storage unit, the second address information IP2 may be used to indicate the column address information of each storage unit, and the fourth control signal CS4 may be used to instruct the memory 1100 to perform a read operation or a write operation.

[0199] The first decoder 300 can be used to decode the first address information IP1 according to the read / write clock signal CLKW, and output M first control signals CS1 (i.e. Figure 7 and Figure 8 The control signal transmitted on the first word line WL11 to the first word line WL1M) is given to the corresponding memory cell.

[0200] The second decoder 401 can be used to decode the second address information IP2 according to the read / write clock signal CLKW and the fourth control signal CS4, and output the first weight data W1 according to the fourth data (which can be the weight data written into the memory 1100, represented by W4) and the obtained second decoding result A2. Figure 7 and Figure 8 The weight data transmitted on the first bit line BL11 and the first bit line BL12) and the third weight data W3 (i.e. Figure 7 and Figure 8 The weight data transmitted on the second bit line BL21 and the second bit line BL22 is given to the corresponding storage unit.

[0201] The second decoder 40H can be used to decode the second address information IP2 according to the read / write clock signal CLKW and the fourth control signal CS4, and output the first weight data W1 (i.e. Figure 7 and Figure 8 The weight data transmitted on the first line BL1n to the first line BL1N) and the third weight data W3 (i.e. Figure 7 and Figure 8 The weight data transmitted on the second bit line BL2n to the second bit line BL2N) is given to the corresponding storage unit.

[0202] It can be understood that the second decoders 401 to 40H can output N channels of first weight data W1 and N channels of third weight data W3 to the memory array 100 .

[0203] In the memory 1100 provided in the embodiment of the present application, the control unit 200 can not only output M-way second input data, M-way second control signal CS2 and M-way third control signal CS3 to the storage array 100, but also output the read / write clock signal CLKW, the first address information IP1, the fourth control signal CS4 and the second address information IP2, and then the first decoder 300 can decode the first address information IP1 and output the M-way first control signal CS1, and the second decoder 401 to the second decoder 40H can decode the second address information IP2 and output the N-way first weight data W1 and the N-way third weight data W3. Since the storage array 100 can realize the logical operation of the first weight data W1 and the third weight data W3 while storing them, the memory 1100 provided in the embodiment of the present application can also realize the simultaneous storage and logical operation of the first weight data W1 and the third weight data W3, thereby realizing the high computing power and high energy efficiency of the memory 1100.

[0204] Since the storage and logical operations of the first weight data W1 and the third weight data W3 are all completed in the storage unit, the memory 1100 provided in the embodiment of the present application can be called a computing in memory (CIM) memory, which can be referred to as a CIM memory for short.

[0205] In a possible implementation, the control unit 200 may include a first controller 201 and a second controller 202. The second controller 202, the first decoder 300, and the second decoders 401 to 40H are all connected to the first controller 201.

[0206] The first controller 201 is used to: output the calculation clock signal CLKC and the second control signal CS2 to the second controller 202, obtain the first address information IP1 and the second address information IP2, and output the read-write clock signal CLKW and the first address information IP1 to the first decoder 300, and output the read-write clock signal CLKW, the second address information IP2 and the fourth control signal CS4 to the second decoder 401 to the second decoder 40H.

[0207] The second controller 202 is used to: divide the second control signal CS2 from the first controller 201 into M second control signals CS2 and transmit them one-to-one to the M second word lines (i.e., the second word line WL21 to the second word line WL2M) in the memory array 100. The second controller 202 can also be used to invert the second control signal CS2 (by an inverter) to obtain a third control signal CS3, and divide the third control signal CS3 into M third control signals CS3 and transmit them one-to-one to the M third word lines (i.e., the third word line WL31 to the third word line WL3M) in the memory array 100.

[0208] The second controller 202 can also be used to: transmit the M second input data (i.e., the input data transmitted on the input lines IN1 to INM) to the logic gate circuit in each storage unit one by one according to the calculation clock signal CLKC, such as Figure 7 Alternatively, the second controller 202 may be used to calculate the M-way first input data (i.e. Figure 8 The first input data IN1-BD to the first input data INM-BD) in the input data IN1-BD to the first input data INM-BD) are inverted (by an inverter), such as Figure 8 As shown, M paths of second input data (ie, input data transmitted on input lines IN1 to INM) are obtained and transmitted to each logic gate circuit one by one.

[0209] Since the second controller 202 is controlled by the first controller 201 and the second controller 202 can output M channels of second input data, the first controller 201 can be called a master controller and the second controller 202 can be called an input controller.

[0210] In one example, if Fig. 9 As shown, the second controller 202 can also output M second control signals CS2 and transmit them to M second word lines. At the same time, the second controller 202 can invert the M second control signals CS2 through M inverters to obtain M third control signals CS3 and transmit them to M third word lines.

[0211] In another example, if Fig.10As shown, the second controller 202 can also output a second control signal CS2, divide the second control signal CS2 into M second control signals CS2 and transmit them to the M second word lines. At the same time, the second controller 202 can invert the second control signal CS2 through an inverter to obtain M third control signals CS3 and transmit them to the M third word lines.

[0212] Furthermore, if Figures 7 to 10 As shown, the memory 1100 may further include one or more amplifiers. One or more amplifiers may be connected to the first controller 201, and the amplifier may also be connected to the second decoder. In the case where the memory includes multiple amplifiers, the multiple amplifiers may be connected to the multiple second decoders in a one-to-one correspondence. The multiple amplifiers may include amplifiers 501 to 50H, the amplifier 501 is connected to the second decoder 401, and the amplifier 50H is connected to the second decoder 40H.

[0213] The second decoder 401 can also be used to: select at least one first weight data W1 from multiple first weight data W1 corresponding to the second decoder 401 (such as two first weight data W1 transmitted on the first bit line BL11 and the second bit line BL12) and transmit it to the amplifier 501 according to the read-write clock signal CLKW, the fourth control signal CS4 and the second decoding result A2, and select at least one third weight data W3 from multiple third weight data W3 corresponding to the second decoder 401 (such as two third weight data W3 transmitted on the second bit line BL21 and the second bit line BL22) and transmit it to the amplifier 501.

[0214] The second decoder 40H can also be used for: selecting at least one first weight data W1 from multiple first weight data W1 corresponding to the second decoder 40H (such as multiple first weight data W1 transmitted on the first bit line BL1n to the first bit line BL1N) and transmitting it to the amplifier 50H according to the read-write clock signal CLKW, the fourth control signal CS4 and the second decoding result A2, and selecting at least one third weight data W3 from multiple third weight data W3 corresponding to the second decoder 40H (such as multiple third weight data W3 transmitted on the second bit line BL2n to the second bit line BL2N) and transmitting it to the amplifier 50H.

[0215] The first controller 201 can also be used to: output the read / write clock signal CLKW to the amplifier 501 to the amplifier 50H. It can be seen that the first controller 201 not only outputs the read / write clock signal CLKW to the first decoder 300 and the second decoder 401 to the second decoder 40H, but also outputs the read / write clock signal CLKW to the amplifier 501 to the amplifier 50H.

[0216] Amplifiers 501 to 50H can be used to amplify and output the difference between the first weight data W1 and the third weight data W3 according to the read / write clock signal CLKW, that is, to obtain and output the fifth data (which can be the weight data of the memory 1100 and can be represented by W5).

[0217] The amplifiers 501 to 50H may be sense amplifiers or the like, which is not limited in the embodiment of the present application.

[0218] Continue to refer Figures 7 to 10 The memory 1100 may further include a plurality of accumulators, which may include accumulators 601 to 60H.

[0219] Optionally, the accumulator (eg, accumulator 601 ) may be used to accumulate the summation results ADD output by the summing unit (eg, summing unit 21 ) in different cycles to obtain and output the accumulated result.

[0220] In some embodiments, the working mode of the memory may include a read-write mode, a storage calculation mode, a calculation mode, and a hold mode. Among them, the read-write mode can be used to indicate that the memory 1100 performs a read operation or a write operation, that is, the memory 1100 only reads and writes. The storage calculation mode can be used to indicate that the memory 1100 performs a storage operation and a calculation operation at the same time, that is, the memory 1100 performs storage and logical operations at the same time. The calculation mode can be used to indicate that the memory 1100 performs a calculation operation, that is, the memory 1100 only performs a calculation operation. The hold mode can be used to indicate that the memory 1100 maintains the first weight data W1 and the third weight data W3, that is, the memory 1100 does not perform a storage operation or a calculation operation.

[0221] The above working modes are introduced below.

[0222] (1) Read-write mode

[0223] The memory 1100 can be used for: Fig.11 As shown, the second controller 202 controls the second control signal CS2 to be a high level. It can be understood that the third control signal CS3 can be a low level, so that each transmission gate circuit in the storage array 100 is closed, and the first weight data W1 and the third weight data W3 are written through each storage unit, and the difference between the first weight data W1 and the third weight data W3 is amplified through the amplifier 501 to the amplifier 50H and the fourth weight data W4 is output.

[0224] Optionally, the timing diagrams of the second control signal CS2, the write clock signal CLKW, the fourth control signal CS4, the calculation clock signal CLKC, the first address information IP1, the second address information IP2, the first control signal CS1, the third weight data W3 and the fourth weight data W4 are as follows: Fig.11 shown. Fig.11 In the calculation clock signal CLKC, the calculation clock signal CLKC can be always at a low level, i and i+1 can represent the number of times the memory 100 performs a write operation, and i+2 and i+3 represent the number of times the memory performs a read operation. It can be understood that when the memory 1100 is in the read-write mode, the write clock signal CLKC, the second input data (which can be represented by IN-D, generally referring to the input data transmitted on the input line IN1 to the input line INM) and the summation result ADD can all be at a low level. Fig.11 Not reflected in.

[0225] (2) Storage Calculation Mode

[0226] The memory 1100 can be used for: Fig.12 As shown, the second controller 202 controls the second control signal CS2 to be high. It can be understood that the third control signal CS3 can be low, so that each transmission gate circuit in the storage array 100 is closed, the first weight data W1 and the third weight data W3 are written through the storage unit, and the difference between the first weight data W1 and the third weight data W3 is amplified through the amplifier 501 to the amplifier 50H and the fourth weight data W4 is output. The memory 1100 can also be used to output the result of the logic operation through each storage unit.

[0227] Optionally, the timing diagrams of the second control signal CS2, the write clock signal CLKW, the fourth control signal CS4, the first address information IP1, the second address information IP2, the first control signal CS1, the third weight data W3, the fourth weight data W4, the calculation clock signal CLKC, the second input data IN-D and the summation result ADD are as shown in Fig.12 shown. Fig.12 In , i and i+1 may represent the number of times the memory 100 performs a write operation, i+2 and i+3 may represent the number of times the memory 100 performs a read operation, and j and j+1 may represent the number of times the memory 100 performs a logical operation.

[0228] from Fig.11 and Fig.12It can be seen that when the memory 1100 is in the read-write mode or the storage calculation mode, the second control signal CS2 is at a high level and each transmission gate circuit is closed. In the read-write mode, the memory 1100 can not only store the first weight data W1 and the third weight data W3, but also amplify and output the difference between the first weight data W1 and the third weight data W3. In the storage calculation mode, the memory 1100 can not only store the first weight data W1 and the third weight data W3, but also amplify and output the difference between the first weight data W1 and the third weight data W3, and also output the logical operation result SUM.

[0229] (3) Calculation mode

[0230] The memory 1100 can be used for: Fig.13 As shown, the second controller 202 controls the second control signal CS2 to be low level, so that each transmission gate circuit in the storage array 1100 is turned on, and the logic operation result is output through each storage unit.

[0231] Optionally, the timing diagrams of the second control signal CS2, the write clock signal CLKW, the calculation clock signal CLKC, the second input data IN-D and the summation result ADD are as follows: Fig.13 shown. Fig.13 In the calculation mode, the write clock signal CLKW can be always at a low level, and j and j+1 can represent the number of times the memory 100 performs a logic operation. It can be understood that when the memory 1100 is in the calculation mode, the fourth control signal CS4, the first address information IP1, the second address information IP2, the first control signal CS1, the third weight data W3 and the fourth weight data W4 can all be at a low level. Fig.13 Not reflected in.

[0232] (4) Hold mode

[0233] The memory 1100 can be used for: Fig.14 As shown, the second controller 202 controls the second control signal CS2 to be low level, so that each transmission gate circuit in the storage array 1100 is turned on, the first weight data W1 or the third weight data W3 from the transmission gate circuit remains unchanged, and the second input data remains unchanged (because the calculation clock signal CLKC remains unchanged), the first weight data W1 and the third weight data W3 are kept in the memory 1100, and the logic operation is stopped. The first weight data W1 and the third weight data W3 are stored in each storage unit.

[0234] Optionally, the timing diagrams of the second control signal CS2, the write clock signal CLKW, the calculation clock signal CLKC and the first control signal CS1 are as follows: Fig.14As shown. The second control signal CS2, the write clock signal CLKW, the calculation clock signal CLKC and the first control signal CS1 can be low level. It can be understood that when the memory 1100 is in the hold mode, the fourth control signal CS4, the first address information IP1, the second address information IP2, the third weight data W3, the fourth weight data W4, the second input data IN-D and the summation result ADD can all be low level. Fig.14 Not reflected in.

[0235] from Fig.13 and Fig.14 It can be seen that when the memory 1100 is in the calculation mode or the holding mode, the second control signal CS2 is at a low level, and each transmission gate circuit is open. In the calculation mode, the output of the logic operation result is realized by the memory 1100, and in the holding mode, the first weight data W1 and the third weight data W3 are retained and stored by the memory 1100.

[0236] The present application also provides a system on chip (SOC) chip (ie, SOC chip). Fig.15 As shown, the SOC chip 1000 may include a processor 1200 and the above-mentioned memory 1100. The memory 1100 may be connected to the processor 1200.

[0237] Exemplarily, the SOC chip 1000 may include one or more memories 1100 (ie, one or more CIM memories), which is not limited in the present embodiment. The one or more CIM memories may be connected to the processor 1200 via a bus 1400. Fig.15 As shown, in the embodiment of the present application, the SOC chip 1000 may include four CIM memories.

[0238] Optionally, refer to Fig.15 The SOC chip 1000 may further include a static random-access memory (SRAM) 1300 , etc. The SRAM 1300 may also be connected to the processor 2000 via a bus 1400 .

[0239] Exemplarily, the SOC chip 1000 can use a neural network algorithm (including convolutional neural networks, vision, text, voice and other multi-modalities), and can be used in artificial intelligence scenarios such as computer vision and natural language processing. The SOC chip 1000 can be a neural network accelerator, a digital signal processor, a finite impulse response filter, etc.

[0240] The present application also provides an electronic device, such as Fig.16The electronic device 1000 may include an off chip memory (OCM) chip 2000 and the SOC chip 1000 . The off chip memory chip 2000 may be connected to the processor 1200 in the SOC chip 1000 via a bus 1400 .

[0241] Exemplary, reference Fig.16 The off-chip storage chip 2000 may include a non-volatile memory (NVM) 2200 and a dynamic random access memory (DRAM) 2100, etc., which is not limited in the embodiment of the present application.

[0242] Furthermore, the NVM 2200 may be connected to the DRAM 2100 , and the DRAM 2100 may be connected to the processor 1200 in the SOC chip 1000 via a bus 1400 .

[0243] Optionally, the electronic device 10000 can be a mobile terminal device such as a mobile phone, a computer, a smart car machine, a smart wearable device, or a fixed terminal device such as a cloud computing server, a data center, etc. Of course, the electronic device can also be other devices, which are not limited in the embodiments of the present application.

[0244] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A storage unit, characterized in that: Including storage circuits, transmission gate circuits and logic gate circuits; Wherein, the storage circuit is used to store the first data, the first control end and the second control end of the storage circuit are both electrically connected to the first electrode line, the first input and output ends of the storage circuit are electrically connected to the second electrode line, the second input and output ends of the storage circuit are electrically connected to the third electrode line, the output end of the storage circuit is electrically connected to the input end of the transmission gate circuit, the control end of the transmission gate circuit is electrically connected to the fourth electrode line, the output end of the transmission gate circuit is electrically connected to the first input end of the logic gate circuit, the second input end of the logic gate circuit is used to receive the second data, and the output end of the logic gate circuit serves as the output end of the storage unit.

2. The storage unit according to claim 1, characterized in that The storage circuit includes a switch circuit and a storage sub-circuit; The first input end of the switch circuit serves as the first control end of the storage circuit, and the second input end of the switch circuit serves as the second control end of the storage circuit; the first input and output ends of the switch circuit serve as the first input and output ends of the storage circuit, and the second input and output ends of the switch circuit serve as the second input and output ends of the storage circuit; the third input and output ends of the switch circuit are electrically connected to the first input and output ends of the storage sub-circuit, and the fourth input and output ends of the switch circuit are electrically connected to the second input and output ends of the storage sub-circuit; the output end of the storage sub-circuit serves as the output end of the storage circuit.

3. The storage unit according to claim 2, characterized in that The switch circuit includes a first switch tube and a second switch tube; The control electrode of the first switch tube serves as the first input terminal of the switch circuit, and the control electrode of the second switch tube serves as the second input terminal of the switch circuit. The control electrodes of the first switch tube and the second switch tube are electrically connected to the first word line for receiving the first control signal. The first electrode of the first switch tube is electrically connected to the first bit line for receiving the first data. The first electrode of the second switch tube is electrically connected to the second bit line for receiving third data; the second electrode of the first switch tube serves as the third input and output terminal of the switch circuit, and the second electrode of the second switch tube serves as the fourth input and output terminal of the switch circuit; The first data and the third data are both 1 or 0, and the first data and the third data are different.

4. The storage unit according to claim 2 or 3, characterized in that: The storage sub-circuit includes a third switch tube, a fourth switch tube, a fifth switch tube and a sixth switch tube; The first pole of each of the third switch tube and the fourth switch tube is used to receive a first working voltage; the second pole of the third switch tube and the first pole of the fifth switch tube are both electrically connected to node A, and the node A serves as the first input and output end of the storage sub-circuit; the control poles of each of the third switch tube and the fifth switch tube are both electrically connected to node B, the second pole of the fourth switch tube and the first pole of the sixth switch tube are both electrically connected to node C, the node B is electrically connected to the node C, and the node C serves as the second input and output end of the storage sub-circuit; the control poles of each of the fourth switch tube and the sixth switch tube are both electrically connected to node D, and the node D is electrically connected to the node A; the second poles of the fifth switch tube and the sixth switch tube are used to receive a second working voltage.

5. The storage unit according to any one of claims 1 to 4, characterized in that: The transmission gate circuit includes a seventh switch tube and an eighth switch tube; The control electrodes of the seventh switch tube and the eighth switch tube are respectively used as the control electrodes of the transmission gate circuit; wherein the control electrode of the seventh switch tube is electrically connected to the second word line for receiving the second control signal; the control electrode of the eighth switch tube is electrically connected to the third word line for receiving the third control signal; the first electrode of the seventh switch tube is electrically connected to the first electrode of the eighth switch tube, as the input end of the transmission gate circuit, and the input end of the transmission gate circuit is electrically connected to the node A or the node C; the second electrode of the seventh switch tube is electrically connected to the second electrode of the eighth switch tube, as the output end of the logic gate circuit; The second control signal and the third control signal are both at a high level or a low level, and the second control signal and the third control signal are different.

6. The storage unit according to claim 5, characterized in that The input end of the transmission gate circuit is electrically connected to the node A, and the logic gate circuit is an AND gate.

7. The storage unit according to claim 5, characterized in that The input end of the transmission gate circuit is electrically connected to the node C, and the logic gate circuit is a NOR gate.

8. A storage array, characterized in that: comprising M first electrode lines, M fourth electrode lines, M input lines, N second electrode lines, N third electrode lines and M×N storage units as claimed in any one of claims 1 to 9; The memory cells in the same row share the first electrode line, the fourth electrode line and the input line, and the memory cells in the same column share the second electrode line and the third electrode line.

9. The storage array according to claim 8, characterized in that: The storage array further includes a summing unit; some or all of the M×N storage units are connected to the summing unit; The summing unit is used to sum the logic operation results output by the logic gate circuit in each storage unit.

10. A memory, characterized in that: comprising a control unit, a first decoder, a second decoder and the storage array according to claim 8 or 9; The control unit is used to: output M-way second data to each storage unit in the storage array according to the calculation clock signal, and output M-way second control signals and M-way third control signals to each storage unit; It is also used to output a read / write clock signal and the first address information of each storage unit to the first decoder, and output a fourth control signal, the read / write clock signal and the second address information of each storage unit to the second decoder; wherein the fourth control signal is used to instruct the memory to perform a read operation or a write operation; The first decoder is used to: decode the first address information according to the read / write clock signal, and output M first control signals to corresponding storage units according to the obtained first decoding result; The second decoder is used to decode the second address information according to the read / write clock signal and the fourth control signal, and output a first data and a third data to a corresponding storage unit according to the fourth data and the obtained second decoding result.

11. The memory according to claim 10, characterized in that: The control unit includes a first controller and a second controller; the second controller, the first decoder and the second decoder are all connected to the first controller; The first controller is used to: output the calculation clock signal and the second control signal to the second controller, obtain the first address information and the second address information, and output the read / write clock signal and the first address information to the first decoder, and output the read / write clock signal, the second address information and the fourth control signal to the second decoder; The second controller is used to: divide the second control signal from the first controller into M second control signals and output them one-to-one to the M second word lines in the storage array; and is also used to invert the second control signal to obtain a third control signal, and divide the third control signal into M third control signals and output them one-to-one to the M third word lines in the storage array; It is also used to output the M-way second data one-to-one to the logic gate circuit in each storage unit according to the calculation clock signal, or to invert the M-way fourth data according to the calculation clock signal to obtain the M-way second data and output them one-to-one to each logic gate circuit.

12. The memory according to claim 11, characterized in that: The memory further comprises an amplifier, the amplifier is connected to the first controller, and the amplifier is also connected to the second decoder; The second decoder is further used to: select at least one first data from the multiple first data corresponding to the second decoder and output it to the amplifier according to the read / write clock signal, the fourth control signal and the second decoding result, and select at least one third data from the multiple third data corresponding to the second decoder and output it to the amplifier; The first controller is further used to: output the read / write clock signal to the amplifier; The amplifier is used to amplify and output the difference between the first data and the third data according to the read / write clock signal.

13. The memory according to claim 12, characterized in that: The working modes of the memory include read-write mode, storage calculation mode, calculation mode and holding mode; Wherein, the read / write mode is used to instruct the memory to perform a read operation or a write operation; The storage computing mode is used to instruct the memory to perform storage operations and computing operations simultaneously; The computing mode is used to instruct the memory to perform a computing operation; The retention mode is used to instruct the memory to retain the first data and the third data.

14. The memory according to claim 13, characterized in that: When the memory is in a read-write mode, the memory is used to: control the second control signal to a high level through the second controller to close each transmission gate circuit in the storage array, write the first data and the third data through each storage unit, and amplify and output the difference between the first data and the third data through the amplifier.

15. The memory according to claim 13, characterized in that: When the memory is in a storage calculation mode, the memory is used to: control the second control signal to a high level through the second controller to close each transmission gate circuit in the storage array, write the first data and the third data through the storage unit, and amplify and output the difference between the first data and the third data through the amplifier; the memory is also used to output the logic operation result through each storage unit.

16. The memory according to claim 13, characterized in that: When the memory is in a calculation mode, the memory is used to: control the second control signal to a low level through the second controller, so that each transmission gate circuit in the storage array is opened, and the logic operation result is output through each storage unit.

17. The memory according to claim 13, characterized in that: When the memory is in the holding mode, the memory is used to: The second controller controls the second control signal to be at a low level, so that each transmission gate circuit in the storage array is turned on, and the first data and the third data are stored through each storage unit.

18. A circuit layout of a storage unit, characterized in that: It includes a substrate, an N-well region, an active region, a gate layer and a metal layer; wherein the active region includes a first active region and a second active region; The substrate and the N-well region are stacked along a first direction, the first active region is arranged on the substrate along the first direction, the second active region is arranged on the N-well region along the first direction, the gate layer is arranged on the active region along the first direction, and the metal layer is arranged on the active region or the gate layer along the first direction.

19. The circuit layout of the memory cell according to claim 18, characterized in that: The first active region includes a first active sub-region and a second active sub-region, and the second active region includes a third active sub-region and a fourth active sub-region; The first active sub-region, the third active sub-region, the fourth active sub-region and the second active sub-region are sequentially arranged in parallel along the second direction; wherein the second direction is perpendicular to the first direction.

20. The circuit layout of the memory cell according to claim 19, characterized in that: The gate layer includes a first gate sublayer, a second gate sublayer, a third gate sublayer, a fourth gate sublayer, a fifth gate sublayer, a sixth gate sublayer, a seventh gate sublayer and an eighth gate sublayer arranged along the third direction; wherein the third direction is perpendicular to the first direction, and the third direction is perpendicular to the second direction; The first gate sublayer, the fourth gate sublayer, the fifth gate sublayer and the eighth gate sublayer are sequentially arranged in parallel along the third direction; the first active sub-region, the third active sub-region and the fourth active sub-region are respectively stacked and connected with the first gate sublayer, the third active sub-region, the fourth active sub-region and the second active sub-region are respectively stacked and connected with the fourth gate sublayer, the fourth active sub-region and the second active sub-region are respectively stacked and connected with the fifth gate sublayer, and the fourth active sub-region and the second active sub-region are respectively stacked and connected with the eighth gate sublayer; The second gate sublayer is located in the extension direction of the first gate sublayer, and the second gate sublayer is stacked and connected to the second active sub-region; the third gate sublayer is located in the extension direction of the fourth gate sublayer, and the third gate sublayer is stacked and connected to the first active sub-region; the sixth gate sublayer and the seventh gate sublayer are both located in the extension direction of the eighth gate sublayer, the sixth gate sublayer is stacked and connected to the first active sub-region, and the seventh gate sublayer is stacked and connected to the third active sub-region.

21. The circuit layout of the memory cell according to claim 20, characterized in that: The metal layer includes a first metal layer and a second metal layer; wherein the first metal layer is arranged along the third direction, and the second metal layer is arranged along the second direction.

22. The circuit layout of the memory cell according to claim 20, characterized in that: The first metal layer includes a first metal sublayer, a second metal sublayer, a third metal sublayer, a fourth metal sublayer, a fifth metal sublayer and a sixth metal sublayer; The first metal sublayer, the third metal sublayer and the fifth metal sublayer are sequentially arranged in parallel along the second direction, the second metal sublayer, the fourth metal sublayer and the sixth metal sublayer are sequentially arranged in parallel along the second direction, the second metal sublayer is located in the extension direction of the first metal sublayer, the fourth metal sublayer is located in the extension direction of the third metal sublayer, and the sixth metal sublayer is located in the extension direction of the fifth metal sublayer; The first metal sublayer and the second metal sublayer are both located between the first gate sublayer and the fourth gate sublayer, the first active sub-region and the third active sub-region are respectively stacked and connected to the first metal sublayer, and the fourth active sub-region and the second active sub-region are respectively stacked and connected to the second metal sublayer; The third metal sublayer is located between the fourth gate sublayer and the seventh gate sublayer, and the first active sub-region and the third active sub-region are respectively stacked and connected with the third metal sublayer; The fourth metal sublayer is located between the fifth gate sublayer and the eighth gate sublayer, and the second active sub-region is stacked and connected to the fourth metal sublayer; The fifth metal sublayer is located at a side of the seventh gate sublayer away from the third metal sublayer in the second direction, and the first active sub-region and the third active sub-region are respectively stacked and connected with the fifth metal sublayer; The sixth metal sublayer is located at a side of the eighth gate sublayer away from the fourth metal sublayer in the second direction, and the fourth active sub-region is stacked and connected to the sixth metal sublayer.

23. The circuit layout of the memory cell according to claim 22, characterized in that: The second metal layer includes a seventh metal sublayer, an eighth metal sublayer, a ninth metal sublayer and a tenth metal sublayer; Among them, the seventh metal sublayer is stacked with the third active sub-region along the first direction, and the first metal sublayer, the fourth gate sublayer and the third metal sublayer are respectively stacked and connected with the seventh metal sublayer; the eighth gate sublayer and the fifth metal sublayer are respectively stacked and connected with the eighth metal sublayer; the ninth metal sublayer is stacked with the fourth active sub-region along the first direction, and the first gate sublayer and the second metal sublayer are respectively stacked and connected with the ninth metal sublayer; the fourth metal sublayer, the eighth gate sublayer and the sixth metal sublayer are respectively stacked and connected with the tenth metal sublayer.

24. The circuit layout of the memory cell according to claim 22 or 23, characterized in that: The first active sub-region is provided with a first through hole and a second through hole; wherein the first through hole is located on a side of the first gate sub-layer away from the first metal sub-layer in the second direction, and is used to connect a first power line; the second through hole is located between the third gate sub-layer and the third metal sub-layer, and is used to connect a second bit line; The second active sub-region is provided with a third through hole, a fourth through hole and a fifth through hole; wherein the third through hole is located on a side of the second gate sublayer away from the second metal sublayer in the second direction, and is used to connect the first bit line; the fourth through hole is located between the fourth gate sublayer and the fifth gate sublayer, and the fifth through hole is located on a side of the eighth gate sublayer away from the fourth metal sublayer in the second direction, and both the fourth through hole and the fifth through hole are used to connect the first power line; The third active sub-region is provided with a sixth through hole, and the fourth active sub-region is provided with a seventh through hole; wherein the sixth through hole is located on a side of the first gate sub-layer away from the first metal sub-layer in the second direction, and the seventh through hole is located between the fourth gate sub-layer and the fifth gate sub-layer, and the sixth through hole and the seventh through hole are both used to connect a second power line; The first power line is used to provide a second operating voltage, and the second power line is used to provide a first operating voltage.

25. The circuit layout of the memory cell according to any one of claims 22 to 24, characterized in that: The second gate sublayer is provided with an eighth through hole, the third gate sublayer is provided with a ninth through hole, and the eighth through hole and the ninth through hole are used to connect the first word line; The fifth gate sublayer is provided with a tenth through hole, the tenth through hole is used to connect an input line, and the input line is used to provide second data; The sixth gate sublayer is provided with an eleventh through hole, and the eleventh through hole is used to connect the third word line; The seventh gate sublayer is provided with a twelfth through hole, and the twelfth through hole is used to connect the second word line; The fourth metal sub-layer is provided with a thirteenth through hole, and the thirteenth through hole is used to connect an output line, and the output line is used to output the logic operation result of the storage unit.

26. A system-on-chip chip, characterized in that: The method comprises a processor and a memory as claimed in any one of claims 10 to 17; the memory is connected to the processor.

27. An electronic device, characterized in that: It comprises an off-chip memory chip and the system-on-chip chip as claimed in claim 26; the off-chip memory chip is connected to the system-on-chip chip.

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