Data processing circuit and circuit system

Abstract

The invention provides a data processing circuit and a circuit system, and the data processing circuit comprises a system-level control module which collects pulse data based on a first instruction, writes the pulse data into a data storage module, reads the pulse data from the data storage module based on a second instruction, carries out the data processing, and outputs the data; the data storage module is connected with the system-level control module and is used for transmitting data at the jump edge of the clock signal so as to realize the write-in and read-out of pulse data; the power supply module is connected with the system-level control module and the data storage module and is used for supplying power to the system-level control module and the data storage module; wherein the sampling frequency of the system-level control module is greater than or equal to two times of the pulse frequency of the pulse data. According to the data processing circuit and the circuit system provided by the invention, the problem that high-speed pulse signals cannot be acquired in real time in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a data processing circuit and a circuit system. Background Art

[0002] With the development of electronic technology, various types of high-speed pulse signals often appear in electronic circuits. These signals not only have large amounts of data, but also have very short durations, generally at the μs level. Conventional microprocessors may not even have time to respond to interrupts before the signal disappears, making it difficult to collect such signals. Taking the semiconductor field as an example, lasers are often used in the semiconductor manufacturing process. By using lasers as light sources, wafer thickness can be measured, wafer surface can be cleaned, etc.; in order to achieve high precision, the laser needs to be monitored, which involves the collection and processing of high-speed pulse signals. In view of this, real-time collection of high-speed pulse signals and processing of their large amounts of data are technical problems that technicians in this field are eager to solve.

[0003] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a data processing circuit and a circuit system for solving the problem in the prior art that high-speed pulse signals cannot be collected in real time.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a data processing circuit, the data processing circuit comprising:

[0006] A system-level control module, based on a first instruction, collects pulse data and writes the pulse data into a data storage module, and based on a second instruction, reads the pulse data from the data storage module and performs data processing before outputting the data;

[0007] A data storage module, connected to the system-level control module, for transmitting data at the transition edge of the clock signal to achieve writing and reading of the pulse data;

[0008] a power module, connected to the system-level control module and the data storage module, and used to supply power to the system-level control module and the data storage module;

[0009] Wherein, the sampling frequency of the system-level control module is greater than or equal to twice the pulse frequency of the pulse data.

[0010] Optionally, the data processing circuit further includes:

[0011] The algorithm storage module is used to store the preset algorithm; after the system-level control module is powered on, the preset algorithm is called from the algorithm storage module to perform corresponding operations based on relevant instructions, and the power supply module is also connected to the algorithm storage module to supply power to it.

[0012] Optionally, the algorithm storage module is implemented using an embedded multimedia controller.

[0013] Optionally, the system-level control module includes a processing logic unit, a first interface unit, a second interface unit, a third interface unit and a fourth interface unit, the processing logic unit serves as a master control unit and performs data acquisition and processing, the first interface unit is connected to the first peripheral device to realize the transmission of instructions and data, the second interface unit is connected to the second peripheral device to realize data acquisition, the third interface unit is connected to the data storage module to realize data writing and reading, and the fourth interface unit is connected to the power supply module to realize power supply, wherein the processing logic unit includes an ARM processor and an FPGA logic resource block, and the first interface unit, the second interface unit and the third interface unit are implemented by a gigabit network interface;

[0014] When the data processing circuit further includes an algorithm storage module, the system-level control module further includes a fifth interface unit, and the algorithm storage module is linked via the fifth interface unit to implement algorithm calling.

[0015] Optionally, the system-level control module further includes a sixth interface unit, through which a third peripheral device is linked to implement feedback control, wherein the pulse data is generated by the third peripheral device and detected by the second peripheral device.

[0016] Optionally, the data storage module includes:

[0017] A data storage unit, connected to the system-level control module, for transmitting data at the transition edge of a clock signal;

[0018] The power filter unit is connected to the power module and the data storage unit, and provides stable power supply to the data storage unit by filtering the working power provided by the power module.

[0019] Optionally, the data storage unit is implemented by a double rate synchronous dynamic random access memory, and / or the power supply filter unit is implemented by a parallel capacitor structure.

[0020] Optionally, the power supply module includes a voltage conversion unit and a linear voltage stabilization unit, which cooperate to convert the input power into the working power required by each module.

[0021] The present invention also provides a circuit system, the circuit system comprising:

[0022] The data processing circuit as described in any one of the above items;

[0023] A first peripheral device, connected to the data processing circuit, used to send a first instruction and a second instruction to the data processing circuit, and receive pulse data output by the data processing circuit;

[0024] The second peripheral device is connected to the data processing circuit and is used to provide the pulse data to the data processing circuit.

[0025] Optionally, the circuit system further includes:

[0026] A third peripheral device is connected to the data processing circuit and the second peripheral device, receives configuration information transmitted by the first peripheral device via the data processing circuit to perform parameter configuration and generate the pulse data, wherein the second peripheral device detects the pulse data generated by the third peripheral device and provides it to the data processing circuit.

[0027] As described above, the data processing circuit and circuit system of the present invention, through the design of system-level control module, data storage module and power supply module, proposes a new high-speed data processing solution, which can perform real-time sampling and high-speed processing of high-speed pulse signals and is suitable for application scenarios with large data volumes. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram showing the structure of a data processing circuit in the first embodiment of the present invention.

[0029] Figure 2 It shows a schematic diagram of the structure of the data storage module in the first embodiment of the present invention.

[0030] Figure 3 Shown is a schematic diagram of the structure of the power module in the first embodiment of the present invention.

[0031] Figure 4 It shows a schematic diagram of the structure of the circuit system in the second embodiment of the present invention.

[0032] Component number description

[0033] 10 Circuit System

[0034] 100 Data processing circuit

[0035] 110 System Level Control Module

[0036] 111 Processing logic unit

[0037] 111a ARM processor

[0038] 111b FPGA logic resource block

[0039] 112 First interface unit

[0040] 113 Second interface unit

[0041] 114 Third interface unit

[0042] 115 Fourth interface unit

[0043] 116 Fifth interface unit

[0044] 117 Sixth interface unit

[0045] 120 Data storage module

[0046] 121 Data storage unit

[0047] 122 Power filter unit

[0048] 130 Power Module

[0049] 131 Voltage conversion unit

[0050] 132 Linear voltage regulator unit

[0051] 140 Algorithm Storage Module

[0052] 200 First Peripheral

[0053] 300 Second peripheral

[0054] 400 Third peripheral DETAILED DESCRIPTION

[0055] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0056] See also Figures 1 to 4 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the form, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0057] Embodiment 1

[0058] like Figure 1 As shown, this embodiment provides a data processing circuit 100 , including a system-level control module 110 , a data storage module 120 , and a power supply module 130 ; further, it also includes an algorithm storage module 140 .

[0059] The system-level control module 110 collects pulse data based on the first instruction and writes the pulse data into the data storage module 120, and reads the pulse data from the data storage module 120 based on the second instruction and outputs the data after data processing. The sampling frequency of the system-level control module 110 is greater than or equal to twice the pulse frequency of the pulse data; the pulse data is usually a high-speed pulse signal, and the pulse frequency is generally tens of megahertz or even hundreds of megahertz, while the sampling frequency of the system-level control module 110 is usually hundreds of megahertz. By using the system-level control module 110 with a higher sampling frequency, high-speed and instant data sampling can be achieved.

[0060] In one example, the system-level control module 110 includes a processing logic unit 111, a first interface unit 112, a second interface unit 113, a third interface unit 114 and a fourth interface unit 115; correspondingly, when the data processing circuit 100 also includes an algorithm storage module 140, the system-level control module 110 also includes a fifth interface unit 116.

[0061] The processing logic unit 111 serves as a master control unit and performs data acquisition and processing, specifically, the acquisition and processing of pulse data; in practical applications, data processing includes at least filtering processing, and of course, may also include encoding processing, etc., without limitation. In one embodiment, the processing logic unit 111 includes an ARM processor 111a and an FPGA logic resource block 111b; wherein the ARM processor 111a serves as a master control unit to receive external instructions (including first instructions and second instructions) and issue various control instructions therefrom, and the FPGA logic resource block 111b performs data acquisition and processing based on the relevant control instructions issued by the ARM processor 111a, and of course, the FPGA logic resource block 111b will also generate various logic control instructions to perform logic control on each module and each unit to enable the circuit to work normally, and in addition, it will provide a clock signal to the data storage module 120.

[0062] The first interface unit 112 is used to link the processing logic unit 111 and the first peripheral device, and the first peripheral device is linked through the first interface unit 112 to realize the transmission of instructions and data; that is, the first instruction and the second instruction issued by the first peripheral device are transmitted to the processing logic unit 111 (specifically the ARM processor 111a) via the first interface unit 112, and the pulse data processed by the processing logic unit 111 (specifically the FPGA logic resource block 111b) is transmitted to the first peripheral device via the first interface unit 112. In one embodiment, the first interface unit 112 is implemented using a gigabit network interface; a gigabit network interface refers to a network interface that supports a speed of 1Gb / s (i.e., gigabits per second), has the characteristics of fast transmission speed, is suitable for application scenarios of high-speed data processing, and can realize high-speed data interaction between the data processing end and the peripheral end.

[0063] The second interface unit 113 is used to link the processing logic unit 111 and the second peripheral device, and the second peripheral device is linked through the second interface unit 113 to realize data collection; that is, the pulse data provided by the second peripheral device is transmitted to the processing logic unit 111 (specifically, the FPGA logic resource block 111b) through the second interface unit 113 to realize pulse data collection. In one embodiment, the second interface unit 113 is implemented using a gigabit network interface to facilitate high-speed data interaction between the data processing end and the peripheral end.

[0064] The third interface unit 114 is used to link the processing logic unit 111 and the data storage module 120, and the data storage module 120 is linked through the third interface unit 114 to realize data writing and reading; that is, the pulse data collected by the processing logic unit 111 (specifically the FPGA logic resource block 111b) is written into the data storage module 120 via the third interface unit 114, and the pulse data stored in the data storage module 120 is read out to the processing logic unit 111 (specifically the FPGA logic resource block 111b) via the third interface unit 114. In one embodiment, the third interface unit 114 is implemented using a gigabit network interface to facilitate high-speed data interaction between the data processing end and the storage end. In actual applications, in order to realize data writing and reading, the processing logic unit 111 (specifically the FPGA logic resource block 111b) will also provide a clock signal to the data storage module 120 via the third interface unit 114, and of course, it will also provide related logic control signals.

[0065] The fourth interface unit 115 is used to link the processing logic unit 111 and the power module 130, and the power module 130 is linked through the fourth interface unit 115 to realize power supply; that is, the power module 130 supplies power to the processing logic unit 111 (specifically, the ARM processor 111a and the FPGA logic resource block 111b) through the fourth interface unit 115, and supplies power to each interface unit through the processing logic unit 111 (specifically, the ARM processor 111a). Among them, the fourth interface unit 115 does not involve high-speed data transmission, so it can be implemented using a conventional type of interface.

[0066] The fifth interface unit 116 is used to link the processing logic unit 111 and the algorithm storage module 140, and the algorithm storage module 140 is linked through the fifth interface unit 116 to implement algorithm calling; that is, the processing logic unit 111 (specifically the ARM processor 111a and the FPGA logic resource block 111b) calls the preset algorithm stored in the algorithm storage module 140 through the fifth interface unit 116 to implement the corresponding function by executing the relevant algorithm. Among them, the fifth interface unit 116 does not involve high-speed data transmission, so it can be implemented using a conventional type of interface.

[0067] In combination with specific application scenarios, the pulse data collected by the data processing circuit 100 of this embodiment is not generated by the second peripheral device, but is obtained by the second peripheral device by detecting the pulse data generated by the third peripheral device, that is, the pulse data is generated by the third peripheral device and detected by the second peripheral device; in order to realize feedback control of the third peripheral device, the system-level control module 110 also includes a sixth interface unit 117. Among them, the sixth interface unit 117 is used to link the processing logic unit 111 and the third peripheral device, and the third peripheral device is linked through the sixth interface unit 117 to realize feedback control of the third peripheral device, specifically, the first peripheral device performs feedback control on the third peripheral device via the first interface unit 112, the processing logic unit 111 and the sixth interface unit 117.

[0068] In the above-mentioned system-level control module 110, when each interface unit is connected to the processing logic unit 111, it is connected to both the ARM processor 111a and the FPGA logic resource block 111b; in one embodiment, each interface unit and the ARM processor 111a, each interface unit and the FPGA logic resource block 111b, and the ARM processor 111a and the FPGA logic resource block 111b are connected through the AXI bus to achieve high-bandwidth, low-latency connection. It should be noted that the number of interfaces in each interface unit can be one or more than one. In addition, the number of interfaces of each interface unit can be equal or different. These should be determined by actual needs and there is no restriction on this.

[0069] The data storage module 120 is connected to the system-level control module 110 and is used to transmit data at the transition edge (including the rising edge and the falling edge) of the clock signal to achieve high-speed writing and high-speed reading of pulse data, which is conducive to high-speed data processing. Figure 2 As shown, the data storage module 120 includes a data storage unit 121 and a power filter unit 122 .

[0070] The data storage unit 121 is connected to the system-level control module 110 and is used to perform data transmission at the transition edge of the clock signal. In one embodiment, the data storage unit 121 is implemented using a double-rate synchronous dynamic random access memory, wherein double-rate means that data transmission occurs at both the rising edge and the falling edge of the clock signal, synchronization means that the writing and reading of data are synchronized with the clock, and dynamic means that the data cannot be saved when the power is off and needs to be periodically refreshed to maintain the data; this type of memory has the ability to process large data at high speed, which can ensure efficient data processing of the circuit of this embodiment.

[0071] As an optional solution, the double-rate synchronous dynamic random access memory is implemented using two NT5CC256M16 chips to obtain sufficient storage capacity; the NT5CC256M16 chip has a low-level voltage of 1.35V, a storage capacity of up to 4G, and a transmission speed of up to 1333Mbps, which can achieve high-speed data writing and reading. Among them:

[0072] In the first NT5CC256M16 chip, the VDD port and the VDDQ port are connected to a 1.35V working power supply, the VSS port and the VSSQ port are connected to a reference ground, the VREFDQ port and the VREFCA port are connected to a reference power supply VTTREF (usually provided by a reference circuit), the VREFDQ port and the VREFCA port are also connected to a 1.35V working power supply via a first capacitor C1 and to a reference ground via a second capacitor C2, the ZQ port is connected to a reference ground via a first resistor R1, and the remaining ports are connected to a system-level control module 110, so as to realize writing and reading of corresponding data through relevant logic control;

[0073] In the second NT5CC256M16 chip, the VDD port and the VDDQ port are connected to a 1.35V working power supply, the VSS port and the VSSQ port are connected to a reference ground, the VREFDQ port and the VREFCA port are connected to a reference power supply VTTREF, the VREFDQ port and the VREFCA port are also connected to a 1.35V working power supply via a third capacitor C3 and to a reference ground via a fourth capacitor C4, the ZQ port is connected to a reference ground via a second resistor R2, and the remaining ports are connected to a system-level control module 110 so as to realize writing and reading of corresponding data through relevant logic control; in addition, the RESET ports in the two chips are also connected to a reference ground via a third resistor R3.

[0074] Among them, the first resistor R1 and the second resistor R2 are used as terminal matching resistors, which can eliminate signal reflection and ensure data accuracy; in actual applications, the resistance of the first resistor R1 and the second resistor R2 is 240Ω, in addition, the capacitance of the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 is 10nF, and the resistance of the third resistor R3 is 4.7KΩ.

[0075] The power filter unit 122 is connected to the data storage unit 121 and the power module 130, and the working power (e.g., 1.35V working power) provided by the power module 130 is filtered to stably supply power to the data storage unit 121. In one embodiment, the power filter unit 122 is implemented using a parallel capacitor structure. As an optional solution, the power filter unit 122 includes sixteen fifth capacitors C5, which are connected in parallel between the 1.35V working power and the reference ground. In practical applications, the capacitance of the fifth capacitor C5 is 47nF.

[0076] The algorithm storage module 140 is used to store preset algorithms so that the system-level control module 110 can call the algorithms. In fact, after the system-level control module 110 is powered on, it first calls the preset algorithms from the algorithm storage module 140 and executes the relevant algorithms to perform corresponding operations based on relevant instructions. For example, based on the first instruction, pulse data is collected and written into the data storage module 120, and based on the second instruction, pulse data is read from the data storage module 120 and processed and then output. In one embodiment, the algorithm storage module 140 is implemented by an embedded multimedia controller (eMMC).

[0077] The power supply module 130 is connected to the system-level control module 110 and the data storage module 120, and is used to supply power to the system-level control module 110 and the data storage module 120; correspondingly, when the data processing circuit 100 also includes an algorithm storage module 140, the power supply module 130 is also connected to the algorithm storage module 140, and is used to supply power to the algorithm storage module 140.

[0078] In an example, Figure 3As shown, the power module 130 includes a voltage conversion unit 131 and a linear voltage stabilization unit 132, which cooperate to convert the input power into the working power required for the operation of each module; the power module 130 ensures the stable operation of each module by providing a stable and reliable working power supply for each module. In one embodiment, the voltage value of the input power supply is 5V, and the working power supply includes a 1.0V working power supply, a 1.35V working power supply, a 1.8V working power supply, a 3.3V working power supply and a VCCIO working power supply, wherein the working power supply required by the system-level control module 110 includes a 1.0V working power supply, a 1.35V working power supply, a 1.8V working power supply, a 3.3V working power supply and a VCCIO working power supply, the working power supply required by the data storage module 120 includes a 1.35V working power supply, and the working power supply required by the algorithm storage module 140 includes a 1.8V working power supply.

[0079] As an optional solution, the voltage conversion unit 131 is implemented by the EA3059 chip, and the linear voltage regulator unit 132 is implemented by the SPX3819M5-3-3 chip. Among them: the EA3059 chip is a kind of DC-DC chip, which has the characteristics of high performance, low ripple, high stability, and multiple power output, and has a wide input voltage range, which can avoid the interference caused by power supply jitter, and has high conversion efficiency, the conversion efficiency is as high as 95%, the output voltage range is wide, and the output current is large, which can reach up to 4A at most; the SPX3819M5-3-3 chip is a kind of LDO chip, which has the characteristics of low ripple and high stability, and has low noise capability, only 40μV, low voltage drop, only 340mV, and low quiescent current, only 90μA.

[0080] In the EA3059 chip, the EN1 port is connected to the 5V input power supply via the fourth resistor R4 and to the reference ground via the sixth capacitor C6, the EN2 port and the EN4 port are connected to each other, the EN3 port is connected to the 5V input power supply via the fifth resistor R5 and to the reference ground via the seventh capacitor C7, the EN4 port is connected to the 1.8V working power supply via the sixth resistor R6 and to the reference ground via the eighth capacitor C8; the VIN1 port is connected to the 5V input power supply and to the reference ground via the ninth capacitor C9 and the tenth capacitor C10 connected in parallel, the VIN2 port is connected to the 5V input power supply and to the reference ground via the eleventh capacitor C10 connected in parallel. The capacitor C11 and the twelfth capacitor C12 are connected to the reference ground, the VIN3 port is connected to the 5V input power supply and connected to the reference ground via the thirteenth capacitor C13 and the fourteenth capacitor C14 connected in parallel, the VIN4 port is connected to the 5V input power supply and connected to the reference ground via the fifteenth capacitor C15 and the sixteenth capacitor C16 connected in parallel, the VCC port is connected to the 5V input power supply and connected to the reference ground via the seventeenth capacitor C17 and the eighteenth capacitor C18 connected in parallel; the GND port, the AGND port, the PGND1 port, the PGND2 port, the PGND3 port and the PGND4 port are connected to the reference ground;

[0081] The LX1 port is connected to the FB1 port via the first inductor L1 and the seventh resistor R7 connected in series, the nineteenth capacitor C19 is connected in parallel to both ends of the seventh resistor R7, the twentieth capacitor C20 and the twenty-first capacitor C21 connected in parallel are connected between the connection node of the first inductor L1 and the seventh resistor R7 and the reference ground, and the FB1 port is connected to the reference ground via the eighth resistor R8, wherein the connection node of the first inductor L1 and the seventh resistor R7 outputs a 1.0V working power supply; the LX2 port is connected to the FB2 port via the second inductor L2 and the ninth resistor R9 connected in series, the twenty-second capacitor C22 is connected in parallel to both ends of the ninth resistor R9, the twenty-third capacitor C23 and the twenty-fourth capacitor C24 are connected in parallel between the connection node of the second inductor L2 and the ninth resistor R9 and the reference ground, and the FB2 port is connected to the reference ground via the tenth resistor R10, wherein the connection node of the second inductor L2 and the ninth resistor R9 outputs a 1.35V working power supply; The third inductor L3 and the eleventh resistor R11 are connected to the FB3 port, the twenty-fifth capacitor C25 is connected in parallel to the two ends of the eleventh resistor R11, the twenty-sixth capacitor C26 and the twenty-seventh capacitor C27 in parallel are connected between the connection node of the third inductor L3 and the eleventh resistor R11 and the reference ground, and the FB3 port is connected to the reference ground via the twelfth resistor R12, wherein the connection node of the third inductor L3 and the eleventh resistor R11 outputs a 1.8V working power supply; the LX4 port is connected to the FB4 port via the fourth inductor L4 and the thirteenth resistor R13 connected in series, the twenty-eighth capacitor C28 is connected in parallel to the two ends of the thirteenth resistor R13, the twenty-ninth capacitor C29 and the thirtieth capacitor C30 are connected in parallel between the connection node of the fourth inductor L4 and the thirteenth resistor R13 and the reference ground, and the FB4 port is connected to the reference ground via the fourteenth resistor R14, wherein the connection node of the fourth inductor L4 and the thirteenth resistor R13 outputs a 3.3V working power supply.

[0082] In practical applications, the resistance of the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6 is 100KΩ, the capacitance of the sixth capacitor C6, the seventh capacitor C7 and the eighth capacitor C8 is 0.01μF, the capacitance of the ninth capacitor C9, the eleventh capacitor C11, the thirteenth capacitor C13, the fifteenth capacitor C15 and the seventeenth capacitor C17 is 10μF, the capacitance of the tenth capacitor C10, the twelfth capacitor C12, the fourteenth capacitor C14, the sixteenth capacitor C16 and the eighteenth capacitor C18 is 0.1μF, the inductance of the first inductor L1, the second inductor L2, the third inductor L3 and the fourth inductor L4 is 1.5μH, the nineteenth capacitor C19, the twenty-second capacitor C22, the twenty-fifth capacitor C The capacitance of the 25th and 28th capacitors C28 is 220pF, the capacitance of the 20th capacitor C20, the 23rd capacitor C23, the 26th capacitor C26 and the 29th capacitor C29 is 0.1μF, the capacitance of the 21st capacitor C21, the 24th capacitor C24, the 27th capacitor C27 and the 30th capacitor C30 is 22μF, the resistance of the seventh resistor R7 is 67KΩ, the resistance of the eighth resistor R8 and the twelfth resistor R12 is 100KΩ, the resistance of the ninth resistor R9 and the eleventh resistor R11 is 200KΩ, the resistance of the tenth resistor R10 is 160KΩ, the resistance of the thirteenth resistor R13 is 510KΩ, and the resistance of the fourteenth resistor R14 is 110KΩ.

[0083] In the SPX3819M5-3-3 chip, the VIN port is connected to the 5V input power supply and connected to the reference ground through the 31st capacitor C31 and the 32nd capacitor C32 connected in parallel, the EN port is connected to the 3.3V working power supply, the GND port is connected to the reference ground, and the VOUT port outputs the VCCIO working power supply and is connected to the reference ground through the 33rd capacitor C33 and the 34th capacitor C34 connected in parallel. In practical applications, the capacitance of the 31st capacitor C31 and the 33rd capacitor C33 is 10μF, and the capacitance of the 32nd capacitor C32 and the 34th capacitor C34 is 0.1μF.

[0084] When the working power supplies are generated by the EA3059 chip and the SPX3819M5-3-3 chip, the generation order of the working power supplies is 1.0V→1.8V→1.35→3.3V→VCCIO. Therefore, in the data processing circuit 100 of this embodiment, each module is powered on in the order of 1.0V→1.8V→1.35→3.3V→VCCIO.

[0085] Embodiment 2

[0086] like Figure 4 As shown, this embodiment provides a circuit system 10, including a data processing circuit 100, a first peripheral device 200 and a second peripheral device 300; further, it also includes a third peripheral device 400.

[0087] The data processing circuit 100 is implemented by using the circuit structure described in the first embodiment. The relevant contents can be found in the above text and will not be described in detail in this embodiment.

[0088] The first peripheral device 200 is connected to the data processing circuit 100, and is used to send the first instruction and the second instruction to the data processing circuit 100, and receive the pulse data output by the data processing circuit 200 for subsequent processing; in actual application, the first peripheral device 200 performs subsequent processing on the received pulse data to monitor the pulse data, so as to realize feedback control. In one embodiment, the first peripheral device 200 is implemented by a host computer.

[0089] The second peripheral device 300 is connected to the data processing circuit 100 and is used to provide pulse data to the data processing circuit 100. In practical applications, the second peripheral device 300 does not directly generate pulse data, but detects the pulse data generated by the third peripheral device 400 and provides it to the data processing circuit 100. In one embodiment, the second peripheral device 300 is implemented by a detector.

[0090] The third peripheral device 400 is connected to the data processing circuit 100 and the second peripheral device 300, and receives the configuration information transmitted by the first peripheral device 200 through the data processing circuit 100 to perform parameter configuration and generate pulse data; when the third peripheral device 400 is feedback-controlled by the first peripheral device 200, the first peripheral device 200 adjusts the configuration information based on the processing result and transmits it to the third peripheral device 400 through the data processing circuit 100 to implement feedback control of the third peripheral device 400. In one embodiment, the third peripheral device 400 is implemented by a laser, and in this case, the configuration information is mainly used to set parameters such as the intensity of the laser pulse.

[0091] In practical applications, the circuit system 10 of this embodiment can be applied in the semiconductor manufacturing process, for example, in a device for measuring the thickness of a wafer by a laser, or in a device for cleaning the surface of a wafer by a laser; adding the circuit system 10 to the above device to monitor the laser and implement feedback control can avoid the problem of wafer damage due to abnormal laser irradiation.

[0092] In summary, the data processing circuit and circuit system of the present invention, through the design of the system-level control module, the data storage module and the power module, proposes a new high-speed data processing solution, which can sample and process high-speed pulse signals in real time and is suitable for application scenarios with large amounts of data. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0093] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A data processing circuit, characterized in that: The data processing circuit comprises: A system-level control module, based on a first instruction, collects pulse data and writes the pulse data into a data storage module, and based on a second instruction, reads the pulse data from the data storage module and performs data processing before outputting the data; A data storage module, connected to the system-level control module, for transmitting data at the transition edge of the clock signal to achieve writing and reading of the pulse data; a power module, connected to the system-level control module and the data storage module, and used to supply power to the system-level control module and the data storage module; Wherein, the sampling frequency of the system-level control module is greater than or equal to twice the pulse frequency of the pulse data.

2. The data processing circuit according to claim 1, characterized in that: The data processing circuit further includes: The algorithm storage module is used to store the preset algorithm; after the system-level control module is powered on, the preset algorithm is called from the algorithm storage module to perform corresponding operations based on relevant instructions, and the power supply module is also connected to the algorithm storage module to supply power to it.

3. The data processing circuit according to claim 2, characterized in that: The algorithm storage module is implemented by an embedded multimedia controller.

4. The data processing circuit according to any one of claims 1 to 3, characterized in that: The system-level control module includes a processing logic unit, a first interface unit, a second interface unit, a third interface unit and a fourth interface unit. The processing logic unit serves as a master control unit and performs data acquisition and processing. The first interface unit is used to link the first peripheral device to realize the transmission of instructions and data. The second interface unit is used to link the second peripheral device to realize data acquisition. The third interface unit is used to link the data storage module to realize data writing and reading. The fourth interface unit is used to link the power supply module to realize power supply. The processing logic unit includes an ARM processor and an FPGA logic resource block. The first interface unit, the second interface unit and the third interface unit are implemented using a gigabit network interface. When the data processing circuit further includes an algorithm storage module, the system-level control module further includes a fifth interface unit, and the algorithm storage module is linked via the fifth interface unit to implement algorithm calling.

5. The data processing circuit according to claim 4, characterized in that: The system-level control module further includes a sixth interface unit, through which a third peripheral device is linked to implement feedback control, wherein the pulse data is generated by the third peripheral device and detected by the second peripheral device.

6. The data processing circuit according to any one of claims 1 to 3, characterized in that: The data storage module comprises: A data storage unit, connected to the system-level control module, for transmitting data at the transition edge of a clock signal; The power filter unit is connected to the power module and the data storage unit, and provides stable power supply to the data storage unit by filtering the working power provided by the power module.

7. The data processing circuit according to claim 6, characterized in that: The data storage unit is implemented by a double rate synchronous dynamic random access memory, and / or the power supply filter unit is implemented by a parallel capacitor structure.

8. The data processing circuit according to any one of claims 1 to 3, characterized in that: The power supply module comprises a voltage conversion unit and a linear voltage stabilization unit, which cooperate to convert input power into working power required by each module.

9. A circuit system, characterized in that: The circuit system comprises: The data processing circuit according to any one of claims 1 to 8; A first peripheral device, connected to the data processing circuit, used to send a first instruction and a second instruction to the data processing circuit, and receive pulse data output by the data processing circuit; The second peripheral device is connected to the data processing circuit and is used to provide the pulse data to the data processing circuit.

10. The circuit system according to claim 9, characterized in that: The circuit system further comprises: A third peripheral device is connected to the data processing circuit and the second peripheral device, receives configuration information transmitted by the first peripheral device via the data processing circuit to perform parameter configuration and generate the pulse data, wherein the second peripheral device detects the pulse data generated by the third peripheral device and provides it to the data processing circuit.

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