Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure and the semiconductor structure. The manufacturing method comprises the following steps: providing a supporting plate which comprises a substrate and a conductive layer positioned on one side of the substrate; a conductive frame is arranged on the side, away from the substrate, of the conductive layer, the conductive frame is connected with the conductive layer, and the conductive frame comprises a base island and a conductive column; a chip is mounted on the base island, the chip comprises a chip front face, a chip back face and a chip side face, and a plurality of welding pads are arranged on the chip front face; the back surface of the chip faces the base island; forming a plastic package layer, wherein the plastic package layer at least encapsulates the side surface of the chip and the side surface of the frame; forming a re-wiring layer on one side, far away from the supporting plate, of the plastic packaging layer, wherein the re-wiring layer is electrically connected with the welding pads and the conductive columns respectively; and the substrate is removed, the conductive layer is patterned to obtain a trace layer, and the trace layer is in direct contact with the conductive columns and the base islands respectively.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] Common semiconductor packaging technologies, such as chip packaging technology, mainly include the following process: first, the front side of the chip is bonded to the carrier and hot-pressed and sealed, the carrier is peeled off to obtain the encapsulation structure, and then a rewiring layer is formed on the encapsulation structure. The rewiring layer is used to lead out the internal circuits of the chip.

[0003] The existing semiconductor structure has the problem of poor heat dissipation effect, which affects the performance of the semiconductor structure. Summary of the invention

[0004] The embodiments of the present application provide a method for manufacturing a semiconductor structure and a semiconductor structure.

[0005] A first aspect of an embodiment of the present application provides a method for manufacturing a semiconductor structure, the manufacturing method comprising:

[0006] Providing a support plate, the support plate comprising a substrate and a conductive layer located on one side of the substrate;

[0007] A conductive frame is arranged on a side of the conductive layer away from the substrate, and the conductive frame is connected to the conductive layer, wherein the conductive frame includes a base island and a conductive column;

[0008] Mounting a chip on the base island, the chip comprising a chip front, a chip back opposite to the chip front, and a chip side connecting the chip front and the chip back, the chip front being provided with a plurality of pads; the chip back facing the base island;

[0009] forming a plastic encapsulation layer, wherein the plastic encapsulation layer at least encapsulates the side surface of the chip and the side surface of the conductive frame;

[0010] A rewiring layer is formed on a side of the plastic encapsulation layer away from the support plate, wherein the rewiring layer is electrically connected to the pad and the conductive column respectively;

[0011] The substrate is removed, and the conductive layer is patterned to obtain a trace layer, wherein the trace layer is in direct contact with the conductive pillar and the base island respectively.

[0012] In one embodiment, the step of disposing a conductive frame on a surface of the conductive layer facing away from the substrate and connecting the conductive frame to the conductive layer comprises:

[0013] Using a screen printing process to arrange solder on the surface of the conductive layer away from the substrate;

[0014] The conductive frame is placed on the solder, and the conductive frame is welded to the conductive layer through the solder.

[0015] In one embodiment, the plastic encapsulation layer encapsulates the front side of the chip; before forming the plastic encapsulation layer, the method for manufacturing the semiconductor structure further includes: determining the position of the bonding pad;

[0016] Before forming a redistribution layer on a side of the plastic encapsulation layer away from the support plate, the method for manufacturing the semiconductor structure further comprises:

[0017] A plurality of openings are formed on a side of the plastic packaging layer away from the support plate according to the position of the welding pad, each of the openings exposes one welding pad; and the rewiring layer is electrically connected to the welding pad through the openings.

[0018] In one embodiment, a conductive convex column is formed on each of the pads, and before forming a redistribution layer on a side of the plastic encapsulation layer away from the support plate, the method for manufacturing the semiconductor structure further comprises: determining a position of each of the conductive convex columns;

[0019] The forming of a rewiring layer on a side of the plastic packaging layer away from the support plate comprises: forming a rewiring layer according to the position of each of the conductive protrusions, wherein the rewiring layer is electrically connected to the conductive protrusions.

[0020] In one embodiment, before forming the plastic encapsulation layer, the method for manufacturing the semiconductor structure further comprises: arranging a passive device on a side of the conductive layer away from the substrate, wherein a pin of the passive device is connected to the conductive layer;

[0021] The plastic encapsulation layer at least encapsulates the side surface of the passive component; the pins of the passive component are electrically connected to the conductive pillars through the trace layer.

[0022] In one embodiment, the pins of the passive device are connected to the conductive layer through solder; before the passive device is arranged on a side of the conductive layer away from the substrate, the method for manufacturing the semiconductor structure further comprises:

[0023] A solder resist material is disposed on a side of the conductive layer away from the substrate, and the solder resist material is at least located in a region between solders connected to two adjacent pins.

[0024] In one embodiment, the trace layer includes a plurality of trace structures, each pin of the passive device is connected to one of the trace structures, and there is a gap between the trace structures connected to adjacent pins of the same passive device;

[0025] After removing the substrate and patterning the conductive layer to obtain a trace layer, the method for manufacturing the semiconductor structure further includes:

[0026] An insulating layer is formed, the insulating layer covers the trace layer and the exposed surface of the conductive frame; part of the material of the insulating layer enters the gap between the trace structure and the passive device through the gap between the trace structures connected to the adjacent pins of the same passive device.

[0027] In one embodiment, after removing the substrate and patterning the conductive layer to obtain a trace layer, the method for manufacturing the semiconductor structure further includes:

[0028] An electrical component is arranged on a side of the trace layer away from the chip. The electrical component includes at least one of a chip and a passive device. The electrical component is electrically connected to the trace layer.

[0029] In one embodiment, the cross-sectional area of ​​the support plate is greater than 300 mm*300 mm.

[0030] A second aspect of an embodiment of the present application provides a semiconductor structure, wherein the semiconductor structure comprises:

[0031] A conductive frame, including a base island and conductive columns;

[0032] A chip is located on the base island, the chip comprises a chip front, a chip back opposite to the chip front, and a chip side connecting the chip front and the chip back, the chip front is provided with a plurality of pads; the chip back faces the base island;

[0033] A plastic encapsulation layer, encapsulating at least the side surface of the chip and the side surface of the conductive frame;

[0034] A redistribution layer, located on a side of the plastic packaging layer away from the back of the chip, and electrically connected to the pad and the conductive column;

[0035] The trace layer is located on a side of the plastic packaging layer away from the redistribution layer, and the trace layer is directly in contact with and connected to the conductive pillar and the base island respectively.

[0036] The main technical effects achieved by the embodiments of the present application are:

[0037] The manufacturing method and semiconductor structure of the semiconductor structure provided in the embodiment of the present application are as follows: a conductive frame connected to the conductive layer is arranged on the side of the conductive layer away from the substrate, and the back side of the chip is mounted on the base island of the conductive frame. Since the conductive frame is prefabricated, the thickness of the base island and the size of the conductive column can be set to be larger, which can improve the heat dissipation capacity of the obtained semiconductor structure and reduce the internal resistance of the semiconductor structure; a trace layer directly in contact with the conductive column and the base island is obtained by graphically processing the conductive layer of the support plate, and the trace layer can further improve the heat dissipation capacity of the semiconductor structure and reduce the internal resistance of the semiconductor structure; by adopting a support plate including a substrate and a conductive layer, the strength of the support plate is relatively large, and the strength of the intermediate structure formed in the manufacturing process of the semiconductor structure can be ensured to be relatively large, and the board is not easily broken during the transfer of the intermediate structure, so the size of the support plate can be set to be relatively large, that is, the manufacturing method provided in the embodiment of the present application can be used for large-size board-level packaging, which helps to improve the manufacturing efficiency of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0039] Figure 2 is a partial cross-sectional view of a first intermediate structure provided by an exemplary embodiment of the present application;

[0040] Figure 3 is a partial cross-sectional view of a second intermediate structure provided by an exemplary embodiment of the present application;

[0041] Figure 4 is a partial cross-sectional view of a third intermediate structure provided by an exemplary embodiment of the present application;

[0042] Figure 5 is a partial cross-sectional view of a fourth intermediate structure provided by an exemplary embodiment of the present application;

[0043] Figure 6 is a partial cross-sectional view of a fifth intermediate structure provided by an exemplary embodiment of the present application;

[0044] Figure 7 is a partial cross-sectional view of a sixth intermediate structure provided by an exemplary embodiment of the present application;

[0045] Figure 8 is a partial cross-sectional view of a sixth intermediate structure provided by another exemplary embodiment of the present application;

[0046] Fig. 9 is a partial cross-sectional view of a seventh intermediate structure provided by an exemplary embodiment of the present application;

[0047] Fig.10is a partial cross-sectional view of an eighth intermediate structure provided by an exemplary embodiment of the present application;

[0048] Fig.11 is a partial cross-sectional view of a ninth intermediate structure provided by an exemplary embodiment of the present application;

[0049] Fig.12 is a partial cross-sectional view of a tenth intermediate structure provided by an exemplary embodiment of the present application;

[0050] Fig.13 is a partial cross-sectional view of an eleventh intermediate structure provided by an exemplary embodiment of the present application;

[0051] Fig.14 is a cross-sectional view of a semiconductor structure provided by an exemplary embodiment of the present application;

[0052] Fig.15 is a cross-sectional view of a semiconductor structure provided by another exemplary embodiment of the present application;

[0053] Fig.16 is a cross-sectional view of a semiconductor structure provided by yet another exemplary embodiment of the present application. Specific embodiments

[0054] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0055] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0056] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0057] Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0058] The present application provides a method for manufacturing a semiconductor structure. Figure 1 As shown, the manufacturing method includes the following steps 110 to 160.

[0059] In step 110 , a support plate is provided, wherein the support plate includes a substrate and a conductive layer located on one side of the substrate.

[0060] In step 120, a conductive frame is disposed on a side of the conductive layer away from the substrate, and the conductive frame is connected to the conductive layer, wherein the conductive frame includes a base island and a conductive column.

[0061] In step 130, a chip is mounted on the base island, the chip comprising a chip front, a chip back opposite to the chip front, and a chip side connecting the chip front and the chip back, the chip front is provided with a plurality of pads; the chip back faces the base island.

[0062] In step 140 , a plastic encapsulation layer is formed, wherein the plastic encapsulation layer at least encapsulates the side surface of the chip and the side surface of the conductive frame.

[0063] In step 150, a rewiring layer is formed on a side of the plastic packaging layer away from the support plate, and the rewiring layer is electrically connected to the pads and the conductive pillars respectively.

[0064] In step 160, the substrate is removed, and the conductive layer is patterned to obtain a trace layer, wherein the trace layer is in direct contact with the conductive pillars and the base islands respectively.

[0065] The manufacturing method of the semiconductor structure provided in the embodiment of the present application is that a conductive frame connected to the conductive layer is set on the side of the conductive layer away from the substrate, and the back side of the chip is mounted on the base island of the conductive frame. Since the conductive frame is prefabricated, the thickness of the base island and the size of the conductive column can be set to be larger, which can improve the heat dissipation capacity of the obtained semiconductor structure and reduce the internal resistance of the semiconductor structure; the trace layer directly in contact with the conductive column and the base island is obtained by graphically processing the conductive layer of the support plate, and the trace layer can further improve the heat dissipation capacity of the semiconductor structure and reduce the internal resistance of the semiconductor structure; by adopting a support plate including a substrate and a conductive layer, the strength of the support plate is relatively large, and the strength of the intermediate structure formed in the manufacturing process of the semiconductor structure can be ensured to be relatively large. In the process of transferring the intermediate structure, it is not easy to break the board, and the size of the support plate can be set to be relatively large, that is, the manufacturing method provided in the embodiment of the present application can be used for large-size board-level packaging, which helps to improve the manufacturing efficiency of the semiconductor structure.

[0066] The following is a detailed introduction to each step of the method for manufacturing a semiconductor structure provided in an embodiment of the present application.

[0067] In step 110 , a support plate is provided, wherein the support plate includes a substrate and a conductive layer located on one side of the substrate.

[0068] In one embodiment, the material of the substrate is an insulating material, for example, the material of the substrate may be glass fiber, so that it is easy to remove the substrate in subsequent steps.

[0069] In one embodiment, the conductive layer is made of metal, for example, copper. Such a conductive layer has good heat dissipation capability and low resistivity, which is more helpful to improve the heat dissipation capability and internal resistance of the semiconductor structure. In some embodiments, the support plate can be a copper-clad substrate.

[0070] In one embodiment, the support plate further comprises a conductive material layer, and the conductive material layer is located on a side of the substrate away from the conductive layer. The provision of the conductive material layer can further enhance the strength of the support plate. In the preparation process of the support plate, an electroplating process is generally used to simultaneously form the conductive layer and the conductive material layer on the substrate. When the support plate comprises the conductive layer and the conductive material layer, compared with a solution in which the support plate only comprises the conductive layer, the conductive material layer does not need to be removed after the electroplating process, which can simplify the preparation process of the support plate and reduce the preparation cost of the support plate.

[0071] In one embodiment, the cross-sectional area of ​​the support plate is greater than 300mm*300mm. With such a configuration, the cross-sectional area of ​​the support plate is relatively large, and large-sized board-level packaging can be realized. In some embodiments, the cross-sectional area of ​​the support plate may be, for example, 600mm*600mm. The cross-sectional area of ​​the support plate is Xmm*Ymm, which means that the cross-sectional area of ​​the support plate is rectangular, and the lengths of the two adjacent sides of the rectangle are Xmm and Ymm respectively. For example, the cross-sectional area of ​​the support plate is 600mm*600mm, which means that the cross-sectional area of ​​the support plate is square, and the side length of the square is 600mm.

[0072] In step 120, a conductive frame is disposed on a side of the conductive layer away from the substrate, and the conductive frame is connected to the conductive layer, wherein the conductive frame includes a base island and a conductive column.

[0073] Through this step, we can obtain Figure 2 The first intermediate structure shown. Figure 2As shown, the support plate 10 includes a substrate 12, a conductive layer 11 and a conductive material layer 13, and the conductive layer 11 and the conductive material layer 13 are located on opposite sides of the substrate 12; the conductive frame 20 is located on the surface of the conductive layer 11 away from the substrate 12 and is connected to the conductive layer 11; the conductive frame 20 includes a base island 21 and a plurality of conductive columns 22, and the base island 21 can be connected to a conductive column 22.

[0074] In one embodiment, the conductive frame 20 is connected to the conductive layer 11 by welding, so that the conductive frame 20 and the conductive layer 11 can be more firmly connected, which helps to improve the strength of the intermediate structure and the strength of the semiconductor structure.

[0075] In one embodiment, the step of providing a conductive frame on a surface of the conductive layer facing away from the substrate and connecting the conductive frame to the conductive layer comprises the following process:

[0076] First, solder is disposed on the surface of the conductive layer facing away from the substrate by using a screen printing process;

[0077] Subsequently, the conductive frame is placed on the solder, and the conductive frame is soldered to the conductive layer through the solder.

[0078] By using the screen printing process to set solder on the surface of the conductive layer away from the substrate, the area where the solder is set is the step of subsequently welding the conductive frame. Therefore, using the screen printing process to set solder can play a role in positioning the conductive frame, preventing the setting position of the conductive frame from being greatly offset, and improving the position accuracy of the conductive frame. The position of the mesh of the screen used in the screen printing process can be determined according to the design position of the conductive frame.

[0079] In one embodiment, the solder is solder paste, which is easy to remove. If the position of the conductive frame is greatly offset, the solder paste between the conductive frame and the conductive layer can be removed, and the conductive frame can be repositioned and soldered to correct its position.

[0080] In step 130, a chip is mounted on the base island, the chip comprising a chip front, a chip back opposite to the chip front, and a chip side connecting the chip front and the chip back, the chip front is provided with a plurality of pads; the chip back faces the base island.

[0081] Through this step, we can obtain Figure 3 The second intermediate structure shown. Figure 3 As shown, the back side of the chip 30 is completely located on the base island 21, so that the heat generated by the chip 30 can be better transferred to the outside through the base island 21. The back side of the chip 30 can be soldered to the base island 21 by solder, or can be mounted on the base island 21 by an adhesive film.

[0082] In one embodiment, the chip 30 is provided with an electrode on the back side of the chip, and the electrode on the back side of the chip 30 is electrically connected to the base island 21 , so that the electrode on the back side of the chip can guide the front side of the chip through the base island 21 and the conductive pillar 22 .

[0083] In one embodiment, Figure 3 As shown, the chip 30 is further provided with a protective layer 32 on the front side thereof, and the protective layer 32 is provided with a plurality of openings 321 , each of which exposes at least a portion of the surface of a pad 31 . The openings 321 and the pads 31 may correspond one to one, and each opening 321 exposes the corresponding pad 31 .

[0084] In one embodiment, before the step of forming the plastic encapsulation layer, the method for manufacturing the semiconductor structure further comprises: arranging a passive device on a side of the conductive layer away from the substrate, wherein the pins of the passive device are connected to the conductive layer. Figure 3 As shown, the pin 81 of the passive device 80 is connected to the conductive layer 11. By arranging the passive device on the side of the conductive layer away from the substrate, the function of the semiconductor structure can be expanded and the performance of the semiconductor structure can be improved. The chip 30 and the passive device 80 are arranged in the horizontal direction, which helps to reduce the thickness of the semiconductor structure and realize the thinness of the semiconductor structure.

[0085] In one embodiment, SMT (Surface Mount Technology) can be used to mount the passive device 80 on the side of the conductive layer 11 away from the substrate 12. Since the surface flatness of the conductive layer 11 away from the substrate 12 is good and the strength of the support plate is relatively large, SMT can also be used to mount the passive device 80 when the size of the support plate is large. Compared with the solution of first forming a plastic layer encapsulating the chip, then cutting the obtained structure, and then using SMT to mount the passive device on the surface of the plastic layer, the embodiment of the present application can directly mount the passive device on a large-sized support plate, saving the process step of cutting the intermediate structure and simplifying the manufacturing process of the semiconductor structure.

[0086] In one embodiment, Figure 3 As shown, the distance between the front surface of the chip 30 and the conductive layer 11 is smaller than the distance between the surface of the conductive pillar 22 away from the conductive layer 11 and the conductive layer 11. In this way, when the plastic encapsulation layer is formed in the subsequent step and then thinned to expose the surface of the conductive pillar 22 away from the conductive layer 11, damage to the front surface of the chip can be avoided.

[0087] Furthermore, the height difference between the surface of the chip front of the chip 30 away from the conductive layer 11 and the surface of the conductive column 22 away from the conductive layer 11 ranges from 30μm to 50μm. This arrangement can effectively avoid the height difference being too small, which may cause damage to the chip front during the thinning of the plastic layer, and can also avoid the height difference being too large, which may cause difficulty in the process when forming an opening on the plastic layer to expose the solder pad. In some embodiments, the height difference between the surface of the chip front of the chip 30 away from the conductive layer 11 and the surface of the conductive column 22 away from the conductive layer 11 may be 30μm, 35μm, 40μm, 45μm, 50μm, etc.

[0088] In one embodiment, Figure 3 As shown, the distance between the surface of the passive device 80 away from the conductive layer 11 and the conductive layer 11 is smaller than the distance between the surface of the conductive pillar 22 away from the conductive layer 11 and the conductive layer 11. In this way, in the subsequent step of forming the plastic encapsulation layer and thinning the plastic encapsulation layer to expose the surface of the conductive pillar 22 away from the conductive layer 11, damage to the passive device 80 can be avoided.

[0089] Furthermore, the height difference between the surface of the passive device 80 away from the conductive layer 11 and the surface of the conductive pillar 22 away from the conductive layer 11 is greater than or equal to 50 μm. This arrangement can effectively avoid damage to the passive device 80 during the thinning process of the plastic packaging layer.

[0090] In one embodiment, the step of disposing a passive component on a side of the conductive layer facing away from the substrate may be performed before step 120 , or may be performed after step 120 , or may be performed simultaneously with step 120 .

[0091] In one embodiment, the pin 81 of the passive device 80 can be soldered to the conductive layer 11 by solder. In this way, the passive device 80 and the conductive layer 11 can be firmly connected to prevent the two from being separated. In the step of setting the solder on the surface of the conductive layer away from the substrate using the screen printing process, the solder used to solder the conductive frame 20 and the conductive layer 11 and the solder used to solder the passive device 80 and the conductive layer 11 can be simultaneously set on the surface of the conductive layer 11 away from the substrate 12, which helps to simplify the manufacturing process of the semiconductor structure.

[0092] In one embodiment, the passive device 80 includes at least one of an inductor, a resistor and a capacitor.

[0093] In step 140 , a plastic encapsulation layer is formed, wherein the plastic encapsulation layer at least encapsulates the side surface of the chip and the side surface of the conductive frame.

[0094] In one embodiment, the step of forming the plastic encapsulation layer may include the following process:

[0095] First, a plastic encapsulation layer is formed, and the plastic encapsulation layer encapsulates the side surface of the chip, the front surface of the chip, the side surface of the conductive column and the surface of the conductive column away from the conductive layer.

[0096] Through this step, we can obtain Figure 4 The third intermediate structure shown. Figure 4 As shown, the thickness of the plastic encapsulation layer is greater than the thickness of the conductive column 22 , and the surface of the conductive column 22 away from the conductive layer 11 , the front side of the chip 30 , and the surface of the passive device 80 away from the conductive layer 11 are all encapsulated by the plastic encapsulation layer 40 ; the plastic encapsulation layer fills the opening 321 of the protective layer 32 .

[0097] Subsequently, the surface of the plastic packaging layer away from the conductive layer is thinned to expose the surface of the conductive pillar away from the conductive layer.

[0098] Through this step, we can obtain Figure 5 The fourth intermediate structure shown. Figure 5 As shown, the surface of the conductive pillar 22 away from the conductive layer 11 is flush with the surface of the plastic layer 40 away from the conductive layer 11 , and the plastic layer 40 still encapsulates the chip front side of the chip 30 and the surface of the passive device 80 away from the conductive layer 11 .

[0099] In one embodiment, before the step of forming the plastic encapsulation layer, some pre-treatment steps, such as chemical cleaning, plasma cleaning, etc., can be performed to remove impurities on the surface of the chip 30, impurities on the surface of the passive device 80, impurities on the surface of the conductive frame 20, and impurities on the surface of the conductive layer 11, so that the plastic encapsulation layer and the chip 30, the passive device 80, the conductive frame 20 and the conductive layer 11 can be more closely connected without delamination or cracking.

[0100] In one embodiment, the material of the plastic encapsulation layer 40 may be a polymer resin, a resin composite material, a polymer composite material, etc. For example, the plastic encapsulation layer 40 may be a resin with a filler, wherein the filler may be an inorganic particle. The plastic encapsulation layer 40 may be formed by injection molding, compression molding, or transfer molding.

[0101] In one embodiment, before the step of forming the plastic encapsulation layer, the method for manufacturing the semiconductor structure further includes: determining the position of the pad. By determining the position of the pad, an opening to expose the pad can be formed on the plastic encapsulation layer according to the position of the pad, which helps to ensure that the pad is exposed by the opening, thereby ensuring the electrical connection between the rewiring layer and the pad. In some embodiments, a position detection device can be used to scan the fourth intermediate structure to determine the position of the pad.

[0102] In another embodiment, conductive convex pillars are formed on each of the pads 31 of the chip 30, and before the step of forming a rewiring layer on the side of the plastic encapsulation layer away from the support plate, the method for manufacturing the semiconductor structure further includes: determining the position of each of the conductive convex pillars. By determining the position of the conductive convex pillars, a rewiring layer can be formed according to the position of the conductive convex pillars, which helps to ensure the electrical connection effect between the rewiring layer and the conductive convex pillars, and ensures that the rewiring layer leads out the pads through the conductive convex pillars.

[0103] In this embodiment, the surface of the conductive protrusion facing away from the conductive layer 11 can be flush with the surface of the plastic layer 40 facing away from the conductive layer 11, that is, the surface of the conductive protrusion facing away from the conductive layer 11 is exposed from the plastic layer 40, so that the subsequently formed rewiring layer is in direct contact with the conductive protrusion, ensuring the electrical connection effect between the rewiring layer and the conductive protrusion.

[0104] In step 150, a rewiring layer is formed on a side of the plastic packaging layer away from the support plate, and the rewiring layer is electrically connected to the pads and the conductive pillars respectively.

[0105] In one embodiment, when no conductive protrusion is formed on the surface of the bonding pad, before the step of forming a redistribution layer on a side of the plastic encapsulation layer away from the support plate, the method for manufacturing the semiconductor structure further includes:

[0106] A plurality of openings are formed on a side of the plastic packaging layer away from the support plate according to the position of the welding pad, each of the openings exposes one welding pad; and the rewiring layer is electrically connected to the welding pad through the openings.

[0107] Through this step, we can obtain Figure 6 The fifth intermediate structure shown. Figure 6 As shown, the plastic layer 40 is provided with openings 41 corresponding to the pads 31 , and each opening 41 exposes a portion of the corresponding pad 31 ; the opening 41 penetrates the portion of the plastic layer 40 located on one side of the protective layer 32 and the portion of the plastic layer 40 located in the opening 321 .

[0108] In one embodiment, the opening 41 may be formed by a laser etching process.

[0109] Through step 150, the following can be obtained: Figure 7 or Figure 8 The sixth intermediate structure shown. Figure 7 or Figure 8 As shown, the rewiring layer 50 is electrically connected to the pad 31 through the conductive portion 52 located in the opening 41; the rewiring layer 50 includes a plurality of wiring structures 51, each pad 31 is electrically connected to a wiring structure 51; the conductive pillar 22 is electrically connected to the wiring structure 51. The conductive portion 52 and the wiring structure 51 can be formed in the same process step to simplify the manufacturing process.

[0110] in, Figure 7 In the illustrated embodiment, a redistribution layer 50 is disposed on the plastic encapsulation layer 40 . Figure 8 In the illustrated embodiment, two rewiring layers 50 are disposed on the plastic encapsulation layer 40, and the wiring structures 51 of the two rewiring layers 50 are electrically connected. In other embodiments, three or more stacked rewiring layers may be disposed on the plastic encapsulation layer 40, and the wiring structures of adjacent rewiring layers are electrically connected.

[0111] In one embodiment, when a conductive protrusion is provided on the pad 31 of the chip 30, a rewiring layer is formed on the side of the plastic encapsulation layer away from the support plate, including: forming a rewiring layer according to the position of each of the conductive protrusions, and the rewiring layer is electrically connected to the conductive protrusion.

[0112] In one embodiment, after step 150, the method for manufacturing the semiconductor structure further includes: forming an insulating material layer encapsulating the rewiring layer, wherein the insulating material layer is exposed on a surface of the rewiring layer facing away from the conductive layer.

[0113] Through this step, we can obtain Fig. 9 The seventh intermediate structure shown. Fig. 9 As shown, the insulating material layer 96 encapsulates the side of the wiring structure 51, and the surface of the wiring structure 51 facing away from the conductive layer 11 exposes the insulating material layer 96. When multiple rewiring layers 50 are provided on the plastic encapsulation layer 40, the rewiring layer 50 farthest from the conductive layer 11 exposes the insulating material layer 96 on the surface facing away from the conductive layer 11.

[0114] In step 160, the substrate is removed, and the conductive layer is patterned to obtain a trace layer, wherein the trace layer is in direct contact with the conductive pillars and the base islands respectively.

[0115] In one embodiment, before the step of removing the substrate, the method for manufacturing the semiconductor structure further comprises: mounting the seventh intermediate structure on a carrier, wherein the support plate is located on a side of the plastic encapsulation layer away from the carrier. Fig.10 The eighth intermediate structure shown. Fig.10 As shown, the insulating material layer 96 and the rewiring layer 50 are mounted on the carrier 62 through the adhesive layer 63. The carrier 62 can provide support during the process of removing the substrate and the process of patterning the conductive layer. In some embodiments, the adhesive layer 63 can be made of an easy-to-peel material so that the carrier 62 can be peeled off later. For example, the adhesive layer 63 can be a thermal release film layer that can lose its viscosity by heating.

[0116] After the step of removing the substrate, the following can be obtained: Fig.11 The ninth intermediate structure shown. Fig.11As shown, only the conductive layer 11 of the support plate 10 is retained. In some embodiments, the substrate can be removed by a grinding process. When the support plate includes a conductive material layer 13, the conductive material layer 13 is removed before removing the substrate. The conductive material layer 13 can be removed by an etching process.

[0117] Through step 160, the following can be obtained: Fig.12 The tenth intermediate structure shown. Fig.12 As shown, the trace layer 70 includes a plurality of trace structures 71; each pin 81 of the passive device 80 is connected to one of the trace structures 71, and different pins 81 are connected to different trace structures 71 to avoid short circuits between different pins 81; the support pillar 22 and the base island 21 can be connected to the trace structures 71 respectively. The pins 81 of the passive device 80 are electrically connected to the conductive pillars 22 through the trace layer 70, so that the pins of the passive device 80 can be electrically connected to the rewiring layer 50 through the conductive pillars 22.

[0118] When the pins 81 of the passive device 80 are connected to the conductive layer 11 through solder, if the solders soldered to the adjacent pins 81 merge together during the reflow soldering process, the adjacent pins 81 may be short-circuited.

[0119] In one embodiment, before the step of arranging a passive device on the side of the conductive layer away from the substrate, the method for manufacturing the semiconductor structure further comprises: arranging a solder resist material on the side of the conductive layer away from the substrate, wherein the solder resist material is at least located in the area between the solders connected to two adjacent pins. When the pins of the passive device are soldered to the conductive layer through solder, the solder resist material can prevent the solders soldered to the adjacent pins from being connected together, thereby avoiding the problem of short circuit of the adjacent pins.

[0120] In another embodiment, after step 160, the method for manufacturing the semiconductor structure further includes: removing solders connected to the adjacent pins. This can avoid the problem of short circuits between adjacent pins. In some embodiments, an etching process can be used to remove solders connected to adjacent pins.

[0121] In another embodiment, before the step of providing a passive device on the side of the conductive layer away from the substrate, the method for manufacturing the semiconductor structure further includes: performing a patterning process on the conductive layer to remove the area between the portions of the conductive layer used to connect to adjacent pins. Since the portion of the conductive layer connected to the adjacent pins is a hollow area, during the process of soldering the pins to the conductive layer, even if the solder flows along the conductive layer, the solder soldered to the adjacent pins will not merge, which can improve the problem of adjacent pins short-circuiting.

[0122] In one embodiment, after the step 160 of removing the substrate and patterning the conductive layer to obtain the trace layer, the method for manufacturing the semiconductor structure further includes the following steps:

[0123] An insulating layer is formed, the insulating layer covers the trace layer and the exposed surface of the conductive frame; part of the material of the insulating layer enters the gap between the trace structure and the passive device through the gap between the trace structures connected to the adjacent pins of the same passive device.

[0124] Through this step, we can obtain Fig.13 The eleventh intermediate structure shown. Fig.13 As shown, the insulating layer 91 covers the side surface of the trace layer 70 and the surface away from the carrier 62, and the insulating layer 91 covers the surface of the conductive frame 20 away from the carrier 62. The insulating layer 91 can protect the trace layer 70 and the conductive frame 20.

[0125] When forming the plastic encapsulation layer 40, due to the small gap between the electrical component 80 and the conductive layer, the material of the plastic encapsulation layer may not be able to fill the gap between the electrical component 80 and the conductive layer completely, and there will be voids between the electrical component 80 and the conductive layer. When forming the insulating layer, due to the gap between the trace structure 71 connected to the adjacent pins 81 of the same passive device 80, the insulating material partially enters the gap between the passive device 80 and the trace structure 71 connected to its pin 81, so that the void between the electrical component 80 and the trace structure 71 connected to its pin 81 can be prevented, which helps to improve the quality of the semiconductor structure; there is no need to fill the filler between the passive device 80 and the trace structure 71, which can simplify the process steps and reduce the process cost; and the gaps between adjacent pins 81 and the gaps between the trace structures connected to adjacent pins are filled with the insulating layer, which can prevent the solder between the pins 81 and the trace structure 71 from melting during the welding process of the semiconductor structure and the circuit board or other structures, resulting in the short circuit of adjacent pins and the short circuit of adjacent trace structures.

[0126] In one embodiment, the method for manufacturing the semiconductor structure further comprises the following steps: removing the carrier, and cutting the obtained structure to obtain a plurality of semiconductor structures. Each semiconductor structure comprises at least one chip.

[0127] Through this step, we can obtain Fig.14 The semiconductor structure shown. Fig.14 As shown, the semiconductor structure includes a chip 30 and a passive device 80 .

[0128] In one embodiment, after removing the carrier and before cutting the obtained structure, the method for manufacturing the semiconductor structure further comprises the following step: forming a plurality of conductive balls on the surface of the rewiring layer away from the plastic encapsulation layer. In this embodiment, the semiconductor structure finally obtained is as follows Fig.15 As shown, at least one conductive ball 97 is formed on the surface of each wiring structure 51. The semiconductor structure can be soldered on the circuit board through the conductive ball 97, which facilitates the connection between the semiconductor structure and the circuit board. The material of the conductive ball 97 can be solder paste, metal tin, tin alloy or nickel gold.

[0129] In one embodiment, after the step 160 of removing the substrate and patterning the conductive layer to obtain the trace layer, the method for manufacturing the semiconductor structure further comprises the following steps: arranging an electrical component on a side of the trace layer away from the chip, the electrical component comprising at least one of a chip and a passive device, and the electrical component being electrically connected to the trace layer. The passive device 80 comprises at least one of an inductor, a resistor and a capacitor.

[0130] In this embodiment, the final semiconductor structure is as follows: Fig.16 As shown. Fig.16 As shown, an electrical component 92 is provided on the side of the trace layer 70 away from the plastic layer 40, and the electrical component 92 is a passive device; the semiconductor structure also includes a rewiring layer 93 located between the electrical component 92 and the trace layer 70, and the rewiring layer 93 is located on the side of the insulating layer 91 away from the plastic layer 40, and includes a plurality of wirings 931, and the pins 921 of the electrical component 92 are electrically connected to the wirings 931; the semiconductor structure also includes an encapsulation layer 94, and the encapsulation layer 94 covers the rewiring layer 93 and the electrical component 92.

[0131] The present application also provides a semiconductor structure. Figures 14 to 16 As shown, the semiconductor structure includes a conductive frame 20, a chip 30, a plastic encapsulation layer 40, a rewiring layer 50 and a trace layer 70. The conductive frame 20 includes a base island 21 and a conductive column 22. The chip 30 is located on the base island 21, and the chip 30 includes a chip front, a chip back opposite to the chip front, and a chip side connecting the chip front and the chip back. The chip front is provided with a plurality of pads 31; the chip back faces the base island 21. The plastic encapsulation layer 40 at least encapsulates the chip side and the side of the conductive frame 20. The rewiring layer 50 is located on the side of the plastic encapsulation layer 40 away from the chip back, and is electrically connected to the pad 31 and the conductive column 22. The trace layer 70 is located on the side of the plastic encapsulation layer 40 away from the rewiring layer 50, and the trace layer 70 is directly in contact with and connected to the conductive column 22 and the base island 21 respectively.

[0132] The embodiment of the semiconductor structure provided in the embodiment of the present application and the embodiment of the method for manufacturing the semiconductor structure belong to the same inventive concept, and the description of the relevant details and beneficial effects can be referred to each other, and will not be repeated here.

[0133] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0134] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0135] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The manufacturing method comprises: Providing a support plate, the support plate comprising a substrate and a conductive layer located on one side of the substrate; A conductive frame is arranged on a side of the conductive layer away from the substrate, and the conductive frame is connected to the conductive layer, wherein the conductive frame includes a base island and a conductive column; Mounting a chip on the base island, the chip comprising a chip front, a chip back opposite to the chip front, and a chip side connecting the chip front and the chip back, the chip front being provided with a plurality of pads; the chip back facing the base island; forming a plastic encapsulation layer, wherein the plastic encapsulation layer at least encapsulates the side surface of the chip and the side surface of the conductive frame; A rewiring layer is formed on a side of the plastic encapsulation layer away from the support plate, wherein the rewiring layer is electrically connected to the pad and the conductive column respectively; The substrate is removed, and the conductive layer is patterned to obtain a trace layer, wherein the trace layer is in direct contact with the conductive pillar and the base island respectively.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The step of arranging a conductive frame on a surface of the conductive layer away from the substrate and connecting the conductive frame to the conductive layer comprises: Using a screen printing process to arrange solder on the surface of the conductive layer away from the substrate; The conductive frame is placed on the solder, and the conductive frame is welded to the conductive layer through the solder.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The plastic encapsulation layer encapsulates the front side of the chip; Before forming the plastic sealing layer, the method for manufacturing the semiconductor structure further includes: determining the position of the bonding pad; Before forming a redistribution layer on a side of the plastic encapsulation layer away from the support plate, the method for manufacturing the semiconductor structure further comprises: A plurality of openings are formed on a side of the plastic packaging layer away from the support plate according to the position of the welding pad, each of the openings exposes one welding pad; and the rewiring layer is electrically connected to the welding pad through the openings.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: A conductive convex column is formed on each of the pads, and before forming a redistribution layer on a side of the plastic encapsulation layer away from the support plate, the method for manufacturing the semiconductor structure further comprises: determining a position of each of the conductive convex columns; The forming of a rewiring layer on a side of the plastic packaging layer away from the support plate comprises: forming a rewiring layer according to the position of each of the conductive protrusions, wherein the rewiring layer is electrically connected to the conductive protrusions.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: Before forming the plastic encapsulation layer, the method for manufacturing the semiconductor structure further comprises: arranging a passive device on a side of the conductive layer away from the substrate, wherein the pins of the passive device are connected to the conductive layer; The plastic encapsulation layer at least encapsulates the side surface of the passive component; the pins of the passive component are electrically connected to the conductive pillars through the trace layer.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: The pins of the passive device are connected to the conductive layer through solder; before the passive device is arranged on the side of the conductive layer away from the substrate, the method for manufacturing the semiconductor structure further includes: A solder resist material is disposed on a side of the conductive layer away from the substrate, and the solder resist material is at least located in a region between solders connected to two adjacent pins.

7. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: The trace layer includes a plurality of trace structures, each pin of the passive device is connected to one of the trace structures, and there is a gap between the trace structures connected to the adjacent pins of the same passive device; After removing the substrate and patterning the conductive layer to obtain a trace layer, the method for manufacturing the semiconductor structure further includes: forming an insulating layer, wherein the insulating layer covers the trace layer and the exposed surface of the conductive frame; Part of the material of the insulating layer enters into the gap between the trace structure and the passive device through the gap between the trace structures connected to the adjacent pins of the same passive device.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein: After removing the substrate and patterning the conductive layer to obtain a trace layer, the method for manufacturing the semiconductor structure further includes: An electrical component is arranged on a side of the trace layer away from the chip. The electrical component includes at least one of a chip and a passive device. The electrical component is electrically connected to the trace layer.

9. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The cross-sectional area of ​​the support plate is greater than 300 mm*300 mm.

10. A semiconductor structure, characterized in that: The semiconductor structure comprises: A conductive frame, including a base island and conductive columns; A chip is located on the base island, the chip comprises a chip front, a chip back opposite to the chip front, and a chip side connecting the chip front and the chip back, the chip front is provided with a plurality of pads; the chip back faces the base island; A plastic encapsulation layer, encapsulating at least the side surface of the chip and the side surface of the conductive frame; A redistribution layer, located on a side of the plastic packaging layer away from the back of the chip, and electrically connected to the pad and the conductive column; The trace layer is located on a side of the plastic packaging layer away from the redistribution layer, and the trace layer is directly in contact with and connected to the conductive pillar and the base island respectively.

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