Semiconductor device and packaging process method thereof

Abstract

The invention relates to the technical field of semiconductors, and discloses a semiconductor device and a packaging process method thereof. The packaging process method of the semiconductor device comprises the following steps of: pre-connecting a cathode electrode, an anode electrode and a gate electrode to a chip through an injection molding process to form an integrated pre-assembly structure for sealing and wrapping the chip; packaging the tube shell on the periphery of the integrated pre-assembly structure; a tube shell cathode of the tube shell is electrically connected with the cathode electrode in a sealed mode, and a tube shell anode of the tube shell is electrically connected with the anode electrode in a sealed mode; and a tube shell cover plate is adopted to seal and cover the tube shell. According to the chip packaging method, the integrated forming link is added before chip packaging, the metal electrodes on the chip are integrally formed and connected to the chip, and glue injection is performed on the integrally formed assembly structure through the injection molding process to wrap the chip, so that the chip is isolated from the external environment, and the purpose of improving the test yield of the chip is achieved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and specifically relates to a semiconductor device and a packaging process method thereof. Background Art

[0002] As core components of power transmission equipment, high-power semiconductor devices must withstand high voltage and high current environments in practical applications. The growing demand for high-voltage and high-current equipment is driving the need for semiconductor devices to operate at even higher voltages and currents. This in turn places higher demands on device cleanliness and protection against discharge breakdown during packaging and testing.

[0003] like Figure 1 As shown, taking GCT devices as an example, the chip packaging process requires multiple testing steps, including factory testing, pre-packaging testing, and post-packaging testing. As chip voltage levels continue to increase, the risk of failure due to sparking and breakdown during high-voltage testing in an air environment (air breakdown strength ~2500V / mm) is also increasing. Therefore, optimizing the packaging structure of high-voltage chips and improving chip test yield are crucial for improving device yield. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor device packaging structure, chip and semiconductor device to solve the technical problem that the existing semiconductor device packaging process has the risk of high-voltage test failure during the chip packaging process.

[0005] In order to achieve the above-mentioned object, the present application provides a semiconductor device packaging process method, which comprises the following steps: S10: pre-connecting the cathode electrode, the anode electrode, and the gate electrode to the chip through an injection molding process to form an integrated pre-assembled structure that seals and wraps the chip; S20: Encapsulating the tube shell on the periphery of the integrated pre-assembled structure; S30: Sealing and electrically connecting the tube case cathode of the tube case to the cathode electrode, and sealing and electrically connecting the tube case anode of the tube case to the anode electrode; S40: using a tube shell cover plate to seal the tube shell.

[0006] In some embodiments, step S10 includes: S111: pre-assembling the anode side of the chip and the anode electrode by sealing through an injection molding process, so that an injection molding sealing layer is formed on both the cathode side and the terminal side of the chip; S121: Opening a first mounting hole and a second mounting hole on the injection molding sealing layer on the cathode side of the chip through an etching process, wherein the first mounting hole and the second mounting hole correspond to reserved positions of the cathode electrode and the gate electrode, respectively; S131: Assemble the cathode electrode and the gate electrode into the first mounting hole and the second mounting hole respectively, so that the cathode electrode and the gate electrode are electrically connected to the chip.

[0007] In some embodiments, the first mounting hole and the second mounting hole both radially penetrate the injection molding sealing layer and extend to the chip, the first mounting hole is adapted to the cathode electrode, and the second mounting hole is adapted to the gate electrode.

[0008] In some implementations, step S111 further includes: Metallizing the opposing connection surfaces of the chip and the anode electrode; Connecting the metallized chip and the anode electrode into a pre-assembled structure using a sintered material through a low-temperature sintering device; The terminal of the pre-assembled structure and the cathode side of the chip are sealed and wrapped with glue to form the injection molding sealing layer.

[0009] In some embodiments, step S10 includes: S141: pre-connecting the cathode electrode, the anode electrode, and the gate electrode to corresponding positions of the chip through a sintering process to form a pre-assembled structure; S151: forming the injection molding sealing layer on the pre-assembled structure through an injection molding process, and sealing the terminal of the pre-assembled structure and the gap between the cathode electrode and the gate electrode with the injection molding sealing layer.

[0010] In some implementations, step S141 further includes: Metallizing the relative connection surfaces of the chip, the anode electrode, the cathode electrode, and the gate electrode; The metallized anode electrode, cathode electrode and gate electrode are connected to the chip through sintering material by low-temperature sintering equipment to form the pre-assembled structure.

[0011] In some embodiments, the ultimate use temperature of the sintered material during sintering is greater than or equal to 150°C.

[0012] In some embodiments, the thickness of the injection-molded sealing layer is 1 mm to 2 mm smaller than the thickness of the cathode electrode.

[0013] In some embodiments, the cathode electrode is a whole piece structure or a multi-ring structure.

[0014] A second aspect of the present application further provides a semiconductor device, which is packaged and prepared using the packaging process method described above, and includes: A chip integrated assembly structure includes a chip and a cathode electrode, an anode electrode, and a gate electrode electrically connected to the chip, wherein the terminals of the chip integrated assembly structure and the gap between the cathode electrode and the gate electrode are sealed and encapsulated by an injection molding sealing layer to hermetically encapsulate the chip; The tube shell is used to package the chip integrated assembly structure. The tube shell is provided with a tube shell cathode and a tube shell anode. The tube shell cathode is connected to the cathode electrode, and the tube shell anode is connected to the anode electrode.

[0015] In some embodiments, the insulation strength of the material of the injection-molded sealing layer is greater than or equal to three times the standoff voltage of the semiconductor device.

[0016] Through the above technical solutions, the semiconductor device and packaging process method thereof provided by the embodiments of the present application have the following beneficial effects: When packaging semiconductor devices, first, an integrated molding step is added to the chip back-end or packaging front-end, and the cathode electrode, anode electrode and gate electrode are pre-connected to the chip through the injection molding process to form an integrated pre-assembled structure that seals and wraps the chip; then the shell is packaged on the periphery of the integrated pre-assembled structure, and the shell cathode of the shell is sealed and electrically connected to the cathode electrode, and the shell anode of the shell is sealed and electrically connected to the anode electrode; finally, the shell cover is used to cover the shell for the next performance test. This application integrates the chip and the various metal electrodes on the chip and performs injection molding and sealing, so that the exposed part of the chip can be sealed and wrapped, so as to achieve physical isolation between the chip and the external environment, thereby avoiding spark breakdown failure caused by contamination during the chip packaging and testing process.

[0017] Other features and advantages of the embodiments of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the embodiments of the present application, but do not constitute a limitation on the embodiments of the present application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without inventive work. In the drawings: Figure 1A schematic diagram of a packaging structure of a semiconductor device in the prior art; Figure 2 A schematic diagram of the packaging structure of the semiconductor device of this application; Figure 3 Schematic diagram of the process flow of the semiconductor device packaging method in the first embodiment of the present application; Figure 4 Schematic diagram of the process flow of the packaging method of the semiconductor device in the second embodiment of the present application.

[0019] Description of Reference Numerals 100. Chip integrated assembly structure; 101. Chip; 102. Cathode electrode; 103. Anode electrode; 104. Gate electrode; 105. Gate insulation seat; 200. Tube shell; 201. Tube shell cover; 300. Injection molding sealing layer; 400. First mounting hole; 401. Second mounting hole. DETAILED DESCRIPTION

[0020] The following describes the specific embodiments of the present application in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present application and are not intended to limit the present application.

[0021] The semiconductor device and the packaging method thereof according to the present application are described below with reference to the accompanying drawings.

[0022] For example Figure 1 The existing press-fit type semiconductor device packaging process has the risk of failure in the high voltage test of the chip 101 packaging process, such as Figure 3 and Figure 4 As shown, the present application provides a packaging process method for a semiconductor device, the packaging process method comprising the steps of: S10: pre-connecting the cathode electrode 102 , the anode electrode 103 and the gate electrode 104 to the chip 101 through an injection molding process to form an integrated pre-assembled structure that seals and wraps the chip 101 ; S20: Encapsulating the tube shell 200 on the periphery of the integrated pre-assembled structure; S30: sealing and electrically connecting the tube case cathode of the tube case 200 to the cathode electrode 102, and sealing and electrically connecting the tube case anode of the tube case 200 to the anode electrode 103; S40: using the tube shell cover plate 201 to cover the tube shell 200 .

[0023] It should be noted that the semiconductor device of the present application is a high-power semiconductor device. The chip 101 and the cathode electrode 102 and anode electrode 103 are all sheet-like structures and are electrically connected in a stacked manner. Specifically, the anode electrode 103 is provided on one side of the chip 101, and the cathode electrode 102 is provided on the side of the chip 101 facing away from the anode electrode 103. With this simple stacked structure in the prior art, part of the chip 101 is exposed to the outside and in direct contact with the external environment. The present application adds an integrated molding step to the front-end packaging of the chip 101. The chip 101 and the metal electrodes (cathode electrode 102, anode electrode 103, and gate electrode 104) are electrically connected to form an integrated structure. The gaps in the integrated structure and the exposed portions of the chip 101 are sealed and filled through an injection molding process. This physically isolates the chip 101 from the external environment, encapsulating the chip 101 with the metal electrodes and the sealing layer formed by the injection molding. This provides isolation and protection for the chip 101, eliminates the possibility of contamination of the chip 101, and improves the test yield of the chip 101 at all stages. The cathode electrode 102 , the anode electrode 103 and the gate electrode 104 may all be molybdenum sheets.

[0024] When packaging a semiconductor device, the chip 101 and the cathode electrode 102, the anode electrode 103, and the gate electrode 104 are first connected through an injection molding process to form an integrated pre-assembled structure, and then the entire integrated pre-assembled structure is packaged in a tube shell 200, and the tube shell cathode and the cathode electrode 102 on the tube shell 200 are sealed and electrically connected through a brazing process, and the tube shell anode and the anode electrode 103 on the tube shell 200 are sealed and electrically connected through a brazing process, and finally the assembled tube shell 200 is covered with a tube shell cover 201. After the packaging is completed, the dynamic and static parameter performance tests of the entire semiconductor device are performed. The packaging process of the present application solves the chip 101 contamination problem from the source by combining the chip 101 and the metal electrode into an integrated packaging structure, and then packaging the entire integrated packaging structure, while simplifying the packaging process and improving the packaging yield.

[0025] When assembling the integrated packaging structure, the following two embodiments can be used: In the first embodiment, step S10 includes: S111: pre-assembling the anode side of the chip 101 and the anode electrode 103 by sealing through an injection molding process, so that an injection molding sealing layer 300 is formed on both the cathode side and the terminal side of the chip 101; S121: A first mounting hole 400 and a second mounting hole 401 are respectively formed on the injection molding sealing layer 300 on the cathode side of the chip 101 by an etching process. The first mounting hole 400 and the second mounting hole 401 correspond to the reserved positions of the cathode electrode 102 and the gate electrode 104, respectively. S131 : Assemble the cathode electrode 102 and the gate electrode 104 into the first mounting hole 400 and the second mounting hole 401 respectively, so that the cathode electrode 102 and the gate electrode 104 are electrically connected to the chip 101 .

[0026] In this embodiment, after the chip 101 completes the terminal process, the terminal glue injection process is temporarily not performed. The anode electrode 103 and the anode side of the chip 101 are pre-assembled through tooling or sintering / welding processes. The pre-assembled structure is then sealed together through glue injection or plastic encapsulation. Since the cathode side of the chip 101 is exposed to the outside, after glue injection, a molded sealing layer 300 can be formed on the cathode side of the chip 101 and the exposed portion of the terminal. Then, a first mounting hole 400 and a second mounting hole 401 are opened at the position of the molded sealing layer 300 corresponding to the cathode side of the chip 101 through an etching / corrosion process. The first mounting hole 400 and the second mounting hole 401 correspond to the reserved positions of the cathode electrode 102 and the gate electrode 104 of the chip 101, respectively, and the openings extend to the electrode mounting positions of the chip 101. Finally, the cathode electrode 102 and the gate electrode 104 are installed in the first mounting hole 400 and the second mounting hole 401 respectively. The present application provides a corresponding first mounting hole 400 and a second mounting hole 401 on the injection molding sealing layer 300, thereby making the integrated assembly process more accurate and eliminating complicated processes. The electrical connection between each metal electrode and the chip 101 is achieved while ensuring sealing.

[0027] In some embodiments, the first mounting hole 400 and the second mounting hole 401 both radially penetrate the injection molding sealing layer 300 and extend to the chip 101 . The first mounting hole 400 is adapted to the cathode electrode 102 , and the second mounting hole 401 is adapted to the gate electrode 104 .

[0028] In this embodiment, since the first mounting hole 400 is used to mount the cathode electrode 102 and the second mounting hole 401 is used to mount the gate electrode 104, the shape of the first mounting hole 400 needs to be adapted to the cathode electrode 102, and the shape of the second mounting hole 401 needs to be adapted to the gate electrode 104. In this way, there is no gap between the first mounting hole 400 and the cathode electrode 102, and no gap between the second mounting hole 401 and the gate electrode. Furthermore, by radially penetrating the first mounting hole 400 and the second mounting hole 401, one end of the cathode electrode 102 in the first mounting hole 400 can contact the chip 101 to achieve electrical connection with the chip 101, and one end of the gate electrode 104 in the second mounting hole 401 can contact the chip 101 to achieve electrical connection with the chip 101, thereby ensuring precise installation and sealed packaging of the cathode electrode 102 and the gate electrode 104.

[0029] In some implementations, step S111 further includes the following steps: Metallizing the opposing connection surfaces of the chip 101 and the anode electrode 103; The metallized chip 101 and the anode electrode 103 are connected into a pre-assembled structure using a sintering material by a low temperature sintering device; The terminal of the pre-assembled structure and the cathode side of the chip 101 are sealed and wrapped with glue to form an injection-molded sealing layer 300 .

[0030] In this embodiment, when assembling the chip 101 and the anode electrode 103, the opposing connecting surfaces of the chip 101 and the anode electrode 103 are first metallized. The purpose of metallization is to ensure wettability of the sintering / welding contact surface. For example, a silver sintering process can be used for metallization, which requires the metallization layer material to be wettable with silver, and can be silver, gold, copper, etc. After metallization is completed, the chip 101 and the anode molybdenum sheet are connected via the sintering material using a dedicated low-temperature sintering device. The process parameters during the sintering process are preferably: a sintering temperature range of 180°C to 300°C, a pressure range of 10MPa to 20MPa, a time of 60 to 120 seconds, and a reducing atmosphere. The low-temperature sintering device can be any common sintering device in the prior art and is not limited here. Finally, an injection molding sealing layer 300 is formed on the pre-assembled structure through an injection molding process to wrap around the chip 101, thus completing the entire integrated assembly process.

[0031] Furthermore, during the injection molding process, the surface of the pre-assembled structure needs to be activated first: by coating the surface to be treated of the pre-assembled structure with a coupling agent to improve the contact surface activity; then the pre-assembled structure to be injected with glue is assembled into a specific fixture, a certain injection space is reserved in the fixture, and the injection material is filled into the mold through the injection machine; during the injection process, multiple cycles of degassing are performed to eliminate the gas in the glue, and finally the pre-assembled structure after injection is cured and formed in a vacuum oven, and finally a sealed injection molding sealing layer 300 is formed on the terminal of the pre-assembled structure and the cathode side of the chip 101.

[0032] In the second embodiment of the present application, step S10 includes: S141: pre-connecting the cathode electrode 102, the anode electrode 103, and the gate electrode 104 to corresponding positions of the chip 101 through a sintering process to form a pre-assembled structure; S151 : forming an injection molding sealing layer 300 on the pre-assembled structure by an injection molding process, and sealingly filling the terminal of the pre-assembled structure and the gap between the cathode electrode 102 and the gate electrode 104 with the injection molding sealing layer 300 .

[0033] In this embodiment, after the chip 101 completes the field termination process, the terminal glue injection process is temporarily omitted. First, the anode electrode 103, cathode electrode 102, and gate molybdenum sheet are pre-connected to the chip 101 through a sintering / welding process to form a pre-assembled structure. The pre-assembled structure is then sealed together through glue injection or a plastic encapsulation process, so that the injection molding sealing layer 300 fills the terminals of the pre-assembled structure and the gaps between the cathode electrode 102 and the gate electrode 104, and finally the assembly is completed. The sintering process parameters in the second embodiment are the same as those in the first embodiment and are not described in detail here.

[0034] In some implementations, step S141 further includes: Metallizing the relative connection surfaces of the chip 101, the anode electrode 103, the cathode electrode 102, and the gate electrode 104; The metallized anode electrode 103 , cathode electrode 102 and gate electrode 104 are connected to the chip 101 through sintering materials using a low-temperature sintering device to form a pre-assembled structure.

[0035] When assembling the various metal electrodes of chip 101, the opposing surfaces of chip 101 and anode electrode 103, the opposing surfaces of chip 101 and cathode electrode 102, and the opposing surfaces of chip 101 and gate electrode 104 are first metallized to ensure wettability of the sintering / soldering contact surfaces. For example, a silver sintering process can be used for metallization, which requires the metallization layer material to be wettable with silver, and can be made of silver, gold, copper, etc. After the metallization of each opposing contact surface is completed, a dedicated low-temperature sintering device is used to connect the chip 101, cathode electrode 102, anode electrode 103, and gate electrode 104 through the sintering material to form a pre-assembled structure. In this embodiment, the process parameters during the sintering process are preferably: a sintering temperature range of 180°C to 300°C, a pressure range of 10MPa to 20MPa, a time of 60 to 120 seconds, and a reducing atmosphere.

[0036] In some embodiments, the maximum operating temperature of the sintering material during sintering is greater than or equal to 150°C. Since the actual operating temperature (junction temperature) of the transistor junctions within the semiconductor device chip 101 is typically 150°C, the operating temperature of the sintering material needs to be no less than 150°C during the semiconductor packaging process to ensure the normal operation of the entire sintering process.

[0037] In some embodiments, since the thickness of the cathode electrode 102 is generally 2.5 mm, during injection molding, the thickness of the entire injection molding sealing layer 300 needs to be designed to be 1 mm to 2 mm smaller than the thickness of the cathode electrode 102, so that the end of the cathode electrode 102 facing away from the chip 101 can extend out from the injection molding sealing layer 300; and, by setting the thickness of the injection molding sealing layer 300 to be smaller than the cathode electrode 102, it can be ensured that there is sufficient contact space between the cathode electrode 102 and the tube shell electrode.

[0038] In some embodiments, the cathode electrode 102 is a whole piece structure or a multi-ring structure. It is understandable that the cathode electrode 102 can be a whole piece of circular structure. In this case, the diameter of the first mounting hole 400 is larger to accommodate a whole piece of cathode electrode 102. Figure 3 and Figure 4 Of course, the cathode electrode 102 can also be a structure in which multiple annular pieces are arranged radially from the inside to the outside. When the cathode electrode 102 is a multi-ring structure, the number of the first mounting holes 400 is the same as the number of rings of the cathode electrode 102 (such as Figure 3 and Figure 4 In the second embodiment shown in FIG. 4 , each ring electrode corresponds to a first mounting hole 400 for adaptive mounting. Furthermore, when the cathode electrode 102 is designed as a multi-ring structure, the pressure of the cathode electrode 102 on the chip 101 can be uniform, improving the uniformity of the chip 101 crimping during the entire packaging process.

[0039] like Figure 2 As shown, the second aspect of the present application also provides a semiconductor device, which is prepared by encapsulating using the packaging process method described above. Since the semiconductor device is encapsulated using the above packaging process method, it has all the beneficial effects brought by the above packaging process method. The semiconductor device of the present application includes a chip integrated assembly structure 100 and a tube shell 200; the chip integrated assembly structure 100 includes a chip 101 and a cathode electrode 102, an anode electrode 103 and a gate electrode 104 electrically connected to the chip 101. The terminal of the chip integrated assembly structure 100 and the gap between the cathode electrode 102 and the gate electrode 104 are sealed and encapsulated by an injection molding sealing layer 300 to seal and wrap the chip 101, thereby preventing the chip 101 from being exposed to the external environment; the tube shell 200 is used to encapsulate the chip integrated assembly structure 100. The tube shell 200 is provided with a tube shell cathode and a tube shell anode. The tube shell cathode is connected to the cathode electrode 102, the tube shell anode is connected to the anode electrode 103, and the end of the gate electrode 104 facing away from the chip 101 is connected to the gate insulating seat 105.

[0040] In this embodiment, the semiconductor device obtained by adopting the above-mentioned packaging process eliminates the need to integrally wrap the chip 101 during the packaging process, eliminates the possibility of the chip 101 being contaminated, can improve the yield of the chip 101 in various links of testing, and improves the packaging efficiency of the semiconductor device.

[0041] In some embodiments, since the injection molding sealing layer 300 wraps the chip 101, in order to prevent the injection molding sealing layer 300 from generating conductivity, the material of the injection molding sealing layer 300 needs to be made into an insulating material to insulate and isolate it from the outside. Preferably, the insulation strength of the material of the injection molding sealing layer 300 is greater than or equal to 3 times the group breaking voltage of the semiconductor device to ensure the strong insulation of the entire injection molding sealing layer 300, thereby improving the safety of the entire semiconductor device.

[0042] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. In the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0043] In this application, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection, or communication; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0044] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0045] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A semiconductor device packaging process method, characterized in that: The packaging process method comprises the steps of: S10: pre-connecting the cathode electrode (102), the anode electrode (103) and the gate electrode (104) to the chip (101) through an injection molding process to form an integrated pre-assembled structure that seals and wraps the chip (101); S20: Encapsulating the tube shell (200) on the periphery of the integrated pre-assembled structure; S30: sealingly and electrically connecting the tube shell cathode of the tube shell (200) to the cathode electrode (102), and sealingly and electrically connecting the tube shell anode of the tube shell (200) to the anode electrode (103); S40: using a tube shell cover plate to seal the tube shell (200).

2. The semiconductor device packaging process according to claim 1, characterized in that: The step S10 comprises: S111: pre-sealing and assembling the anode side of the chip (101) and the anode electrode (103) by an injection molding process, so that an injection molding sealing layer (300) is formed on both the cathode side and the terminal side of the chip (101); S121: opening a first mounting hole (400) and a second mounting hole (401) on the injection molding sealing layer (300) on the cathode side of the chip (101) through an etching process, respectively, the first mounting hole (400) and the second mounting hole (401) corresponding to reserved positions of the cathode electrode (102) and the gate electrode (104), respectively; S131: Assembling the cathode electrode (102) and the gate electrode (104) into the first mounting hole (400) and the second mounting hole (401) respectively, so that the cathode electrode (102) and the gate electrode (104) are electrically connected to the chip (101).

3. The semiconductor device packaging process according to claim 2, characterized in that: The first mounting hole (400) and the second mounting hole (401) both radially penetrate the injection-molded sealing layer (300) and extend to the chip (101); the first mounting hole (400) is adapted to the cathode electrode (102), and the second mounting hole (401) is adapted to the gate electrode (104).

4. The semiconductor device packaging process according to claim 2, characterized in that: The step S111 further includes: Metallizing the relative connection surfaces of the chip (101) and the anode electrode (103); The metallized chip (101) and the anode electrode (103) are connected into a pre-assembled structure by using a low-temperature sintering device using a sintering material; The terminal of the pre-assembled structure and the cathode side of the chip (101) are sealed and wrapped with glue injection to form the injection-molded sealing layer (300).

5. The semiconductor device packaging process method according to claim 1, characterized in that: The step S10 comprises: S141: pre-connecting the cathode electrode (102), the anode electrode (103) and the gate electrode (104) to corresponding positions of the chip (101) through a sintering process to form a pre-assembled structure; S151: forming an injection molding sealing layer (300) on the pre-assembled structure through an injection molding process, and sealing the injection molding sealing layer (300) to fill the terminal of the pre-assembled structure and the gap between the cathode electrode (102) and the gate electrode (104).

6. The semiconductor device packaging process method according to claim 5, characterized in that: The step S141 further includes: Metallizing the relative connection surfaces of the chip (101), the anode electrode (103), the cathode electrode (102), and the gate electrode (104); The metallized anode electrode (103), the cathode electrode (102) and the gate electrode (104) are connected to the chip (101) through a sintering material using a low-temperature sintering device to form the pre-assembled structure.

7. The semiconductor device packaging process according to claim 4 or 6, characterized in that: The maximum use temperature of the sintered material during sintering is greater than or equal to 150°C.

8. The semiconductor device packaging process method according to claim 2 or 5, characterized in that: The thickness of the injection-molded sealing layer (300) is 1 mm to 2 mm smaller than the thickness of the cathode electrode (102).

9. The semiconductor device packaging process according to claim 1, characterized in that: The cathode electrode (102) is a whole piece structure or a multi-ring structure.

10. A semiconductor device, characterized in that: The semiconductor device is packaged and prepared by the packaging process method according to any one of claims 1 to 9, and the semiconductor device comprises: A chip integrated assembly structure (100), comprising a chip (101) and a cathode electrode (102), an anode electrode (103) and a gate electrode (104) electrically connected to the chip (101), wherein the terminal of the chip integrated assembly structure (100) and the gap between the cathode electrode (102) and the gate electrode (104) are sealed and packaged by an injection molding sealing layer (300) to seal and wrap the chip (101); The tube shell (200) is used to package the chip integrated assembly structure (100); the tube shell (200) is provided with a tube shell cathode and a tube shell anode; the tube shell cathode is connected to the cathode electrode (102), and the tube shell anode is connected to the anode electrode (103).

11. The semiconductor device according to claim 10, characterized in that The insulation strength of the material of the injection-molded sealing layer (300) is greater than or equal to three times the group-breaking voltage of the semiconductor device.

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