Manufacturing method of semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure. The manufacturing method comprises the steps that a plastic package assembly is provided, the plastic package assembly comprises a plurality of chips, a plurality of lead frame units correspondingly connected with the chips respectively, a plastic package layer and an electric connecting piece, each lead frame unit comprises a plurality of pins, and the plastic package layer at least packages the chips and the corresponding lead frame units, an open groove with part or all of the plastic packaging layers removed is formed between every two adjacent lead frame units, pins of every two adjacent lead frame units are provided with opposite pin side surfaces facing the corresponding open groove, the pins of every two adjacent lead frame units are connected through an electric connecting piece, and the electric connecting piece is located at the bottom of the corresponding open groove. An insulating layer located at the bottom of the groove is arranged on the surface of the electric connecting piece. Forming a solder layer on the exposed surface of the lead frame; and removing the electric connecting piece. According to the manufacturing method, the risk of wiredrawing caused by cutting the solder layer is reduced, and the problem that the semiconductor structure is short-circuited due to the fact that the wiredrawing falls between the two adjacent pins after falling off is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure. Background Art

[0002] A chip packaging technology may include the following process: first, a lead frame is mounted on a carrier board, the lead frame includes a frame, a connecting part located in the frame and a plurality of pins, the pins are connected to the connecting part, and the connecting part is connected to the frame; then, the chip is mounted on the lead frame, and the pins are electrically connected to the chip pads; then, a plastic sealing layer is formed; then, cutting is performed to form grooves on the sides of the exposed pin parts; then, a tin plating layer is formed on the exposed surface of the lead frame by an electroplating process; finally, a cutting process is used to remove the connecting part and the frame.

[0003] In the above chip packaging technology, in the process of cutting and removing the connecting part, the tin-plated layer formed on the surface of the connecting part will produce tin wire. After the tin wire falls off, it will fall between adjacent pins, causing a short circuit between the adjacent pins, affecting the yield of the product. Summary of the invention

[0004] The embodiment of the present application provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure includes: providing a plastic encapsulation component, the plastic encapsulation component including a plurality of chips, a plurality of lead frame units respectively connected to the plurality of chips, a plastic encapsulation layer and an electrical connector, the lead frame unit including a plurality of pins, the plastic encapsulation layer at least encapsulating the chip and the corresponding lead frame unit, a groove from which part or all of the plastic encapsulation layer is removed is provided between two adjacent lead frame units, the pins of two adjacent lead frame units have a pin side surface facing and opposite to the groove, the pins of the two lead frame units are connected by the electrical connector, the electrical connector is located at the bottom of the groove, and the surface of the electrical connector is provided with an insulating layer located at the bottom of the groove;

[0005] forming a solder layer on the exposed surface of the lead frame;

[0006] Remove the electrical connector.

[0007] In some embodiments, providing a plastic package assembly includes:

[0008] Providing a lead frame, the lead frame comprising the plurality of lead frame units and connecting ribs connecting pins of adjacent lead frame units;

[0009] Arranging a plurality of chips on the lead frame units respectively and correspondingly, and arranging a plastic packaging layer covering the plurality of chips and the lead frame to form a plastic packaging structure;

[0010] A first slot is formed; the first slot is located between two adjacent lead frame units and is formed by opening a portion of the depth inward from the side where the lead frame is located in the plastic package structure; wherein a portion of the thickness of the connecting rib is retained at the bottom of the first slot to form the electrical connector;

[0011] A first insulating layer is disposed on the exposed surface of the electrical connector; wherein a first preset distance exists between the edge of the first insulating layer and the pin side surfaces of the two adjacent lead frame units or the edge of the first insulating layer contacts the pin side surfaces of the two adjacent lead frame units.

[0012] In some embodiments, when there is a first preset distance between the edge of the first insulating layer and the side surface of the pin, the first preset distance is less than or equal to 0.1 mm;

[0013] When the edge of the first insulating layer contacts the side surfaces of the leads of the two adjacent lead frame units, after the first insulating layer is provided, the remaining groove depth in the first groove is greater than half of the thickness of the leads of the two adjacent lead frame units.

[0014] In some embodiments, the depth of the first groove is less than the thickness of the pins of the two adjacent lead frame units, and the depth of the first groove is greater than half of the thickness of the pins of the two adjacent lead frame units.

[0015] In some embodiments, after forming a solder layer on the exposed surface of the lead frame, the method includes:

[0016] Cutting is performed along the first groove to form a plurality of semiconductor structures; wherein the cutting along the first groove includes removing the electrical connector and removing a portion of the plastic packaging layer located within the orthographic projection range of the first groove in the thickness direction of the plastic packaging structure.

[0017] In some embodiments, after forming a solder layer on the exposed surface of the lead frame and before removing the electrical connector, the method includes:

[0018] The first insulating layer is removed.

[0019] In some embodiments, providing a plastic package assembly includes:

[0020] Providing a lead frame, the lead frame comprising the plurality of lead frame units and connecting ribs connecting pins of adjacent lead frame units;

[0021] Arranging a plurality of chips on the lead frame units respectively and correspondingly, and arranging a plastic packaging layer covering the plurality of chips and the lead frame to form a plastic packaging structure;

[0022] The connecting ribs are removed and a second slot is formed; the second slot is located between adjacent lead frame units and is formed by opening a portion of the thickness inward from the side of the lead frame in the plastic package structure;

[0023] An electrical connection structure having a second insulating layer on its surface is arranged in the second groove; the electrical connection structure serves as the electrical connector and connects the pin side surfaces of two adjacent lead frame units; wherein the second insulating layer extends a second preset distance from the pin side surfaces of the two adjacent lead frame units toward the middle of the second groove.

[0024] In some embodiments, the second preset distance is greater than or equal to 20 μm; and / or,

[0025] The depth of the second groove is greater than the thickness of the pins of the two adjacent lead frame units, and the depth of the second groove on the opening side of the second insulating layer facing the second groove is greater than half the thickness of the pins of the two adjacent lead frame units.

[0026] In some embodiments, removing the electrical connector comprises:

[0027] removing the electrical connection structure having the second insulating layer on the surface;

[0028] When or after removing the electrical connection structure, the method includes: cutting along the second groove to form a plurality of semiconductor structures.

[0029] In some embodiments, providing a plastic package assembly includes:

[0030] Providing a lead frame, the lead frame comprising the plurality of lead frame units and connecting ribs connecting pins of adjacent lead frame units;

[0031] A plurality of chips are respectively arranged on the lead frame unit, and a plastic packaging layer covering the plurality of chips and the lead frame is arranged to form a plastic packaging structure; the lead frame has a first surface facing away from the chip, and the first surface is exposed;

[0032] forming a first solder layer on a first surface of the lead frame;

[0033] Cutting the plastic package structure formed with the first solder layer to form a plurality of intermediate semiconductor structures; the pins of the lead frame units in the intermediate semiconductor structures have exposed pin side surfaces;

[0034] A plurality of the intermediate semiconductor structures are spaced apart on a conductive layer, and the conductive layer is connected to the first solder layer; wherein a third groove is formed at least between two adjacent intermediate semiconductor structures, the conductive layer serves as the electrical connector, and a third insulating layer is provided on the surface of the conductive layer located in the third groove.

[0035] In some embodiments, the conductive layer includes a peripheral region of the outermost intermediate semiconductor structure away from the adjacent intermediate semiconductor structure, and the third insulating layer is further located on the peripheral region of the conductive layer;

[0036] The intermediate semiconductor structure molding layer has a first molding surface flush with the first surface of the lead frame, and the third insulating layer is also located between the conductive layer and the first molding surface.

[0037] In some embodiments, there is a third preset distance between the edge of the third insulating layer and the plane where the corresponding pin side surface is located, and the third preset distance is consistent with the thickness of the first solder layer.

[0038] In some embodiments, forming a solder layer on the exposed surface of the lead frame comprises:

[0039] forming a second solder layer on the pin side surface;

[0040] After removing the electrical connections, a plurality of semiconductor structures are formed.

[0041] In some embodiments, after the second solder layer is formed on the lead side surface, the second solder layer covers the entire area of ​​the lead side surface.

[0042] In some embodiments, before disposing a plurality of the intermediate semiconductor structures on the conductive layer, the method includes:

[0043] Disposing the conductive layer on a carrier;

[0044] After forming a second solder layer on the pin side surface, the method further includes:

[0045] The carrier plate is removed.

[0046] The main technical effects achieved by the embodiments of the present application are:

[0047] In the manufacturing method of the semiconductor structure provided in the embodiment of the present application, the pins of adjacent lead frame units are connected by the electrical connector, and the electrical connector is provided with an insulating layer in at least a part of the area between two adjacent lead frame units, so that when a solder layer is formed on the exposed surface of the lead frame, a large area solder layer will not be formed between the pins of two adjacent lead frame units, so that when the electrical connector is subsequently removed or the semiconductor structure is formed by cutting, the risk of wiredrawing due to cutting the solder layer is reduced, thereby improving the problem of short circuit in the semiconductor structure caused by the wiredrawing falling between two adjacent pins after falling off, and the product yield of the semiconductor structure can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0049] Figures 2 to 12 is a manufacturing process diagram provided by an exemplary embodiment of the present application; wherein, Figure 6 yes Figure 5 The corresponding three-dimensional structure diagram of structure A shown; Figure 8 yes Figure 7 The three-dimensional structure diagram corresponding to position B in the structure shown;

[0050] Figures 13 to 17 is a partial manufacturing process diagram provided by another exemplary embodiment of the present application;

[0051] Figures 18 to 25 It is a partial manufacturing process diagram provided by yet another exemplary embodiment of the present application. DETAILED DESCRIPTION

[0052] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0053] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0054] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0055] Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0056] The present application provides a method for manufacturing a semiconductor structure. Figure 1 As shown, the method for manufacturing the semiconductor structure includes the following steps 110 to 130 .

[0057] In step 110, a plastic encapsulation component is provided, the plastic encapsulation component comprising a plurality of chips, a plurality of lead frame units respectively connected to the plurality of chips, a plastic encapsulation layer and an electrical connector, the lead frame unit comprising a plurality of pins, the plastic encapsulation layer at least encapsulating the chip and the corresponding lead frame unit, a groove from which part or all of the plastic encapsulation layer is removed is provided between two adjacent lead frame units, the pins of two adjacent lead frame units have pin side surfaces facing and opposite to the groove, the pins of the two lead frame units are connected by the electrical connector, the electrical connector is located at the bottom of the groove, and an insulating layer located at the bottom of the groove is provided on the surface of the electrical connector;

[0058] In step S120, a solder layer is formed on the exposed surface of the lead frame;

[0059] In step 130, the electrical connector is removed.

[0060] In the manufacturing method of the semiconductor structure provided in the embodiment of the present application, the pins of adjacent lead frame units are connected by the electrical connector, and the electrical connector is provided with an insulating layer in at least a part of the area between two adjacent lead frame units, so that when a solder layer is formed on the exposed surface of the lead frame, a large area solder layer will not be formed between the pins of two adjacent lead frame units, so that when the electrical connector is subsequently removed or the semiconductor structure is formed by cutting, the risk of wiredrawing due to cutting the solder layer is reduced, thereby improving the problem of short circuit in the semiconductor structure caused by the wiredrawing falling between two adjacent pins after falling off, and the product yield of the semiconductor structure can be improved.

[0061] The semiconductor structure formed by the semiconductor structure manufacturing method can be a Quad Flat No-leads Package (QFN) structure, which can be used as an electronic component for automobiles or other electronic products.

[0062] The following is a detailed introduction to each step of the method for manufacturing a semiconductor structure provided in an embodiment of the present application.

[0063] First, please combine Figures 2 to 12 As shown, in some embodiments, in step S110, providing a plastic package component may include the following steps S111 to S114:

[0064] In step S111, a lead frame is provided, wherein the lead frame includes the plurality of lead frame units and connecting ribs connecting pins of adjacent lead frame units;

[0065] In step S112, a plurality of chips are respectively disposed on the lead frame units, and a plastic packaging layer covering the plurality of chips and the lead frame is disposed to form a plastic packaging structure;

[0066] In step S113, a first slot is formed; the first slot is located between two adjacent lead frame units and is formed by opening a portion of the depth inward from the side of the lead frame in the plastic package structure; wherein a portion of the thickness of the connecting rib is retained at the bottom of the first slot to form the electrical connector;

[0067] In step S114, a first insulating layer is provided on the exposed surface of the electrical connector; wherein a first preset distance exists between the edge of the first insulating layer and the pin side surface of the two adjacent lead frame units or the edge of the first insulating layer contacts the pin side surface of the two adjacent lead frame units.

[0068] like Figure 2 As shown, in step S111, a lead frame 1 is provided. The lead frame 1 includes the plurality of lead frame units 10 and connecting ribs 13 connecting pins 11 of adjacent lead frame units 10. The lead frame units are Figure 2 The position corresponding to the first area S1 in the lead frame includes the base island 12 and a plurality of pins 11 located on at least one side of the base island 12. The connecting rib 13 is the portion corresponding to the second area S2 between adjacent lead frame units 10. The connecting rib 13 corresponding to the second area S2 will be removed when the semiconductor structure is subsequently formed.

[0069] The lead frame 1 has a first surface 1101 and a second surface 1102 which are opposite to each other.

[0070] like Figure 3 and Figure 4As shown, a plurality of chips 2 are respectively disposed on the lead frame unit 10 , and a plastic packaging layer 3 covering the plurality of chips 2 and the lead frame 1 is disposed to form a plastic packaging structure 1000 .

[0071] like Figure 5 and Figure 6 As shown, in step S113, a first slot 101 is formed in the plastic package structure 1000, forming a plastic package structure 1001 having the first slot 101. The first slot 101 is located between two adjacent lead frame units 10 and is formed by opening a portion of the depth inward from the side where the lead frame 1 is located in the plastic package structure 1000. Part of the thickness of the connecting rib 13 (such as the portion of the connecting rib indicated by 131) is retained at the bottom of the first slot 101 to form the electrical connector.

[0072] Preferably, the width of the first slot 101 is greater than the width of the connecting rib 13. When subsequently cutting to form a semiconductor structure, cutting can be performed along the first slot 101, preferably along a cutting line 102 in the first slot 101, wherein the connection between the first connecting rib 13 and the lead 11 can be located on the cutting line 102.

[0073] like Figure 7 and Figure 8 As shown, in step S114, a first insulating layer 61 is provided on the exposed surface of the electrical connector (ie, the connecting rib 131). A first preset distance d1 exists between the edge of the first insulating layer 61 and the lead side surfaces 111 of the two adjacent lead frame units 10.

[0074] At this point, a plastic encapsulation component 1002 is formed. The plastic encapsulation component 1002 includes a plurality of chips 2, a plurality of lead frame units 10 respectively connected to the plurality of chips 2, a plastic encapsulation layer 3 and a portion of a connecting rib 131. The lead frame unit 10 includes a plurality of pins 11. The plastic encapsulation layer 3 at least encapsulates the chip 2 and the corresponding lead frame unit 10. A first slot 101 is provided between two adjacent lead frame units 10, where a portion of the plastic encapsulation layer 3 and a portion of the connecting rib 131 are removed. The pins 11 of the two adjacent lead frame units 10 have a pin side surface 111 facing the first slot 101 and opposite to each other. The pins 11 of the two lead frame units 10 are connected by a portion of the connecting rib 131. The portion of the connecting rib 131 is located at the bottom of the first slot 101, and the surface of the portion of the connecting rib 131 is provided with an insulating layer 61 located at the bottom of the first slot 101. A first preset distance d1 is provided between the edge of the first insulating layer 61 and the pin side surface 111 of the two adjacent lead frame units 10.

[0075] In this embodiment, the pin 11 includes a first portion 113 having a pin side surface 111, and a second portion 114 located at the bottom of the first slot 101 and connecting part of the connecting rib 131 and the first portion 113. The second portion 114 may be as thick as the connecting rib 131. Accordingly, when forming the first slot 101, the portion of the pin 11 located above the second portion 114 is also removed to form a stepped pin consisting of the first portion 113 and the second portion 114. The edge of the first insulating layer 61 mentioned here has a first preset distance d1 from the pin side surface 111 of the two adjacent lead frame units 10, which can be understood as the edge of the first insulating layer 61 having a first preset distance d1 from the pin side surface 111 of the first portion 113. Accordingly, in combination Figure 5 and Figure 6 As shown, the first slot 101 is formed by the pin side surface 111 of the first portion 113 , the second portion 114 , a portion of the connecting rib 131 and the corresponding plastic packaging layer.

[0076] When there is a first preset distance d1 between the edge of the first insulating layer 61 and the pin side surface 111, the first preset distance d1 is less than or equal to 0.1 mm, and the first preset distance d1 is much smaller than the distance from the cutting line 102 to the pin side surface 111, so as to ensure that when a solder layer is subsequently formed on the pin side surface 111, the solder layer is at a certain distance from the cutting line, and when a semiconductor structure is subsequently cut to form, the cutting tool will not touch the solder layer formed on the pin side surface 111. Moreover, in this embodiment, a solder layer can also be formed between the edge of the first insulating layer 61 and the pin side surface 111, which is conducive to ensuring the solder height of the pin side surface when the solder layer is subsequently formed.

[0077] In some embodiments, the depth of the first groove 101 is less than the thickness of the pin 11 of the two adjacent lead frame units 10, and the depth of the first groove 101 is greater than half the thickness of the pin 11 of the two adjacent lead frame units 10 to ensure the solder height on the side surface of the pin when the solder layer is subsequently formed.

[0078] Combination Figure 7 As shown, in the plastic package assembly 1002 provided in step S110 , the first surface 1101 of the lead frame 1 is exposed, and the area of ​​the groove wall of the first groove 101 in the lead frame 1 except the area covered by the first insulating layer 61 is also exposed.

[0079] It should be noted that, in some other embodiments, the edge of the first insulating layer 61 contacts the pin side surface 111 of the two adjacent lead frame units 10, that is, directly contacts the pin side surface 111 of the first portion 113. In this way, the first insulating layer 61 is easier to set. In this embodiment, after the first insulating layer 61 is set, the remaining groove depth in the first slot 101 should still be greater than half the thickness of the pin 11 of the two adjacent lead frame units 10.

[0080] like Fig. 9 As shown, in step S120, a solder layer 70 is formed on the exposed surface of the lead frame 1 to form Fig. 9 An intermediate structure 1003 is shown.

[0081] like Fig. 9 As shown, when there is a first preset distance d1 between the edge of the first insulating layer 61 and the pin side surface 111 of the pin 11, after the solder layer 70 is formed on the exposed surface of the lead frame 1, the solder layer 70 is formed on the side of the pin side surface 111 of the lead frame 1 where the connecting rib 131 is close to the first surface 1101, and on the first surface 1101 of the lead frame 1.

[0082] When the edge of the first insulating layer 61 contacts the pin side surfaces 111 of the two adjacent lead frame units 10, after the solder layer is formed on the exposed surface of the lead frame, the solder layer 70 is formed on the side of the pin side surface 111 of the lead frame located on the first insulating layer 61 close to the first surface 1101, and the first surface 1101 of the lead frame 1.

[0083] like Fig.10 As shown, after forming the solder layer 70 on the exposed surface of the lead frame 1 in step S120 and before removing the electrical connector in step S130, the method includes the following step S140:

[0084] In step S140: removing the first insulating layer 61, forming Fig.10 An intermediate structure 1004 is shown.

[0085] Of course, in some embodiments, step S140 may not be included.

[0086] like Fig.11 As shown, after forming the solder layer 70 on the exposed surface of the lead frame 1 in step S120, the method includes the following step S1300:

[0087] In step S1300, cutting is performed along the first groove 101 to form a plurality of semiconductor structures 1005; wherein, the cutting along the first groove 101 includes removing the electrical connector (i.e., the first connecting rib 131) and removing a portion of the plastic encapsulation layer 3 that is within the range of the positive projection of the first groove 101 in the thickness direction of the plastic encapsulation structure.

[0088] The connection between the first connecting rib 131 and the pin 11 in the first slot 101 is located on the cutting line 102, and the cutting line 102 is located on one side of the side wall of the first slot 101 close to the middle of the first connecting rib 132. When cutting, cutting is performed along the cutting line 102, and the part between the cutting lines is cut off.

[0089] Fig.11 The semiconductor structure 1005 shown is a semiconductor structure obtained after step S1300, in which a first preset distance d1 is provided between the edge of the first insulating layer 61 and the pin side surface 111 of the pin 11. When the edge of the first insulating layer 61 contacts the pin side surfaces 111 of the two adjacent lead frame units 10, the following can be obtained after step S1300: Fig.12 A semiconductor structure 1006 is shown.

[0090] Please combine Figures 2 to 4 and 13 to Fig.17 As shown, in some other embodiments, step S110 of providing a plastic package component may include the following steps S111, S112, S115 and S116.

[0091] In step S111, a lead frame is provided, wherein the lead frame includes the plurality of lead frame units 10 and connecting ribs for connecting the leads 11 of adjacent lead frame units 10;

[0092] In step S112, a plurality of chips are respectively disposed on the lead frame unit 10, and a plastic packaging layer covering the plurality of chips and the lead frame is disposed to form a plastic packaging structure;

[0093] In step S115, the connecting ribs are removed and a second slot is formed; the second slot is located between adjacent lead frame units 10 and is formed by opening a portion of the thickness inward from the side of the lead frame in the plastic package structure;

[0094] In step S116, an electrical connection structure having a second insulating layer on its surface is provided in the second groove; the electrical connection structure serves as the electrical connector and connects the side surfaces of the pins 11 of two adjacent lead frame units 10; wherein the second insulating layer extends a second preset distance from the side surfaces of the pins 11 of the two adjacent lead frame units 10 toward the middle of the second groove.

[0095] like Figures 2 to 4 As shown, step S111 and step S112 can refer to the above related description. After step S112, the plastic package structure 1000 is obtained.

[0096] Please combine Fig.13 As shown, in step S115, the connecting rib 13 is removed and a second slot 201 is formed to form Fig.13 The plastic packaging structure 2001 shown. In the plastic packaging structure 2001, the second slot 201 is located between adjacent lead frame units 10 and is formed by opening a portion of the thickness inward from the side of the plastic packaging structure 2001 where the lead frame 1 is located.

[0097] Preferably, the width of the second slot 201 is greater than the width of the connecting rib 13. The width of the second slot 201 may be the same as the width of the first slot 101.

[0098] The electrical connection structure with the second insulating layer on the surface may include a conductive layer with conductive properties and a second insulating layer arranged on the conductive layer.

[0099] In some embodiments, please combine Fig.14 As shown, in step S116, the connection layer 8 may be firstly arranged in the second groove 201, and then the second insulating layer 62 may be arranged on the exposed surface of the connection layer 8. The second insulating layer 62 extends from the edge of the connection layer 8 to the middle of the connection layer 8 by a second preset distance d2. In other embodiments, before step S116, the second insulating layer 62 may be firstly arranged on the surface of the connection layer 8 to form an electrical connection structure. The second insulating layer 62 extends from the edge of the connection layer 8 to the middle of the connection layer by a second preset distance d2. In step S116, the formed electrical connection structure is arranged in the second groove 201.

[0100] The connecting layer 8 specifically serves as the electrical connector and connects the side surfaces of the pins 11 of two adjacent lead frame units 10; wherein the second insulating layer 62 extends from the side surfaces of the pins 11 of the two adjacent lead frame units 10 to the middle of the second slot 201 by a second preset distance d2.

[0101] So far, it has formed Fig.14The plastic encapsulation component 2002 shown. The plastic encapsulation component 2002 includes a plurality of chips 2, a plurality of lead frame units 10 respectively connected to the plurality of chips 2, a plastic encapsulation layer 3 and a connecting rib 131, the lead frame unit 10 includes a plurality of pins 11, the plastic encapsulation layer 3 at least encapsulates the chip 2 and the corresponding lead frame unit 10, a second slot 201 is provided between two adjacent lead frame units 10, the connecting rib 13 and part of the plastic encapsulation layer 3 are removed, the pins 11 of the two adjacent lead frame units 10 have a pin side surface 111 facing the second slot 201 and opposite to each other, the pins 11 of the two lead frame units 10 are electrically connected through the connecting layer 8, the connecting layer 8 is located at the bottom of the second slot 201, and the surface of the connecting layer 8 is provided with a second insulating layer 62 located at the bottom of the second slot 201. The second insulating layer 62 extends from the side surface of the pins 11 of the two adjacent lead frame units 10 to the middle of the second slot 201 by a second preset distance d2. The pin side surface 111 of the plastic package component 2002 is a flush surface.

[0102] In this embodiment, the pin 11 has a continuous and smooth pin side surface 111. When the width of the second slot 201 is greater than the width of the connecting rib 13, when forming the second slot 201, in addition to removing the connecting rib 13 and part of the plastic encapsulation layer 3, part of the pin portion from the pin side surface 111 to the connecting rib 13 is also removed.

[0103] In some embodiments, the second preset distance d2 is greater than or equal to 20 μm, so that after the solder layer is subsequently formed, the edge of the connection layer 8 is separated from the solder layer, which facilitates the subsequent removal of the connection layer 8 .

[0104] In this embodiment, the second insulating layer 62 covers a portion of the width of the connection layer 8 near the edge. In some other embodiments, the middle region of the exposed surface of the connection layer 8 may also be provided with a second insulating layer.

[0105] In some embodiments, the depth of the second groove 201 is greater than the thickness of the pins 11 of the two adjacent lead frame units 10, and the depth of the second groove 201 on the opening side of the second insulating layer 62 toward the second groove 201 is greater than half the thickness of the pins 11 of the two adjacent lead frame units 10 to ensure the solder height on the side surface of the pin when the solder layer is subsequently formed.

[0106] like Fig.15 As shown, in step S120, a solder layer 70 is formed on the exposed surface of the lead frame 1 to form Fig.16 The intermediate structure 2003 is shown. In the intermediate structure 2003, solder layers 71 and 72 are formed on the first surface 1101 of the lead frame 1 and the lead side surface 111 on the side of the connection layer 8 close to the first surface 1101, respectively.

[0107] In some embodiments, in step S130, only the electrical connection structure having the second insulating layer on the surface thereof may be removed.

[0108] like Fig.16 As shown, in step S130 , removing the electrical connection member includes removing the electrical connection structure having the second insulating layer 62 on the surface, exposing the second groove 201 , and forming an intermediate structure 2004 .

[0109] Here, the electrical connection structure can be removed by cutting. The electrical connection structure can be cut along the thickness direction of the intermediate structure 2003, specifically, along the side of the solder layer 72 away from the pin, for example, along the Fig.15 The dotted line 103 is cut to cut the electrical connection structure into a first portion 801 located between the two dotted lines 103, and a second portion 802 and a third portion 803 outside the two dotted lines 103, and the first portion 801 is first taken out from the second slot 201, and then the second portion 802 and the third portion 803 are taken out.

[0110] like Fig.17 As shown, after step S130, the method includes the following step S1510:

[0111] In step S150 , cutting is performed along the second slot 201 to form a plurality of semiconductor structures 2005 .

[0112] In this embodiment, cutting along the second slot 201 can actually be understood as cutting along the cutting line 102 inside the second slot 201 , and the connection between the connecting rib 13 and the pin 11 can be located on the cutting line 102 .

[0113] In some other embodiments, in step S130 , when removing the electrical connection structure having the second insulating layer 62 on the surface, it further includes cutting along the second groove 201 to form a plurality of semiconductor structures.

[0114] Specifically, when cutting, the electrical connection structure with the second insulating layer 62 on the surface and the plastic encapsulation layer 3 can be cut along the cutting line 102 in the thickness direction of the intermediate structure 2003 to form a plurality of semiconductor structures while removing the electrical connection structure with the second insulating layer 62 on the surface. Similar to the above method, when cutting along the cutting line 102, the electrical connection structure can be cut into a first part located between the two cutting lines 102, and a second part and a third part outside the two cutting lines 102. Compared with the above method, the first part, the second part and the third part here can be more easily removed after cutting.

[0115] Please combine Figures 2 to 4 as well as Figures 18 to 25As shown, in some other embodiments, providing a plastic package component in step S110 may specifically include the following steps S111, S112 and S117 to S119:

[0116] In step S111, a lead frame is provided, wherein the lead frame includes the plurality of lead frame units 10 and connecting ribs for connecting the leads 11 of adjacent lead frame units 10;

[0117] In step S112, a plurality of chips are respectively disposed on the lead frame unit 10, and a plastic packaging layer covering the plurality of chips and the lead frame is disposed to form a plastic packaging structure; the lead frame has a first surface facing away from the chip, and the first surface is exposed;

[0118] In step S117, forming a first solder layer on the first surface of the lead frame;

[0119] In step S118, the plastic package structure formed with the first solder layer is cut into pieces to form a plurality of intermediate semiconductor structures; the pins 11 of the lead frame unit 10 in the intermediate semiconductor structures have exposed side surfaces of the pins 11;

[0120] In step S119, a plurality of the intermediate semiconductor structures are spaced apart on a conductive layer, and the conductive layer is connected to the first solder layer; wherein a third groove is formed at least between two adjacent intermediate semiconductor structures, the conductive layer serves as the electrical connector, and a third insulating layer is provided on the surface of the conductive layer located in the third groove.

[0121] like Figures 2 to 4 As shown, step S111 and step S112 may refer to the above related description.

[0122] like Fig.18 As shown, in step S117, a first solder layer 71 is formed on the first surface 1101 of the lead frame 1; that is, a first solder layer 71 is formed on the first surface 1101 of the lead frame 1 in the plastic package structure 1000 formed in step S112, forming a Fig.18 The plastic package structure 3001 is shown.

[0123] Optionally, a cutting path 301 is formed in the plastic encapsulation structure 3001 to form the plastic encapsulation structure 3002. The width of the cutting path 301 is greater than the width of the connecting rib 13.

[0124] like Fig. 20 As shown, in step S118, the plastic package structure (such as the plastic package structure 3002) formed with the first solder layer 71 is cut to form a plurality of intermediate semiconductor structures 3003; the pins 11 of the lead frame unit 10 in the intermediate semiconductor structure have exposed side surfaces of the pins 11;

[0125] like Fig. 20 , Fig.21 and Fig. 22 As shown, in step S119, a plurality of the intermediate semiconductor structures 3003 are spaced apart on the conductive layer 9, and the conductive layer 9 is connected to the first solder layer 71; wherein a third slot 302 is formed at least between two adjacent intermediate semiconductor structures 3003, the conductive layer 9 serves as the electrical connector, and a third insulating layer 63 is provided on the surface of the conductive layer 9 located in the third slot 302, forming a Fig. 22 The plastic package component 3005 shown in FIG. 6 is a portion of the third insulating layer on the surface of the third slot 302 .

[0126] In some embodiments, the conductive layer 9 includes a peripheral region 901 located at the outermost intermediate semiconductor structure 3003 away from the adjacent intermediate semiconductor structure 3003. To facilitate the removal of the conductive layer 9, the third insulating layer 63 is also located on the peripheral region 901 of the conductive layer 9. Fig. 20 and Fig.21 632 shown.

[0127] In some embodiments, the molding layer 3 of the intermediate semiconductor structure 3003 has a first molding surface 31 flush with the first surface 1101 of the lead frame, and the third insulating layer 63 is also located between the conductive layer 9 and the first molding surface 31 , that is, located in the portion 633 in the gap 310 .

[0128] In some embodiments, a third preset distance d3 is present between the edge of the third insulating layer 63 and the plane where the corresponding side surface of the lead 11 is located, and the third preset distance d3 is consistent with the thickness of the first solder layer 71 .

[0129] The third preset distance d3 may be the same as the thickness of the first solder layer 71 , or slightly larger or smaller.

[0130] In some embodiments, the third preset distance d3 can be set to a distance value less than or equal to 0.05 mm.

[0131] like Fig.23 As shown, forming a solder layer on the exposed surface of the lead frame in step S120 includes:

[0132] A second solder layer 72 is formed on the pin side surface 111 to form a Fig.23 The intermediate structure 3005 is shown.

[0133] like Fig.24 and Fig.25 Accordingly, after the electrical connectors are removed in step S130 , a plurality of semiconductor structures 3006 can be formed.

[0134] After the second solder layer 72 is formed on the side surface of the lead 11 , in the formed semiconductor structure 3006 , the second solder layer 72 covers the entire area of ​​the side surface 111 of the lead.

[0135] The conductive layer 9 may be a plate-like structure formed of a conductive material with a certain strength, or may be a conductive film layer formed of a conductive material.

[0136] In some embodiments, when the conductive layer 9 is a conductive film layer, the conductive film layer can also be supported by a carrier. Accordingly, before the plurality of intermediate semiconductor structures are spaced apart on the conductive layer in step S119, the method includes the following step S160:

[0137] In step S160, the conductive layer is disposed on a carrier;

[0138] Accordingly, after forming the second solder layer 72 on the side surface of the lead 11 in step S120, the method further includes the following step S170:

[0139] In step S170, the carrier board is removed.

[0140] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0141] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0142] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The manufacturing method comprises: A plastic encapsulation component is provided, the plastic encapsulation component comprising a plurality of chips, a plurality of lead frame units respectively connected to the plurality of chips, a plastic encapsulation layer and an electrical connector, the lead frame unit comprising a plurality of pins, the plastic encapsulation layer at least encapsulating the chip and the corresponding lead frame unit, a groove from which part or all of the plastic encapsulation layer is removed is provided between two adjacent lead frame units, the pins of two adjacent lead frame units have pin side surfaces facing and opposite to the groove, the pins of the two lead frame units are connected by the electrical connector, the electrical connector is located at the bottom of the groove, and an insulating layer located at the bottom of the groove is provided on the surface of the electrical connector; forming a solder layer on the exposed surface of the lead frame; Remove the electrical connector.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The provision of a plastic package assembly comprises: Providing a lead frame, the lead frame comprising the plurality of lead frame units and connecting ribs connecting pins of adjacent lead frame units; Arranging a plurality of chips on the lead frame units respectively and correspondingly, and arranging a plastic packaging layer covering the plurality of chips and the lead frame to form a plastic packaging structure; A first slot is formed; the first slot is located between two adjacent lead frame units and is formed by opening a portion of the depth inward from the side where the lead frame is located in the plastic package structure; wherein a portion of the thickness of the connecting rib is retained at the bottom of the first slot to form the electrical connector; A first insulating layer is disposed on the exposed surface of the electrical connector; wherein a first preset distance exists between the edge of the first insulating layer and the pin side surfaces of the two adjacent lead frame units or the edge of the first insulating layer contacts the pin side surfaces of the two adjacent lead frame units.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: When there is a first preset distance between the edge of the first insulating layer and the side surface of the pin, the first preset distance is less than or equal to 0.1 mm; When the edge of the first insulating layer contacts the side surfaces of the leads of the two adjacent lead frame units, after the first insulating layer is provided, the remaining groove depth in the first groove is greater than half of the thickness of the leads of the two adjacent lead frame units.

4. The method for manufacturing a semiconductor structure according to claim 2, wherein: The depth of the first groove is less than the thickness of the pins of the two adjacent lead frame units, and the depth of the first groove is greater than half of the thickness of the pins of the two adjacent lead frame units.

5. The method for manufacturing a semiconductor structure according to claim 2, wherein: After forming a solder layer on the exposed surface of the lead frame, the method comprises: Cutting is performed along the first groove to form a plurality of semiconductor structures; wherein the cutting along the first groove includes removing the electrical connector and removing a portion of the plastic packaging layer located within the orthographic projection range of the first groove in the thickness direction of the plastic packaging structure.

6. The method for manufacturing a semiconductor structure according to claim 2, wherein: After forming a solder layer on the exposed surface of the lead frame and before removing the electrical connector, the method comprises: The first insulating layer is removed.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein: The provision of a plastic package assembly comprises: Providing a lead frame, the lead frame comprising the plurality of lead frame units and connecting ribs connecting pins of adjacent lead frame units; Arranging a plurality of chips on the lead frame units respectively and correspondingly, and arranging a plastic packaging layer covering the plurality of chips and the lead frame to form a plastic packaging structure; The connecting ribs are removed and a second slot is formed; the second slot is located between adjacent lead frame units and is formed by opening a portion of the thickness inward from the side of the lead frame in the plastic package structure; An electrical connection structure having a second insulating layer on its surface is arranged in the second groove; the electrical connection structure serves as the electrical connector and connects the pin side surfaces of two adjacent lead frame units; wherein the second insulating layer extends a second preset distance from the pin side surfaces of the two adjacent lead frame units toward the middle of the second groove.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein: The second preset distance is greater than or equal to 20 μm; and / or, The depth of the second groove is greater than the thickness of the pins of the two adjacent lead frame units, and the depth of the second groove on the opening side of the second insulating layer facing the second groove is greater than half the thickness of the pins of the two adjacent lead frame units.

9. The method for manufacturing a semiconductor structure according to claim 7, wherein: The removing of the electrical connection member comprises: removing the electrical connection structure having the second insulating layer on the surface; When or after removing the electrical connection structure, the method includes: cutting along the second groove to form a plurality of semiconductor structures.

10. The method for manufacturing a semiconductor structure according to claim 1, wherein: The provision of a plastic package assembly comprises: Providing a lead frame, the lead frame comprising the plurality of lead frame units and connecting ribs connecting pins of adjacent lead frame units; A plurality of chips are respectively arranged on the lead frame unit, and a plastic packaging layer covering the plurality of chips and the lead frame is arranged to form a plastic packaging structure; the lead frame has a first surface facing away from the chip, and the first surface is exposed; forming a first solder layer on a first surface of the lead frame; Cutting the plastic package structure formed with the first solder layer to form a plurality of intermediate semiconductor structures; the pins of the lead frame units in the intermediate semiconductor structures have exposed pin side surfaces; A plurality of the intermediate semiconductor structures are spaced apart on a conductive layer, and the conductive layer is connected to the first solder layer; wherein a third groove is formed at least between two adjacent intermediate semiconductor structures, the conductive layer serves as the electrical connector, and a third insulating layer is provided on the surface of the conductive layer located in the third groove.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein: The conductive layer includes a peripheral region of the outermost intermediate semiconductor structure away from the adjacent intermediate semiconductor structure, and the third insulating layer is also located on the peripheral region of the conductive layer; The intermediate semiconductor structure molding layer has a first molding surface flush with the first surface of the lead frame, and the third insulating layer is also located between the conductive layer and the first molding surface.

12. The method for manufacturing a semiconductor structure according to claim 10 or 11, characterized in that: There is a third preset distance between the edge of the third insulating layer and the plane where the corresponding pin side surface is located, and the third preset distance is consistent with the thickness of the first solder layer.

13. The method for manufacturing a semiconductor structure according to claim 10, wherein: The forming of a solder layer on the surface exposed by the lead frame comprises: forming a second solder layer on the pin side surface; After removing the electrical connections, a plurality of semiconductor structures are formed.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein: After the second solder layer is formed on the lead side surface, the second solder layer covers the entire area of ​​the lead side surface.

15. The method for manufacturing a semiconductor structure according to claim 13 or 14, characterized in that: Before disposing a plurality of the intermediate semiconductor structures on the conductive layer in an interval, the method comprises: Disposing the conductive layer on a carrier; After forming a second solder layer on the pin side surface, the method further includes: The carrier plate is removed.

Images