Semiconductor device and forming method thereof
By forming a barrier layer in front of the buried layer region of the semiconductor device, the problem of step height difference between the N-type buried layer region and the non-N-type buried layer region is solved, and a flat surface and higher device reliability are achieved.
Patent Information
- Application Number
- CN202510238822.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2025-05-02
AI Technical Summary
In semiconductor manufacturing processes, there is a step height difference between the N-type buried layer region and the non-N-type buried layer region, resulting in the mask layer remaining in the subsequent process, which in turn causes semiconductor device failure.
Before annealing treatment is performed on the substrate, the reactants are transported to the substrate, and the barrier layer is formed on the surface of the substrate, and the reactants do not react chemically with the substrate and the buried layer region to avoid height difference and doped element escape.
The top surface of the buried layer area is ensured to be flush with the front surface of the substrate, providing a flat surface for subsequent semiconductor processes, avoiding device failure problems, and improving the reliability and stability of semiconductor devices.
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Figure CN119920752A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a method for forming the same. Background Art
[0002] As a semiconductor structure, the N-type buried layer is often used in high-voltage devices and plays an electrical isolation role to improve the reliability and stability of semiconductor devices such as high-voltage devices. In the semiconductor manufacturing process, the method for forming the N-type buried layer is usually to implant doping ions with a low diffusion coefficient into the substrate, and then activate the doping ions by high-temperature thermal drive to ensure that the N-type buried layer has a high doping density and a low diffusion range. However, in the process of activating the doping ions in the substrate at high temperature, it is necessary to form a thermal oxide layer to reduce the escape of the doping elements, thereby ensuring the doping density of the formed N-type buried layer. The current mainstream process is to form the thermal oxide layer by wet oxidation. However, in the process of forming the thermal oxide layer by the wet oxidation method, the oxidation rate of silicon in the N-type buried layer into which the doping ions have been implanted is greater than the oxidation rate of silicon in the non-N-type buried layer region (i.e., the peripheral region of the N-type buried layer), resulting in a step height (Step Height) between the N-type buried layer region and the non-N-type buried layer region after the thermal oxide layer is formed by the wet oxidation method, that is, the N-type buried layer region is lower than the non-N-type buried layer region. In the subsequent semiconductor device manufacturing process, the step height difference always exists, which may cause the SIN mask layer to remain on the active area above the N-type buried layer area. After forming the STI (shallow trench isolation structure), the remaining SIN cannot be removed, thereby causing the failure of the semiconductor device.
[0003] Therefore, how to reduce the step height between buried regions such as N-type buried regions and non-buried regions such as non-N-type buried regions, thereby reducing the probability of failure of semiconductor devices and improving the performance of semiconductor devices, is a technical problem that needs to be solved urgently. Summary of the invention
[0004] The present invention provides a semiconductor device and a method for forming the same, which are used to reduce the step height between buried regions such as N-type buried regions and non-buried regions such as non-N-type buried regions, thereby reducing the probability of failure of the semiconductor device and improving the performance of the semiconductor device.
[0005] According to some embodiments, the present invention provides a method for forming a semiconductor device, comprising the following steps:
[0006] forming a substrate, the substrate comprising a front surface and a back surface that are relatively distributed along a first direction, and the substrate has a first doping element therein;
[0007] Implanting a second doping element into the substrate to form a buried region in the substrate, wherein the conductivity type of the first doping element is opposite to the conductivity type of the second doping element;
[0008] Transporting reactants to the substrate to form a barrier layer on the surface of the substrate, wherein the reactants do not chemically react with the substrate and the buried layer region;
[0009] The substrate is subjected to annealing treatment, and the top surface of the buried layer region after the annealing treatment is flush with the front surface of the substrate.
[0010] In some embodiments, the specific steps of implanting the second doping element into the substrate to form a buried region in the substrate include:
[0011] forming a photoresist layer on the substrate, wherein the photoresist layer has an opening penetrating the photoresist layer along the first direction;
[0012] The second doping element is implanted into the substrate along the opening to form the buried region, wherein the top surface of the buried region is flush with the front surface of the substrate.
[0013] In some embodiments, before forming a photoresist layer on the substrate, the following steps are further included:
[0014] A protection layer is formed covering the front surface of the substrate.
[0015] In some embodiments, the material of the substrate includes silicon; and the specific steps of forming the protection layer covering the front surface of the substrate include:
[0016] Providing an initial substrate, the initial substrate comprising a first surface and a second surface oppositely distributed along the first direction;
[0017] A thermal oxidation process is adopted to oxidize a portion of the initial substrate from the first surface to form the protection layer, and the remaining initial substrate below the protection layer serves as the substrate.
[0018] In some embodiments, the first doping element is a P-type element, and the second doping element is an antimony element.
[0019] In some embodiments, the specific steps of transferring reactants to the substrate and forming a barrier layer on the surface of the substrate include:
[0020] The reactant is transported onto the protective layer to form the barrier layer including silicon nitride on the surface of the protective layer.
[0021] In some embodiments, the specific steps of transferring the reactant onto the protective layer to form the barrier layer including silicon nitride on the surface of the protective layer include:
[0022] The reactant is transported onto the protective layer, and a plasma enhanced chemical vapor deposition process is used to form the barrier layer including silicon nitride on the surface of the protective layer.
[0023] In some embodiments, the following steps are also included:
[0024] The parameters of the plasma enhanced chemical vapor deposition process are adjusted to form the barrier layer having a thickness greater than that of the protective layer on the surface of the protective layer.
[0025] In some embodiments, the specific steps of annealing the buried layer region include:
[0026] The substrate is annealed by a furnace annealing process, and the top surface of the buried layer region after the annealing is flush with the front surface of the substrate.
[0027] In some embodiments, after annealing the buried layer region, the method further includes the following steps:
[0028] The barrier layer and the protective layer are removed by a wet etching process to expose the front surface of the substrate and the top surface of the buried layer region.
[0029] According to some other embodiments, the present invention also provides a semiconductor device formed by the method for forming a semiconductor device as described above; the semiconductor device comprises:
[0030] A substrate, the substrate comprising a front surface and a back surface that are relatively distributed along a first direction, and the substrate has a first doping element therein;
[0031] A buried region is located in the substrate, the buried region includes a second doping element, the conductivity type of the first doping element is opposite to the conductivity type of the second doping element, and the top surface of the buried region is flush with the front surface of the substrate.
[0032] In some embodiments, the first doping element is a P-type element, and the second doping element is an antimony element.
[0033] The semiconductor device and the method for forming the same provided by the present invention form a barrier layer on the surface of the substrate by transferring reactants to the substrate before annealing the buried layer region into which the second doping element is injected, and the reactants do not chemically react with the substrate and the buried layer region. On the one hand, since the reactants used to form the barrier layer do not chemically react with the substrate and the buried layer region, consumption of the substrate and the buried layer region is avoided, and the height difference caused by the different chemical reaction rates of the substrate and the buried layer region is avoided, ensuring that the top surface of the buried layer region is flush with the front surface of the substrate after the annealing treatment, providing a flat surface for the implementation of subsequent semiconductor processes, and avoiding the subsequent device failure problem caused by the residue of the mask layer; on the other hand, the barrier layer can prevent the second doping element in the buried layer region from escaping during the subsequent annealing treatment, ensuring the doping concentration in the buried layer region, thereby improving the reliability and stability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 is a flow chart of a method for forming a semiconductor device in a specific embodiment of the present invention;
[0035] Figure 2 is a schematic structural diagram of an initial substrate in a specific embodiment of the present invention;
[0036] Figure 3 is a schematic diagram of the structure after forming a protective layer in a specific embodiment of the present invention;
[0037] Figure 4 is a schematic diagram of the structure after a photoresist layer is formed in a specific embodiment of the present invention;
[0038] Figure 5 is a schematic diagram of the structure when the second doping element is injected into the substrate in a specific embodiment of the present invention;
[0039] Figure 6 is a schematic diagram of the structure after the photoresist layer is removed in a specific embodiment of the present invention;
[0040] Figure 7 is a schematic diagram of the structure after forming a barrier layer in a specific embodiment of the present invention;
[0041] Figure 8 is a schematic structural diagram of a substrate after annealing in a specific embodiment of the present invention;
[0042] Fig. 9 It is a schematic diagram of the structure after removing the protective layer and the barrier layer in a specific embodiment of the present invention.
[0043] Description of Reference Numerals
[0044] 20 Initial substrate
[0045] 201 First Surface
[0046] 202 Second Surface
[0047] 30 Substrate
[0048] 301 Front
[0049] 302 Back
[0050] 31 Protective layer
[0051] 40 Photoresist layer
[0052] 41 Opening
[0053] 60 buried layer area
[0054] 70 Barrier layer DETAILED DESCRIPTION
[0055] The specific implementation manner of the semiconductor device and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.
[0056] This specific embodiment provides a method for forming a semiconductor device. Figure 1 FIG. 1 is a flow chart of a method for forming a semiconductor device in a specific embodiment of the present invention. Figure 1 As shown, the method for forming the semiconductor device comprises the following steps:
[0057] Step S11, forming a substrate, wherein the substrate comprises a front surface and a back surface that are relatively distributed along a first direction, and wherein a first doping element is present in the substrate;
[0058] Step S12, implanting a second doping element into the substrate to form a buried region in the substrate, wherein the conductivity type of the first doping element is opposite to the conductivity type of the second doping element;
[0059] Step S13, transferring reactants to the substrate to form a barrier layer on the surface of the substrate, and the reactants do not chemically react with the substrate and the buried layer region;
[0060] Step S14, annealing the buried layer region, wherein the top surface of the buried layer region after the annealing is flush with the front surface of the substrate.
[0061] Figure 2 is a schematic structural diagram of an initial substrate in a specific embodiment of the present invention, Figure 3 is a schematic diagram of the structure after forming a protective layer in a specific embodiment of the present invention, Figure 4is a schematic diagram of the structure after the photoresist layer is formed in a specific embodiment of the present invention, Figure 5 is a schematic diagram of the structure when the second doping element is injected into the substrate in a specific embodiment of the present invention, Figure 6 3 is a schematic diagram of the structure after removing the photoresist layer in a specific embodiment of the present invention. In some embodiments, the specific steps of injecting the second doping element into the substrate 30 to form the buried layer region 60 in the substrate 30 include:
[0062] A photoresist layer 40 is formed on the substrate 30. The photoresist layer 40 has an opening 41 penetrating the photoresist layer 40 along the first direction D1. Figure 4 As shown;
[0063] The second doping element is implanted into the substrate 30 along the opening 41 to form the buried region 60, and the top surface of the buried region 60 is flush with the front surface 301 of the substrate 30. Figure 6 shown.
[0064] In some embodiments, before forming the photoresist layer 40 on the substrate 30, the following steps are further included:
[0065] A protective layer 31 is formed to cover the front surface 301 of the substrate 30, such as Figure 3 shown.
[0066] In some embodiments, the material of the substrate 30 includes silicon; the specific steps of forming the protection layer 31 covering the front surface 301 of the substrate 30 include:
[0067] An initial substrate 20 is provided, wherein the initial substrate 20 includes a first surface 201 and a second surface 202 that are oppositely distributed along the first direction D1. Figure 2 As shown;
[0068] A thermal oxidation process is used to oxidize a portion of the initial substrate 20 from the first surface 201 to form the protective layer 31, and the remaining initial substrate 20 below the protective layer 31 serves as the substrate 30. Figure 3 shown.
[0069] For example, an initial substrate 20 doped with the first doping element is provided. In one example, the initial substrate 20 is a silicon substrate or a silicon-on-insulator substrate. The initial substrate 20 includes the first surface 201 and the second surface 202 that are relatively distributed along the first direction D1. Figure 2As shown. The initial substrate 20 is first cleaned by a wet cleaning process to remove organic pollutants, particulate matter and other impurities on the surface of the initial substrate 20. Then, a thermal oxidation process can be used to oxidize part of the initial substrate 20 from the first surface 201 of the initial substrate 20 to form the protective layer 31 made of silicon dioxide. The remaining initial substrate 20 below the protective layer 31 serves as the substrate 30, as shown. Figure 3 As shown. The surface of the substrate 30 facing the protective layer 31 serves as the front side 301 of the substrate 30, and the second surface 202 of the initial substrate 20 serves as the back side 302 of the substrate 30. The protective layer 31 covers the front side 301 of the substrate 30. On the one hand, it can protect the front side 301 of the substrate 30 to prevent the front side 301 of the substrate 30 from being contaminated; on the other hand, it can serve as a protective layer for the subsequent injection of the second doping element, thereby better protecting the substrate 30.
[0070] After forming the protective layer 31, the photoresist layer 40 is formed by spin coating photoresist, exposure and development, etc., wherein the photoresist layer 40 has the opening 41 penetrating the photoresist layer 40 along the first direction D1 and exposing the protective layer 31. Figure 4 In one example, the photoresist layer 40 may include a plurality of the openings 41 arranged at intervals at least along the second direction D2, so as to facilitate the subsequent simultaneous formation of a plurality of the buried regions 60 arranged at intervals, wherein the second direction D2 intersects the first direction D1 perpendicularly. Then, the second doping element is injected vertically from the openings 41 into the interior of the substrate 30 along the first direction D1, as shown in FIG. Figure 5 As shown, Figure 5 The solid arrow in the figure indicates the injection direction of the second doping element. After the second doping element is injected, the buried region 60 is formed in the substrate 30. Figure 6 As shown, the top surface of the buried region 60 (i.e., the surface of the buried region 60 facing away from the back surface 302 of the substrate 30) is flush with the front surface 301 of the substrate 30. Next, a high temperature ashing process is used to remove most of the photoresist layer 40, and a wet etching process is used to remove the remaining photoresist layer 40 to expose the protective layer 31. Figure 6 In one example, the etchant used in the wet etching process includes hydrogen peroxide and sulfuric acid. In another example, the etchant used in the wet etching process includes hydrogen peroxide and ammonia.
[0071] In some embodiments, the first doping element is a P-type element, and the second doping element is an antimony element.
[0072] For example, the substrate 30 is a P-type substrate doped with a P-type element, and the second doping element is an N-type element. Since antimony has a low diffusion coefficient, the doping concentration of the buried layer region 60 after subsequent annealing can be ensured, thereby ensuring the electrical isolation performance of the buried layer region 60.
[0073] Figure 7 70 is a schematic diagram of a structure after forming a barrier layer in a specific embodiment of the present invention. In some embodiments, the specific steps of transferring reactants to the substrate 30 and forming a barrier layer 70 on the surface of the substrate 30 include:
[0074] The reactant is transported onto the protection layer 31 to form the barrier layer 70 , which includes silicon nitride, on the surface of the protection layer 31 .
[0075] In some embodiments, the specific steps of transferring the reactant onto the protective layer 31 and forming the barrier layer 70 made of silicon nitride on the surface of the protective layer 31 include:
[0076] The reactants are transported onto the protective layer 31, and a barrier layer 70 including silicon nitride is formed on the surface of the protective layer 31 by a plasma enhanced chemical vapor deposition process. Figure 7 shown.
[0077] For example, after removing the photoresist layer 40, the substrate 30 formed with the protective layer 31 and the buried region 60 is cleaned again by a wet cleaning process. Then, a plasma enhanced chemical vapor deposition process is used to transfer a plurality of the reactants to the surface of the protective layer 31, and a chemical reaction occurs between the plurality of the reactants to form a barrier layer 70 of silicon nitride on the surface of the protective layer 31. The barrier layer 70 is used to block the escape of the second doping element during the subsequent annealing process. Since all the reactants transferred do not react chemically with silicon, that is, all the reactants transferred do not react chemically with the substrate 30 and the buried region 60, not only the consumption of the substrate 30 and the buried region 60 is avoided, the stability of the size of the buried region 60 is ensured, and the height difference caused by the different reaction rates of the substrate 30 and the buried region 60 can be effectively avoided, so that after the formation of the barrier layer 70, the front surface of the substrate 30 still remains flush with the top surface of the buried region 60. The use of the plasma enhanced chemical vapor deposition process to form the barrier layer 70 is helpful to improve the density of the barrier layer 70, thereby helping to further prevent the second doping element from escaping during the subsequent annealing process.
[0078] In some embodiments, the method for forming a semiconductor device further includes the following steps:
[0079] The parameters of the plasma enhanced chemical vapor deposition process are adjusted to form the barrier layer 70 having a thickness greater than that of the protection layer 31 on the surface of the protection layer 31 .
[0080] Specifically, the parameters of the plasma enhanced chemical vapor deposition process include any one of the deposition time, deposition temperature, deposition pressure, and reaction gas dosage of the plasma enhanced chemical vapor deposition process, or a combination of two or more thereof. By making the thickness of the barrier layer 70 greater than the thickness of the protective layer 31, the escape of the second doping element during the subsequent annealing process can be further effectively avoided.
[0081] Figure 8 30 is a schematic diagram of the structure after the substrate is annealed in a specific embodiment of the present invention. In some embodiments, the specific steps of annealing the substrate 30 include:
[0082] The substrate 30 is annealed by a furnace annealing process. After the annealing process, the top surface of the buried layer region 60 is flush with the front surface 301 of the substrate 30. Figure 8 shown.
[0083] Specifically, the substrate is heated by a furnace annealing process, so that the second doping element in the buried region 60 in the substrate 30 is pushed forward and activated at high temperature, so that the second doping element diffuses in the substrate 30. Because the barrier layer 70 for preventing the second doping element from escaping is formed above the substrate 30 before the annealing process is implemented, there is no need to add a thermal oxidation process to consume silicon during the annealing process, thereby avoiding the height difference caused by the different consumption rates of silicon in the substrate 30 and the buried region 60, so that after the annealing process, the top surface of the buried region 60 remains flush with the front surface 301 of the substrate 30, as shown in FIG. Figure 8 shown.
[0084] Fig. 9 1 is a schematic diagram of the structure after removing the protective layer and the barrier layer in a specific embodiment of the present invention. In some embodiments, after annealing the buried layer region 60, the following steps are also included:
[0085] The barrier layer 70 and the protective layer 31 are removed by wet etching process to expose the front surface 301 of the substrate 30 and the top surface of the buried layer region 60. Fig. 9 shown.
[0086] For example, the barrier layer 70 and the protective layer 31 are removed by a wet etching process, and the exposed front side 301 of the substrate 30 is flush with the top surface of the buried layer region 60, thereby providing a smooth surface for the subsequent deposition of an epitaxial layer on the front side 301 of the substrate 30 by a chemical vapor deposition process and the preparation of a high-voltage device structure on the epitaxial layer, thereby avoiding the failure of semiconductor devices caused by residual film material due to height differences in subsequent processes.
[0087] This specific embodiment also provides a semiconductor device, which is formed by the method for forming a semiconductor device as described above, see Figure 1-Figure 9 The schematic diagram of the structure of the semiconductor device can be found in Fig. 9 .like Figure 1-Figure 9 As shown, the semiconductor device comprises:
[0088] A substrate 30, wherein the substrate 30 comprises a front surface 301 and a back surface 302 which are relatively distributed along a first direction D1, and the substrate 30 has a first doping element therein;
[0089] The buried region 60 is located in the substrate 30 , and the buried region 60 includes a second doping element, the conductivity type of the first doping element is opposite to the conductivity type of the second doping element, and the top surface of the buried region 60 is flush with the front surface 301 of the substrate 30 .
[0090] In some embodiments, the first doping element is a P-type element, and the second doping element is an antimony element.
[0091] The semiconductor device and the method for forming the same provided in this specific embodiment form a barrier layer on the surface of the substrate by transferring reactants to the substrate before annealing the buried region injected with the second doping element, and the reactants do not chemically react with the substrate and the buried region. On the one hand, since the reactants used to form the barrier layer do not chemically react with the substrate and the buried region, consumption of the substrate and the buried region is avoided, thereby avoiding the height difference caused by the different chemical reaction rates of the substrate and the buried region, ensuring that the top surface of the buried region is flush with the front surface of the substrate after the annealing treatment, providing a flat surface for the implementation of subsequent semiconductor processes, and avoiding the subsequent device failure problem caused by the residue of the mask layer; on the other hand, the barrier layer can prevent the second doping element in the buried region from escaping during the subsequent annealing treatment, ensuring the doping concentration in the buried region, thereby improving the reliability and stability of the semiconductor device.
[0092] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A method for forming a semiconductor device, characterized in that: The steps include: forming a substrate, the substrate comprising a front surface and a back surface that are relatively distributed along a first direction, and the substrate has a first doping element therein; Implanting a second doping element into the substrate to form a buried region in the substrate, wherein the conductivity type of the first doping element is opposite to the conductivity type of the second doping element; Transporting reactants to the substrate to form a barrier layer on the surface of the substrate, wherein the reactants do not chemically react with the substrate and the buried layer region; The buried layer region is annealed, and the top surface of the buried layer region after the annealing is flush with the front surface of the substrate.
2. The method for forming a semiconductor device according to claim 1, wherein: The specific steps of implanting a second doping element into the substrate to form a buried layer region in the substrate include: forming a photoresist layer on the substrate, wherein the photoresist layer has an opening penetrating the photoresist layer along the first direction; The second doping element is implanted into the substrate along the opening to form the buried region, wherein the top surface of the buried region is flush with the front surface of the substrate.
3. The method for forming a semiconductor device according to claim 2, wherein: Before forming a photoresist layer on the substrate, the method further includes the following steps: A protection layer is formed covering the front surface of the substrate.
4. The method for forming a semiconductor device according to claim 3, wherein: The material of the substrate includes silicon; the specific steps of forming a protective layer covering the front surface of the substrate include: Providing an initial substrate, the initial substrate comprising a first surface and a second surface oppositely distributed along the first direction; A thermal oxidation process is adopted to oxidize a portion of the initial substrate from the first surface to form the protection layer, and the remaining initial substrate below the protection layer serves as the substrate.
5. The method for forming a semiconductor device according to claim 1, wherein: The first doping element is a P-type element, and the second doping element is an antimony element.
6. The method for forming a semiconductor device according to claim 3, wherein: The specific steps of transferring reactants to the substrate and forming a barrier layer on the surface of the substrate include: The reactant is transported onto the protective layer to form the barrier layer including silicon nitride on the surface of the protective layer.
7. The method for forming a semiconductor device according to claim 6, wherein: The specific steps of transferring the reactant to the protective layer to form the barrier layer including silicon nitride on the surface of the protective layer include: The reactant is transported onto the protective layer, and a plasma enhanced chemical vapor deposition process is used to form the barrier layer including silicon nitride on the surface of the protective layer.
8. The method for forming a semiconductor device according to claim 7, wherein: The following steps are also included: The parameters of the plasma enhanced chemical vapor deposition process are adjusted to form the barrier layer having a thickness greater than that of the protective layer on the surface of the protective layer.
9. The method for forming a semiconductor device according to claim 1, wherein: The specific steps of annealing the buried layer region include: The substrate is annealed by a furnace annealing process, and the top surface of the buried layer region after the annealing is flush with the front surface of the substrate.
10. The method for forming a semiconductor device according to claim 6, wherein: After annealing the buried layer region, the following steps are also included: The barrier layer and the protective layer are removed by a wet etching process to expose the front surface of the substrate and the top surface of the buried layer region.
11. A semiconductor device, characterized in that: The semiconductor device is formed by the method for forming a semiconductor device according to claim 1; the semiconductor device comprises: A substrate, the substrate comprising a front surface and a back surface that are relatively distributed along a first direction, and the substrate has a first doping element therein; A buried region is located in the substrate, the buried region includes a second doping element, the conductivity type of the first doping element is opposite to the conductivity type of the second doping element, and the top surface of the buried region is flush with the front surface of the substrate.
12. The semiconductor device according to claim 11, characterized in that The first doping element is a P-type element, and the second doping element is an antimony element.