Method and apparatus for dynamically increasing amplifier slew rate

Abstract

The invention relates to a method and apparatus for dynamically increasing amplifier slew rate. An example apparatus includes a first transistor 320 having a first terminal and a control terminal; a second transistor 322 having a first terminal and a control terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor; a third transistor 324 having a first terminal and a control terminal; a fourth transistor 326 having a first terminal and a control terminal, the first terminal of the fourth transistor being coupled to the first terminal of the third transistor; a feedback circuitry 312 coupled to the first transistor, the second transistor, the third transistor, and the fourth transistor; current source circuitry 314 having a first terminal and a second terminal, the first terminal of the current source circuitry being coupled to the feedback circuitry; swivel assist circuitry 316 coupled to the first transistor, the second transistor, the third transistor, and the fourth transistor, the feedback circuitry, and the current source circuitry.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of and priority to U.S. Provisional Patent Application No. 63 / 546,622, filed on October 21, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present description relates generally to amplifiers and, more particularly, to methods and apparatus for dynamically increasing the slew rate of an amplifier. Background Art

[0004] As electronic devices continue to advance, systems need to be able to safely operate at higher and higher powers and at higher and higher speeds. In amplifier circuitry, increasingly complex circuitry can handle higher output voltages, output currents, and operating speeds. Such circuitry enables amplifier circuitry to safely support a wide range of operating conditions. Summary of the invention

[0005] For methods and apparatus for dynamically increasing the slew rate of an amplifier, an example apparatus includes: a first transistor having a first terminal and a control terminal; a second transistor having a first terminal and a control terminal, the first terminal of the second transistor being coupled to the first terminal of the first transistor; a third transistor having a first terminal and a control terminal; a fourth transistor having a first terminal and a control terminal, the first terminal of the second transistor being coupled to the first terminal of the third transistor; a feedback circuit system having a first terminal, a second terminal, a third terminal, and a fourth terminal; a current source circuit system having a first terminal and a second terminal, the first terminal of the current source circuit system being coupled to the first terminal of the feedback circuit system; a slew assist circuit system having a first terminal, a second terminal, a third terminal, and a fourth terminal. A first terminal of the slewing assist circuit system is coupled to a control terminal of the first transistor, a control terminal of the second transistor, and a second terminal of the feedback circuit system, a second terminal of the slewing assist circuit system is coupled to a control terminal of the third transistor, a control terminal of the fourth transistor, and a third terminal of the feedback circuit system, a third terminal of the slewing assist circuit system is coupled to a fourth terminal of the feedback circuit system, and a fourth terminal of the slewing assist circuit system is coupled to a second terminal of the current source circuit system; and a current mirror circuit system having a first terminal and a second terminal, a first terminal of the current mirror circuit system is coupled to a fifth terminal of the slewing assist circuit system, and a second terminal of the current mirror circuit system is coupled to a sixth terminal of the slewing assist circuit system. Other examples are described.

[0006] For methods and apparatus for dynamically improving amplifier slew rate, an example apparatus includes: a first transistor configured to receive a first input; a second transistor configured to receive a second input; an input transistor circuit system coupled to the first transistor and the second transistor, the input transistor circuit system configured to generate a first output and a second output based on the first input and the second input; a slew assist circuit system coupled to the first transistor, the second transistor, and the input transistor circuit system, the slew assist circuit system configured to generate a third output and a fourth output in response to a transient between the first input and the second input; and an output stage circuit system coupled to the input transistor circuit system and the slew assist circuit system, the output stage circuit system configured to: generate an output voltage based on the first output and the second output; and use the third output and the fourth output to improve the slew rate of the transient of the output voltage. Other examples are described.

[0007] For methods and apparatus for dynamically increasing an amplifier slew rate, an example apparatus includes: a feedback circuit system having a first terminal, a second terminal, and a third terminal; a current source circuit system having a first terminal and a second terminal, the first terminal of the current source circuit system being coupled to the first terminal of the feedback circuit system; a first transistor having a first terminal, a second terminal, and a control terminal; a second transistor having a first terminal, a second terminal, and a control terminal; a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor being coupled to the second terminal of the current source circuit system and the first terminal of the first transistor; a fourth transistor having a first terminal, a second terminal, and a control terminal; a fifth transistor having a first terminal and a control terminal, A first terminal of a fifth transistor is coupled to a second terminal of the third transistor and a first terminal of the fourth transistor, a control terminal of the fifth transistor is coupled to a second terminal of the feedback circuitry, a control terminal of the first transistor, and a control terminal of the second transistor; a sixth transistor having a first terminal and a control terminal, a first terminal of the sixth transistor is coupled to a second terminal of the first transistor and a first terminal of the second transistor, a control terminal of the sixth transistor is coupled to a third terminal of the feedback circuitry, a control terminal of the third transistor, and a control terminal of the fourth transistor; and a current mirror circuitry having a first terminal and a second terminal, a first terminal of the current mirror circuitry is coupled to a second terminal of the second transistor, and a second terminal of the current mirror circuitry is coupled to a second terminal of the fourth transistor. Other examples are described. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram of example amplifier circuitry including example input stage circuitry and example output stage circuitry.

[0009] Figure 2 It includes dynamically improving Figure 1 The slew rate of the output stage circuit system is the slew rate of the auxiliary circuit system Figure 1 A block diagram of an example of an input stage circuit system.

[0010] Figure 3 yes Figure 1 and 2 A schematic diagram of an example of an input stage circuit system.

[0011] Figure 4 It is a system that includes clamping circuits. Figure 1 , 2 and a block diagram of another example of an input stage circuit system of 3.

[0012] Figure 5 is included Figure 4 An example of a clamping circuit system Figure 1 , 2 , 3 and 4 are schematic diagrams of examples of input stage circuit systems.

[0013] Figure 6 is included Figure 4 and 5 Another example of a clamping circuit system Figure 1 , 2 , 3, 4 and 5 are schematic diagrams of another example of the input stage circuit system.

[0014] Figure 7 is a flowchart representing example operations that may be at least one of: executed, instantiated, or used Figure 1 , 2 , 3, 4, 5 and 6 are implemented to dynamically increase Figure 1 The slew rate of the amplifier circuit system.

[0015] Figure 8 yes Figure 1 A timing diagram of an example operation of the amplifier circuit system.

[0016] Fig. 9 yes Figure 1 FIG. 1 is another timing diagram of an example operation of an amplifier circuit system.

[0017] The drawings are not necessarily drawn to scale. In general, the same reference numerals in the drawings and the specification refer to the same or similar features and / or parts (functionally and / or structurally). Although the drawings show regions with clear lines and boundaries, some or all of these lines and boundaries may be idealized. In practice, boundaries or lines may be invisible, blended, or irregular. DETAILED DESCRIPTION

[0018] As electronic devices continue to advance, systems need to be able to safely operate at higher and higher powers and at higher and higher speeds. In amplifier circuitry, increasingly complex circuitry can handle higher output voltages, output currents, and operating speeds. Such circuitry enables amplifier circuitry to safely support a wide range of operating conditions.

[0019] When the amplifier circuit system supports a rail-to-rail output voltage of a dynamic range, the output signal of the amplifier circuit system can have a voltage between a high-side power supply voltage (e.g., a power supply voltage) and a low-side power supply voltage (e.g., a reference voltage). In a high voltage device, the difference between the first power supply voltage and the second power supply voltage of the amplifier circuit system becomes larger and larger. For example, in an 85 volt (V) system, the amplifier circuit system can generate an output voltage in the range of 85 volts. In some such systems, the amplifier circuit system is constructed to have a swing of up to 85 volts at the output. Such a relatively large swing at the output of the amplifier circuit system prolongs the time that the amplifier circuit system is in a transient state. The transient state is an operating state that occurs when the amplifier circuit system transitions from a first output voltage to a second output voltage. When in a transient state, the output of the amplifier circuit system reflects an inaccurate input. An ideal amplifier will adjust the output in response to the input voltage instantaneously. However, the delay and settling time of the amplifier circuit system will cause the amplifier circuit system to operate for a certain duration in a transient state.

[0020] The speed at which the amplifier circuit system adjusts the output in response to input changes is characterized by the slew rate. The slew rate is a measure of the voltage per unit time (e.g., millivolts per second) of the amount of possible adjustment of the output by the amplifier circuit system. Increasing the slew rate of the amplifier circuit system shortens the duration of transient operation, thereby increasing the bandwidth of the amplifier circuit system.

[0021] Some amplifier circuit systems include a high voltage input switch, an input transistor circuit system, a feedback circuit system, and an output stage circuit system. One method of increasing the slew rate of the amplifier circuit system is to increase the current of the signal path. The main signal path through the amplifier circuit system starts from the high voltage switch, which receives the first input and the second input of the amplifier circuit system. The high voltage switch can be implemented using a high voltage transistor. The high voltage switch controls a relatively low voltage transistor of the input transistor circuit system, and the relatively low voltage transistor uses a tail current source to generate an intermediate signal path output representing the first input and the second input. In such a design, the high voltage switch protects the transistors of the input transistor circuit system from the high voltage of the first input and the second input.

[0022] During steady-state operating conditions (e.g., no transients at the input of the amplifier circuit system), the output stage circuit system generates an output signal in response to the intermediate signal path output. In some designs, the feedback circuit system generates a feedback current in response to transients at the first input and the second input of the amplifier circuit system. The feedback circuit system uses the feedback current to pull down the control voltage, thereby enhancing (e.g., increasing) the tail current of the intermediate signal path output. During a slew event condition (e.g., there is a transient at the input of the amplifier circuit system), enhancing the tail current of the intermediate signal path output will increase the slew rate of the stable output signal. However, increasing the tail current of the intermediate signal path output will increase the overshoot of the output of the amplifier circuit system, thereby extending the small signal settling time of the amplifier circuit system. This extension of the small signal settling time will offset at least a portion of the increased slew rate. In addition, as the transient at the input of the amplifier circuit system stabilizes, the feedback circuit system allows the control voltage to stabilize, thereby setting the tail current back to a steady-state value. However, when the tail current transitions from the enhanced tail current to the steady-state tail current, the delay in the transition between the currents may result in a relatively high transconductance. Such delays therefore cause stability issues that further extend the settling time of the amplifier circuitry.

[0023] The examples described herein include methods and devices for dynamically improving the slew rate of an amplifier using a slew auxiliary circuit system. In some of the described examples, the amplifier circuit system includes a first current source circuit system, an input transistor circuit system, a feedback circuit system, a slew auxiliary circuit system, a second current source circuit system, a current mirror circuit system, a driver circuit system, and a power stage circuit system. The amplifier circuit system receives a first input signal at a first transistor and receives a second input signal at a second transistor. The first transistor and the second transistor cause the input transistor circuit system to generate an intermediate signal path output based on the values ​​of the first input signal and the second input signal and the setting current from the first current source circuit system. The driver circuit system generates a high-side control signal and a low-side control signal based on the intermediate signal path output. The power stage circuit system generates an output signal by using a high-side control signal and a low-side control signal to control a high-side transistor and a low-side transistor.

[0024] In the described example, during steady-state operating conditions (e.g., no transients at the input of the amplifier circuitry), the slewing assist circuitry directs the slewing assist current from the second current source circuitry to the common terminal, which supplies the common potential. During steady-state operating conditions, the slewing assist circuitry uses a pair of cross-coupled transistors (e.g., a relatively large transistor cross-coupled with a relatively small transistor) that implement cascode biasing to further reduce the current from the second current source into the main signal path. This control method is known as minimum selector cascode.

[0025] During a slewing event condition (e.g., a transient at the input of the amplifier circuit system), the feedback circuit system generates a feedback current in response to the transient. The feedback circuit system uses the feedback current to pull down the control voltage, thereby enhancing the slewing auxiliary current from the second current source circuit system. In some described examples, the current mirror circuit system absorbs the mirror current of the slewing auxiliary current to increase the speed at which the feedback circuit system pulls down the control voltage. In addition, in some examples, the clamp circuit system prevents the current mirror circuit system from absorbing the slewing auxiliary current during steady-state conditions. During the slewing event condition, the slewing auxiliary circuit system turns on the first pair of transistors to form a first current path, and the first current path supplies the enhanced slewing auxiliary current to the current mirror circuit system. In addition, during the slewing event condition, the slewing auxiliary circuit system forms a second current path from the second pair of transistors to the common potential by turning on the cross-coupled cascode transistors to guide the non-ideal current. In such operation, the cross-coupled cascode transistors reduce the supply of the non-ideal current to the second pair of transistors.

[0026] The current mirror circuit system receives a slewing auxiliary current at one of the first output or the second output of the slewing auxiliary circuit system. The current mirror circuit system generates a first bias voltage in response to the current at the first output of the slewing auxiliary circuit system, and generates a second bias voltage in response to the current at the second output of the slewing auxiliary circuit system. The power stage circuit system receives the first bias voltage or the second bias voltage from the current mirror circuit system. The first bias voltage causes the power stage circuit system to absorb current from the low-side transistor by mirroring the slewing auxiliary current. Absorbing current from the low-side transistor increases the slew rate of the rising edge at the output of the amplifier circuit system. The second bias voltage causes the power stage circuit system to supply current to the high-side transistor by mirroring the slewing auxiliary current. Supplying current to the high-side transistor increases the slew rate of the falling edge at the output of the amplifier circuit system.

[0027] Advantageously, supplying current to the high-side transistor increases the slew rate of the amplifier circuit system to generate a falling edge on the output signal. Advantageously, sinking current from the low-side transistor increases the slew rate of the amplifier circuit system to generate a rising edge on the output signal. Advantageously, the slew assist circuit system can increase the slew rate of the amplifier circuit system without increasing the current output by the intermediate signal path. Advantageously, reducing the current output by the intermediate signal path reduces the overshoot of the output signal of the amplifier circuit system, thereby shortening the small signal settling time of the output signal. Advantageously, as the amplifier circuit system recovers from the slew event condition, the slew assist circuit system uses a common source and common gate bias and a minimum selector control to direct non-ideal current from the main signal path.

[0028] Figure 1is a diagram of an example amplifier circuit system 100 including an example input stage circuit system 105 and an example output stage circuit system 110. Figure 1 In the example of , the output stage circuit system 110 includes a driver circuit system 115 and a power stage circuit system 120 . Figure 1 The example power stage circuit system 120 includes a first example transistor 125, a first example capacitor 130, a second example transistor 135, a first example voltage source circuit system 140, a third example transistor 145, a fourth example transistor 150, a second example capacitor 155, a fifth example transistor 160, a sixth example transistor 165, a seventh example transistor 170, an eighth example transistor 175 and a second example voltage source circuit system 180.

[0029] The amplifier circuit system 100 has a first input terminal, a second input terminal, and an output terminal. The first input terminal and the second input terminal are configured to be coupled to an external circuit system that supplies a first input (IN1) and a second input (IN2). In some examples, the first input and the second input represent a differential input signal pair. The transient state at the first input and the second input represents a transition of data of the differential input signal pair. In such examples, when the input switches from one logic level (e.g., logic one, logic zero) to another logic level, the amplifier circuit system 100 transitions the output voltage (V OUT ).exist Figure 1 In an example of , the input stage circuit system 105 dynamically increases the slew rate of the transition of the output of the amplifier circuit system 100 in response to the transient at the first input and the second input. Advantageously, increasing the slew rate shortens the response time of the amplifier circuit system 100.

[0030] Input stage circuit system 105 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal. The first terminal and the second terminal of input stage circuit system 105 are configured to be coupled to external circuit systems that supply the first input and the second input of amplifier circuit system 100. The second terminal, the third terminal, the fourth terminal, and the fifth terminal of input stage circuit system 105 are coupled to output stage circuit system 110. Figure 2 , 3 , 4, 5 and 6 illustrate and describe examples of input stage circuitry 105.

[0031] Output stage circuit system 110 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal, the second terminal, the third terminal, and the fourth terminal of output stage circuit system 110 are coupled to input stage circuit system 105. The fifth terminal of output stage circuit system 110 is configured to be coupled to an external circuit system. This external circuit system is configured to receive the output of amplifier circuit system 100.

[0032] Driver circuit system 115 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal and the second terminal of driver circuit system 115 are coupled to input stage circuit system 105. The second terminal and the third terminal of driver circuit system 115 are coupled to power stage circuit system 120. Figure 1 In an example of the present invention, the driver circuit system 115 is configured as a class AB driver circuit system that linearly controls the power stage circuit system 120 based on the signal from the input stage circuit system 105. In such an example, the driver circuit system 115 is configured to generate a high-side control signal and a low-side control signal in response to the signal from the input stage circuit system 105 to control the conduction of the power stage circuit system 120.

[0033] The power stage circuit system 120 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal and the second terminal of the power stage circuit system 120 are coupled to the input stage circuit system 105. The third terminal and the fourth terminal of the power stage circuit system 120 are coupled to the driver circuit system 115. The fifth terminal of the power stage circuit system 120 is configured to be coupled to an external circuit system that receives the output of the amplifier circuit system 100. Figure 1 In the example of , power stage circuitry 120 is configured to generate the output of amplifier circuitry 100 in response to a bias voltage from input stage circuitry 105 and a control signal from driver circuitry 115. Alternatively, power stage circuitry 120 may be modified to receive current from input stage circuitry 105.

[0034] Transistor 125 has a first terminal, a second terminal and a control terminal. The first terminal of transistor 125 is coupled to capacitors 130, 155, transistor 150 and the output terminal of amplifier circuit system 100. The second terminal of transistor 125 is coupled to a common terminal for supplying a common potential (e.g., ground, AVSS, etc.). The control terminal of transistor 125 is coupled to driver circuit system 115, capacitor 130 and transistors 135, 145, 175. In some instances, transistor 125 is referred to as a low-side field effect transistor (FET). In such instances, driver circuit system 115 uses a low-side control signal to control transistor 125.

[0035] Capacitor 130 has a first terminal and a second terminal. The first terminal of capacitor 130 is coupled to driver circuitry 115 and transistors 125, 145. The second terminal of capacitor 130 is coupled to transistors 125, 150, 175, capacitor 155, and an output terminal of amplifier circuitry 100. Figure 1In examples of, capacitor 130 represents a Miller capacitance between the terminals of transistor 125. In some examples, capacitor 130 is illustrated or described as a non-ideal (eg, parasitic) capacitance. In other examples, capacitor 130 may not be illustrated.

[0036] Transistor 135 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 135 is coupled to driver circuitry 115, transistors 125, 145, 175, and capacitor 130. The second terminal of transistor 135 is coupled to a common terminal that supplies a common potential. The control terminal of transistor 135 is coupled to input stage circuitry 105 that supplies a second bias voltage (Bias2). Figure 1 In the example of , transistor 135 is configured to sink current from transistors 125, 145 and capacitor 130. In this example, transistor 135 adjusts the slew rate of transistor 125 by sinking current from capacitor 130. Advantageously, adjusting the second bias voltage adjusts the slew rate of transistor 125 by compensating capacitor 130 with excess charge.

[0037] The voltage source circuit system 140 has a first terminal and a second terminal. The first terminal of the voltage source circuit system 140 is coupled to the transistor 145. The second terminal of the voltage source circuit system 140 is coupled to a common terminal for supplying a common potential. Figure 1 In some examples, voltage source circuitry 140 is configured as bias circuitry that ensures transistor 145 is in an operational state (e.g., conducting current). Transistor 145 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 145 is coupled to driver circuitry 115, transistors 150, 170, 175, and capacitor 155. The second terminal of transistor 145 is coupled to driver circuitry 115, transistors 125, 135, 175, and capacitor 130. The control terminal of transistor 145 is coupled to voltage source circuitry 140. In some examples, transistor 145 is configured as common-mode regulation circuitry that regulates the common-mode voltage (V CM ). Alternatively, voltage source circuitry 140 and transistor 145 may be removed or replaced by alternative circuitry.

[0038] Transistor 150 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 150 is coupled to a power supply terminal for supplying a power supply voltage (VDD). The second terminal of transistor 150 is coupled to transistor 125, capacitors 130, 155, and an output terminal of amplifier circuit system 100. The control terminal of transistor 150 is coupled to driver circuit system 115, transistors 145, 170, 175, and capacitor 155. In some examples, transistor 150 is referred to as a high-side field effect transistor (FET). In such examples, driver circuit system 115 controls transistor 150 using a high-side control signal.

[0039] Capacitor 155 has a first terminal and a second terminal. The first terminal of capacitor 155 is coupled to transistors 125, 150, capacitor 130, and the output terminal of amplifier circuitry 100. The second terminal of capacitor 155 is coupled to driver circuitry 115 and transistors 145, 150, 170, 175. Figure 1 In examples of, capacitor 155 represents the Miller capacitance between the terminals of transistor 150. In some examples, capacitor 155 is illustrated or described as a non-ideal (eg, parasitic) capacitance. In other examples, capacitor 155 may not be illustrated.

[0040] Transistor 160 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 160 is coupled to transistors 165 and 170. The second terminal of transistor 160 is coupled to a common terminal for supplying a common potential. The control terminal of transistor 160 is coupled to input stage circuit system 105 for supplying a first bias voltage (Bias1). Figure 1 In the example of , transistor 160 is configured to sink current from transistor 165 in response to a first bias voltage.

[0041] Transistor 165 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 165 is coupled to a power supply terminal for supplying a power supply voltage. The second terminal and the control terminal of transistor 165 are coupled to transistors 160, 170. Transistor 170 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 170 is coupled to a power supply terminal for supplying a power supply voltage. The second terminal of transistor 170 is coupled to driver circuitry 115, transistors 145, 150, 175, and capacitor 155. The control terminal of transistor 170 is coupled to transistors 160, 165.

[0042] exist Figure 1In the example of , transistors 165, 170 are configured as current mirror circuitry that mirrors the current sunk by transistor 160. Alternatively, power stage circuitry 120 can be modified to remove transistors 165, 170 or replace the transistors with alternative current mirror circuitry or current source circuitry. Advantageously, transistor 170 supplies a current proportional to the current through transistor 160 to transistors 145, 150 and capacitor 155. Advantageously, adjusting the first bias voltage adjusts the slew rate of transistor 150 by compensating capacitor 155 for excess charge.

[0043] Transistor 175 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 175 is coupled to driver circuitry 115, transistors 125, 135, 145, and capacitor 130. The second terminal of transistor 175 is coupled to driver circuitry 115, transistors 145, 150, 170, and capacitor 155. The control terminal of transistor 175 is coupled to voltage source circuitry 180. Voltage source circuitry 180 has a first terminal and a second terminal. The first terminal of voltage source circuitry 180 is coupled to a power supply terminal that supplies a power supply voltage. The second terminal of voltage source circuitry 180 is coupled to transistor 175.

[0044] exist Figure 1 In the example of , transistors 125, 145 are n-channel metal oxide semiconductor field effect transistors (MOSFETs). Alternatively, transistors 125, 145 may be n-channel field effect transistors (FETs), n-channel insulated gate bipolar transistors (IGBTs), n-channel junction field effect transistors (JFETs), NPN bipolar junction transistors (BJTs), or p-type equivalent devices with slight modifications. Figure 1 In the example of , transistors 135, 160 are NPN BJTs. Alternatively, transistors 135, 160 may be n-channel MOSFETs, n-channel FETs, n-channel IGBTs, n-channel JFETs, or p-type equivalent devices with slight modifications. Figure 1In the example of , transistors 150, 165, 170, 175 are p-channel MOSFETs. Alternatively, transistors 150, 165, 170, 175 may be p-channel FETs, p-channel IGBTs, p-channel JFETs, PNP BJTs, or N-type equivalent devices with slight modifications. Transistors 125, 135, 145, 150, 160, 165, 170, 175 may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 125, 135, 145, 150, 160, 165, 170, 175 may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0045] In an example operation, the input stage circuit system 105 receives a first input and a second input from an external circuit system. The input stage circuit system 105 generates a first intermediate signal path output and a second intermediate signal path output in response to the first input and the second input. The driver circuit system 115 generates a high-side control signal and a low-side control signal based on the first intermediate signal path output and the second intermediate signal path output. The power stage circuit system 120 generates the output of the amplifier circuit system 100 by controlling the transistor 150 using the high-side control signal and controlling the transistor 125 using the low-side control signal.

[0046] In such example operation, input stage circuitry 105 generates a first bias voltage and a second bias voltage in response to determining a transient at a first input and a second input of amplifier circuitry 100. Power stage circuitry 120 uses the first bias voltage to control transistor 160. Transistors 165, 170 mirror the current through transistor 160 to supply current to transistor 150, which compensates for excess charge of capacitor 155. Power stage circuitry 120 uses the second bias voltage to control transistor 135, which sinks current from transistor 125 and compensates for excess charge of capacitor 130. Advantageously, the first bias voltage and the second bias voltage control the supply of current to and from capacitors 130, 155, thereby adjusting the slew rate of amplifier circuitry 100. Advantageously, supplying current to transistor 150 increases the slew rate of a falling edge at the output of amplifier circuitry 100. Advantageously, sinking current from transistor 125 increases the slew rate of a rising edge at the output of amplifier circuitry 100. Example operations of input stage circuitry 105 to generate intermediate signal path outputs and bias voltages are described further below.

[0047] Figure 2 is a block diagram of an example input stage circuit system 200, the example input stage circuit system 200 is Figure 1An example of input stage circuit system 105 is shown in FIG. Figure 2 In the example, the input stage circuit system 200 includes a first transistor 205, a second transistor 210, a first current source circuit system 215, an input transistor circuit system 220, a bias circuit system 225, a feedback circuit system 230, a second current source circuit system 235, a slew assist circuit system 240 and a current mirror circuit system 245. Figure 2 The example input stage circuitry 200 is configured to be coupled to external circuitry that supplies a first input and a second input and Figure 1 The output stage circuit system 110 is provided.

[0048] Transistor 205 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 205 is configured to be coupled to an external circuit system that supplies a first input. The second terminal of transistor 205 is coupled to input transistor circuit system 220, slew boost feedback circuit system, and slew assist circuit system 240. The control terminal of transistor 205 is coupled to transistor 210, feedback circuit system 230, slew assist circuit system 240, and may be coupled to a common mode regulator circuit system that regulates the common mode voltage (V CM ).

[0049] Transistor 210 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 210 is configured to be coupled to an external circuit system that supplies a second input. The second terminal of transistor 210 is coupled to input transistor circuit system 220, feedback circuit system 230, and slewing assist circuit system 240. The control terminal of transistor 210 is coupled to transistor 205, feedback circuit system 230, slewing assist circuit system 240, and may be coupled to a common-mode regulator circuit system that regulates the common-mode voltage of input stage circuit system 200.

[0050] The current source circuitry 215 has a terminal coupled to the input transistor circuitry 220. Figure 3 , 4 , 5 and 6 illustrate and describe an example of current source circuit system 215. Figure 2 In an example of , the current source circuit system 215 is configured to supply a fixed current (also referred to as a tail current). In such an example, the tail current has a magnitude that shortens the small signal settling time by reducing the overshoot caused by the high-side control signal and the low-side control signal.

[0051] Input transistor circuitry 220 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal of input transistor circuitry 220 is coupled to current source circuitry 215. The second terminal of input transistor circuitry 220 is coupled to transistor 205, feedback circuitry 230, and slewing assist circuitry 240. The third terminal of input transistor circuitry 220 is coupled to transistor 210, feedback circuitry 230, and slewing assist circuitry 240. The fourth and fifth terminals of input transistor circuitry 220 are configured to be coupled to Figure 1 The driver circuit system 115, or more generally coupled to the output stage circuit system 110. Figure 2 In the example of , the input transistor circuit system 220 generates an intermediate signal path output based on the first input and the second input of the input stage circuit system 200. Figure 3 and 5 An example of input transistor circuitry 220 is illustrated and described.

[0052] The bias circuitry 225 has a terminal coupled to the rotary boost feedback circuitry. Figure 2 In the example of , bias circuit system 225 is configured to bias feedback circuit system 230. In such an example, bias circuit system 225 ensures that feedback circuit system 230 is in an operational state regardless of steady-state conditions. Figure 3 , 5 Examples of bias circuitry 225 are illustrated and described in FIGS.

[0053] Feedback circuit system 230 has a first terminal, a second terminal, a third terminal, a fourth terminal and a fifth terminal. The first terminal of feedback circuit system 230 is coupled to transistor 205, input transistor circuit system 220 and slew assist circuit system 240. The second terminal of feedback circuit system 230 is coupled to transistor 210, input transistor circuit system 220 and slew assist circuit system 240. The third terminal of feedback circuit system 230 is coupled to transistors 205, 210, slew assist circuit system 240, and can be coupled to a common-mode regulator circuit system, which regulates the common-mode voltage of input stage circuit system 200. The fourth terminal of feedback circuit system 230 is coupled to bias circuit system 225. The fifth terminal of feedback circuit system 230 is coupled to current source circuit system 235. Figure 3 , 5 An example of feedback circuit system 230 is illustrated and described in FIGS.

[0054] The current source circuit system 235 has a first terminal and a second terminal. The first terminal of the current source circuit system 235 is coupled to the feedback circuit system 230. The second terminal of the current source circuit system 235 is coupled to the swing assist circuit system 240. Figure 2 In the example of , the current source circuit system 235 is configured to supply the slewing assist current to the slewing assist circuit system 240 based on the feedback circuit system 230. Figure 3 , 5 An example of current source circuit system 235 is illustrated and described in FIGS.

[0055] The slewing assist circuit system 240 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal and a sixth terminal. The first terminal of the slewing assist circuit system 240 is coupled to the transistor 205, the input transistor circuit system 220 and the feedback circuit system 230. The second terminal of the slewing assist circuit system 240 is coupled to the transistor 210, the input transistor circuit system 220 and the feedback circuit system 230. The third terminal of the slewing assist circuit system 240 is coupled to the transistors 205, 210, and can be coupled to the common-mode regulator circuit system, which regulates the common-mode voltage of the input stage circuit system 200. The fourth terminal and the fifth terminal of the slewing assist circuit system 240 are coupled to the current mirror circuit system 245. Figure 3 , 5 6 illustrate and describe an example of the swing assist circuit system 240.

[0056] The current mirror circuit system 245 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal and the second terminal of the current mirror circuit system 245 are coupled to the slewing assist circuit system 240. The third terminal and the fourth terminal of the current mirror circuit system 245 are configured to be coupled to Figure 1 The power stage circuit system 120, or more generally coupled to the output stage circuit system 110. Figure 2 In an example of , the current mirror circuit system 245 is constructed to generate a bias voltage that is coupled to a transistor (eg, Figure 1 When the control terminals of the transistors 135 and 160 are connected, the current of the rotation auxiliary circuit system 240 is mirrored. Figure 3 , 5 An example of current mirror circuit system 245 is illustrated and described in and 6.

[0057] exist Figure 2In the example of , transistors 205, 210 are n-channel MOSFETs. Alternatively, transistors 205, 210 may be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or p-type equivalent devices with slight modifications. Transistors 205, 210 may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 205, 210 may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0058] In an example operation, the input stage circuit system 200 receives a first input and a second input from an external circuit system. The input transistor circuit system 220 generates a first intermediate signal path output and a second intermediate signal path output in response to the first input and the second input. In such an example operation, the current mirror circuit system 245 generates a first bias voltage and a second bias voltage to mirror the current of the slewing assist circuit system 240. During steady-state operation (e.g., there are no transients at the first input and the second input), the slewing assist circuit system 240 directs the slewing assist current from the current source circuit system 235 away from the current mirror circuit system 245. However, during a slewing event operation (e.g., there are transients at the first input and the second input), the feedback circuit system 230 generates a feedback current that pulls down the control voltage and increases the slewing assist current of the current source circuit system 235. In addition, during the slewing event operation, the slewing assist circuit system 240 begins to supply current to the current mirror circuit system 245, which generates the first bias voltage and the second bias voltage. Advantageously, the first bias voltage and the second bias voltage represent an enhanced slew assist current of the slew assist circuit system 240 during slew event operation. Advantageously, the slew assist circuit system 240 dynamically increases the slew rate of the output stage circuit system 110 during slew event operation of the input stage circuit system 200. Figure 7 An example operation of input stage circuitry 200 is further described.

[0059] Figure 3 is a schematic diagram of an example input stage circuit system 300, the example input stage circuit system 300 is Figure 1 and 2 Another example of an input stage circuit system 105, 200. Figure 3 In the example, the input stage circuit system 300 includes a first transistor 302, a second transistor 304, a first current source circuit system 306, an input transistor circuit system 308, a bias circuit system 310, a feedback circuit system 312, a second current source circuit system 314, a slew assist circuit system 316 and a current mirror circuit system 318. Figure 3The example input transistor circuitry 308 includes a third example transistor 320 , a fourth example transistor 322 , a fifth example transistor 324 , and a sixth example transistor 326 . Figure 3 The example bias circuitry 310 includes a third example current source circuitry 328 , a seventh example transistor 330 , and a first example resistor 332 . Figure 3 The example feedback circuit system 312 includes an eighth example transistor 334, a second example resistor 336, a ninth example transistor 338, a third example resistor 340, a fourth example current source circuit system 342, an example capacitor 344, a tenth example transistor 346, a fourth example resistor 348, a fifth example resistor 350, an eleventh example transistor 352, a twelfth example transistor 354, a sixth example resistor 356, a thirteenth example transistor 358 and a fourteenth example transistor 360. Figure 3 The example current source circuitry 314 includes a seventh example resistor 362 and a fifteenth example transistor 364 . Figure 3 The example slewing assist circuit system 316 includes a sixteenth example transistor 366 , a seventeenth example transistor 368 , an eighteenth example transistor 370 , a nineteenth example transistor 372 , a twentieth example transistor 374 , and a twenty-first example transistor 376 . Figure 3 The example current mirror circuitry 318 includes a twenty-second example transistor 378 and a twenty-third example transistor 380 .

[0060] Transistor 302 is coupled to transistor 304, input transistor circuitry 308, feedback circuitry 312, slew assist circuitry 316, and may be coupled to external circuitry that supplies a first input. Transistor 302 is Figure 2 304 is coupled to transistor 302, input transistor circuitry 308, feedback circuitry 312, slew assist circuitry 316, and may be coupled to external circuitry that supplies a second input. Transistor 304 is Figure 2 An example of transistor 210 .

[0061] The current source circuit system 306 is coupled to the input transistor circuit system 308 and the power supply terminal that supplies the power supply voltage. The current source circuit system 306 is Figure 2 The input transistor circuit system 308 is coupled to the transistors 302, 304, the feedback circuit system 312, the slew assist circuit system 316, and is configured to couple to Figure 1 The output stage circuit system 110. The input transistor circuit system 308 is Figure 2 An example of input transistor circuitry 220 .

[0062] The bias circuit system 310 is coupled to the feedback circuit system 312, a power supply terminal for supplying a power supply voltage, and a common terminal for supplying a common potential. Figure 2 2. The feedback circuit system 312 is coupled to the transistors 302, 304, the input transistor circuit system 308, the bias circuit system 310, the current source circuit system 314 and the slew assist circuit system 316. The feedback circuit system 312 is Figure 2 An example of feedback circuit system 230.

[0063] Current source circuitry 314 is coupled to feedback circuitry 312 and slew assist circuitry 316. Current source circuitry 314 is Figure 2 The slewing assist circuit system 316 is coupled to the transistors 302, 304, the input transistor circuit system 308, the feedback circuit system 312, the current source circuit system 314, the current mirror circuit system 318 and the common terminal for supplying a common potential. The slewing assist circuit system 316 is Figure 2 The current mirror circuit system 318 is coupled to the slewing assist circuit system 316, the common terminal for supplying a common potential, and is configured to be coupled to the output stage circuit system 110. The current mirror circuit system 318 is Figure 2 An example of a current mirror circuit system 245.

[0064] Transistor 320 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of transistor 320 is coupled to current source circuitry 306 and transistor 324. The second terminal of transistor 320 is coupled to transistor 322. The third terminal (also referred to as the body terminal) of transistor 320 is coupled to transistor 324 and may be coupled to a common-mode regulator circuitry that regulates the common-mode voltage (V CM ). The control terminal of transistor 320 is coupled to transistors 302, 322, feedback circuit system 312, and slewing assist circuit system 316. Transistor 322 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 322 is coupled to transistor 320. The second terminal of transistor 322 is configured to be coupled to Figure 1 The driver circuit system 115 of the embodiment of the present invention is coupled to the output stage circuit system 110, or more generally to the output stage circuit system 110. The control terminal of transistor 322 is coupled to transistors 302, 320, feedback circuit system 312 and slew assist circuit system 316. Transistors 320, 322 are configured to generate a first intermediate signal path output based on a first input at transistor 302.

[0065] Transistor 324 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of transistor 324 is coupled to current source circuitry 306 and transistor 320. The second terminal of transistor 324 is coupled to transistor 326. The third terminal (also referred to as the body terminal) of transistor 324 is coupled to transistor 320 and may be coupled to a common-mode regulator circuitry that regulates the common-mode voltage (V CM ). A control terminal of transistor 324 is coupled to transistors 304, 326, feedback circuitry 312, and slewing assist circuitry 316. Transistor 326 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 326 is coupled to transistor 324. The second terminal of transistor 326 is configured to be coupled to driver circuitry 115, or more generally to output stage circuitry 110. The control terminal of transistor 326 is coupled to transistors 304, 324, feedback circuitry 312, and slewing assist circuitry 316. Transistors 324, 326 are configured to generate a second intermediate signal path output based on a second input at transistor 304.

[0066] The current source circuit system 328 has a first terminal and a second terminal. The first terminal of the current source circuit system 328 is coupled to a power supply terminal that supplies a power supply voltage. The second terminal of the current source circuit system 328 is coupled to the feedback circuit system 312 and the transistor 330. The transistor 330 has a first terminal, a second terminal, and a control terminal. The first terminal and the control terminal of the transistor 330 are coupled to the feedback circuit system 312 and the current source circuit system 328. The second terminal of the transistor 330 is coupled to the resistor 332. The resistor 332 has a first terminal and a second terminal. The first terminal of the resistor 332 is coupled to the transistor 330. The second terminal of the resistor 332 is coupled to the common terminal that supplies a common potential. In some examples, the resistor 332 is constructed as a current limiting resistor that limits the current flowing through the transistor 330. In Figure 3 In the example of , transistor 330 biases feedback circuitry 312 by generating a control voltage at a control terminal of transistor 330 that is proportional to the current from current source circuitry 328 .

[0067] Transistor 334 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 334 is coupled to current source circuitry 314, transistors 338, 346, current source circuitry 342, and capacitor 344. The second terminal of transistor 334 is coupled to resistor 336 and transistor 360. The control terminal of transistor 334 is coupled to bias circuitry 310 and transistor 338. Resistor 336 has a first terminal and a second terminal. The first terminal of resistor 336 is coupled to transistors 334, 360. The second terminal of resistor 336 is coupled to a common terminal for supplying a common potential. Figure 3 In the example of , resistor 336 is configured to control transistor 334 in response to current from transistor 360 .

[0068] Transistor 338 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 338 is coupled to current source circuitry 314, transistors 334, 346, current source circuitry 342, and capacitor 344. The second terminal of transistor 338 is coupled to resistor 340 and transistor 354. The control terminal of transistor 338 is coupled to bias circuitry 310 and transistor 334. Resistor 340 has a first terminal and a second terminal. The first terminal of resistor 340 is coupled to transistors 338, 354. The second terminal of resistor 340 is coupled to a common terminal for supplying a common potential. Figure 3 In the example of , resistor 340 is configured to control transistor 338 in response to current from transistor 354 .

[0069] The current source circuit system 342 has a first terminal and a second terminal. The first terminal of the current source circuit system 342 is coupled to a power supply terminal that supplies a power supply voltage. The second terminal of the current source circuit system 342 is coupled to the current source circuit system 314, transistors 334, 338, 346, and capacitor 344. Capacitor 344 has a first terminal and a second terminal. The first terminal of the capacitor 344 is coupled to the power supply terminal that supplies the power supply voltage. The second terminal of the capacitor 344 is coupled to the current source circuit system 314, 342, and transistors 334, 338, 346. In some examples, the current source circuit system 342 and the capacitor 344 are configured as a pull-up circuit system that pulls up a voltage to control the current source circuit system 314 and the transistor 346. In such examples, adjusting the current from the current source circuit system 342 or the capacitance of the capacitor 344 adjusts the duration of the current source circuit system 314 supplying the enhanced slewing assist current.

[0070] Transistor 346 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 346 is coupled to resistor 348. The second terminal of transistor 346 is coupled to resistors 350, 356. The control terminal of transistor 346 is coupled to current source circuitry 314, 342, transistors 334, 338, and capacitor 344. Resistor 348 has a first terminal and a second terminal. The first terminal of resistor 348 is coupled to a power supply terminal that supplies a power supply voltage. The second terminal of resistor 348 is coupled to transistor 346. In some examples, transistor 346 and resistor 348 are configured as current source circuitry that supplies current to resistors 350, 356 in response to a voltage at the control terminal of transistor 346. In such examples, resistor 348 is configured as current limiting circuitry that controls the current through transistor 346.

[0071] Resistor 350 has a first terminal and a second terminal. The first terminal of resistor 350 is coupled to transistor 346 and resistor 356. The second terminal of resistor 350 is coupled to transistor 352. Transistor 352 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of transistor 352 is coupled to resistor 350. The second terminal of transistor 352 is coupled to transistor 354. The third terminal (also referred to as the body terminal) of transistor 352 is coupled to transistors 302, 304, 358, and slewing assist circuitry 316. The control terminal of transistor 352 is coupled to transistors 302, 354, input transistor circuitry 308, and slewing assist circuitry 316. Transistor 354 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 354 is coupled to transistor 352. The second terminal of transistor 354 is coupled to transistor 338 and resistor 340. The control terminal of transistor 354 is coupled to transistors 302, 352, input transistor circuitry 308, and slew assist circuitry 316. Figure 3 In the example of , the resistor 350 and the transistors 352 , 354 are configured to form a first current path for a feedback current based on the transistor 302 .

[0072] Resistor 356 has a first terminal and a second terminal. The first terminal of resistor 356 is coupled to transistor 346 and resistor 350. The second terminal of resistor 356 is coupled to transistor 358. Transistor 358 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of transistor 358 is coupled to resistor 356. The second terminal of transistor 358 is coupled to transistor 360. The third terminal (also referred to as the body terminal) of transistor 358 is coupled to transistors 302, 304, and slewing assist circuitry 316. The control terminal of transistor 358 is coupled to transistors 304, 360, input transistor circuitry 308, and slewing assist circuitry 316. Transistor 360 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 360 is coupled to transistor 358. The second terminal of transistor 360 is coupled to transistor 334 and resistor 336. The control terminal of transistor 360 is coupled to transistors 304, 358, input transistor circuitry 308, and slew assist circuitry 316. Figure 3 In the example of , resistor 356 and transistors 358 , 360 are configured to form a second current path for the feedback current based on transistor 304 .

[0073] Resistor 362 has a first terminal and a second terminal. The first terminal of resistor 362 is coupled to a power supply terminal that supplies a power supply voltage. The second terminal of resistor 362 is coupled to transistor 364. Transistor 364 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 364 is coupled to resistor 362. The second terminal of transistor 364 is coupled to slewing assist circuit system 316. The control terminal of transistor 364 is coupled to feedback circuit system 312.

[0074] Transistor 366 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of transistor 366 is coupled to current source circuitry 314 and transistor 370. The second terminal of transistor 366 is coupled to transistors 368, 376. The third terminal (also referred to as the body terminal) of transistor 366 is coupled to transistors 302, 304, 370, and feedback circuitry 312. The control terminal of transistor 366 is coupled to transistors 302, 368, 374, input transistor circuitry 308, and feedback circuitry 312. Transistor 368 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 368 is coupled to transistors 366, 376. The second terminal of transistor 368 is coupled to current mirror circuitry 318. The control terminal of transistor 368 is coupled to transistors 302, 366, 374, input transistor circuitry 308, and feedback circuitry 312. In Figure 3 In the example of , transistors 366 , 368 are configured to form a first current path for a slewing auxiliary current based on transistor 302 .

[0075] Transistor 370 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of transistor 370 is coupled to current source circuitry 314 and transistor 366. The second terminal of transistor 370 is coupled to transistors 372, 374. The third terminal (also referred to as the body terminal) of transistor 370 is coupled to transistors 302, 366, input transistor circuitry 308, and feedback circuitry 312. The control terminal of transistor 370 is coupled to transistors 304, 372, 376, input transistor circuitry 308, and feedback circuitry 312. Transistor 372 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 372 is coupled to transistors 370, 374. The second terminal of transistor 372 is coupled to current mirror circuitry 318. The control terminal of transistor 372 is coupled to transistors 304, 370, 376, input transistor circuitry 308, and feedback circuitry 312. In Figure 3 In the example of , transistors 370 , 372 are configured to form a second current path for a slewing auxiliary current based on transistor 304 .

[0076] Transistor 374 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 374 is coupled to transistors 370, 372. The second terminal of transistor 374 is coupled to a common terminal for supplying a common potential. The control terminal of transistor 374 is coupled to transistors 302, 366, 368, input transistor circuitry 308, and feedback circuitry 312. Figure 3 In the example of , transistor 374 is configured to adjust the second current path of the slewing auxiliary current to direct the current based on transistor 302 away.

[0077] Transistor 376 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 376 is coupled to transistors 366, 368. The second terminal of transistor 376 is coupled to a common terminal that supplies a common potential. The control terminal of transistor 376 is coupled to transistors 304, 370, 372, input transistor circuitry 308, and feedback circuitry 312. Figure 3 In the example of , transistor 376 is configured to adjust the first current path of the slewing assist current to direct the current based on transistor 304 away.

[0078] Transistor 378 has a first terminal, a second terminal, and a control terminal. The first terminal and the control terminal of transistor 378 are coupled to the swing assist circuit system 316 and are configured to couple to Figure 1 transistor 160, or more generally coupled to Figure 1The power stage circuit system 120, or even more generally coupled to the output stage circuit system 110. The second terminal of the transistor 378 is coupled to the common terminal for supplying a common potential. Figure 3 In an example of , transistor 378 generates a first bias voltage in response to current from slewing assist circuitry 316. In such an example, transistor 378 is configured to control transistor 160, which sinks a current proportional to the current through transistor 378 in response to the first bias voltage.

[0079] Transistor 380 has a first terminal, a second terminal, and a control terminal. The first terminal and the control terminal of transistor 380 are coupled to the swing assist circuit system 316 and are configured to couple to Figure 1 The transistor 135 is coupled to the power stage circuit system 120, or more generally to the output stage circuit system 110. The second terminal of the transistor 378 is coupled to the common terminal for supplying a common potential. Figure 3 In an example of, transistor 380 generates a second bias voltage in response to current from slewing assist circuitry 316. In such an example, transistor 380 is configured to control transistor 135, which sinks a current proportional to the current through transistor 380 in response to the second bias voltage.

[0080] exist Figure 3 In the example of , transistors 302, 304 are n-channel MOSFETs. Alternatively, transistors 302, 304 may be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or p-type equivalent devices with slight modifications. Figure 3 In the example of , transistors 320, 322, 324, 326, 346, 352, 354, 358, 360, 364, 366, 368, 370, 372, 374, 376 are p-channel MOSFETs. Alternatively, transistors 320, 322, 324, 326, 346, 352, 354, 358, 360, 364, 366, 368, 370, 372, 374, 376 may be p-channel FETs, p-channel IGBTs, p-channel JFETs, PNP BJTs, or n-type equivalent devices with slight modifications. Figure 3In the example of FIG. 1 , transistors 330 , 334 , 338 , 378 , 380 are NPN BJTs. Alternatively, transistors 330 , 334 , 338 , 378 , 380 may be n-channel MOSFETs, n-channel FETs, n-channel IGBTs, n-channel JFETs, or p-type equivalent devices with slight modifications. Transistors 302 , 304 , 320 , 322 , 324 , 326 , 330 , 334 , 338 , 346 , 352 , 354 , 358 , 360 , 364 , 366 , 368 , 370 , 372 , 374 , 376 , 378 , 380 may be depletion mode devices, drain extension devices, enhancement mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 302, 304, 320, 322, 324, 326, 330, 334, 338, 346, 352, 354, 358, 360, 364, 366, 368, 370, 372, 374, 376, 378, 380 may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0081] In example operation, transistors 302, 304 receive one of a first input or a second input. Transistors 320, 322 generate a first intermediate signal path output in response to the first input at transistor 302, and transistors 324, 326 generate a second intermediate signal path output in response to the second input at transistor 304. During steady-state operation (e.g., no transients at transistors 302, 304), current source circuitry 342 and capacitor 344 pull up control terminals of transistors 346, 364, thereby reducing feedback current and slewing assist current. In such example operation, transistors 368, 370, 374, 376 implement a minimum selector control that uses transistors 374, 376 to sink slewing assist current and reduce any current flowing to transistors 378, 380. Advantageously, during steady-state operation, feedback circuitry 312 configures current source circuitry 314 to supply a reduced slewing assist current. In addition, the slewing assist circuit system 316 further reduces the slewing assist current supply to the current mirror circuit system 318 by implementing a minimum selector bias for transistors 374, 376. In such an example, transistors 374, 376 have a cascode bias resulting from the size of transistors 374, 376 relative to transistors 368, 372. Advantageously, when transistors 374, 376 are conducting current, the cascode bias of transistors 368, 372, 374, 376 reduces the current through transistors 368, 372. Figure 7 Such cascode biasing is further described.

[0082] In other example operations, during a slew event operation (e.g., a transient at transistors 302, 304), a transient input configuration passes through one of the first feedback current paths or the second feedback current paths of transistors 352, 354, 358, 360. One of the first feedback current or the second feedback current turns off one of transistors 334, 338 and fully turns on the other of transistors 334, 338. The other of transistors 334, 338 pulls down the control terminal of transistors 346, 364 to increase the feedback current and the slew assist current. In addition, the transient input configuration passes through one of the first slew assist current paths or the second slew assist current paths of transistors 366, 368, 370, 372. One of the first slew assist current paths or the second slew assist current paths that supplies an enhanced slew assist current to one of transistors 378, 380 is referred to as a preferred path. One of transistors 378, 380 coupled to the preferred path generates a bias voltage that increases the slew rate of amplifier circuit system 100. Advantageously, the slewing assist circuit system 316 dynamically supplies an enhanced slewing assist current to the current mirror circuit system 318 during the slewing event operation. Figure 7 An example operation of input stage circuitry 300 is further described.

[0083] Figure 4 is a block diagram of an example input stage circuit system 400, which is Figure 1 , 2 3 and 105. In yet another example of the input stage circuit system 105, 200, 300. Figure 4 In the example of , the input stage circuit system 400 includes: Figure 2 transistors 205, 210; Figure 2 Current source circuit systems 215, 235; Figure 2 Input transistor circuit system 220; Figure 2 Bias circuit system 225; Figure 2 Feedback circuit system 230; Figure 2 A swing auxiliary circuit system 240; Figure 2 a current mirror circuit system 245; and a clamp circuit system 410. Figure 4 The example input stage circuitry 400 is configured to be coupled to external circuitry that supplies a first input and a second input and Figure 1 The output stage circuit system 110 is provided.

[0084] exist Figure 4In the example of , the feedback circuit system 230 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and may be constructed to have a sixth terminal. The first terminal of the feedback circuit system 230 is coupled to the transistor 205, the input transistor circuit system 220, and the slew assist circuit system 240. The second terminal of the feedback circuit system 230 is coupled to the transistor 210, the input transistor circuit system 220, and the slew assist circuit system 240. The third terminal of the feedback circuit system 230 is coupled to the transistors 205, 210, the slew assist circuit system 240, and may be coupled to a common-mode regulator circuit system that regulates the common-mode voltage of the input stage circuit system 200. The fourth terminal of the feedback circuit system 230 is coupled to the bias circuit system 225. The fifth terminal of the feedback circuit system 230 is coupled to the current source circuit system 235. The sixth terminal of the feedback circuit system 230 is coupled to the current mirror circuit system 245. In combination Figure 3 , 5 An example of feedback circuit system 230 is illustrated and described in FIGS.

[0085] exist Figure 4 In the example of , the slewing assist circuit system 240 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, a seventh terminal and an eighth terminal. The first terminal of the slewing assist circuit system 240 is coupled to the transistor 205, the input transistor circuit system 220 and the feedback circuit system 230. The second terminal of the slewing assist circuit system 240 is coupled to the transistor 210, the input transistor circuit system 220 and the feedback circuit system 230. The third terminal of the slewing assist circuit system 240 is coupled to the transistors 205, 210, and can be coupled to the common-mode regulator circuit system, which regulates the common-mode voltage of the input stage circuit system 200. The fourth terminal and the fifth terminal of the slewing assist circuit system 240 are coupled to the current mirror circuit system 245, and can be coupled to the clamp circuit system 410. The seventh terminal and the eighth terminal of the slewing assist circuit system 240 are coupled to the clamp circuit system 410. In combination Figure 3 , 5 6 illustrate and describe an example of the swing assist circuit system 240.

[0086] exist Figure 4 In the example of , the current mirror circuit system 245 has a first terminal, a second terminal, a third terminal, a fourth terminal, and may have a fifth terminal. The first terminal and the second terminal of the current mirror circuit system 245 are coupled to the slewing assist circuit system 240, and may be coupled to the clamp circuit system 410. The third terminal and the fourth terminal of the current mirror circuit system 245 are configured to be coupled to Figure 1The power stage circuit system 120, or more generally coupled to the output stage circuit system 110. The fifth terminal of the current mirror circuit system 245 is coupled to the feedback circuit system 230. Figure 3 , 5 An example of current mirror circuitry 245 is illustrated and described in FIGS.

[0087] The clamp circuit system 410 has a first terminal, a second terminal, and may have a third terminal and a fourth terminal. The first terminal and the second terminal of the clamp circuit system 410 are coupled to the slewing assist circuit system 240. The third terminal and the fourth terminal of the clamp circuit system 410 are coupled to the slewing assist circuit system 240 and the current mirror circuit system 245. Figure 5 and 6 An example of clamping circuitry 410 is illustrated and described.

[0088] exist Figure 4 In the example of , transistors 205, 210 are n-channel MOSFETs. Alternatively, transistors 205, 210 may be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or p-type equivalent devices with slight modifications. Transistors 205, 210 may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 205, 210 may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0089] In an example operation, the clamp circuit system 410 generates a first clamp voltage and a second clamp voltage in response to current from the slewing assist circuit system 240. The first clamp voltage and the second clamp voltage are configured to reduce the slewing assist current supply from the slewing assist circuit system 240 to the current mirror circuit system 245. Advantageously, the clamp circuit system 410 uses the first clamp voltage and the second clamp voltage to reduce the slewing assist current supply to the current mirror circuit system 245. Advantageously, the clamp circuit system 410 is configured to clamp the slewing assist circuit system 240 using the first clamp voltage and the second clamp voltage. Figure 7 An example operation of input stage circuitry 400 is further described.

[0090] Figure 5 is a schematic diagram of an example input stage circuit system 500, the example input stage circuit system 500 is Figure 1 , 2 , 3 and 4 are another example of input stage circuit systems 105, 200, 300, 400. Figure 5 In the example of , the input stage circuit system 500 includes: Figure 3Transistors 302, 304; Figure 3 Current source circuit systems 306, 314; Figure 3 Input transistor circuit system 308; Figure 3 Bias circuit system 310; Figure 3 Feedback circuit system 312; Figure 3 A swing auxiliary circuit system 316; Figure 3 a current mirror circuit system 318; and a clamp circuit system 510. Figure 5 An example input transistor circuit system 308 includes Figure 3 Transistors 320, 322, 324, 326. Figure 5 The example bias circuitry 310 includes Figure 3 Current source circuit system 328, Figure 3 The transistor 330 and Figure 3 Resistor 332. Figure 5 The example feedback circuitry 312 includes: Figure 3 transistors 334, 338, 346, 352, 354, 358, 360; Figure 3 Resistors 336, 340, 348, 356; Figure 3 The current source circuit system 342; and Figure 3 Capacitor 344. Figure 5 The example current source circuit system 314 includes Figure 3 The resistor 362 and Figure 3 of transistor 364. Figure 5 An example swing assist circuit system 316 includes Figure 3 Transistors 366, 368, 370, 372, 374, 376. Figure 5 An example current mirror circuit system 318 includes Figure 3 Transistors 378, 380. Figure 5 The example clamp circuitry 510 includes a first example resistor 520 and a second example resistor 530 .

[0091] exist Figure 5 In the example of FIG. 5 , the slewing assist circuit system 316 is coupled to the transistors 302, 304, the input transistor circuit system 308, the feedback circuit system 312, the current source circuit system 314, the current mirror circuit system 318, and the clamp circuit system 510. The slewing assist circuit system 316 is Figure 2 and 4 The clamp circuit system 510 is coupled to the slewing assist circuit system 316 and the common terminal for supplying a common potential. The clamp circuit system 510 is Figure 4 An example of a clamping circuit system 410 is shown.

[0092] Resistor 520 has a first terminal and a second terminal. The first terminal of resistor 520 is coupled to transistor 374, or more generally to slewing assist circuitry 316. The second terminal of resistor 520 is coupled to a common terminal that supplies a common potential. Resistor 530 has a first terminal and a second terminal. The first terminal of resistor 530 is coupled to transistor 376, or more generally to slewing assist circuitry 316. The second terminal of resistor 530 is coupled to a common terminal that supplies a common potential.

[0093] In example operation, resistor 520 generates a first clamp voltage in response to current from transistor 374, and resistor 530 generates a second clamp voltage in response to current from transistor 376. In such example operation, the first clamp voltage biases transistor 374 to turn off transistor 368, and the second clamp voltage biases transistor 376 to turn off transistor 372. Advantageously, the first clamp voltage and the second clamp voltage further reduce the slewing assist current supplied to current mirror circuitry 318 by completely disabling transistors 368, 372. Figure 7 An example operation of input stage circuitry 500 is further described.

[0094] Figure 6 is a schematic diagram of an example input stage circuit system 600, the example input stage circuit system 600 is Figure 1 , 2 , 3, 4 and 5 of another example of input stage circuit system 105, 200, 300, 400, 500. Figure 6 In the example of FIG. 5 , the input stage circuit system 600 includes: Figure 3 and 5 Transistors 302, 304; Figure 3 and 5 Current source circuit systems 306, 314; Figure 3 and 5 Input transistor circuit system 308; Figure 3 and 5 Bias circuit system 310; Figure 3 and 5 Feedback circuit system 312; Figure 3 and 5 The slew assist circuit system 316; the current mirror circuit system 605; and the clamp circuit system 610. Figure 6 An example input transistor circuit system 308 includes Figure 3 and 5 Transistors 320, 322, 324, 326. Figure 6 The example bias circuitry 310 includes Figure 3 and 5Current source circuit system 328, Figure 3 and 5 The transistor 330 and Figure 3 and 5 Resistor 332. Figure 6 The example feedback circuitry 312 includes: Figure 3 and 5 transistors 334, 338, 346, 352, 354, 358, 360; Figure 3 and 5 Resistors 336, 340, 348, 356; Figure 3 and 5 The current source circuit system 342; and Figure 3 and 5 Capacitor 344. Figure 6 The example current source circuit system 314 includes Figure 3 and 5 The resistor 362 and Figure 3 and 5 of transistor 364. Figure 6 An example swing assist circuit system 316 includes Figure 3 and 5 Transistors 366, 368, 370, 372, 374, 376. Figure 6 The example current mirror circuit system 605 includes a first example transistor 615 , a second example transistor 620 , a third example transistor 625 , and a fourth example transistor 630 . Figure 6 The example clamp circuitry 610 includes a first example resistor 635 , a second example resistor 640 , a fifth example transistor 645 , a sixth example transistor 650 , a seventh example transistor 655 , and an eighth example transistor 660 .

[0095] Current mirror circuitry 605 is coupled to feedback circuitry 312, slew assist circuitry 316, clamp circuitry 610, and is configured to couple to Figure 1 The power stage circuitry 120, or more generally coupled to Figure 1 The output stage circuit system 110. The current mirror circuit system 605 is Figure 2 , 3 , 4 and 5. Clamp circuit system 610 is coupled to slew assist circuit system 316 and current mirror circuit system 605. Clamp circuit system 610 is Figure 4 and 5 Another example of a clamping circuit system 410, 510.

[0096] Transistor 615 has a first terminal, a second terminal, and a control terminal. The first terminal and the control terminal of transistor 615 are coupled to transistor 368, or more generally to slewing assist circuitry 316, clamp circuitry 610, transistor 620, and may be coupled to output stage circuitry 110. The second terminal of transistor 615 is coupled to a common terminal for supplying a common potential. Transistor 620 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 620 is coupled to transistors 334, 338, 346, or more generally to feedback circuitry 312 and transistor 630. The second terminal of transistor 620 is coupled to a common terminal for supplying a common potential. The control terminal of transistor 620 is coupled to slewing assist circuitry 316, clamp circuitry 610, transistor 615, and may be coupled to output stage circuitry 110.

[0097] Transistor 625 has a first terminal, a second terminal, and a control terminal. The first terminal and the control terminal of transistor 625 are coupled to transistor 372, or more generally to slewing assist circuitry 316, clamp circuitry 610, transistor 630, and may be coupled to output stage circuitry 110. The second terminal of transistor 625 is coupled to a common terminal for supplying a common potential. Transistor 630 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 630 is coupled to feedback circuitry 312 and transistor 620. The second terminal of transistor 630 is coupled to a common terminal for supplying a common potential. The control terminal of transistor 630 is coupled to slewing assist circuitry 316, clamp circuitry 610, transistor 625, and may be coupled to output stage circuitry 110.

[0098] Resistor 635 has a first terminal and a second terminal. The first terminal of resistor 635 is coupled to the swing assist circuit system 316 and transistors 645, 650. The second terminal of resistor 635 is coupled to a common terminal for supplying a common potential. Resistor 635 is Figure 5 Another example of a resistor 520 is shown in FIG. 6. Resistor 640 has a first terminal and a second terminal. The first terminal of resistor 640 is coupled to the swing assist circuit system 316 and transistors 655, 660. The second terminal of resistor 640 is coupled to a common terminal for supplying a common potential. Resistor 640 is Figure 5 Another example of resistor 530.

[0099] Transistor 645 has a first terminal, a second terminal, and a control terminal. The first terminal and the control terminal of transistor 645 are coupled to the slewing assist circuit system 316, the resistor 635, and the transistor 650. The second terminal of transistor 645 is coupled to the common terminal for supplying a common potential. Transistor 650 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 650 is coupled to the slewing assist circuit system 316 and the current mirror circuit system 605. The second terminal of transistor 650 is coupled to the common terminal for supplying a common potential. The control terminal of transistor 650 is coupled to the slewing assist circuit system 316, the resistor 635, and the transistor 645.

[0100] Transistor 655 has a first terminal, a second terminal, and a control terminal. The first terminal and the control terminal of transistor 655 are coupled to the slewing assist circuit system 316, the resistor 640, and the transistor 660. The second terminal of transistor 655 is coupled to the common terminal for supplying a common potential. Transistor 660 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 660 is coupled to the slewing assist circuit system 316 and the current mirror circuit system 605. The second terminal of transistor 660 is coupled to the common terminal for supplying a common potential. The control terminal of transistor 660 is coupled to the slewing assist circuit system 316, the resistor 640, and the transistor 655.

[0101] exist Figure 6 In the example of , transistors 615, 620, 625, 630, 645, 650, 655, 660 are NPN BJTs. Alternatively, transistors 615, 620, 625, 630, 645, 650, 655, 660 may be n-channel MOSFETs, n-channel FETs, n-channel IGBTs, n-channel JFETs, or p-type equivalent devices with slight modifications. Transistors 615, 620, 625, 630, 645, 650, 655, 660 may be depletion-type devices, drain-extended devices, enhancement-type devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 615, 620, 625, 630, 645, 650, 655, 660 may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0102] In example operation, transistors 620, 630 mirror the current through transistors 615, 625, which current represents the slew assist current. Transistors 620, 630 increase the speed at which feedback circuitry 312 pulls down the control terminals of transistors 346, 364. Transistors 645, 655 mirror the current through resistors 635, 640. Transistors 650, 660 sink current from slew assist circuitry 316 through resistors 635, 640. Advantageously, when current flows through resistors 635, 640, transistors 650, 660 reduce the slew assist current supplied to current mirror circuitry 605. Advantageously, transistors 650, 660 reduce the likelihood that transistors 620, 630 will use non-ideal slew assist current from slew assist circuitry 316 to pull down the control terminals of transistors 346, 364. As described below in conjunction with Figure 7 An example operation of input stage circuitry 600 is further described.

[0103] Figure 7 is a flow diagram representing example operations 700 that may be at least one of: executed, instantiated, or used Figure 1 , 2 , 3, 4, 5 and 6 of the input stage circuit system 105, 200, 300, 400, 500, 600 or more generally Figure 1 The exemplary embodiment of the amplifier circuit system 100 is implemented as shown in FIG. Figure 7 The example operation 700 begins at block 705, where Figure 2 , 3 , 4, 5, and 6 receive differential inputs to transistors 205, 210, 302, 304. (Block 705). In some examples, external circuitry supplies a first input signal and a second input signal to transistors 205, 210, 302, 304. For example, programmable circuitry can supply a pulse width modulated (PWM) signal to the first input and the second input of amplifier circuitry 100. In such examples, the PWM signal controls transistors 205, 210, 302, 304.

[0104] Figure 2 , 3, 4, 5 and 6 generate signal path outputs based on the differential inputs. (Block 710). In some instances, transistors 205, 210, 302, 304 control input transistor circuit systems 220, 308 in response to differential input signals at the inputs of amplifier circuit system 100. In such instances, transistors 320, 322 generate a first signal path output, and transistors 324, 326 generate a second signal path output. For example, when a first input signal turns on transistors 205, 302 and a second input signal turns off transistors 210, 304, transistors 320, 322 are turned off and transistors 324, 326 are turned on. In such instances, transistors 320, 322 generate a first signal path output having a logic low state, and transistors 324, 326 generate a second signal path output having a logic high state. Figure 7 In the example of , the signal from the input transistor circuitry 220, 308 is part of the input signal path responsive to the first signal path output and the second signal path output representing the received input signal.

[0105] Figure 1 The output stage circuit system 110 generates an output signal in response to the signal path output. (Block 715). In some described examples, Figure 1 The driver circuit system 115 receives the signal path output from the input stage circuit system 105. In such examples, the driver circuit system 115 generates a high-side control signal and a low-side control signal in response to the signal path output. For example, the driver circuit system 115 can be a class AB amplifier that implements AB control to generate a high-side control signal and a low-side control signal. In AB control, the high-side control signal and the low-side control signal can control the transistors 125 and 150 to be in a linear operating region (e.g., partially conducting current). This control enables the power stage circuit system 120 to generate an output signal in the form of an analog value.

[0106] Figure 2 , 3 , 4, 5 and 6 of the feedback circuit system 230, 312 and Figure 2 , 3 , 4, 5 and 6, the slewing assist circuit system 240, 316 determines whether there is a slewing event. (Block 720). In some examples, the feedback circuit system 230, 312 and the slewing assist circuit system 240, 316 switch between two operating modes. In the first operating mode (also referred to as steady-state operation), the feedback circuit system 230, 312 and the slewing assist circuit system 240, 316 have stabilized in response to the current of the transistors 205, 210, 302, 304 being a fixed value. In such steady-state operation, Figure 3The transistors 352, 354, 358, 360 are Figure 3 The resistors 336, 340 supply a fixed current, and Figure 3 The transistors 376 and 374 are Figure 2 , 3 , 4, 5 and 6 current source circuit systems 235, 314 sink current. In a second operating mode (also referred to as a slew event operation), in response to transistors 205, 210, 302, 304 receiving a transient input signal, feedback circuit systems 230, 312 and slew assist circuit systems 240, 316 transition from a first current path to a second current path. For example, a rising edge of the first input signal switches transistors 205, 302 from off to on, and a falling edge of the second input signal transitions transistors 210, 304 from on to off. Such slew event operations are further described below in conjunction with blocks 725-775.

[0107] If the feedback circuitry 230, 312 and the swing assist circuitry 240, 316 determine that there is no swing event (eg, block 720 returns a “no” result), control passes back to block 705. For example, the feedback circuitry 230, 312 and the swing assist circuitry 240, 316 remain in steady-state operation.

[0108] If the feedback circuit system 230, 312 and the slewing assist circuit system 240, 316 determine that there is a slewing event (e.g., block 720 returns a "yes" result), the feedback circuit system 230, 312 generates a feedback current using the differential input. (Block 725). In some examples, the feedback circuit system 230, 312 generates a feedback current through a first current path or a second current path. The first current path of the feedback circuit system 230, 312 is controlled by the transistor 205, 302 and flows through the resistor 340, 350 and the transistor 346, 352, 354. The second current path of the feedback circuit system 230, 312 is controlled by the transistor 210, the transistor 304 and flows through the resistor 336, 356 and the transistor 346, 358, 360. When a slew event occurs (e.g., a rising edge occurs at one input and a falling edge occurs at the other input), feedback circuit system 230, 312 generates a feedback current by turning on a transistor in one of the first current path or the second current path and turning off a transistor in the other of the first current path or the second current path. For example, when the first input signal turns off transistor 205, 302 and the second input signal turns on transistor 210, 304, transistor 352, 354 turns on and transistor 358, 360 turns off. In this example, transistor 352, 354 supplies feedback current to resistor 340.

[0109] Figure 2 ,3 , 4, 5 and 6 bias the feedback circuit system 225, 310. (Block 730). In some examples, the bias circuit system 225, 310 is constructed as a current mirror circuit system that generates a reference voltage that biases the feedback circuit system 312. For example, Figure 3 , 5 The transistor 330 of the control transistor 334, 338 injects the Figure 3 , 5 The current of the current source circuitry 328 of transistors 334, 338 is substantially equal to the current of the current source circuitry 328 of transistors 334, 338. In such examples, the bias circuitry 225, 310 ensures that the feedback circuitry 230, 312 is in an operational state responsive to the bias voltages applied to the control terminals of transistors 334, 338.

[0110] The slewing assist circuit system 240, 316 generates a slewing assist current based on the differential input. (Block 735). In some examples, the slewing assist circuit system 240, 316 generates a slewing assist current through a first current path or a second current path. The first current path of the slewing assist circuit system 240, 316 is controlled by the transistor 205, 302 and flows from the current source circuit system 235, 314 through the transistor 366, 368. The second current path of the slewing assist circuit system 240, 316 is controlled by the transistor 210, 304 and flows from the current source circuit system 235, 314 through the transistor 370, 372. When a slewing event occurs (e.g., a rising edge occurs at one input and a falling edge occurs at the other input), the slewing assist circuit system 240, 316 generates the slewing assist current by turning on the transistor of one of the first current path or the second current path and turning off the transistor of the other of the first current path or the second current path.

[0111] In addition, when the first current path is effective, transistors 205 and 302 are also turned on. Figure 3 , 5 and transistor 374 of 6, and when the second current path is effective, transistors 210, 304 are turned on Figure 3 , 5 In some examples, transistors 374, 376 are sized relatively large relative to transistors 368, 372. In such examples, transistors 374, 376 sink a multiple of any current through transistors 368, 372. This sizing of transistors 368, 372, 374, 376 reduces non-ideal currents flowing through transistors 368, 372 when they are off. In other examples, transistors 374, 376 are coupled to Figure 4 , 5 and the clamping circuit systems 410, 510, 610 of 6, Figure 5 and 6 Resistors 520, 530, 635, 640 generate a voltage that completely disables transistors 368, 372 in response to current from transistors 374, 376. In such examples, clamp circuitry 410, 510, 610 uses current from transistors 368, 372 to further reduce non-ideal current through transistors 368, 372.

[0112] Feedback circuitry 230, 312 pulls down the control voltage. (Block 740). In some examples, feedback circuitry 230, 312 uses feedback current from transistors 354, 360 to turn off one of transistors 334, 338 and fully turn on the other of transistors 334, 338. For example, when transistor 205, 302 turns on transistors 352, 354, transistors 352, 354 supply feedback current to resistor 340, which generates a voltage that reverse biases transistor 338 and turns it off. In such examples, when transistor 210, 304 turns off transistors 358, 360, bias circuitry 225, 310 causes transistor 334 to fully conduct current, which pulls down the control voltage at the control terminal of transistors 346, 364.

[0113] The feedback circuitry 230, 312 and the current source circuitry 235, 314 determine whether the control voltage is less than the threshold voltage. (Block 745). In some examples, in response to the slewing operation of the feedback circuitry 230, 312, one of the transistors 334, 338 pulls down the control voltage at the control terminal of the transistor 346, 364. In such examples, the transistor 334, 338 increases the current supplied to the feedback circuitry 230, 312 and the slewing assist circuitry 240, 316. When the feedback circuitry 230, 312 and the current source circuitry 235, 314 determine that the control voltage is not less than the threshold voltage (e.g., block 745 returns a "no" result), control proceeds to return to block 745.

[0114] When the feedback circuitry 230, 312 and the current source circuitry 235, 314 determine that the control voltage is less than the threshold voltage (e.g., block 745 returns a "yes" result), the current source circuitry 235, 314 increases the slewing assist current. (Block 750). In some examples, transistor 364 is a p-channel field effect transistor that is configured to increase the current supply to the slewing assist circuitry 240, 316 as the gate-source voltage decreases. In such examples, in response to the feedback circuitry 312 pulling down the control voltage at the control terminal of transistor 364, transistor 364 increases the current supply to the slewing assist circuitry 240, 316.

[0115] Figure 2 , 3 , 4, 5 and 6 generate a bias voltage based on the slewing assist current. (Block 755). In some examples, the current mirror circuit system 245, 318, 605 uses the slewing assist current from the transistor 368, 372 to generate a first bias voltage and a second bias voltage. In such examples, the first bias voltage is proportional to the current through the transistor 366, 368, and the second bias voltage is proportional to the current through the transistor 370, 372. For example, when the transistor 205, 302 turns on the transistor 366, 368, 374, the transistor 366, 368 turns on the transistor 370, 372. Figure 3 , 5 The transistors 378 and 615 supply the slewing assist current, which sets the first bias voltage to be proportional to the slewing assist current. In such an example, when the transistors 210 and 304 turn off the transistors 370, 372 and 376, the transistors 370 and 372 fail to supply the slewing assist current. Figure 3 , 5 The transistors 380 and 625 supply current, which sets the second bias voltage to be approximately equal to the common potential. In addition, when the transistors 205 and 302 turn on the transistor 374 and the transistors 210 and 304 turn off the transistors 370, 372, and 376, the transistor 374 reduces the non-ideal current through the transistor 372 by absorbing a relatively large portion of the non-ideal current.

[0116] Output stage circuitry 110 uses the bias voltage to increase the slew rate of the edge of the output signal. (Block 760). In some examples, power stage circuitry 120 mirrors the slew assist current in response to receiving the bias voltage from current mirror circuitry 245, 318, 605. In such examples, transistor 135 increases the slew rate of the rising edge of the output signal by sinking a replica of the current through transistor 372 from the control terminal of transistor 125 and capacitor 130. Similarly, transistors 160, 165, 170 increase the slew rate of the falling edge of the output signal by supplying a replica of the current through transistor 368 to the control terminal of transistor 150 and capacitor 155.

[0117] The feedback circuitry 230, 312 and the slewing assist circuitry 240, 316 determine whether the input currents of the differential inputs are approximately equal. (Block 765). In some examples, as the currents from the transistors 205, 210, 302, 304 begin to stabilize after the slewing event, the feedback circuitry 230, 312 and the slewing assist circuitry 240, 316 begin to approach steady-state operation. If the feedback circuitry 230, 312 and the slewing assist circuitry 240, 316 determine that the input currents of the differential inputs are not approximately equal (e.g., block 765 returns a “no” result), control proceeds back to block 765.

[0118] If the feedback circuitry 230, 312 and the slewing assist circuitry 240, 316 determine that the input currents of the differential inputs are approximately equal (e.g., block 765 returns a "yes" result), the feedback circuitry 230, 312 reduces the slewing assist current. (Block 770). In some examples, when the feedback circuitry 230, 312 is in steady-state operation, the current source circuitry 342 and the capacitor 344 pull up the control voltage at the control terminal of the transistor 364. In such examples, the feedback circuitry 230, 312 reduces the current supplied to the slewing assist circuitry 240, 316.

[0119] The slewing assist circuitry 240, 316 directs excess slewing assist current away. (Block 775). In some instances, as further described above, transistors 374, 376 are sized to be substantially larger than transistors 368, 372 to reduce excess non-ideal slewing assist current from transistors 366, 370 being supplied to current mirror circuitry 245, 318, 605. In some such instances, clamping circuitry 410, 510, 610 further prevents excess non-ideal slewing assist current by clamping slewing assist circuitry 240, 316 to a voltage that completely disables transistors 366, 370. In addition, clamping circuitry 410, 610 includes circuitry for directly absorbing excess non-ideal slewing assist current. For example, Figure 6 The transistors 645, 655 of FIG. 374 sink a current (e.g., a non-ideal current) proportional to the current from the transistors 374, 376. In such an example, Figure 6 The transistors 650, 660 sink a replica of the current through the transistors 645, 655 to further reduce the non-ideal current supplied to the current mirror circuitry 245, 318, 605. Control passes back to block 705.

[0120] Although reference Figure 7 The illustrated flowchart describes an example method, but implementations may also be used in this specification. Figure 1 , 2, 3, 4, 5 and 6 of the input stage circuit system 105, 200, 300, 400, 500, 600 or more generally Figure 1 Many other methods of the amplifier circuit system 100 are possible. For example, the execution order of the blocks can be changed, or some of the described blocks can be changed, removed, or combined. Similarly, in the manufacturing process, additional operations can be included before, between, or after the blocks shown in the illustrated example.

[0121] Figure 8 yes Figure 1 A timing diagram 800 of an example operation of the amplifier circuit system 100 is shown. Figure 8 In the example of FIG. 8 , timing diagram 800 includes a signal path boost tail current 810 and a separate slew assist path boost tail current 820. The signal path boost tail current 810 illustrates operation of an amplifier circuit system using circuit system to increase the slew rate of an output by increasing the current of the signal path. For example, the current of the signal to the driver circuit system is boosted during a slew event. The separate slew assist path boost tail current 820 illustrates operation of an amplifier circuit system using circuit system to increase the current of the signal path. Figure 2 , 3 , 4, 5 and 6 of the rotation auxiliary circuit system 240, 316 to generate a separate signal to dynamically enhance Figure 1 The slew rate of the power stage circuitry 120 affects the operation of the amplifier circuitry 100. Advantageously, the separate slew auxiliary path enhancement tail current 820 settles faster than the signal path enhancement tail current 810.

[0122] Fig. 9 yes Figure 1 A timing diagram 900 of an example operation of the amplifier circuit system 100 is shown. Fig. 9 In the example of FIG. 9 , timing diagram 900 includes a signal path boost output signal 910, a separate slew auxiliary path boost output signal 920, and an ideal output signal 930. The signal path boost output signal 910 illustrates operation of an amplifier circuit system using circuit system to increase the slew rate of the output by increasing the current of the signal path. For example, the current of the signal to the driver circuit system is increased during a slew event. The separate slew auxiliary path boost output signal 920 illustrates operation of an amplifier circuit system using circuit system to increase the current of the signal path. Figure 2 , 3 , 4, 5 and 6 of the rotation auxiliary circuit system 240, 316 to generate a separate signal to dynamically enhance Figure 1 The operation of the amplifier circuit system 100 with the slew rate of the power stage circuit system 120 is shown in FIG. The ideal output signal 930 illustrates a target output signal having a nearly instantaneous transition from a first voltage to a second voltage. Advantageously, the slew auxiliary path enhancement output signal 920 can have a greater slew rate than the signal path enhancement output signal 910.

[0123] "Include" and "comprising" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim uses any form of "include" or "comprising" (e.g., comprises, includes, comprising, including, having, etc.) as a leading phrase or within any type of claim recitation, additional elements, terms, etc. may be present without exceeding the scope of the corresponding claim or recitation. As used herein, the phrase "at least" when used as a transitional term, such as in the leading phrase of a claim, is open-ended in the same manner as the terms "include" and "comprising" are open-ended. The term "and / or" when used in the form of, for example, A, B, and / or C, refers to any combination or subset of A, B, C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" refers to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and things, the phrase "at least one of A or B" refers to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the implementation or execution of a process, instruction, action, activity, etc., the phrase "at least one of A and B" refers to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the implementation or execution of a process, instruction, action, activity, etc., the phrase "at least one of A or B" refers to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0124] As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude the plural. As used herein, the term "a" or "an" object refers to one or more of the objects. The terms "a" (or an), "one or more," and "at least one" are used interchangeably herein. In addition, although listed separately, multiple components, elements, or actions may be implemented by, for example, the same entity or object. In addition, although individual features may be included in different instances or claims, these features may be combined, and the inclusion in different instances or claims does not imply that the combination of features is not feasible and / or disadvantageous.

[0125] As used herein, unless otherwise stated, the term "above" describes the relationship of two parts relative to the earth. A first part is above a second part if the second part has at least one portion between the earth and the first part. Likewise, as used herein, a first part is "below" a second part when the first part is closer to the earth than the second part. As mentioned above, a first part can be above or below a second part, with one or more of the following: with other parts in between, without other parts in between, the first part and the second part in contact, or the first part and the second part not in direct contact with each other.

[0126] As used in this patent, stating that any part (e.g., a layer, film, region, area, or plate) is in any way located on another part (e.g., located on, positioned on, disposed on, or formed on, etc.) indicates that the referenced part is in contact with the other part, or that the referenced part is above the other part with one or more intermediate parts positioned therebetween.

[0127] As used herein, unless otherwise indicated, connection references (e.g., fit, coupled, connected, and joined) may include intermediate members between elements referenced by at least one of the connection reference or relative movement between those elements. Thus, connection references do not necessarily infer that two elements are directly connected or in fixed relation to each other. As used herein, stating that any part is "in contact with" another part is defined to mean that there are no intermediate parts between the two parts.

[0128] Unless otherwise specifically stated, descriptors such as "first", "second", "third", etc. are used herein without imposing or otherwise indicating a priority in a list, a physical order, a meaning of arrangement, or ordering in any way, but are merely used as at least one of a label or arbitrary name to distinguish elements to facilitate understanding of the described examples. In some examples, the descriptor "first" may be used to refer to an element in a specific embodiment, while the same element may be referred to in the claims by different descriptors such as "second" or "third". In such cases, such descriptors are used only to clearly identify those elements within the context of the discussion (e.g., within the claims), where the elements may, for example, otherwise share the same name.

[0129] As used herein, "substantially" and "approximately" modify the subject matter / values ​​thereof to recognize the potential for variations that occur in real-world applications. For example, "substantially" and "approximately" may modify dimensions that may not be exact due to at least one of manufacturing tolerances or other real-world imperfections. For example, unless otherwise specified herein, "substantially" and "approximately" may indicate that such dimensions may be within a tolerance range of + / - 10%.

[0130] As used herein, the phrase "communication," including variations thereof, encompasses one or a combination of direct communication or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication or constant communication, but also includes selective communication at at least one of periodic intervals, predetermined intervals, non-periodic intervals, or one-time events.

[0131] As used herein, "programmable circuitry" is defined as including at least one of: (i) one or more special-purpose circuits (e.g., application-specific circuits (ASICs)) that are constructed to perform specific operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), or (ii) one or more general-purpose semiconductor-based circuits that can be programmed with instructions to perform one or more specific functions or operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit systems include a programmable microprocessor, such as: a central processing unit (CPU), which can execute a first instruction to implement one or more operations or functions; a field programmable gate array (FPGA), which can be programmed with a second instruction to configure and / or construct the FPGA to instantiate one or more operations or functions corresponding to the first instruction; a graphics processor unit (GPU), which can execute a first instruction to implement one or more operations or functions; a digital signal processor (DSP), which can execute a first instruction to implement one or more operations or functions; an XPU; a network processing unit (NPU); one or more microcontrollers, which can execute a first instruction to implement one or more operations or functions; or an integrated circuit, such as an application specific integrated circuit (ASIC). For example, the XPU may be implemented by a heterogeneous computing system that includes multiple types of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and any combination thereof) and orchestration technology (e.g., an application programming interface (API)) that can distribute computing tasks to any one or more of the multiple types of programmable circuit systems that are suitable and available to perform computing tasks.

[0132] As used herein, an integrated circuit / circuitry is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, a programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system-on-chip (SoC), etc.

[0133] In this specification, the term "coupled" may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0134] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed by at least one of firmware or software programming of the device, by at least one of the construction or layout of the hardware components and interconnections of the device, or by a combination thereof.

[0135] As used herein, the terms "terminal", "node", "interconnect", "pin" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to the interconnection between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components or their terminations.

[0136] In the present specification and claims, a "circuitry" described may include one or more circuits. A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., one or a combination of resistors, capacitors, or inductors), or one or more sources (e.g., voltage sources and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., at least one of a semiconductor die or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements or sources at or after the manufacturing time, for example by at least one of an end user or a third party, to form the described structure.

[0137] The circuit described herein can be reconfigured to include a replacement component to provide functionality at least partially similar to the functionality available before the component replacement. Unless otherwise specified, the component shown as a resistor generally represents any one or more elements coupled in series and / or in parallel to provide the impedance amount represented by the resistor shown. For example, a resistor or capacitor shown and described as a single component in this article may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described as a single component in this article may alternatively be a plurality of resistors or capacitors coupled in series between two nodes identical to a single resistor or capacitor. Although some elements of the described examples are included in the integrated circuit and other elements are outside the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as being outside the integrated circuit may be included in the integrated circuit, and some features described as being inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are at least one of: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; or (iv) incorporated in / on the same printed circuit board.

[0138] The use of the phrase "ground" in the foregoing description includes at least one of: chassis ground, ground line ground, floating ground, virtual ground, digital ground, common ground, or any other form of ground that is applicable or suitable for the teachings of this specification. Unless otherwise stated, "about", "approximately" or "substantially" before a value means + / -10% of the value, or if the value is zero, it means a reasonable range of values ​​around zero.

[0139] Modifications may be made in the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims

1. A device comprising: a first transistor having a first terminal and a control terminal; a second transistor having a first terminal and a control terminal, the first terminal of the second transistor being coupled to the first terminal of the first transistor; a third transistor having a first terminal and a control terminal; a fourth transistor having a first terminal and a control terminal, the first terminal of the second transistor being coupled to the first terminal of the third transistor; a feedback circuit system having a first terminal, a second terminal, a third terminal, and a fourth terminal; a current source circuit system having a first terminal and a second terminal, the first terminal of the current source circuit system being coupled to the first terminal of the feedback circuit system; a slewing assist circuit system having a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal and a sixth terminal, the first terminal of the slewing assist circuit system being coupled to the control terminal of the first transistor, the control terminal of the second transistor and the second terminal of the feedback circuit system, the second terminal of the slewing assist circuit system being coupled to the control terminal of the third transistor, the control terminal of the fourth transistor and the third terminal of the feedback circuit system, the third terminal of the slewing assist circuit system being coupled to the fourth terminal of the feedback circuit system, and the fourth terminal of the slewing assist circuit system being coupled to the second terminal of the current source circuit system; as well as A current mirror circuit system has a first terminal and a second terminal, the first terminal of the current mirror circuit system is coupled to the fifth terminal of the slew assist circuit system, and the second terminal of the current mirror circuit system is coupled to the sixth terminal of the slew assist circuit system.

2. The apparatus according to claim 1, further comprising: a fifth transistor having a first terminal and a control terminal, the first terminal of the fifth transistor being coupled to the control terminal of the first transistor, the control terminal of the second transistor, the second terminal of the feedback circuitry, and the first terminal of the slew assist circuitry; as well as a sixth transistor having a first terminal and a control terminal, the first terminal of the sixth transistor being coupled to the control terminal of the third transistor, the control terminal of the fourth transistor, the third terminal of the feedback circuit system, and the second terminal of the slewing auxiliary circuit system, the control terminal of the sixth transistor being coupled to the fourth terminal of the feedback circuit system, the third terminal of the slewing auxiliary circuit system, and the control terminal of the fifth transistor.

3. The apparatus of claim 1, wherein the swing assist circuitry comprises: a fifth transistor having a first terminal, a second terminal, and a control terminal; a sixth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the sixth transistor being coupled to the first terminal of the current mirror circuitry; a seventh transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the seventh transistor being coupled to the second terminal of the current source circuitry and the first terminal of the fifth transistor; an eighth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the eighth transistor being coupled to the second terminal of the current mirror circuitry; a ninth transistor having a first terminal and a control terminal, the first terminal of the ninth transistor being coupled to the second terminal of the fifth transistor and the second terminal of the sixth transistor, the control terminal of the ninth transistor being coupled to the third terminal of the feedback circuitry, the control terminal of the seventh transistor, and the control terminal of the eighth transistor; as well as a tenth transistor having a first terminal and a control terminal, the first terminal of the tenth transistor being coupled to the second terminal of the seventh transistor and the second terminal of the eighth transistor, the control terminal of the tenth transistor being coupled to the second terminal of the feedback circuit system, the control terminal of the fifth transistor, and the control terminal of the sixth transistor.

4. The apparatus of claim 1, wherein the swing assist circuit system further has a seventh terminal and an eighth terminal, and the apparatus further comprises: a first resistor having a first terminal and a second terminal, the first terminal of the first resistor being coupled to the seventh terminal of the swing assist circuitry; as well as A second resistor having a first terminal and a second terminal, the first terminal of the second resistor being coupled to the eighth terminal of the swing assist circuitry, and the second terminal of the second resistor being coupled to the second terminal of the first resistor.

5. The apparatus of claim 1 , wherein the current mirror circuitry comprises: a fifth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth transistor being coupled to the fifth terminal of the swing assist circuitry and the control terminal of the fifth transistor; and A sixth transistor having a first terminal, a second terminal and a control terminal, the first terminal of the sixth transistor being coupled to the sixth terminal of the slewing assist circuit system and the control terminal of the sixth transistor, and the second terminal of the sixth transistor being coupled to the second terminal of the fifth transistor.

6. The device according to claim 1, wherein the slewing assist circuit system further has a seventh terminal and an eighth terminal, and the device further includes a clamp circuit system having a first terminal, a second terminal, a third terminal and a fourth terminal, the first terminal of the clamp circuit system being coupled to the fifth terminal of the slewing assist circuit system and the first terminal of the current mirror circuit system, the second terminal of the clamp circuit system being coupled to the sixth terminal of the slewing assist circuit system and the second terminal of the current mirror circuit system, the third terminal of the clamp circuit system being coupled to the seventh terminal of the slewing assist circuit system, and the fourth terminal of the clamp circuit system being coupled to the eighth terminal of the slewing assist circuit system.

7. The apparatus of claim 1 , wherein the second transistor further has a second terminal, the fourth transistor further has a second terminal, the current mirror circuitry further has a third terminal and a fourth terminal, and the apparatus further comprises an output stage circuitry comprising: a driver circuit system having a first terminal, a second terminal, a third terminal, and a fourth terminal, the first terminal of the driver circuit system being coupled to the second terminal of the second transistor, the second terminal of the driver circuit system being coupled to the second terminal of the fourth transistor; and A power stage circuit system having a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the first terminal of the power stage circuit system is coupled to the third terminal of the current mirror circuit system, the second terminal of the power stage circuit system is coupled to the fourth terminal of the current mirror circuit system, the third terminal of the power stage circuit system is coupled to the third terminal of the driver circuit system, and the fourth terminal of the power stage circuit system is coupled to the fourth terminal of the driver circuit system.

8. A device comprising: a first transistor configured to receive a first input; a second transistor configured to receive a second input; input transistor circuitry coupled to the first transistor and the second transistor, the input transistor circuitry configured to generate a first output and a second output based on the first input and the second input; slewing assist circuitry coupled to the first transistor, the second transistor, and the input transistor circuitry, the slewing assist circuitry configured to generate a third output and a fourth output in response to a transient between the first input and the second input; as well as an output stage circuitry coupled to the input transistor circuitry and the slew assist circuitry, the output stage circuitry being configured to: generating an output voltage based on the first output and the second output; and The third output and the fourth output are used to increase a transient slew rate of the output voltage.

9. The apparatus of claim 8, further comprising current mirror circuitry coupled to the slewing assist circuitry and the output stage circuitry, the current mirror circuitry configured to: Performing mirror processing on the first current of the third output; performing mirror processing on the second current of the fourth output; as well as The output stage circuitry is caused to increase the slew rate by supplying the first current and the second current.

10. The apparatus of claim 8, wherein the swing assist circuitry is further configured to generate a fifth output and a sixth output, and the apparatus further comprises: a first resistor coupled to the swing assist circuitry, the first resistor configured to clamp the fifth output of the swing assist circuitry to a first voltage, the first voltage being used to disable the third output; as well as A second resistor coupled to the swing assist circuitry is configured to clamp the sixth output of the swing assist circuitry to a second voltage, the second voltage being used to disable the fourth output.

11. The apparatus of claim 8, further comprising clamp circuitry coupled to the slewing assist circuitry, the clamp circuitry configured to: clamping the fifth output to a first voltage for disabling the third output; clamping the sixth output to a second voltage for disabling the fourth output; and In response to disabling the third output and the fourth output, the output stage circuitry is prevented from receiving excessive current from the third output and the fourth output.

12. The apparatus of claim 8, further comprising: current source circuitry coupled to the slewing assist circuitry, the current source circuitry configured to supply current to the slewing assist circuitry in response to a control voltage; as well as feedback circuitry coupled to the first transistor, the second transistor, the input transistor circuitry, the slew assist circuitry, and the current source circuitry, the feedback circuitry configured to: responsive to the transient between the first input and the second input, setting the control voltage to a first voltage; as well as In response to clamping the control voltage, the current source circuitry is caused to supply current to the slewing assist circuitry.

13. The apparatus of claim 12, further comprising current mirror circuitry coupled to the slewing assist circuitry, the output stage circuitry, and the feedback circuitry, the current mirror circuitry configured to: Performing mirror processing on the first current of the third output; performing mirror processing on the second current of the fourth output; as well as A response time of the feedback circuitry in setting the control voltage is shortened by supplying the first current and the second current.

14. The apparatus of claim 8, wherein the output stage circuitry comprises: a driver circuitry coupled to the input transistor circuitry, the driver circuitry configured to generate a first control signal and a second control signal in response to the first output and the second output to implement AB control; and a power stage circuit system coupled to the slewing assist circuit system and the driver circuit system, the power stage circuit system being configured to: generating the output voltage in response to the first control signal and the second control signal; and The slew rate of the transient state of the output voltage is increased in response to currents of the third output and the fourth output.

15. An apparatus comprising: a feedback circuit system having a first terminal, a second terminal, and a third terminal; a current source circuit system having a first terminal and a second terminal, the first terminal of the current source circuit system being coupled to the first terminal of the feedback circuit system; a first transistor having a first terminal, a second terminal and a control terminal; a second transistor having a first terminal, a second terminal, and a control terminal; a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor being coupled to the second terminal of the current source circuitry and the first terminal of the first transistor; a fourth transistor having a first terminal, a second terminal, and a control terminal; a fifth transistor having a first terminal and a control terminal, the first terminal of the fifth transistor being coupled to the second terminal of the third transistor and the first terminal of the fourth transistor, the control terminal of the fifth transistor being coupled to the second terminal of the feedback circuitry, the control terminal of the first transistor, and the control terminal of the second transistor; a sixth transistor having a first terminal and a control terminal, the first terminal of the sixth transistor being coupled to the second terminal of the first transistor and the first terminal of the second transistor, the control terminal of the sixth transistor being coupled to the third terminal of the feedback circuitry, the control terminal of the third transistor, and the control terminal of the fourth transistor; as well as A current mirror circuit system has a first terminal and a second terminal, the first terminal of the current mirror circuit system is coupled to the second terminal of the second transistor, and the second terminal of the current mirror circuit system is coupled to the second terminal of the fourth transistor.

16. The apparatus of claim 15, wherein the current mirror circuitry comprises: a seventh transistor having a first terminal and a control terminal, the first terminal of the seventh transistor being coupled to the second terminal of the second transistor and to the control terminal of the seventh transistor; and An eighth transistor has a first terminal and a control terminal, the first terminal of the eighth transistor being coupled to the second terminal of the fourth transistor and the control terminal of the eighth transistor.

17. The apparatus of claim 16, wherein the feedback circuitry further has a fourth terminal, and the current mirror circuitry further comprises: a ninth transistor having a first terminal and a control terminal, the control terminal of the ninth transistor being coupled to the second terminal of the second transistor, the first terminal of the seventh transistor, and the control terminal of the seventh transistor; and a tenth transistor having a first terminal and a control terminal, the first terminal of the tenth transistor being coupled to the fourth terminal of the feedback circuit system and the first terminal of the ninth transistor, the control terminal of the tenth transistor being coupled to the second terminal of the fourth transistor, the first terminal of the eighth transistor, and the control terminal of the eighth transistor.

18. The apparatus of claim 15, wherein the fifth transistor further has a second terminal, the sixth transistor further has a second terminal, and the apparatus further comprises: a first resistor having a terminal coupled to the second terminal of the fifth transistor; as well as A second resistor has a terminal coupled to the second terminal of the fifth transistor.

19. The apparatus of claim 15 , further comprising an input transistor circuit system having a first terminal and a second terminal, the first terminal of the input transistor circuit system being coupled to the second terminal of the feedback circuit system, the control terminal of the first transistor, the control terminal of the second transistor, and the control terminal of the fifth transistor, and the second terminal of the input transistor circuit system being coupled to the third terminal of the feedback circuit system, the control terminal of the third transistor, the control terminal of the fourth transistor, and the control terminal of the sixth transistor.

20. The apparatus of claim 19, wherein the current mirror circuit system further has a third terminal and a fourth terminal, the input transistor circuit system further has a third terminal and a fourth terminal, and the apparatus further comprises an output stage circuit system having a first terminal, a second terminal, a third terminal and a fourth terminal, the first terminal of the output stage circuit system being coupled to the third terminal of the input transistor circuit system, the second terminal of the output stage circuit system being coupled to the fourth terminal of the input transistor circuit system, the third terminal of the output stage circuit system being coupled to the third terminal of the current mirror circuit system, and the fourth terminal of the output stage circuit system being coupled to the fourth terminal of the current mirror circuit system.

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