Distributed programmable gain amplifier

Abstract

The invention relates to a distributed programmable gain amplifier. An amplifier includes a first transmission line from a first terminal to a second terminal. The first transmission line is characterized by a first characteristic impedance that matches a resistance of a source from which a first signal is coupled to the second terminal. The amplifier includes a first resistor having a first resistance and a second resistor having a second resistance coupled between the second terminal and a third terminal. The first resistance and the second resistance are adjustable to match an input impedance at the second terminal to the first characteristic impedance and tune a gain of a second signal at the third terminal relative to the first signal at the second terminal. The amplifier includes a second transmission line from the third terminal to a third resistor having a third resistance, the second transmission line being characterized by a second characteristic impedance matching the third resistance.

Description

Technical Field

[0001] The present disclosure relates to apparatus for high-speed electrical / optical communications. Background Art

[0002] Advances in high-speed optical communication technology have driven the need for high-speed serializers / deserializers (SerDes) and optical transceivers to facilitate fast and reliable data transmission over both short and long distances through electrical and optical channels. Programmable gain amplifiers (PGAs) play an integral role in both SerDes and optical transceivers. The PGA is used to amplify or attenuate data signals before converting them between their series and parallel forms in a SerDes or before converting them between their electrical and optical forms in an optical transceiver. The PGA receives high-speed signals whose amplitudes may vary significantly and amplifies / attenuates them to a constant amplitude so that the substream circuits maintain signal integrity in the face of noise and signal loss, thereby ensuring that data can be accurately transmitted and received.

[0003] As technology evolves beyond 100Gb / s PAM4 SerDes, existing PGA structures may not be sufficient to achieve the required large bandwidth, gain range, and linearity. Higher data rates require larger signal bandwidths. At the same time, this also means that the PGA used for parallel processing requires larger load circuits, which makes it more difficult for programmable gain to achieve large bandwidths. Since parasitic capacitance and inductance dominate at high frequencies, the gain at high frequencies cannot be controlled as easily by resistors and / or transconductance as at low frequencies. If the large input signal is not attenuated by the PGA before reaching the first stage of the active transistor, the linearity of the signal path will be degraded, and the first stage of the active transistor may be saturated and pushed into the nonlinear region. Therefore, an improved PGA is needed to achieve integrated performance, broadband gain control, and excellent linearity over a large bandwidth (e.g., 55GHz or higher). Summary of the invention

[0004] In one aspect, the present disclosure relates to an apparatus comprising: a first circuit comprising a first transmission line starting from a first terminal and terminating at a second terminal, the first terminal being coupled to a source to receive a first signal, the source being coupled to ground via a first resistor characterized by a first resistance, the first transmission line being characterized by a first impedance equal to the first resistance; a second circuit comprising at least a second resistor characterized by a second resistance and a third resistor characterized by a third resistance, the second resistor being coupled between the second terminal and ground, the third resistor being coupled between the second terminal and a third terminal, the second circuit being configured to transmit the first signal from the first terminal to the second terminal and provide a gain to the second signal at the third terminal relative to the first signal; and a third circuit comprising a second transmission line starting from the third terminal and terminating with a fourth resistor, the fourth resistor being grounded and characterized by a fourth resistance, the second transmission line being characterized by a second impedance equal to the fourth resistance.

[0005] In another aspect, the present disclosure relates to an apparatus comprising: a first transmission line disposed from a first terminal to a second terminal, the first terminal coupled to a source to receive a first signal, the source coupled to ground via a first resistor characterized by a first resistance, the first transmission line configured to transmit the first signal from the first terminal to the second terminal; a second resistor characterized by a second resistance coupled between the second terminal and ground; a third resistor characterized by a third resistance coupled between the second terminal and a third terminal, the second resistance and the third resistance being adjustable to configure the first transmission line with a first impedance-matched termination at the second terminal and provide a gain to a second signal at the third terminal relative to the first signal at the second terminal; a second transmission line disposed from the third terminal to a fourth resistor, the fourth resistor coupled to the ground and characterized by a fourth resistance, the second transmission line configured to have a second impedance-matched termination for transmitting the second signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] A further understanding of the nature and advantages of particular embodiments may be achieved by reference to the remainder of the specification and the accompanying drawings, in which like reference numerals are used to refer to similar components. In some instances, a sub-label is associated with a reference numeral to denote one of multiple similar components. When a reference numeral is cited without specifying an existing sub-label, the reference numeral is intended to refer to all such multiple similar components.

[0007] Figure 1 is a schematic block diagram of a broadband gain amplifier according to some embodiments of the subject technology.

[0008] Figure 2 is a simplified circuit diagram of a distributed programmable gain amplifier in accordance with an embodiment of the subject technology.

[0009] Figure 3 is a schematic graph of resistor-controlled gain across full bandwidth based on a distributed programmable gain amplifier in accordance with an embodiment of the subject technology.

[0010] Figure 4 is a simplified diagram showing an example of a variable resistor R2 of a distributed programmable gain amplifier according to an embodiment of the subject technology.

[0011] Figure 5 is a graph of multiple gain curves across the full bandwidth for certain settings of a distributed programmable gain amplifier according to some embodiments of the subject technology.

[0012] Figure 6 is a graph of multiple input return loss curves across full bandwidth for the same settings of a distributed programmable gain amplifier according to some embodiments of the subject technology. DETAILED DESCRIPTION

[0013] The present disclosure relates to devices for high-speed electrical / optical communications. In one embodiment, a broadband programmable gain amplifier is provided, which includes a distributed input network configured to set impedance-matched input coupling and impedance-matched termination to transmit signals with low return loss in a large bandwidth. The device also includes a resistor-based network embedded in the distributed input network to achieve programmable gain of the signal with a wide gain range and consistent gain tuning across a large bandwidth. It is important to note that other alternative embodiments exist.

[0014] The following description is presented to enable one skilled in the art to make and use the invention and to incorporate the invention into the context of a particular application. Various modifications and various uses in different applications will be apparent to one skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Therefore, the present invention is not intended to be limited to the embodiments presented, but to conform to the widest scope consistent with the principles and novel features disclosed herein.

[0015] In the following detailed description, many specific details are set forth in order to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention may be practiced without necessarily being limited to these specific details. In other examples, in order to avoid obscuring the present invention, well-known structures and devices are shown in block diagram form rather than in detail.

[0016] The reader should pay attention to all papers and documents filed at the same time as this specification and open to the public with this specification, and the contents of all such papers and documents are incorporated herein by reference. Unless otherwise expressly stated, all features disclosed in this specification (including any attached claims, abstracts and drawings) can be replaced by alternative features for the same, equivalent or similar purposes. Therefore, unless otherwise expressly stated, each feature disclosed is only an example of a series of equivalent or similar features.

[0017] Furthermore, any element in a claim that does not explicitly state “means for” performing a specific function or “step for” performing a specific function should not be interpreted as a “means” or “step” clause as provided in 35 USC 112, paragraph 6. Specifically, the use of “step of” or “action of” in a claim is not intended to invoke the provisions of USC 112, paragraph 6.

[0018] When an element is referred to herein as being "connected" or "coupled" to another element, it is understood that the element may be directly connected to the other element, or that there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that there are no intervening elements in a "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which there may be intervening elements.

[0019] When an element is referred to herein as being "disposed" in some manner relative to another element (e.g., disposed on, between, below, adjacent to, or in some other relative manner), it is understood that the element may be disposed directly relative to the other element (e.g., directly on the other element) or have intervening elements between the elements. In contrast, when an element is referred to as being "directly disposed" relative to another element, it is understood that there are no intervening elements in the "direct" example. However, the presence of a direct placement does not exclude other examples where there may be intervening elements.

[0020] Similarly, when an element is referred to herein as being "joined" to another element, it is understood that the element may be directly joined to the other element (without any intervening elements) or with intervening elements between the joined elements. In contrast, when an element is referred to as being "directly joined" to another element, it is understood that there are no intervening elements in the "direct" joining between the elements. However, the presence of direct joining does not exclude other forms of joining, in which there may be intervening elements.

[0021] Likewise, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer may include a plurality of different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include a plurality of dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include intermediate elements present between the coupled or connected layers. In contrast, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intermediate elements between the layers. However, the presence of a directly coupled or connected layer does not exclude other connections in which intermediate elements may be present.

[0022] Moreover, the terms left, right, front, back, top, bottom, forward, reverse, clockwise and counterclockwise are used for explanation purposes only and are not limited to any fixed direction or orientation. Instead, the terms are only used to indicate the relative position and / or direction between the various parts of an object and / or component.

[0023] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that unless the context otherwise indicates, intermediate processes may occur before and / or after any portion of the described process, and further various procedures may be reordered, added, and / or omitted according to various embodiments.

[0024] Unless otherwise indicated, all numbers used herein to express quantities, sizes, etc. should be understood to be modified by the term "about" in all instances. In this application, unless otherwise specifically stated, the use of the singular includes the plural, and unless otherwise indicated, the use of the terms "and" and "or" means "and / or". Moreover, the use of the terms "including" and "having" and other forms (such as "includes, included", "has, have and had") should be considered non-exclusive. Similarly, unless otherwise explicitly stated, for example, "element" or "component" encompasses both elements and components including one unit and elements and components including more than one unit.

[0025] As used herein, the phrase "at least one of" preceding a list of items, and the terms "and" or "or" used to separate any of the items, modify the list as a whole rather than each member of the list (i.e., each item). The phrase "at least one of" does not require selection of at least one of each of the items listed; rather, the phrase allows for a meaning that includes at least one of any of the items and / or at least one of any combination of items. By way of example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers only to A, B, and C; and / or any combination of A, B, and C. Where selection of "at least one of each of A, B, and C" or, alternatively, "at least one of A, at least one of B, and at least one of C" is intended, it is expressly described as such.

[0026] A general aspect includes an apparatus configured as a wideband programmable gain amplifier. The apparatus also includes a first circuit. The first circuit may include a first transmission line starting from a first terminal and terminating at a second terminal, the first terminal being coupled to a source to receive a first signal, the source being coupled to ground via a first resistor characterized by a first resistance, the first transmission line being characterized by a first impedance equal to the first resistance. The apparatus also includes a second circuit. The second circuit may include at least a second resistor characterized by a second resistance and a third resistor characterized by a third resistance, the second resistor being coupled between the second terminal and ground, the third resistor being coupled between the second terminal and a third terminal, the second circuit being configured to transmit the first signal from the first terminal to the second terminal, and providing a gain of the second signal at the third terminal relative to the first signal. The apparatus also includes a third circuit. The third circuit may include a second transmission line starting from the third terminal and terminating with a fourth resistor, the fourth resistor being grounded and characterized by a fourth resistance, the second transmission line being characterized by a second impedance equal to the fourth resistance.

[0027] Embodiments may include one or more of the following features. The apparatus, wherein the second transmission line includes one or more inductor-capacitor segments coupled in series, wherein each inductor in the one or more inductor-capacitor segments is arranged in series in the second transmission line, and each capacitor in the one or more inductor-capacitor segments is arranged in parallel between the second transmission line and the ground to configure the second transmission line with an impedance matching termination. The third circuit is configured to have a third impedance for the second signal from the third terminal downstream, the third impedance being equal to the second impedance. The second circuit is configured to have a fourth impedance for the first signal from the second terminal downstream, the fourth impedance being equal to the parallel combination of the second resistance and the sum of the third resistance plus the third impedance. The second resistance and the third resistance are adjustable to set the fourth impedance equal to the first impedance so as to configure the first line with an impedance matching termination at the second terminal. The first circuit is configured to have a fifth impedance for the first signal from the first terminal downstream, the fifth impedance being equal to the first impedance. The first circuit is configured to transmit the first signal from the first terminal to the second terminal with a return loss of at least less than -10 dB across a full bandwidth of 55 GHz or higher. The gain is based on a ratio of the second impedance relative to the sum of the second impedance and the third resistance. The gain has a tunable range of at least 11 dB across a full bandwidth of 55 GHz or higher. The gain is substantially consistent within 2 dB across a full bandwidth of 55 GHz or higher. The third resistor may include an array of resistors having different resistances controlled by corresponding switches. The switch may include a transistor having a gate terminal, the gate terminal coupled to a first terminal of a fifth resistor having a resistance greater than 100 Kohm, the fifth resistor having a second terminal coupled to a control signal. The first line may include one or more inductor-capacitor segments coupled in series, wherein each inductor in the one or more inductor-capacitor segments is arranged in series in the first line, and each capacitor in the one or more inductor-capacitor segments is arranged in parallel between the first line and the ground. The device may include at least a fourth circuit. The fourth circuit may include a transistor coupled to the second transmission line to provide an output signal based on the second signal at the third terminal.

[0028] Another general aspect includes a distributed programmable gain amplifier device. The device also includes a first transmission line arranged from a first terminal to a second terminal, the first terminal coupled to a source to receive a first signal, the source coupled to ground via a first resistor characterized by a first resistance, the first transmission line configured to transmit the first signal from the first terminal to the second terminal. The device also includes a second resistor characterized by a second resistance coupled between the second terminal and ground. The device also includes a third resistor characterized by a third resistance coupled between the second terminal and a third terminal, the second resistance and the third resistance being adjustable to configure the first transmission line with a first impedance matching terminal at the second terminal and provide a gain of a second signal at the third terminal relative to the first signal at the second terminal. The device also includes a second transmission line arranged from the third terminal to a fourth resistor, the fourth resistor coupled to the ground and characterized by a fourth resistance, the second transmission line configured to have a second impedance matching terminal for transmitting the second signal.

[0029] Embodiments may include one or more of the following features. The apparatus, wherein the first transmission line may include one or more inductor-capacitor segments, wherein each inductor is arranged in series and each capacitor is arranged in parallel, the one or more inductor-capacitor segments being characterized by a first impedance equal to the first resistance. The second transmission line may include one or more inductor-capacitor segments, wherein each inductor is arranged in series and each capacitor is arranged in parallel, the one or more inductor-capacitor segments being characterized by a second impedance equal to the fourth resistance. The second transmission line is configured to have a third impedance for the second signal from the third terminal downstream, the third impedance being equal to the second impedance. The apparatus is configured to have a fourth impedance for the first signal from the second terminal downstream based on the product of the second resistance and the sum of the third resistance plus the third impedance divided by the sum of the second resistance plus the third resistance plus the third impedance, the fourth impedance being equal to the first impedance due to the first impedance matching termination at the second terminal. The gain is approximately unity across a full bandwidth of 55 GHz or higher and has a tunable range of at least 11 dB based on a ratio of the second impedance relative to a sum of the second impedance and the third resistance, wherein the third resistance is adjustable and the second impedance is equal to the fourth resistance.

[0030] In modern communication networks, high-speed serializers / deserializers (SerDes) and optical transceivers are often used to facilitate fast and reliable data transmission across both short and long distances. A programmable gain amplifier (PGA) can be used to amplify the input signal before serialization, thereby ensuring that the input signal can be accurately received and deserialized at the other end. PGAs can be used at both the transmitting end and the receiving end. On the transmitter side, the PGA can amplify the electrical signal and then convert the electrical signal into an optical signal, thereby ensuring that the signal can travel a longer distance. On the receiver side, the PGA can amplify the received signal and then convert the received signal back into an electrical signal, thereby ensuring that the signal can be accurately interpreted.

[0031] As high-speed communication systems require higher (>100 Gb / s) data rates, existing PGA designs cannot provide satisfactory performance of large bandwidth, wideband gain control, and excellent linearity at the same time. Figure 1 A simplified block diagram of a broadband gain amplifier according to some embodiments of the subject technology is shown. A broadband programmable gain amplifier 100 is configured with a distributed input network 101 to artificially divide an input signal and distribute it to multiple gain stages. At each gain stage, the divided input signal can be adjusted individually, and all gain stages together cover a wider frequency range. In an alternative view, the distributed input network 101 can be configured to optimize the interface between a signal source and a gain circuit 120 (e.g., representing a gain stage) via an input coupling circuit 111 and a gain circuit 120 and an output coupling circuit 112 for a subsequent stage or load.

[0032] In one embodiment, the distributed input network 101 designed for the gain amplifier can use an artificial transmission line, which is usually composed of cascaded inductors and capacitors, to handle signal amplification / attenuation by simulating the characteristics of an ideal transmission line. In general, in the context of the subject technology, an artificial transmission line refers to a structured network of passive components (usually inductors and capacitors) arranged in a manner that simulates the electrical properties and behavior of a traditional transmission line. Unlike natural transmission lines, these artificial structures allow designers to fine-tune specific electrical characteristics, providing greater control over signal integrity, impedance characteristics, and other key parameters. The artificial transmission line can be implemented as a series of cascaded inductor-capacitor (LC) segments, or other topologies to achieve the desired transmission line characteristics may have multiple sections. In each segment, the input coupling circuit 111 is located at the beginning of the artificial transmission line and is responsible for matching the impedance of the signal source to the artificial transmission line. The output coupling circuit 112 is located at the end of the artificial transmission line of the distributed network, thereby performing the opposite function of the input coupling, matching the impedance of the transmission line to the load or the next stage. A gain circuit 120 representing at least one of a plurality of gain stages distributed along an artificial transmission line is disposed between the input coupling circuit 111 and the output coupling circuit 112 and is responsible for amplifying / attenuating the signal as it traverses the line. The input coupling circuit 111 and the output coupling circuit 112 may include, for example, a series of reactive and resistive components, typically consisting of cascaded inductors and capacitors, to minimize reflections and maximize power transfer. The gain circuit 120 may include components such as switches, variable capacitors, or variable resistors to adjust the properties of the artificial transmission line and apply gain or attenuation to the signal as it traverses the stages. In addition, the gain circuit 120 may cause the gain or attenuation to be programmable and achieve linear performance over a wide frequency range.

[0033] Figure 2 is a simplified circuit diagram of a distributed programmable gain amplifier according to an embodiment of the subject technology. This figure is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. In a particular embodiment, a distributed gain amplifier is provided by implementing a distributed input network for achieving large bandwidth and an embedded resistor network for achieving a flexible gain adjustment mechanism and linear performance over a wide frequency range. Figure 2, the distributed input network consists of one artificial transmission line configured to couple to the signal source 20 at the input stage 201 so as to receive the input signal with minimal loss and generate an output signal with the desired gain / attenuation to the output stage 231 with minimal gain variation across the full bandwidth. This input signal may be a single-ended signal. In an alternative scenario, another artificial transmission line may be added to handle differential input signals, where one artificial transmission line is configured to receive and process an input signal with a positive polarity, while another artificial transmission line, which may be configured identically, is configured to receive and process another input signal with a negative polarity.

[0034] refer to Figure 2 In the circuit system of the invention, one artificial transmission line of the distributed gain amplifier is a first transmission line 211 (also referred to as a first circuit) starting from a first terminal P0 and terminating at a second terminal P1. The first terminal P0 is directly coupled to a signal source 20 to receive a first signal V1. The signal source may be terminated to be grounded via a resistor having a resistance Rs. The first circuit 211 is configured to allow an input signal from the signal source 20 to be transmitted from the first terminal P0 to the second terminal P1. The distributed gain amplifier also includes a second circuit 221 coupled sequentially between the second terminal P1 and the third terminal P2. The distributed gain amplifier also includes another artificial transmission line (a second transmission line 212 (also referred to as a third circuit)) starting from the third terminal P2 and terminating to be grounded via a resistor having a resistance Rt. The second circuit 221 and the third circuit 212 are configured to adjust the characteristics of the artificial transmission line under the control of the artificial transmission line and provide a gain to a second signal V2 at the third terminal P2. In one embodiment, the output stage 231 includes at least a fourth circuit 23 coupled to the second transmission line 212 to deliver an output signal based on the second signal V2. The fourth circuit 23 is based on transistors. In another embodiment, the output stage 231 further includes a fifth circuit 24. The fourth circuit 23 and the fifth circuit 24 are respectively coupled to two segments of the third circuit 212 to deliver output signals based on the second signal V2.

[0035] In a particular embodiment, the first transmission line 211 (the first circuit of the amplifier) ​​is represented by a series of inductor-capacitor (LC) segments cascaded in a chain, wherein all inductors are connected in series in a line from a first terminal P0 to a second terminal P1, and all capacitors are coupled in parallel to ground from corresponding intersections on the lines of the inductors. L and C represent inductance and capacitance, respectively. A series of inductor-capacitor (LC) segments are used to simulate parasitic capacitance in an input transmission line coupled to a signal source, and these inductors with corresponding inductances are used to separate the parasitic capacitance into individual (small) capacitors, and any number of LC segments may be arranged depending on design choices based on actual signal transmission characteristics. A series of segments in the inductor-capacitor (LC) segment may be given by a first characteristic impedance Z given by the following equation: 01 Characterized by

[0036]

[0037] The impedance of a lossless transmission line is represented by where L is the inductance per unit length or segment and C is the capacitance per unit length or segment. Figure 2 , an example of the first transmission line 211 includes at least a first LC segment. Optionally, the first transmission line 211 also includes a second LC segment. The first LC segment includes a first inductor L1 and a first capacitor C1. The second LC segment includes a second inductor L2 and a second capacitor C2. L2 is coupled to L1 in series in the transmission line. C2 and C1 are arranged in parallel between the transmission line and ground. Optionally, there are more LC segments arranged or cascaded in a similar manner to the first two segments. Each inductor is arranged in series with other inductors, and each capacitor is arranged in parallel with other capacitors. In one embodiment, by selecting appropriate values ​​for the inductors and capacitors in the series LC segments, the first transmission line 211 is configured to allow the input signal from the signal source 20 to be coupled to the first signal V1 at the second terminal with maximum power transmission or minimum return loss when the signal crosses the artificial transmission line. This can be achieved if the first transmission line 211 is configured to have an impedance matching terminal.

[0038] A transmission line with an impedance-matched termination refers to a propagation medium such as a coaxial cable, a microstrip line, or any other form of propagation medium, where the impedance of the load or terminal of the propagation medium is coordinated with the inherent characteristic impedance Z0 of the transmission line itself. For a transmission line arranged from a starting terminal coupled to a signal source (or receiving a signal from the signal source) to an ending terminal coupled to a load (or outputting a signal downstream from the load), the transmission line can be configured to have an impedance-matched termination at both the starting terminal and the ending terminal. Figure 2In the embodiment, the source 20 is terminated by a resistor Rs. The source impedance in such a model may be represented primarily by the resistance of that resistor, i.e., the source impedance is primarily the source resistance. At higher frequencies, even a simple resistor may introduce some parasitic inductance or capacitance due to the physical structure or layout on the circuit board. In an embodiment, these parasitic elements may be included in the first transmission line 211 (or the first circuit). The transmission line 211 may be represented by a first characteristic impedance Z 01 to characterize, depending on the topological configuration of the LC segment. If the first characteristic impedance Z 01 If Rs is equal to Rs, then the impedance matching condition is achieved at the starting terminal P0. At the end terminal, if the characteristic impedance of the transmission line is equal to the load impedance at the end terminal, that is, the impedance seen when the signal is transmitted downstream from the end terminal, then the transmission line is regarded as an impedance matching terminal at the end terminal. For example, Figure 2 , the impedance of the signal from the downstream second terminal P2 corresponds to the load impedance seen by the signal from all circuit elements of the downstream terminal P2 (all resistors, inductors and capacitors in the corresponding circuit structures of the second circuit 221 and the third circuit 212).

[0039] In some implementations, the second transmission line 212 or the third circuit of the amplifier may also be represented by a series of LC segments in a similar configuration, and more specifically, terminated by a resistor Rt. Figure 2 In the example shown in , the second transmission line 212 includes a third LC segment and a fourth LC segment coupled in series in a line from a third terminal P2 to a terminal resistor Rt. The third LC segment includes a third inductor L3 and a third capacitor C3. The fourth LC segment includes a fourth inductor L4 and a fourth capacitor C4. The terminal resistor Rt is coupled to ground, which may be accompanied by a capacitor C5 coupled in parallel from the line to ground. Capacitors C3, C4, C5 represent parasitic capacitances of other circuit devices. Optionally, the second transmission line 212 includes only one LC segment terminated by a combination of C5 and Rt. Optionally, there are more LC segments arranged or cascaded in a manner similar to the first two segments. Each inductor is arranged in series with the other inductors, and each capacitor is arranged in parallel with the other capacitors. In Figure 2 In the example shown in FIG. 1 , the second transmission line 212 has a second characteristic impedance Z 02 The terminating resistor Rt allows the second transmission line 212 to be configured to allow the artificial transmission line of C3-L3-C4-L4-C5 to have an impedance matched termination, such that Rt=Z 02 Due to the impedance matching terminal, the impedance seen by the signal transmitted from the downstream third terminal P2 is always equal to the second characteristic impedance Z due to the impedance matching terminal. 02In one embodiment, the impedance matching termination condition associated with the second transmission line 212 is configured to be effective over a wide frequency range. For example, a design under the present disclosure has a wide bandwidth, such as 55 GHz or higher. Higher frequency ranges are possible.

[0040] The second circuit 221 is composed of at least a first resistor R1 and a second resistor R2 disposed between the first transmission line 211 and the second transmission line 212. The first resistor R1 (variable resistor) is coupled between the second terminal P1 and ground. The second resistor R2 (also a variable resistor) is coupled between the second terminal P1 and the third terminal P2. The second circuit 221 is configured as a gain circuit of an amplifier, thereby acting as a gain stage disposed in an artificial transmission line to provide a second signal V2 at the third terminal P2, the second signal having a tunable gain relative to the first signal V1 at the second terminal P1. Both R1 and R2 are variable, thereby providing a flexible way to achieve gain control with a substantially frequency-independent mechanism across a wide frequency range.

[0041] Assuming that the second transmission line 212 is coupled in series to the second resistor R2, they form a resistor divider for the signal traversing the second circuit 221. Therefore, the gain is provided by the following equation:

[0042] V2 / V1=Z 02 / (R2 + Z 02 ) (2)

[0043] This is tuned by adjusting R2. Since the input impedance of the second transmission line at the third terminal is also the same as the impedance from the downstream third terminal P2 to its terminal (for the second signal V2). In addition, the second characteristic impedance Z 02 =Equal to the terminal resistance Rt. Therefore, the gain is essentially independent of the frequency of the signal but can be tuned by changing the resistance R2. This tunable mechanism for gain also provides a programmable gain range. The lower limit of the gain range can be expanded indefinitely, but the upper limit of the gain range is limited by parasitic resistances in the signal path. Depending on the specific design choices of the artificial transmission line of the distributed gain amplifier according to the subject technology, Z can be achieved at least for full bandwidth up to very high frequencies (e.g., 55 GHz or higher). 02 = Rt. This bandwidth of interest is primarily limited by the associated capacitance in the artificial transmission line and can be extended by dividing the associated capacitance into smaller capacitances.

[0044] In a specific embodiment, the design selection of the second circuit 221 is also related to the design of the first circuit 211 to configure the first transmission line with an impedance matching termination at the second terminal P1. Specifically, the impedance (for the signal) from the second terminal P1 toward the third terminal P2 and the second transmission line 212 can be determined by the first resistor R1 and the second resistor R2 and the second transmission line Z 02 The parallel combination of the sum of the impedances of R1||(R2+Z 02 ). The design choices of both the second circuit 221 (via the variable resistors R1 and R2) and the first circuit 211 (via the plurality of LC segments) are set to make the impedance from the downstream second terminal P2 equal to the first characteristic impedance,

[0045] R1||(R2 + Z 02 )=Z 01 (3)

[0046] This makes the first transmission line P2 terminated with impedance matching at the second terminal, i.e., the impedance from the downstream second terminal P1 equal to the first characteristic impedance of the first transmission line 211. Due to the impedance matching termination of the first transmission line, the impedance from the downstream first terminal P0 (for the first signal V1) should be equal to the first characteristic impedance Z 01 By selecting appropriate values ​​for the inductors and capacitors in the LC segment chain of the first transmission line 211, the first characteristic impedance Z 01 Can be equal to source resistance Rs, Z 01 =Rs. Therefore, the input impedance of the first transmission line 211 at the first terminal P0 must also be equal to the source resistance Rs. Under impedance matching conditions at both the starting terminal P0 and the terminating terminal P1 of the first transmission line 211, excellent minimum reflection is achieved for the signal to be transmitted through the first transmission line 211. The input signal (first signal V1) received from the source 20 can be coupled from the first terminal P0 to the second terminal P1 with minimal (substantially zero) return loss.

[0047] Figure 3 is a schematic graph of resistor-controlled gain across full bandwidth based on a distributed programmable gain amplifier according to an embodiment of the subject technology. This figure is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. Figure 2The schematic curve diagram of the gain of the amplifier disclosed in shows that the gain can be tuned by adjusting the two resistors R1 and R2. When the first resistor R1 increases and the second resistor R2 decreases, the gain value increases while maintaining the input resistance and matching of the first transmission line. The gain range obviously depends on the variable resistance of R1 and R2, and is also obviously limited by the parasitic resistance in the signal path. The schematic curve diagram also shows that, at least for the frequencies of interest from low to high F0, the gain at each level is basically consistent with respect to frequency. F0 can be used to characterize the operating bandwidth of the amplifier. As described in the previous paragraph, the gain depends primarily on the resistor network established on the first resistor R1, the second resistor R2 and the terminal resistor Rt. Due to the second characteristic impedance Z 02 Equal to Rt over a wide frequency range, so the gain is essentially frequency independent. Figure 3 exhibit Figure 2 The present disclosure of amplifiers in can achieve that limit by pushing the value F0 to 55 GHz or higher before we notice tailing.

[0048] In some embodiments, the first resistor R1 and the second resistor R2 can be tuned by configuring each of them as a switched resistor array. For example, R1 or R2 includes a plurality of resistors of increasing resistance, wherein each resistor is controlled by a switch that can turn the resistor on or off to allow the resistance of R1 or R2 to be tuned. Figure 4 is a simplified diagram showing an example of a variable resistor R2 of a distributed programmable gain amplifier according to an embodiment of the subject technology. The switch used to control the resistor (R2) is a transistor, wherein the source and drain of the transistor are respectively coupled to two terminals of the resistor in the array. The gate of the transistor is coupled to a control signal (Ctrl) through a resistor with a large resistance (e.g., 100KOhm or higher). Using a large gate resistor allows the gate voltage used to control the on or off state of the transistor to follow the input signal in the transmission line. As shown in FIG. Figure 4 As shown in , the variable resistor R2 controlled by the large gate resistor on the left side of the figure is equivalent to the circuit system on the right side of the figure. In this transistor configuration, the gate-source voltage Vgs and the gate-drain voltage Vgd must not be modulated by the input signal so that the switch resistance is linear and does not distort the input signal. At the same time, the parasitic capacitance Cgs between the gate and the source and the parasitic capacitance Cgd between the gate and the drain are not loaded into the signal path to cause the gain to change. Therefore, within a certain tunable range, the gain can be kept consistent for a large bandwidth. In another embodiment, as Figure 4As shown in the right part of , the function of the large gate resistor can be explained as a pair of diodes connected to the gate terminal of the transistor. The leakage current keeps the source / drain / gate at the same DC voltage level, and the diode in the "off" state behaves like an oversized resistor. When the control signal "Ctrl" is switched in two states, one of the pair of diodes is briefly turned on, providing fast switching preferably for tuning the gain. In general, these tunable resistors R1 or R2 can be made in a compact layout in a small footprint, which results in a small parasitic capacitance in the transmission line for achieving high impedance. The control signal "Ctrl" can be provided by a controller that is programmable to provide programmable gain for a broadband amplifier across a wide frequency range.

[0049] Figure 5 is a graph of multiple gain curves across the full bandwidth for certain settings of a distributed programmable gain amplifier according to some embodiments of the subject technology. This figure is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. Figure 5 Display based on Figure 2 Graphs of multiple gain curves across full bandwidth for some optimized settings of a distributed programmable gain amplifier shown in FIG. The parasitic capacitance in the first transmission line is divided into a first capacitor C1 = 30 fF and a second capacitor C2 = 60 fF by two inductors L1 and L2. By selecting appropriate inductance values ​​for L1 and L2, the first characteristic impedance Z 01 The parasitic capacitance in the second transmission line is divided into a third capacitor C3 = 100 fF, a fourth capacitor C4 = 100 fF and a fifth capacitor C5 = 30 fF by two inductors L3 and L4. By selecting appropriate inductance values ​​for L3 and L4 and the terminal resistor Rt, the second characteristic impedance Z 02 The terminal resistor Rt is matched.

[0050] As a result of the impedance matching design of both the first transmission line and the second transmission line, the gain circuit between these transmission lines can be configured to tune the amplifier gain based on R1 / (R2+Rt), where Rt=Z 02 .like Figure 5 As shown in Figure 1, the gain is shown to be approximately independent of frequency. Approximately uniform gain control can be achieved with a gain variation of slightly less than 2 dB across the full bandwidth of 55 GHz or higher. This demonstrates that distributed gain amplifiers have a large bandwidth that meets the needs of modern high-speed communication systems. By changing the resistance of R1 or E2, the gain is programmable and can be varied over a large range of at least greater than 11 dB, as shown in Figure 1. Figure 5The lower limit of the gain range can be extended indefinitely, but the upper limit of the gain range is limited by the parasitic resistance in the signal path.

[0051] Figure 6 is a graph of multiple input return loss curves across full bandwidth for the same settings of a distributed programmable gain amplifier according to some embodiments of the subject technology. This figure is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. Figure 6 exhibit Figure 2 The distributed programmable gain amplifier shown in Figure 5 The parasitic capacitance in the first transmission line is divided into a first capacitor C1 = 30 fF and a second capacitor C2 = 60 fF by two inductors L1 and L2. By selecting appropriate inductance values ​​for L1 and L2, the first characteristic impedance Z 01 Matched with the source resistance Rs. Due to the matched termination at the second terminal, the input impedance of the first transmission line is equal to the first characteristic impedance Z 01 , which provides excellent conditions for causing minimum return loss of the signal traversing the first transmission line. Figure 6 As shown in FIG. 1 , the return loss is less than -10 dB for full bandwidth (55 GHz or higher in this example). Higher frequencies are also achievable within the same range of the subject technology. This allows the input signal to be coupled to the gain stage with maximum power transfer.

[0052] In some embodiments, Figure 2 The distributed input network used in the example shown in can be extended to have any number of inductor-capacitor (or resistor) segments. Figure 2 The transmission line of the design can be implemented in single-ended and differential circuits. The components used to construct the artificial transmission line can be implemented in a variety of forms and processes. For example, the components can be provided as discrete devices (capacitors, inductors or resistors) on a printed circuit board (PCB). Another option is that the components can also be provided as integrated devices in a CMOS process. In some embodiments, the resistor network associated with the second circuit and the third circuit can be implemented in different processes including sliding resistors in discrete implementations, switched resistor arrays in CMOS processes, and voltage-controlled resistors. The broadband gain programmability of the distributed gain amplifier enables the SerDes to cope with a wide range of operating environments, such as SerDes transceivers and high-speed switching applications of >200Gb / s.

[0053] Although the above is a complete description of specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustration should not be taken as limiting the scope of the invention, which is defined by the appended claims.

Claims

1. A device comprising: a first circuit comprising a first transmission line starting at a first terminal and terminating at a second terminal, the first terminal being coupled to a source to receive a first signal, the source being coupled to ground via a first resistor characterized by a first resistance, the first transmission line being characterized by a first impedance equal to the first resistance; a second circuit including at least a second resistor characterized by a second resistance coupled between the second terminal and ground and a third resistor characterized by a third resistance coupled between the second terminal and a third terminal, the second circuit being configured to transmit the first signal from the first terminal to the second terminal and provide a gain to the second signal at the third terminal relative to the first signal; and A third circuit includes a second transmission line starting from the third terminal and terminating with a fourth resistor, the fourth resistor being grounded and characterized by a fourth resistance, the second transmission line being characterized by a second impedance equal to the fourth resistance.

2. The apparatus of claim 1 , wherein the second transmission line comprises one or more serially coupled inductor-capacitor segments, wherein each inductor of the one or more inductor-capacitor segments is arranged in series in the second transmission line, and each capacitor of the one or more inductor-capacitor segments is arranged in parallel between the second transmission line and the ground to configure the second transmission line with an impedance-matched termination. 3 . The apparatus of claim 2 , wherein the third circuit is configured to have a third impedance for the second signal from the third terminal downstream, the third impedance being equal to the second impedance.

4. The apparatus of claim 3, wherein the second circuit is configured to have a fourth impedance for the first signal from the second downstream terminal, the fourth impedance being equal to a parallel combination of the second resistance and a sum of the third resistance plus the third impedance.

5. The apparatus of claim 4, wherein the second resistor and the third resistor are adjustable to set the fourth impedance equal to the first impedance so as to configure the first transmission line with an impedance-matched termination at the second terminal. 6 . The apparatus of claim 5 , wherein the first circuit is configured to have a fifth impedance for the first signal from the first terminal downstream, the fifth impedance being equal to the first impedance. 7 . The apparatus of claim 6 , wherein the first circuit is configured to transmit the first signal from the first terminal to the second terminal with a return loss of less than −10 dB across a full bandwidth of 55 GHz or higher.

8. The apparatus of claim 1, wherein the gain is based on a ratio of the second impedance relative to a sum of the second impedance and the third resistance.

9. The apparatus of claim 8, wherein the gain has a range of at least 11 dB across a full bandwidth of 55 GHz or higher.

10. The apparatus of claim 8, wherein the gain is approximately consistent within 2 dB across a full bandwidth of 55 GHz or higher.

11. The apparatus of claim 1, wherein the third resistor comprises an array of resistors having different resistances controlled by corresponding switches.

12. The apparatus of claim 11, wherein the switch comprises a transistor having a gate terminal coupled to a first terminal of a fifth resistor having a resistance greater than 100 KOhm, the fifth resistor having a second terminal coupled to a control signal.

13. The apparatus of claim 1 , wherein the first transmission line comprises one or more series-coupled inductor-capacitor segments, wherein each inductor in the one or more inductor-capacitor segments is arranged in series in the first transmission line, and each capacitor in the one or more inductor-capacitor segments is arranged in parallel between the first transmission line and the ground.

14. The apparatus of claim 1, further comprising at least a fourth circuit comprising a transistor coupled to the second transmission line to provide an output signal based on the second signal at the third terminal.

15. An apparatus comprising: a first transmission line disposed from a first terminal to a second terminal, the first terminal being coupled to a source to receive a first signal, the source being coupled to ground via a first resistor characterized by a first resistance, the first transmission line being configured to transmit the first signal from the first terminal to the second terminal; a second resistor characterized by a second resistance coupled between the second terminal and ground; a third resistor characterized by a third resistance coupled between the second terminal and the third terminal, the second resistance and the third resistance being adjustable to configure the first transmission line with a first impedance-matched termination at the second terminal and to provide gain to a second signal at the third terminal relative to the first signal at the second terminal; A second transmission line is disposed from the third terminal to a fourth resistor coupled to the ground and characterized by a fourth resistance, the second transmission line being configured to have a second impedance matched termination for transmitting the second signal.

16. The apparatus of claim 15, wherein the first transmission line comprises one or more inductor-capacitor segments, wherein each inductor is arranged in series and each capacitor is arranged in parallel, the one or more inductor-capacitor segments being characterized by a first impedance equal to the first resistance.

17. The apparatus of claim 16, wherein the second transmission line comprises one or more inductor-capacitor segments, wherein each inductor is arranged in series and each capacitor is arranged in parallel, the one or more inductor-capacitor segments being characterized by a second impedance equal to the fourth resistance.

18. The apparatus of claim 17, wherein the second transmission line is configured to have a third impedance for the second signal from the third terminal downstream, the third impedance being equal to the second impedance across a full bandwidth of 55 GHz or higher due to the second impedance-matched termination.

19. The apparatus of claim 18, configured to have a fourth impedance for the first signal from the second downstream terminal based on a parallel combination of the second resistance and the sum of the third resistance plus the third impedance, the fourth impedance being equal to the first impedance due to the first impedance matching termination at the second terminal.

20. The apparatus of claim 17, wherein the gain is approximately unity across a full bandwidth of 55 GHz or higher and has a tunable range of at least 11 dB based on a ratio of the second impedance relative to a sum of the second impedance and the third resistance, wherein the third resistance is adjustable and the second impedance is equal to the fourth resistance.

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