A DMA-based uninterrupted sampling method for ADC
By dividing the buffer into upper and lower half-buffers and combining DMA half-transfer interrupt and cyclic transfer modes, the data processing delay problem in the DMA sampling method is solved, realizing uninterrupted acquisition and processing of ADC signals and improving system efficiency.
Patent Information
- Application Number
- CN202411920412.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2026-02-06
- Estimated Expiration
- 2044-12-25
AI Technical Summary
In existing technologies, DMA-based ADC sampling methods result in data processing delays and reduced system efficiency at high sampling rates, making it impossible to achieve uninterrupted sampling and affecting the execution of other CPU tasks.
By dividing the buffer into upper and lower half-buffers, and combining DMA half-transfer interrupt and cyclic transfer modes, parallel execution of data transmission and processing is achieved, ensuring uninterrupted ADC sampling.
This enables uninterrupted acquisition and processing of ADC signals, reduces data processing latency, and improves system efficiency and sampling performance.
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Figure CN119921771B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of data sampling, and particularly relates to an ADC uninterrupted sampling method based on DMA. BACKGROUND
[0002] An analog-to-digital converter (ADC) is mainly used for converting a continuously transmitted analog signal into a digital signal, so that a processor (CPU) can quickly process and analyze the transmitted information. When the sampling rate (the number of times of collecting an analog signal per second) is low, a trigger sampling is usually used, for example, sampling is triggered once per second. When the sampling rate is high, a continuous sampling is used, the ADC continuously samples at a certain sampling rate, and the CPU is notified to read the sampling data after the sampling is completed. However, the CPU usually executes many tasks, and the CPU is frequently notified to read the ADC data, which can reduce the efficiency of the system. Therefore, when the sampling rate is high, a direct memory access (DMA) mode is usually used to read the ADC data, that is, the DMA is notified after the sampling is completed, and the DMA automatically stores the data in a specified memory buffer. When the CPU needs to use the data, the CPU processes the data. Figure 1 Fig. 1 shows a typical use method of the ADC based on the DMA.
[0003] In the typical use method of the ADC based on the DMA, the size of the DMA buffer is M, the size of the ADC signal to be continuously collected is N, the ADC sampling rate is Vc, and the speed of the CPU processing the ADC data is Vp. Since the size of the system memory and the DMA buffer is limited, the size of M is limited. When N>M, the ADC conversion and the DMA transmission need to be re-enabled after the data in the buffer is processed, which can cause the ADC signal to be interrupted. In the case of digital filtering, signal analysis and the like, the interruption is not allowed. The ADC sampling and the CPU processing the data are sequentially performed, and the data processing delay is M / Vc. The data processing delay is high. Each time the CPU is notified to process the data, M data need to be processed, and the single data processing time is M / Vp. The instantaneous large amount of data to be processed can affect the execution of other tasks by the CPU.
[0004] If an ADC uninterrupted sampling method can be provided, the completeness of the sampling data can be well ensured, and the sampling data can be stably processed. SUMMARY
[0005] The application solves the technical problem of overcoming the deficiencies of the prior art, and provides an ADC uninterrupted sampling method based on DMA. The ADC uninterrupted sampling method based on DMA uses a DMA half-transmission interrupt and a DMA cyclic transmission mode to realize ADC uninterrupted sampling without length limitation, and the CPU processes the sampling data in parallel, so that the sampling performance and efficiency are improved.
[0006] The technical scheme adopted by the present application is as follows: the present application comprises an ADC unit, a DMA unit and a CPU unit, the input end of the ADC unit is connected with a signal source, the output end of the ADC unit is communicated with the CPU unit through the DMA unit, the DMA unit comprises a DMA controller and a buffer manager connected with each other, and the sampling method further comprises the following specific steps:
[0007] Step S1, initializing the ADC unit, the DMA controller and the buffer manager, wherein the ADC unit is configured in a continuous conversion mode, the DMA controller is configured in a loop mode, the buffer manager sets the buffer pointer and the buffer size, and sets the upper half buffer flag and the lower half buffer flag as empty, and initializes the half buffer pending signal quantity as 0;
[0008] Step S2, starting the ADC unit to continuously sample and convert, and the DMA controller transmits the converted data to the buffer manager;
[0009] Step S3, when the data transmitted by the DMA controller is greater than half of the current buffer size, a DMA transmission half-interrupt is generated, the interrupt signal is sent to the CPU unit, the CPU unit executes the DMA transmission half-interrupt processing, the DMA transmission half-interrupt processing checks the lower half buffer flag, if the lower half buffer flag is empty, the flag is cleared and the transmission is continued, and then a half buffer pending signal quantity is released;
[0010] Step S4, the operation of releasing the half buffer pending signal quantity in step S3 wakes up the data processing thread, the data processing thread acquires the signal quantity and processes the data in the upper half buffer; when the data processing is completed, the upper half buffer flag is set as empty, and the half buffer pending signal quantity is continuously waited;
[0011] Step S5, when the data transmitted by the DMA controller is greater than the current buffer size, a DMA transmission completion interrupt is generated, the interrupt signal is sent to the CPU unit, the CPU unit executes the DMA transmission completion interrupt processing, the DMA transmission completion interrupt processing checks the upper half buffer flag, if the upper half buffer flag is empty, the flag is cleared and the transmission is continued, and then a half buffer pending signal quantity is released;
[0012] Step S6, the operation of releasing the half buffer pending signal quantity in step S3 wakes up the data processing thread, the data processing thread acquires the signal quantity and processes the data in the lower half buffer; when the data processing is completed, the lower half buffer flag is set as empty, and the half buffer pending signal quantity is continuously waited;
[0013] Step S7, since the ADC unit is configured in continuous conversion mode, the DMA controller is configured in cycle mode, the DMA controller will automatically start transmission from the buffer start address after each transmission is completed, repeating steps S3 to S6 until the end of the collection.
[0014] From the above scheme, it can be seen that by adopting the method of dividing the buffer into upper and lower halves, the upper and lower buffer functions are alternated, one half is used for DMA data transmission, and the other half is used for CPU data processing, thereby realizing the effect of parallel execution of data transmission and data processing. Further, it ensures that the entire sampling process does not need to pause DMA, and also does not limit the data collection length, achieving the effect of uninterrupted ADC sampling.
[0015] A preferred scheme is to first perform data caching of the upper half buffer when entering step S3 from step S2.
[0016] A preferred scheme is that in step S3, if the lower half buffer flag is not empty, it indicates that the buffer is overflowed, at this time, according to the specific circumstances, the corresponding error handling function is executed.
[0017] A preferred scheme is that in step S5, if the upper half buffer is not empty, it indicates that the buffer is overflowed, at this time, according to the specific circumstances, the corresponding error handling function is executed. BRIEF DESCRIPTION OF DRAWINGS
[0018] Figure 1 is a typical use method flow chart of the ADC based on DMA;
[0019] Figure 2 is a system block diagram of the present application;
[0020] Figure 3 is a flowchart of the present application. DETAILED DESCRIPTION
[0021] As Figure 2 and Figure 3As shown, in the embodiment, the application comprises an ADC unit, a DMA unit and a CPU unit, an input end of the ADC unit is connected with a sampling signal source, an output end of the ADC unit is communicated with the CPU unit through the DMA unit, the DMA unit comprises a DMA controller and a buffer manager connected with each other; the ADC unit is used for converting external analog signals into digital signals; the DMA controller is used for transmitting the converted digital signals from the ADC into the DMA buffer in sequence; the buffer manager is composed of a DMA buffer and two flag bits and a semaphore; the CPU unit has the following functions: 1. used for processing the data carried by the DMA into the buffer; 2. when the DMA controller generates a DMA transmission half-interrupt, performing DMA transmission half-interrupt processing; 3. when the DMA controller generates a DMA transmission completion interrupt, performing DMA transmission completion interrupt processing; the sampling method further comprises the following specific steps:
[0022] Step S1, initializing the ADC unit, the DMA controller and the buffer manager, wherein the ADC unit is configured in a continuous conversion mode; the DMA controller is configured in a loop mode, when the buffer is filled, the DMA controller automatically starts transmitting data from the first byte of the buffer; the buffer manager sets the buffer pointer and the buffer size, and sets the upper half buffer flag and the lower half buffer flag as empty, and initializes the half buffer pending semaphore as 0;
[0023] Step S2, starting the ADC unit to continuously sample and convert, the DMA controller transmits the converted data into the buffer manager, and the buffer manager starts buffering data from the start position of the buffer;
[0024] Step S3, when the data transmitted by the DMA controller is greater than half of the current buffer size, a DMA transmission half-interrupt is generated, the interrupt signal is sent to the CPU unit, the CPU unit performs DMA transmission half-interrupt processing, the DMA transmission half-interrupt processing checks the lower half buffer flag, if the lower half buffer flag is empty, the flag is cleared and the transmission continues, and then a half buffer pending semaphore is released; if the lower half buffer flag is not empty, it indicates that the buffer is overflowed, at this time, a corresponding error processing function is executed according to the specific situation;
[0025] Step S4, the operation of releasing the half buffer pending semaphore in step S3 wakes up the data processing thread, the data processing thread acquires the semaphore and processes the data in the upper half buffer; at this time, the whole system is in a parallel running state of data processing and data communication; when the data processing is completed, the upper half buffer flag is set as empty, and the half buffer pending semaphore is continuously waited.
[0026] Step S5, when the data transmitted by the DMA controller is greater than the current buffer size, a DMA transfer completion interrupt is generated, the interrupt signal is sent to the CPU unit, the CPU unit executes DMA transfer completion interrupt processing, the DMA transfer completion interrupt processing performs upper half buffer flag checking, if the upper half buffer flag is empty, the flag is cleared and the transmission is continued, then a half buffer pending semaphore is released; if the upper half buffer is not empty, it indicates that the buffer is overflowed, at this time, the corresponding error processing function is executed according to the specific situation;
[0027] Step S6, the operation of releasing the half buffer pending semaphore in step S3 wakes up the data processing thread, the data processing thread acquires the semaphore and processes the data in the lower half buffer; at this time, the whole system is in a parallel running state of data processing and data communication; when the data processing is completed, the lower half buffer flag is set to empty, and the half buffer pending semaphore is continued to be waited;
[0028] Step S7, since the ADC unit is configured in continuous conversion mode and the DMA controller is configured in loop mode, the DMA controller automatically starts transmission from the buffer start address after each transmission is completed, and steps S3 to S6 are repeated until the collection is completed.
[0029] Through the alternation of upper and lower half buffer functions, one half is used for DMA data transmission and the other half is used for CPU data processing, and data transmission and data processing are executed in parallel. Since the DMA loop mode is used, the whole process does not need to pause DMA, and the data collection length is not limited, and uninterrupted ADC signal collection and processing can be realized. Every half buffer is collected and processed once, the data processing delay is M / 2Vc, and the single data processing time is M / 2Vp, which is better than the typical use method based on DMA.
[0030] Although the embodiments of the present application are described in actual schemes, but do not constitute a limitation on the meaning of the present application, for those skilled in the art, according to the modification of the embodiments and the combination with other schemes according to the present application are obvious.
Claims
1. A DMA-based uninterrupted ADC sampling method, comprising an ADC unit, a DMA unit, and a CPU unit, wherein the input terminal of the ADC unit is connected to a signal source, and the output terminal of the ADC unit communicates with the CPU unit through the DMA unit, wherein the DMA unit includes a DMA controller and a buffer manager connected to each other, characterized in that, The sampling method also includes the following specific steps: Step S1: Initialize the ADC unit, the DMA controller, and the buffer manager, wherein the ADC unit is configured in continuous conversion mode, the DMA controller is configured in cyclic mode, the buffer manager sets the buffer pointer and buffer size, and sets the upper half buffer flag and the lower half buffer flag to empty, and initializes the number of unprocessed semaphores in the half buffer to 0. Step S2: Start the continuous sampling conversion of the ADC unit, and the DMA controller transmits the converted data to the buffer manager; Step S3: When the data transmitted by the DMA controller is greater than half of the current buffer size, a DMA transfer half-interruption is generated. The interrupt signal is sent to the CPU unit. The CPU unit performs DMA transfer half-interruption processing. The DMA transfer half-interruption processing checks the lower half-buffer flag. If the lower half-buffer flag is empty, the flag is cleared and transmission continues. Then, a half-buffer pending signal is released. The operation of releasing the half-buffer semaphore in steps S4 and S3 wakes up the data processing thread. The data processing thread acquires the semaphore and processes the data in the upper half-buffer. When the data processing is completed, the upper half-buffer flag is set to empty, and the thread continues to wait for the half-buffer semaphore to be processed. Step S5: When the data transmitted by the DMA controller is greater than the current buffer size, a DMA transfer completion interrupt will be generated. The interrupt signal is sent to the CPU unit. The CPU unit performs DMA transfer completion interrupt processing. The DMA transfer completion interrupt processing checks the upper half buffer flag. If the upper half buffer flag is empty, the flag is cleared and the transmission continues. Then, a half buffer of semaphore is released for processing. In steps S6 and S3, the operation of releasing the half-buffer semaphore to be processed wakes up the data processing thread. The data processing thread acquires the semaphore and processes the data in the lower half-buffer. When the data processing is completed, the lower half-buffer flag is set to empty, and the thread continues to wait for the half-buffer semaphore to be processed. Step S7: Since the ADC unit is configured in continuous conversion mode and the DMA controller is configured in cyclic mode, the DMA controller will automatically start transmitting from the starting address of the buffer after each transmission is completed, repeating steps S3 to S6 until the acquisition ends.
2. The DMA-based uninterrupted ADC sampling method according to claim 1, characterized in that, When moving from step S2 to step S3, the data in the upper half buffer is cached first.
3. The DMA-based uninterrupted ADC sampling method according to claim 1, characterized in that: If the lower half buffer flag is not empty in step S3, it indicates a buffer overflow. In this case, the corresponding error handling function will be executed according to the specific situation.
4. The DMA-based uninterrupted ADC sampling method according to claim 1, characterized in that: If the upper half of the buffer is not empty in step S5, it indicates a buffer overflow. In this case, the corresponding error handling function will be executed according to the specific situation.
Citation Information
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