DAC circuit with ISI dynamic error detection and compensation

Abstract

A DAC circuit with dynamic ISI error detection and compensation comprises a subunit array composed of a plurality of DAC subunits, an ISI detection module, a comparator and a serial peripheral interface (SPI) module, the DAC subunit array receives digital signals and clock signals and outputs analog signals, the ISI detection module generates detection voltage according to the analog signals and outputs the detection voltage to the comparator, and the SPI module outputs the detection voltage to the comparator. And the comparator outputs an instruction to the SPI module according to the comparison result so as to control the compensation control of the subunit array. The method is realized by using a passive device independent of a Sigma-Delta analog-to-digital converter, so that rapid DAC static error detection and compensation and real-time DAC dynamic inter-symbol crosstalk error detection and compensation can be realized; a dynamic inter-symbol crosstalk error detection and compensation circuit is integrated in a DAC circuit, so that the on-chip dynamic inter-symbol crosstalk error detection and compensation function of the DAC is realized.

Description

Technical Field

[0001] The present invention relates to a technology in the field of digital-to-analog conversion, in particular to a DAC circuit with dynamic inter-symbol interference (ISI) error detection and compensation. Background Art

[0002] Analog-to-digital converters in the fields of wireless communications and radar detection are usually implemented using a continuous-time Sigma-Delta architecture. In order to achieve higher energy efficiency in the continuous-time Sigma-Delta architecture, a lower oversampling rate, multi-bit sub-quantizers, and multi-bit feedback digital-to-analog converters are usually used in the design. However, the dynamic performance of the multi-bit feedback digital-to-analog converter is limited by inter-symbol interference (ISI), which limits the performance of the analog-to-digital converter. Summary of the invention

[0003] In view of the deficiency that the prior art cannot realize background real-time ISI detection and calibration and on-chip automatic ISI detection and calibration, the present invention proposes a DAC circuit with dynamic ISI error detection and compensation, which is realized by using passive devices independent of a Sigma-Delta analog-to-digital converter, and can realize fast DAC static error detection and compensation, and real-time DAC dynamic inter-symbol crosstalk error detection and compensation; by integrating a dynamic inter-symbol crosstalk error detection and compensation circuit in a DAC circuit, the on-chip dynamic inter-symbol crosstalk error detection and compensation function of the DAC is realized.

[0004] The present invention is achieved through the following technical solutions:

[0005] The present invention relates to a DAC circuit with dynamic ISI error detection and compensation, comprising: a sub-unit array composed of a plurality of DAC sub-units, an ISI detection module, a comparator and a serial peripheral interface (SPI) module, wherein: the DAC sub-unit array receives a digital signal and a clock signal to output an analog signal, the ISI detection module generates a detection voltage according to the analog signal and outputs it to the comparator, and the comparator outputs an instruction to the SPI module according to the comparison result to control the compensation control of the sub-unit array.

[0006] The present invention relates to a dynamic ISI error detection and compensation method based on the above circuit, which performs ISI error detection reset and inter-symbol crosstalk error detection on a DAC subunit in sequence: in the reset stage, an output multi-way selection switch at the output of the detected DAC subunit connects the output node of the subunit to an ISI detection module to detect its output static error, and connects the N-type current source of the subunit to a common auxiliary N-type current source to calibrate the static error; in the inter-symbol crosstalk error detection stage, a passive integrator in the ISI detection module is used to save the dynamic inter-symbol crosstalk error generated when the switch in the DAC subunit is switched, and an ISI calibration module is controlled according to the output voltage of the passive integrator to calibrate the error caused by the inter-symbol crosstalk of the digital-to-analog converter. Technical Effects

[0007] The present invention uses a passive integrator in a DAC circuit to perform ISI error detection and calibration, and only uses a passive circuit and works independently of an analog-to-digital converter. Compared with the prior art, the loop delay in the Sigma-Delta analog-to-digital converter has little effect, the hardware overhead is small, and real-time DAC dynamic inter-code crosstalk error detection and compensation can be achieved. A 6-bit non-return-to-zero DAC prototype that can perform real-time dynamic inter-code crosstalk error detection and compensation. Compared with other architectures, the advantage of the present invention is that dynamic inter-code crosstalk error detection and compensation are independent of other modules, so the DAC does not rely on its application scenario, and dynamic inter-code crosstalk error detection and compensation can be performed. It has little effect on the loop delay in the Sigma-Delta analog-to-digital converter, the hardware overhead is small, and real-time DAC dynamic inter-code crosstalk error detection and compensation can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic diagram of the structure of the present invention;

[0009] Figure 2 It is the schematic diagram of the circuit related to ISI detection;

[0010] Figure 3 This is a schematic diagram of the ISI calibration module;

[0011] Figure 4 It is the signal relationship diagram of the ISI detection stage;

[0012] Figure 5 The following is a spectrum diagram of the test results of the embodiment. DETAILED DESCRIPTION

[0013] like Figure 1As shown, this embodiment relates to a DAC circuit with dynamic ISI error detection and compensation, including: a sub-unit array composed of 64 DAC sub-units, an ISI detection module, a comparator and a serial peripheral interface (SPI) module, wherein: the sub-unit array receives a digital signal and a clock signal to output an analog signal, the ISI detection module generates a detection voltage according to the analog signal and outputs it to the comparator, and the comparator outputs an instruction to the SPI module according to the comparison result to perform compensation control on the sub-unit array.

[0014] The digital signal is, but not limited to, a 64-bit thermometer code digital signal D in <63:0>, each DAC subunit receives a one-bit thermometer code digital signal.

[0015] The DAC subunit includes: a D flip-flop, an ISI calibration module, a switch driver, a current source module with a switch, and a multiplexer (MUX) connected in sequence, wherein: the D flip-flop controlled by a clock signal receives a one-bit digital signal and outputs an instruction S1 to the ISI calibration module to generate an instruction S2 for controlling the switch driver, and the switch driver then generates a switch drive signal S3 to control the switch of the current source module, and the analog signal S4 generated by the current source module is determined by the MUX to be output as an analog signal or output to the ISI detection module.

[0016] like Figure 2 As shown, the current source module includes: five transistors M1-M5, a P-type current source I1 and an N-type current source I2, wherein: the output end of the P-type current source I1 is connected to the transistors M1 and M2, the output end of the N-type current source I2 is connected to the third and fourth transistors M3 and M4, the first and third transistors M1 and M3 are connected to the first input end DAC of the multiplexer outp , the second and fourth transistors M2 and M4 are connected to the second input terminal DAC of the multiplexer outn .

[0017] The first to fourth transistors M1 - M4 control the output current of the P-type current source I1 and the N-type current source I2 to flow to the DAC outp Or DAC outn The ideal output current value of the P-type current source I1 is slightly greater than the output current of the N-type current source I2. For example, I1 ideally outputs a static current of 28.5uA, and I2 ideally outputs a static current of 27.5uA. The fifth transistor M5 is switched on and off according to the digital enable signal en_calibration. , controlling the output of the auxiliary N-type current source to be connected to the N-type current source of the i-th DAC sub-unit, so as to make the output current of the N-type current source equal to the output current of the P-type current source.

[0018] like Figure 2 As shown, the multiplexer includes: two selection outputs, wherein: the input of the multiplexer is DAC outp With DAC outn The two output ports of the multiplexer are connected to the output ports of the DAC out with ISI detection module.

[0019] like Figure 2 As shown, the ISI detection module includes: a sixth transistor M6 as an auxiliary N-type current source, a seventh transistor M7 and two capacitors C as passive integrators D With C ref , where: Storage capacitor C D and reference capacitor C ref Connected through the seventh transistor M7, the storage capacitor C D The detection voltage V CD , reference capacitor C ref The reference voltage V ref , detection voltage V CD With reference voltage V ref The size will be compared by the comparator with the reference voltage V ref The output current of the sixth transistor M6 serving as an auxiliary N-type current source is controlled.

[0020] like Figure 3 As shown, the ISI calibration module is composed of four transistors M8-M 11 The programmable output edge adjustment circuit is composed of a circuit that calibrates the ISI error by changing the rising edge and falling edge delay of the output signal S2, wherein: the ninth and tenth transistors M9 and M 10 The effective aspect ratio of the eighth and eleventh transistors M8 and M 11 The effective aspect ratio is determined by the binary code control word CTRL p <2:0> and CTRL n <2:0> control. For example, the control code CTRL p The larger the code value of <2:0>, the larger the effective aspect ratio of the eighth transistor M8. Binary code control word CTRL p <2:0> and CTRL n <2:0> is controlled by the SPI module.

[0021] The eighth and eleventh transistors M8 and M 11 The effective length-to-width ratio of the eighth transistor M8 determines the rising and falling edge delays of the output signal S2. The larger the effective length-to-width ratio of the eighth transistor M8, the smaller the rising edge delay of the output signal S2. 11 The smaller the effective aspect ratio is, the greater the delay of the falling edge of the output signal S2 is.

[0022] like Figure 4 As shown, this embodiment relates to a dynamic ISI error detection and compensation method based on the above circuit, and performs dynamic ISI error detection reset and inter-symbol interference error detection on the DAC sub-units in sequence.

[0023] The reset means that when the i-th DAC subunit enters the reset phase of dynamic ISI error detection, the enable signal en_cali Switch to high level, connect the auxiliary N-type current source (M6) to the DAC sub-unit, and control MUX to connect the output of this DAC sub-unit to the ISI detection module. The enable signal en_detect switches to high level, controls transistor M7 to turn on, and connects capacitor C D With C ref At the same time, the switch control signal D swp+ / - Switch to low level, switch control signal D swn+ / - Switch to high level, connect P-type current source I1 and N-type current source I2. Due to the device error of the actual circuit, the output current of current sources I1 and I2 will deviate from the ideal design value. The ideal output current value of I1 is slightly larger than I2, which ensures that the actual current I1 is still larger than I2. Since I1 is larger than I2, the current output of this DAC subunit will be given to capacitor C D and C ref Charging, voltage V CD and V ref will continue to increase. As the voltage V ref As the voltage C increases, the output current of the auxiliary N-type current source (M6) will gradually increase, gradually compensating for the difference in the current outputs of the current sources I1 and I2. When the sum of the current outputs of the current source I2 and the auxiliary N-type current source is equal to the output current of the current source I1, the circuit reaches a balanced state, and the voltage C D and C ref The voltage remains constant.

[0024] The dynamic ISI error detection means that the i-th DAC subunit enters the dynamic ISI error detection detection phase, during which the switch control signal D swp+ / - With D swn+ / - The digital signal D is input by the digital-to-analog converter in Control (eg: when D in is high level, then D swp+ is high level, D swp- is low level, D swn+ is high level, D swn- is low level). The enable signal en_detect switches to a low level, controlling the transistor M7 to be non-conductive, so that the capacitor C D With C ref The current sources I1 and I2 are connected to the capacitor C D Since the static error between current sources I1 and I2 has been compensated by the auxiliary N-type current source, when the input signal D in When the voltage V CD Remains unchanged. When the input signal D in When switching, the dynamic output error of the DAC subunit will cause the voltage V CD changes with the voltage V ref When the input signal D in The switching times increase, the voltage V CD With voltage V ref The difference between them will gradually increase. Then, the voltage V CD With voltage V ref , and get the relative relationship between the two. CD With voltage V ref The relative relationship between them can be used to calibrate the dynamic error generated by the digital-to-analog converter subunit through the ISI calibration module.

[0025] like Figure 5 As shown, this is the test spectrum of the device, which is obtained by a 2048-point fast Fourier transform (FFT) algorithm, and the test results are obtained by averaging 10 test results. It can be seen from the test results that after enabling dynamic ISI calibration, the second harmonic drops by about 6.3dB, the fourth harmonic drops by about 16dB, and the signal-to-noise-distortion ratio (SNDR) increases by about 5.2dB. The content of the present invention significantly improves the performance of the Sigma-Delta analog-to-digital converter prototype.

[0026] The above-mentioned specific implementation can be partially adjusted in different ways by those skilled in the art without departing from the principle and purpose of the present invention. The protection scope of the present invention shall be based on the claims and shall not be limited by the above-mentioned specific implementation. Each implementation scheme within its scope shall be subject to the constraints of the present invention.

Claims

1. A DAC circuit with dynamic ISI error detection and compensation, characterized in that: include: A sub-unit array composed of several DAC sub-units, an ISI detection module, a comparator and a serial peripheral interface (SPI) module, wherein: the DAC sub-unit array receives a digital signal and a clock signal and outputs an analog signal, the ISI detection module generates a detection voltage according to the analog signal and outputs it to the comparator, and the comparator outputs an instruction to the SPI module according to the comparison result to control the compensation control of the sub-unit array.

2. The DAC circuit with dynamic ISI error detection and compensation according to claim 1, characterized in that: The DAC subunit includes: a D flip-flop, an ISI calibration module, a switch driver, a current source module with a switch, and a multiplexer (MUX) connected in sequence, wherein: the D flip-flop controlled by a clock signal receives a one-bit digital signal and outputs an instruction to the ISI calibration module to generate an instruction to control the switch driver, and the switch driver then generates a switch drive signal to control the switch of the current source module. The analog signal generated by the current source module is determined by the MUX to be output as an analog signal or output to the ISI detection module.

3. The DAC circuit with dynamic ISI error detection and compensation according to claim 2, characterized in that: The ISI calibration module is a programmable output edge adjustment circuit, which calibrates the ISI error by changing the rising edge and falling edge delay of the signal outputted by it.

4. The DAC circuit with dynamic ISI error detection and compensation according to claim 1, characterized in that: The current source module includes: five transistors, a P-type current source and an N-type current source, wherein: the output end of the P-type current source is respectively connected to the first and second transistors, the output end of the N-type current source is respectively connected to the third and fourth transistors, the first and third transistors are respectively connected to the first input end of the multiplexer, and the second and fourth transistors are respectively connected to the second input end of the multiplexer.

5. The DAC circuit with dynamic ISI error detection and compensation according to claim 1, characterized in that: The ISI detection module includes: a sixth transistor and a seventh transistor as auxiliary N-type current sources and two storage capacitors and a reference capacitor as passive integrators, wherein: the storage capacitor and the reference capacitor are connected through the seventh transistor, the detection voltage is stored on the storage capacitor, and the reference voltage is stored on the reference capacitor. The magnitude of the detection voltage and the reference voltage will be compared through a comparator, and the reference voltage controls the output current magnitude of the sixth transistor as an auxiliary N-type current source.

6. The DAC circuit with dynamic ISI error detection and compensation according to claim 1, characterized in that: The ISI calibration module is a programmable output edge adjustment circuit composed of four transistors, which calibrates the ISI error by changing the rising edge and falling edge delay of the output signal, wherein: the effective aspect ratio of the ninth and tenth transistors is fixed, and the effective aspect ratio of the eighth and eleventh transistors is controlled by binary code control words respectively.

7. A dynamic ISI error detection and compensation method based on the circuit described in any one of claims 1 to 6, characterized in that: The DAC subunit is sequentially subjected to ISI error detection reset and inter-symbol crosstalk error detection: in the reset stage, the output multiplexer at the output of the detected DAC subunit connects the output node of the subunit to the ISI detection module to detect its output static error, and the N-type current source of the subunit is connected to a common auxiliary N-type current source to calibrate the static error; in the inter-symbol crosstalk error detection stage, the dynamic inter-symbol crosstalk error generated when the switch in the DAC subunit is switched is saved by the passive integrator in the ISI detection module, and the error caused by the inter-symbol crosstalk of the digital-to-analog converter is calibrated according to the output voltage of the passive integrator by controlling the ISI calibration module.

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