Communication device, data transmission method and chip

Abstract

The invention provides a communication device, a data transmission method and a chip, relates to the technical field of communication, and is used for reducing time delay deviation between different paths during multi-channel transmission and improving the precision of deviation adjustment. The communication device comprises a time delay processing circuit and a plurality of transmission circuits, and a receiving circuit of each transmission circuit is used for receiving channel data, sending a marking signal to the time delay processing circuit and sending the marking signal and the channel data to a sending circuit; the sending circuit of each transmission circuit is used for receiving the marking signal and the channel data, sending the marking signal to the time delay processing circuit, and sending the channel data according to a sending clock; and the time delay processing circuit is used for determining the time delay deviation among the channel data transmitted by the plurality of transmission circuits according to the mark signals transmitted by the receiving circuits and the transmitting circuits of the plurality of transmission circuits, and adjusting the transmitting clock of at least one transmission circuit according to the time delay deviation.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a communication device, a data transmission method and a chip. Background Art

[0002] In the field of communication technology, there is usually a scenario where two communication devices transmit data through a relay device, and any communication device and the relay device transmit data through multiple channels. In addition, when transmitting data through multiple channels, there are usually certain requirements for the delay deviation (skew) between multiple channels, otherwise the delay deviation is large and will cause transmission failure. At present, when the data of multiple channels passes through a relay device, the relay device processes it independently based on the channel. For example, the data of each channel is cached and clock tracked separately, and the data cache and clock tracking between different channels are not related, which leads to a certain delay deviation of the data of multiple channels when passing through the relay device. Summary of the invention

[0003] The present application provides a communication device, a data transmission method and a chip for reducing the delay deviation between different paths during multi-channel transmission and improving the accuracy of deviation adjustment.

[0004] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, a communication device is provided, which includes: a delay processing circuit, and multiple transmission circuits coupled to the delay processing circuit, the multiple transmission circuits corresponding to multiple channels one by one, and each transmission circuit in the multiple transmission circuits including a receiving circuit and a transmitting circuit; the receiving circuit of each transmission circuit is used to receive channel data of the corresponding channel, and send a mark signal to the delay processing circuit, and send the mark signal and the channel data to the transmitting circuit in the transmission circuit; the transmitting circuit of each transmission circuit is used to receive the mark signal and the channel data, send the mark signal to the delay processing circuit, and send the channel data according to a transmitting clock; the delay processing circuit is used to determine the delay deviation between the channel data transmitted by the multiple transmission circuits according to the mark signal sent by the receiving circuit and the transmitting circuit of the multiple transmission circuits, and adjust the transmitting clock of at least one transmission circuit in the multiple transmission circuits according to the delay deviation.

[0006] In the above technical solution, when receiving channel data, the receiving circuit of each transmission circuit will send a mark signal to the delay processing circuit, and send the mark signal and the data to the sending circuit of the transmission circuit. When receiving the mark signal and the channel data, the sending circuit of each transmission circuit will also send the mark signal to the delay processing circuit. In this way, the delay processing circuit can perform end-to-end measurement on the transmitted channel data according to the mark signal transmitted by the receiving circuit and the sending circuit of each transmission circuit to determine the delay deviation between different channel data, and adjust the delay of the path where the channel data of multiple channels are located according to the delay deviation, or adjust the delay of the channel data transmitted by at least one transmission circuit among the multiple transmission circuits, that is, the delay deviation between the transmission paths corresponding to the channel data of the multiple channels, so as to reduce the delay deviation between different paths and improve the accuracy of deviation adjustment.

[0007] In a possible implementation of the first aspect, the multiple channels are multiple channels bound in the same port, that is, the multiple channels are bound in a certain manner for transmitting data in the form of multiple channels. Optionally, the port can be a high-speed data port, so that the channel data transmitted by each channel can also be high-speed data or high-speed data signals.

[0008] In a possible implementation of the first aspect, the marker signal is sent periodically; and / or the period of sending the marker signal is configurable. In the above possible implementation, by periodically sending the marker signal, the transmitted channel data can be effectively measured end-to-end, while improving the accuracy of the measured delay of the communication data.

[0009] In a possible implementation of the first aspect, the receiving circuit of each transmission circuit includes: a deserializer and a measurement trigger circuit; the deserializer is used to receive serial channel data and convert the serial channel data into parallel channel data; the measurement trigger circuit is used to generate the mark signal and send the mark signal to the deserializer and the delay processing circuit; the deserializer is also used to receive the mark signal and send the mark signal and the channel data to the transmission circuit. In the above possible implementation, the delay processing circuit can perform end-to-end measurement on the transmitted channel data, while improving the accuracy of the measured delay of the communication data.

[0010] In a possible implementation of the first aspect, the delay processing circuit includes: a delay measurement circuit and a delay adjustment circuit; the delay measurement circuit is used to determine the delay of the channel data transmitted by the transmission circuit according to the mark signal sent by the receiving circuit and the sending circuit of each transmission circuit; the delay adjustment circuit is used to determine the delay deviation between the channel data transmitted by the multiple transmission circuits according to the delay of the channel data transmitted by the multiple transmission circuits, and adjust the transmission clock of at least one transmission circuit among the multiple transmission circuits according to the delay deviation. In the above possible implementation, by adjusting the transmission clock of at least one transmission circuit among the multiple transmission circuits, the delay deviation between different paths can be reduced and the accuracy of deviation adjustment can be improved.

[0011] In a possible implementation of the first aspect, the delay adjustment circuit is further used to: determine the at least one transmission circuit and output delay adjustment information according to the delay deviation between the channel data transmitted by the multiple transmission circuits, and the delay adjustment information is used to adjust the transmission clock of the at least one transmission circuit. In the above possible implementation, by adjusting the transmission clock of at least one transmission circuit among the multiple transmission circuits, the delay deviation between different paths can be reduced and the accuracy of deviation adjustment can be improved.

[0012] In a possible implementation of the first aspect, each transmission circuit further includes a clock tracking circuit; the clock tracking circuit is used to receive the delay adjustment information and output clock information according to the delay adjustment information, and the clock information is used to adjust the transmission clock of the transmission circuit. In the above possible implementation, by adjusting the transmission clock of the transmission circuit, the delay deviation between different paths can be reduced and the accuracy of the deviation adjustment can be improved.

[0013] In a second aspect, a data transmission method is provided, which is applied to a communication device, wherein the communication device includes: a delay processing circuit, and multiple transmission circuits coupled to the delay processing circuit, the multiple transmission circuits correspond one-to-one to multiple channels, and each transmission circuit in the multiple transmission circuits includes a receiving circuit and a transmitting circuit; the method includes: the receiving circuit of each transmission circuit receives channel data of the corresponding channel, and sends a mark signal to the delay processing circuit, and sends the mark signal and the channel data to the transmitting circuit in the transmission circuit; the transmitting circuit of each transmission circuit receives the mark signal and the channel data, sends the mark signal to the delay processing circuit, and sends the channel data according to a transmitting clock; the delay processing circuit determines the delay deviation between the channel data transmitted by the multiple transmission circuits according to the mark signal sent by the receiving circuit and the transmitting circuit of the multiple transmission circuits, and adjusts the transmitting clock of at least one transmission circuit in the multiple transmission circuits according to the delay deviation.

[0014] In a possible implementation manner of the second aspect, the multiple channels are multiple channels bound in the same port; and / or the mark signal is sent periodically; and / or the period for sending the mark signal is configurable.

[0015] In a possible implementation of the second aspect, the receiving circuit of each transmission circuit includes a deserializer and a measurement trigger circuit; the receiving circuit of each transmission circuit receives channel data of the corresponding channel, and sends a mark signal to the delay processing circuit, and sends the mark signal and the channel data to the transmitting circuit in the transmission circuit, including: the deserializer receives serial channel data and converts the serial channel data into parallel channel data; the measurement trigger circuit generates the mark signal and sends the mark signal to the deserializer and the delay processing circuit; the deserializer receives the mark signal, and sends the mark signal and the channel data to the transmitting circuit.

[0016] In a possible implementation of the second aspect, the delay processing circuit includes a delay measurement circuit and a delay adjustment circuit; the delay processing circuit determines the delay deviation between channel data transmitted by the multiple transmission circuits according to the mark signal sent by the receiving circuit and the sending circuit of the multiple transmission circuits, and adjusts the sending clock of at least one transmission circuit among the multiple transmission circuits according to the delay deviation, including: the delay measurement circuit determines the delay of the channel data transmitted by the transmission circuit according to the mark signal sent by the receiving circuit and the sending circuit of each transmission circuit; the delay adjustment circuit determines the delay deviation between the channel data transmitted by the multiple transmission circuits according to the delay of the channel data transmitted by the multiple transmission circuits, and adjusts the sending clock of at least one transmission circuit among the multiple transmission circuits according to the delay deviation.

[0017] In a possible implementation of the second aspect, the delay adjustment circuit adjusts the transmission clock of at least one transmission circuit among the multiple transmission circuits according to the delay deviation, including: the delay adjustment circuit determines the at least one transmission circuit and outputs delay adjustment information according to the delay deviation between channel data transmitted by the multiple transmission circuits, and the delay adjustment information is used to adjust the transmission clock of the at least one transmission circuit.

[0018] In a possible implementation of the second aspect, each transmission circuit also includes a clock tracking circuit; the method also includes: the clock tracking circuit receives the delay adjustment information, outputs clock information according to the delay adjustment information, and the clock information is used to adjust the transmission clock of the transmission circuit.

[0019] According to a third aspect, a chip is provided, comprising a packaging substrate and a communication device disposed on the packaging substrate, wherein the communication device is the communication device provided by the first aspect or any possible implementation of the first aspect.

[0020] In another aspect of the present application, a computer-readable storage medium is provided, in which a computer program or instruction is stored. When the computer program or instruction is executed, the data transmission method provided by the first aspect or any possible implementation of the first aspect is implemented.

[0021] In another aspect of the present application, a computer program product is provided, which includes: a computer program (also referred to as code, or instruction), which, when executed, enables a computer to execute a data transmission method provided in the first aspect or any possible implementation of the first aspect.

[0022] It can be understood that the beneficial effects that can be achieved by any of the data transmission methods, chips, computer-readable storage media and computer program products provided above can correspond to the beneficial effects in the communication device provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the structure of a communication system provided in an embodiment of the present application;

[0024] Figure 2 A schematic diagram of transmitting data through multiple channels provided in an embodiment of the present application;

[0025] Figure 3 A schematic diagram of another embodiment of the present application providing data transmission through multiple channels;

[0026] Figure 4 A schematic diagram of the structure of a communication device provided in an embodiment of the present application;

[0027] Figure 5 A schematic diagram of the structure of a communication device provided in an embodiment of the present application;

[0028] Figure 6 A flowchart of a data transmission method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0030] In the present application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, a and b, a and c, b and c, a, b and c; where a, b and c can be single or plural.

[0031] The embodiments of the present application use words such as "first" and "second" to distinguish objects with similar names, functions or effects. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity and execution order. The term "coupled" is used to indicate electrical connection, including direct connection through wires or connection terminals or indirect connection through other devices. Therefore, "coupled" should be regarded as a broad electronic communication connection.

[0032] In this application, the words "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the words "exemplary" or "for example" is intended to present the related concepts in a concrete way.

[0033] Before introducing the embodiments of the present application, the technical terms and application scenarios involved in the present application are first introduced and explained.

[0034] Lane: It can refer to a path for transmitting signals. The lane can support unidirectional transmission or bidirectional transmission. When the lane supports unidirectional transmission, the lane can include a pair of differential signal lines; when the lane supports bidirectional transmission, the lane can include two pairs of differential signal lines.

[0035] Port: may refer to a physical port used for connecting and communicating between devices, and the physical port may also be referred to as an interface. Among them, a port may include multiple channels, and multiple channels in the same port may be bound together for data transmission. Optionally, the port may include but is not limited to: Ethernet port, optical communication port, universal serial bus (USB) port, high definition multimedia interface port (HDMI), miniHDMI port, micro HDMI port, display port (DP), unified multimedia interconnection (UMMI) port, high-speed serial computer expansion bus (Peripheral Component Interconnect Express, PCIE) port, type A (type-A) port, type B (type-B) port and type C (type-C) port, etc.

[0036] Skew: refers to the delay skew between data transmitted in multiple channels when data is transmitted through the multiple channels. The delay skew can also be called propagation delay difference.

[0037] De-skew: De-skew refers to the process of adjusting and compensating multiple channels to ensure that the receiving end can correctly receive and process data from multiple channels when there is a certain delay deviation between the channels. De-skew can also be called multi-channel alignment or delay deviation adjustment.

[0038] The technical solution provided in the present application can be applied to a communication system supporting transmission through multiple channels, and the communication system may include multiple devices, and the multiple devices may be connected through transmission media such as optical fibers or cables. Optionally, each of the multiple devices may include a port (or interface), and the port may include multiple channels. The ports of the multiple devices may also be connected through a transmission medium, and data may be transmitted through multiple channels in the port. For ease of understanding, the structure of the communication system is illustrated below by taking the multiple devices including three devices, and the three devices including a sending device, a relay device, and a receiving device as an example.

[0039] Figure 1A schematic diagram of the structure of a communication system provided in an embodiment of the present application. The communication system includes a sending device 110, a relay device 120 and a receiving device 130. The sending device 110 and the relay device 120, as well as the relay device 120 and the receiving device 130 are connected via a transmission medium. The sending device 110 can send data to the relay device, and the relay device 120 can send received data to the receiving device 130.

[0040] In the communication system, multiple channels may be included between the sending device 110 and the relay device 120, and between the relay device 120 and the receiving device 130. The sending device 110 may send user data to the relay device 120 through the multiple channels, such as sending user data on the multiple channels in a serial manner. When the relay device 120 receives the data of the multiple channels, it may perform clock data recovery and cache processing on the data of the multiple channels respectively, and then send the data of the multiple channels to the receiving device 130. Optionally, the relay device 120 may also adjust the delay of the multiple channels to ensure that the delay of the multiple channels is as consistent as possible. When the receiving device 130 receives the data of the multiple channels, it performs clock data recovery on the data of the multiple channels, aligns the data of the multiple channels, and then uniformly parses the user data according to the agreed protocol.

[0041] In a possible embodiment, the sending device 110 includes a first port, the relay device 120 includes a second port, the first port of the sending device 110 and the second port of the relay device 120 both include multiple channels and are connected in a one-to-one correspondence, and the sending device 110 can send user data to the relay device 120 through the multiple channels. Similarly, the relay device 120 can also include a third port, the receiving device 130 can include a fourth port, the third port of the relay device 120 and the fourth port of the receiving device 130 can also both include multiple channels and are connected in a one-to-one correspondence, and the relay device 120 sends data in the multiple channels to the receiving device 130 through the multiple channels.

[0042] It is understandable that the above Figure 1 In the example, the transmission device 110 and the relay device 120 include 4 channels, the relay device 120 and the transmission device 110 include 4 channels, and the 4 channels are represented as channel 0 to channel 3. Figure 1 The structure of the communication system shown is merely exemplary and does not constitute a limitation to the embodiments of the present application.

[0043] In the related art, when the data of the above-mentioned multiple channels pass through the relay device 120, the relay device 120 performs independent processing based on the channel. For example, the data of each channel is cached and clock tracked separately, and the data caching and clock tracking between different channels are not related, which leads to a certain delay deviation in the data of multiple channels when passing through the relay device.

[0044] For example, Figure 2 As shown, taking the case where the multiple channels include two channels represented as 0 and 1 as an example, the relay device may include a clock and data recovery (CDR) chip, and the CDR chip may include: a deserializer 0, a data buffer module 0, a clock tracking module 0, and a serializer 0 corresponding to channel 0, and a deserializer 1, a data buffer module 1, a clock tracking module 1, and a serializer 1 corresponding to channel 1. Specifically, the deserializer 0 is used to receive data from channel 0, obtain the recovered clock of the data, and perform serial-to-parallel conversion on the data and store it in the data buffer module 0; the clock tracking module 0 is used to output the first clock information according to the recovered clock of the data; the serializer 0 is used to perform parallel-to-serial conversion on the data in the data buffer module 0, and send the converted data according to the first sending clock generated by the first clock information. The deserializer 1 is used to receive data from channel 1, obtain the recovered clock of the data, and store the data in the data cache module 1 after serial-to-parallel conversion; the clock tracking module 1 is used to output second clock information according to the recovered clock of the data; the serializer 1 is used to perform parallel-to-serial conversion on the data in the data cache module 1, and send the converted data according to the second sending clock generated by the second clock information.

[0045] The data of channel 0 and the data of channel 1 are stored in data cache module 0 and data cache module 1 respectively, that is, the data caches of the two channels are unrelated, and the corresponding caches will have different depths, so that the cache delays of the two channels are inconsistent, resulting in an increase in the delay deviation of the two channels; in addition, the clock phases of the two channels are inconsistent, with a maximum difference of one clock cycle of parallel data, which also causes the delay deviation of the two channels to increase by one clock cycle of parallel data.

[0046] In addition, the related art also proposes a solution for adjusting the delay deviation of multiple channels, specifically, by associating the watermark of the data cache (i.e., the preset cache depth threshold) with the clock tracking module of the same channel. When the depth of the data cache of a certain channel exceeds the fixed watermark, the corresponding sending clock is adjusted through the clock tracking module of the channel, that is, the sending clock corresponding to the channel is adjusted to make the cache depths of the multiple channels the same. For example, Figure 3As shown, a fixed waterline is set for data cache module 0 and data cache module 1, data cache module 0 is associated with clock tracking module 0, and data cache module 1 is associated with clock tracking module 1.

[0047] The above scheme can only be adjusted based on the waterline of the data cache, and the adjustment granularity is a cache depth unit, which corresponds to a clock cycle. The delay deviation within a clock cycle cannot be adjusted, that is, the path delay deviation outside the cache and the phase deviation of the sending clock cannot be adjusted.

[0048] Based on this, an embodiment of the present application provides a communication device and a data transmission method applied to the communication device, wherein the communication device can perform end-to-end measurement of the channel data of each channel in a plurality of channels, and adjust the delay deviation between the plurality of channels according to the measurement result, so as to adjust the delay of the path where the channel data of the plurality of channels are located, and reduce the delay deviation between different paths. The scheme can improve the deviation measurement accuracy between the plurality of channels, and improve the accuracy of the deviation adjustment. Exemplarily, the communication device can reduce the delay deviation between the plurality of channels from tens of nanoseconds (ns) to hundreds of picoseconds (ps). The technical scheme of the embodiment of the present application is described in detail below.

[0049] Figure 4 A structural schematic diagram of a communication device provided for an embodiment of the present application. The communication device may be a device, for example, the communication device may be a network device or a relay device; or, the communication device may be a chip applied to a device, for example, the communication device may be a CDR chip. The communication device may include: a delay processing circuit 10, and a plurality of transmission circuits 20 coupled to the delay processing circuit 10, the plurality of transmission circuits 20 corresponding one-to-one to a plurality of channels, and each transmission circuit in the plurality of transmission circuits 20 includes a receiving circuit RX and a transmitting circuit TX. Among them, the plurality of channels may be a plurality of channels bound to the same port, that is, the plurality of channels are bound together for transmitting data in the form of multiple channels. Optionally, the port may be a high-speed data port, so that the channel data transmitted by each channel may also be high-speed data or a high-speed data signal.

[0050] Above Figure 4 In the figure, it is taken as an example that the multiple channels include a first channel and a second channel, the multiple transmission circuits 20 include a first transmission circuit 21 corresponding to the first channel, and a second transmission circuit 22 corresponding to the second channel, the first transmission circuit 21 includes a first receiving circuit RX1 and a first transmitting circuit TX1, and the second transmission circuit 22 includes a second receiving circuit RX2 and a second transmitting circuit TX2.

[0051] In the communication device, the receiving circuit RX of each transmission circuit can be used to: receive the channel data of the corresponding channel, send a mark signal to the delay processing circuit, and send the mark signal and the channel data to the transmitting circuit TX in the transmission circuit. Optionally, the receiving circuit RX of each transmission circuit can send the mark signal and the channel data to the transmitting circuit TX at the same time through different signal lines.

[0052] Optionally, the marking signal may be sent periodically. That is, the receiving circuit RX of each transmission circuit may also be used to periodically send the marking signal to the delay processing circuit 10, and periodically send the marking signal to the transmitting circuit TX in the transmission circuit. The period of sending the marking signal may be configured. For example, the period may be configured through configuration information, so that the receiving circuit RX of each transmission circuit may be used to obtain the configuration information and send the marking signal according to the period configured by the configuration information.

[0053] Optionally, the marker signal of each transmission circuit may be sent periodically according to the recovered clock of the transmission circuit; or, the marker signal of each transmission circuit may be sent periodically according to the reference clock. The recovered clock and the reference clock may be co-source clocks, that is, the recovered clock and the reference clock may correspond to the same clock source.

[0054] Exemplarily, in the first transmission circuit 21, the first receiving circuit RX1 is used to receive the channel data D1 of the first channel, obtain the recovery clock rxclk1 corresponding to the channel data D1, and send the first mark signal S1 to the delay processing circuit, and send the first mark signal S1 and the channel data D1 to the first transmitting circuit TX1. Similarly, in the second transmission circuit 22, the second receiving circuit RX2 is used to receive the channel data D2 of the second channel, obtain the recovery clock rxclk2 corresponding to the channel data D2, and send the second mark signal S2 to the delay processing circuit, and send the second mark signal S2 and the channel data D2 to the second transmitting circuit TX2.

[0055] In the communication device, the transmission circuit TX of each transmission circuit can be used to: receive the mark signal and the channel data, send the mark signal to the delay processing circuit 10, and send the channel data according to the transmission clock. Optionally, the transmission clock of each transmission circuit can be generated according to the recovery clock of the transmission circuit, or the transmission clock can track the recovery clock, or the transmission clock is generated according to the clock tracking information of the recovery clock, and the embodiment of the present application does not impose specific restrictions on this.

[0056] Exemplarily, in the first transmission circuit 21, the first transmission circuit TX1 is used to receive the first mark signal S1 and the channel data D1, and send the first mark signal S1 to the delay processing circuit, and send the channel data D1 according to the first transmission clock txclk1. Similarly, in the second transmission circuit 22, the second transmission circuit TX2 is used to receive the second mark signal S2 and the channel data D2, send the second mark signal S2 to the delay processing circuit, and send the channel data D2 according to the second transmission clock txclk2.

[0057] In the communication device, the delay processing circuit 10 can be used to determine the delay deviation between the channel data transmitted by the multiple transmission circuits 20 according to the mark signals sent by the receiving circuit RX and the sending circuit TX of the multiple transmission circuits 20, and adjust the sending clock of at least one transmission circuit among the multiple transmission circuits 20 according to the delay deviation.

[0058] The at least one transmission circuit may include one or more transmission circuits. The at least one transmission circuit may include some transmission circuits among the multiple transmission circuits 20 (i.e., adjusting the transmission clocks of some transmission circuits among the multiple transmission circuits), or include all transmission circuits (i.e., adjusting the transmission clocks of all transmission circuits among the multiple transmission circuits), which is not specifically limited in the embodiments of the present application.

[0059] Optionally, the at least one transmission circuit includes one or more transmission circuits with larger delay among the multiple transmission circuits 20, that is, the one or more transmission circuits with larger delay among the multiple transmission circuits are adjusted so that the delay of the one or more transmission circuits with larger delay is consistent with the delay of the transmission circuit with smaller delay.

[0060] In addition, the delay deviation between the channel data transmitted by the multiple transmission circuits 20 may refer to the delay determined according to the channel data transmitted by the multiple transmission circuits 20. The delay deviation between the channel data transmitted by the multiple transmission circuits 20 may also be referred to as the delay deviation between the multiple channels, or as the delay deviation between the multiple transmission circuits. In one example, the delay deviation between the multiple transmission circuits 20 may be the difference between the delay corresponding to the multiple transmission circuits 20 and the delay corresponding to the reference transmission circuit, and the reference transmission circuit may be the transmission circuit with the smallest delay among the multiple transmission circuits, or any one of the multiple transmission circuits. In another example, the delay deviation between the multiple transmission circuits 20 may be the difference between the delay corresponding to the multiple transmission circuits 20 and a certain reference delay.

[0061] Exemplarily, the multiple transmission circuits 20 include 8 transmission circuits. Assuming that the delays corresponding to the 8 transmission circuits are different and the delay corresponding to the first transmission circuit is the smallest, the at least one transmission circuit may include 7 transmission circuits (i.e., the second transmission circuit to the eighth transmission circuit). The delay deviation of each of the 7 transmission circuits relative to the first transmission circuit may specifically be: the difference between the delay corresponding to the transmission circuit and the delay corresponding to the first transmission circuit.

[0062] Furthermore, adjusting the transmission clock of at least one transmission circuit among the multiple transmission circuits 20 may specifically refer to: adjusting the delay of the channel data transmitted by at least one transmission circuit among the multiple transmission circuits 20, that is, adjusting the delay deviation between the channel data transmitted by the multiple transmission circuits 20, or adjusting the delay deviation between the transmission paths corresponding to the channel data of the multiple channels, so as to reduce the delay deviation between different paths. The adjustment accuracy of the above-mentioned delay deviation depends on the accuracy of the transmission clock of the transmission circuit, so that this solution can greatly provide the adjustment accuracy compared with the solution in the related art, that is, this solution has a very high adjustment accuracy.

[0063] Optionally, for each transmission circuit, the delay processing circuit 10 can record the sending time when receiving the marking signal sent by the receiving circuit RX in the transmission circuit, and can record the receiving time when receiving the marking signal sent by the transmitting circuit TX in the transmission circuit, and determine the delay of the channel data transmitted in the transmission circuit according to the sending time and the receiving time (that is, the path delay is calculated by the start time and the end time of the channel data in the corresponding transmission path). Among them, the recorded time information can be called a timestamp, for example, recording the sending time to obtain the sending timestamp, and recording the receiving time to obtain the receiving timestamp. Afterwards, the delay processing circuit 10 can determine the delay deviation between the channel data transmitted by the multiple transmission circuits 20 according to the delay of the channel data transmitted by the multiple transmission circuits.

[0064] Exemplarily, the delay processing circuit 10 may be used to: record the sending time A0 when receiving the first mark signal S1 sent by the first receiving circuit RX1, record the receiving time A0' when receiving the first mark signal S1 sent by the first transmitting circuit TX1, and determine the delay dly0 of the channel data D1 transmitted by the first transmission circuit 21 according to the sending time A0 and the receiving time A0'. Similarly, the delay processing circuit 10 may also be used to: record the sending time A1 when receiving the second mark signal S2 sent by the second receiving circuit RX2, record the receiving time A1' when receiving the second mark signal S2 sent by the second transmitting circuit TX2, and determine the delay dly1 of the channel data D2 transmitted by the second transmission circuit 22 according to the sending time A1 and the receiving time A1'. Afterwards, the delay processing circuit 10 may determine the delay deviation between the channel data D1 transmitted by the first transmission circuit 21 and the channel data D2 transmitted by the second transmission circuit 22 according to the delays dly0 and dly1, for example, the delay deviation between the second transmission circuit 22 and the first transmission circuit 21 is dly1-dly0.

[0065] Optionally, the delay processing circuit 10 can also be used to: quantify the delay of the channel data transmitted by each transmission circuit. For example, the delay processing circuit 10 can be used to quantify the delay dly0 corresponding to the first transmission circuit 21 into first delay information based on a certain time unit, and quantify the delay dly1 corresponding to the second transmission circuit 22 into second delay information based on a corresponding time unit, and then determine the delay deviation between the second transmission circuit 22 and the first transmission circuit 21 according to the first delay information and the second delay information.

[0066] Further, combined with Figure 4 ,like Figure 5 As shown, the receiving circuit RX of each transmission circuit may include: a deserializer and a measurement trigger circuit. Optionally, the sending circuit TX of each transmission circuit may include: a serializer.

[0067] In the receiving circuit RX of each transmission circuit, the deserializer can be used to: receive serial channel data, and convert the serial channel data into parallel channel data. The measurement trigger circuit can be used to: generate the mark signal, and send the mark signal to the deserializer and the delay processing circuit, such as periodically generating the mark signal according to the recovery clock. The deserializer can also be used to: receive the mark signal, and send the mark signal and the channel data to the transmission circuit TX of the transmission circuit, such as merging the mark signal and the channel data and sending them to the transmission circuit TX, so that the mark signal can be transmitted to the transmission circuit TX along with the channel data, that is, the mark signal runs through the receiving side to the transmitting side of the channel data in the transmission circuit. Correspondingly, in the transmission circuit TX of each transmission circuit, the serializer can be used to: receive the mark signal and the parallel channel data, convert the received parallel channel data into serial channel data, and send the serial channel data according to the transmission clock. Optionally, the deserializer is also used to: obtain the recovery clock corresponding to the channel data, and the recovery clock can refer to the clock for sending the channel data recovered by the deserializer from the channel data.

[0068] Optionally, the deserializer includes a serial receiving interface, through which the deserializer can receive serial channel data; the serializer includes a serial transmitting interface, through which the serializer can send the serial channel data to the outside.

[0069] Above Figure 5 In the description, the first receiving circuit RX1 includes a first deserializer 211 and a first measurement trigger circuit 212, the second receiving circuit RX2 includes a second deserializer 221 and a second measurement trigger circuit 222, the first transmitting circuit TX1 includes a first serializer 213, and the second transmitting circuit TX2 includes a second serializer 223.

[0070] Exemplarily, the first deserializer 211 is used to: receive the serial channel data D1 of the first channel, convert the serial channel data D1 into parallel channel data D1, and obtain the recovery clock rxclk1 corresponding to the channel data D1, and send the recovery clock rxclk1 to the first measurement trigger circuit 212. The first measurement trigger circuit 212 is used to: receive the recovery clock rxclk1, and periodically generate a first mark signal S1 according to the recovery clock rxclk1, and send the first mark signal S1 to the first deserializer 211 and the delay processing circuit 10. The first deserializer 211 is also used to: receive the first mark signal S1, and send the first mark signal S1 and the parallel channel data D1 to the first transmitting circuit TX1, for example, merge the first mark signal S1 and the parallel channel data D1 and send them to the first transmitting circuit TX1. The first transmitting circuit TX1 is used to receive the first marking signal S1 and parallel channel data D1, convert the received parallel channel data D1 into serial channel data D1, send the serial channel data D1 according to the transmitting clock, and send the first marking signal S1 to the delay processing circuit.

[0071] Similarly, the second deserializer 221 is used to receive the serial channel data D2 of the second channel, convert the serial channel data D2 into parallel channel data D2, obtain the recovery clock rxclk2 corresponding to the channel data D2, and send the recovery clock rxclk2 to the second measurement trigger circuit 222. The second measurement trigger circuit 222 is used to receive the recovery clock rxclk2, and periodically generate a second mark signal S2 according to the recovery clock rxclk2, and send the first mark signal S1 to the second deserializer 221 and the delay processing circuit 10. The second deserializer 221 is also used to receive the second mark signal S2, and send the second mark signal S2 and the parallel channel data D2 to the second transmitting circuit TX2, for example, the second mark signal S2 and the parallel channel data D2 are combined and sent to the second transmitting circuit TX2. The second transmitting circuit TX2 is used to: receive the second marking signal S2 and parallel channel data D2, convert the received parallel channel data D2 into serial channel data D2, send the serial channel data D2 according to the transmitting clock, and send the second marking signal S2 to the delay processing circuit 10.

[0072] Further, such as Figure 5 As shown, the delay processing circuit 10 may include: a delay measurement circuit 101 and a delay adjustment circuit 102 .

[0073] In the delay processing circuit 10, the delay measurement circuit 101 can be used to determine the delay of the channel data transmitted by the transmission circuit according to the mark signal sent by the receiving circuit RT and the transmitting circuit TX of each transmission circuit. The delay adjustment circuit 102 can be used to determine the delay deviation between the channel data transmitted by the multiple transmission circuits 20 according to the delay of the channel data transmitted by the multiple transmission circuits, and adjust the transmission clock of at least one transmission circuit in the multiple transmission circuits 20 according to the delay deviation.

[0074] In a possible embodiment, the delay adjustment circuit 102 is used to adjust the transmission clock of at least one transmission circuit among the multiple transmission circuits 20 according to the delay deviation, which may specifically include: the delay adjustment circuit 102 is used to determine the at least one transmission circuit and output delay adjustment information according to the delay deviation between the channel data transmitted by the multiple transmission circuits, and the delay adjustment information is used to adjust the transmission clock of the at least one transmission circuit.

[0075] For each transmission circuit in the at least one transmission circuit, the delay adjustment information may include a frequency control word and an adjustment time for adjusting clock parameters. The frequency control word may be used to control the frequency of the transmission clock, and the adjustment time may be used to indicate the duration of adjusting the transmission clock.

[0076] In addition, the adjustment times corresponding to different transmission circuits in the at least one transmission circuit may be the same, that is, the at least one transmission circuit completes the adjustment of its respective transmission clock within the same time length; or, the adjustment times corresponding to different transmission circuits in the at least one transmission circuit may also be different, that is, the at least one transmission circuit may complete the adjustment of its respective transmission clock within different time lengths.

[0077] Optionally, the delay adjustment circuit 102 may be used to query a preset corresponding relationship to determine a frequency control word corresponding to each transmission circuit according to the delay deviation corresponding to the transmission circuit, and the preset corresponding relationship may be used to indicate frequency control words corresponding to different delay deviations. Exemplarily, the preset corresponding relationship may be a table or a formula, etc., and the embodiments of the present application do not impose specific restrictions on this.

[0078] Optionally, the measurement accuracy of the delay measurement circuit 101 is configurable, for example, the measurement accuracy can be configured to microseconds or picoseconds, etc.; and / or, the accuracy of the delay adjustment circuit 102 is configurable, for example, the accuracy of the frequency control word output by the delay adjustment circuit 102 is configurable, or the accuracy of the adjustment time output by the delay adjustment circuit 102 is configurable.

[0079] Further, such as Figure 5 As shown, each transmission circuit also includes a clock tracking circuit 30. Figure 5In the description, it is taken that the first transmission circuit 21 further includes the first clock tracking circuit 31 and the second transmission circuit 22 further includes the second clock tracking circuit 32 as an example.

[0080] In the communication device, the clock tracking circuit 30 can be used to: receive the delay adjustment information, and output the first clock information according to the delay adjustment information, wherein the first clock information is used to adjust the transmission clock of the transmission circuit TX of the transmission circuit. Exemplarily, the clock tracking circuit 30 can be used to convert the frequency control word and adjustment time in the first clock adjustment information into the parameters of the serializer adjustment clock, and send the parameters of the adjustment clock to the serializer; when the serializer receives the parameters of the adjustment clock, the clock frequency and phase of the transmission clock can be adjusted according to the parameters of the adjustment clock to adjust the corresponding delay.

[0081] Optionally, the clock tracking circuit 30 can also be used to: receive the recovered clock output by the deserializer of the same transmission circuit, and the transmit clock fed back by the serializer, and output second clock information based on the recovered clock and the transmit clock. The second clock information can also be called clock tracking information. The second clock information can be used to generate the transmit clock of the transmit circuit TX of the transmission circuit.

[0082] Exemplarily, the first clock tracking circuit 31 may be used to receive the recovery clock rxclk1 output by the first deserializer 211 and the transmission clock fed back by the first serializer 213, and output clock information for generating the transmission clock of the first transmission circuit 21 according to the recovery clock rxclk1 and the transmission clock; the first clock tracking circuit 31 may also be used to receive the delay adjustment information corresponding to the first transmission circuit 21 output by the delay processing circuit 10, and output clock information for adjusting the transmission clock of the first transmission circuit 21 according to the delay adjustment information. Similarly, the second clock tracking circuit 32 may be used to receive the recovery clock rxclk2 output by the second deserializer 221 and the transmission clock fed back by the second serializer 223, and output clock information for generating the transmission clock of the second transmission circuit 22 according to the recovery clock rxclk2 and the transmission clock; the second clock tracking circuit 32 may also be used to receive the delay adjustment information corresponding to the second transmission circuit 22 output by the delay processing circuit 10, and output clock information for adjusting the transmission clock of the second transmission circuit 22 according to the delay adjustment information.

[0083] Optionally, the adjustment accuracy (or compensation accuracy) of the clock tracking circuit 30 for adjusting the transmission clock is configurable, for example, the compensation accuracy of the first clock tracking circuit 31 and the compensation accuracy of the second clock tracking circuit 32 are configurable.

[0084] In some possible embodiments, Figure 5As shown, each transmission circuit further includes a data buffer circuit 40. In the communication device, the data buffer circuit 40 of each transmission circuit can be used to store a tag signal and channel data, such as storing a tag signal and parallel channel data output by a deserializer. Accordingly, the serializer of the transmission circuit can also be used to obtain a tag signal and channel data from the data buffer circuit 40, such as obtaining a tag signal and parallel channel data from the data buffer circuit 40. Figure 5 In the description, it is taken that the first transmission circuit 21 further includes a first data buffer circuit 41 and the second transmission circuit 22 further includes a second data buffer circuit 42 as an example.

[0085] Exemplarily, the first data cache circuit 41 is used to store the first marking signal S1 and the parallel channel data D1 output by the first deserializer 211, and the second data cache circuit 42 is used to store the second marking signal S2 and the parallel channel data D2 output by the second deserializer 221; the first serializer 213 is used to obtain the first marking signal S1 and the parallel channel data D1 from the first data cache circuit 41, and the second serializer 214 is used to obtain the second marking signal S2 and the parallel channel data D2 from the second data cache circuit 42.

[0086] In the communication device provided in the embodiment of the present application, the receiving circuit RX of each transmission circuit will send a mark signal to the delay processing circuit 10 when receiving the channel data, and send the mark signal and the data together to the sending circuit TX of the transmission circuit. When the sending circuit TX of each transmission circuit receives the mark signal and the channel data, it will also send the mark signal to the delay processing circuit 10, so that the delay processing circuit can perform end-to-end measurement on the transmitted channel data according to the mark signal transmitted by the receiving circuit RX and the sending circuit TX of each transmission circuit, so as to determine the delay deviation between different channel data, and adjust the delay of the path where the channel data of multiple channels are located according to the delay deviation, or adjust the delay of the channel data transmitted by at least one transmission circuit in the multiple transmission circuits 20, that is, the delay deviation between the transmission paths corresponding to the channel data of the multiple channels, so as to reduce the delay deviation between different paths and improve the accuracy of the deviation adjustment. After testing, the communication device can reduce the delay deviation between the multiple channels from tens of nanoseconds (ns) to hundreds of picoseconds (ps).

[0087] Figure 6 A data transmission method is provided in an embodiment of the present application. The method can be applied to the communication device provided above. The method may include the following steps.

[0088] S401: The receiving circuit of each transmission circuit receives channel data of a corresponding channel, sends a mark signal to a delay processing circuit, and sends the mark signal and the channel data to a sending circuit in the transmission circuit.

[0089] Optionally, the multiple channels corresponding to the multiple transmission circuits may be multiple channels bound in the same port; and / or, the marking signal is sent periodically; and / or, the period for sending the marking signal is configurable.

[0090] In a possible embodiment, when the receiving circuit of each transmission circuit includes a deserializer and a measurement trigger circuit, the above S401 may include: the deserializer receives serial channel data and converts the serial channel data into parallel channel data; the measurement trigger circuit generates the mark signal and sends the mark signal to the deserializer and the delay processing circuit; the deserializer receives the mark signal and sends the mark signal and the channel data to the transmission circuit. Optionally, when receiving the serial channel data, the deserializer may also obtain a recovery clock corresponding to the channel data.

[0091] S402: The sending circuit of each transmission circuit receives the mark signal and the channel data, sends the mark signal to the delay processing circuit, and sends the channel data according to the sending clock.

[0092] Optionally, the transmission clock of each transmission circuit is generated by the transmission circuit of the transmission circuit according to the recovery clock of the transmission channel.

[0093] In a possible embodiment, the above S402 may specifically include: a serializer in a transmitting circuit of each transmission circuit receives a marking signal and parallel channel data, converts the received parallel channel data into serial channel data, and transmits the serial channel data according to a transmitting clock.

[0094] S403: The delay processing circuit determines the delay deviation between the channel data transmitted by the multiple transmission circuits according to the mark signals sent by the receiving circuits and the sending circuits of the multiple transmission circuits, and adjusts the sending clock of at least one transmission circuit among the multiple transmission circuits according to the delay deviation.

[0095] In a possible embodiment, when the delay processing circuit includes a delay measurement circuit and a delay adjustment circuit, the above S403 may include: the delay measurement circuit determines the delay of the channel data transmitted by the transmission circuit according to the mark signal sent by the receiving circuit and the sending circuit of each transmission circuit; the delay adjustment circuit determines the delay deviation between the channel data transmitted by the multiple transmission circuits according to the delay of the channel data transmitted by the multiple transmission circuits, and adjusts the sending clock of at least one transmission circuit among the multiple transmission circuits according to the delay deviation.

[0096] Optionally, the delay adjustment circuit adjusts the transmission clock of at least one transmission circuit among the multiple transmission circuits according to the delay deviation, including: the delay adjustment circuit determines the at least one transmission circuit and outputs delay adjustment information based on the delay deviation between the channel data transmitted by the multiple transmission circuits, and the delay adjustment information is used to adjust the transmission clock of the at least one transmission circuit.

[0097] Furthermore, when each transmission circuit also includes a clock tracking circuit, the method may also include: the clock tracking circuit receives the delay adjustment information, and outputs clock information according to the delay adjustment information, and the clock information is used to adjust the transmission clock of the transmission circuit.

[0098] Optionally, the method may also include: the clock tracking circuit receives the recovered clock output by the deserializer of the same transmission circuit, and the transmit clock fed back by the serializer, and outputs second clock information based on the recovered clock and the transmit clock. The second clock information may also be called clock tracking information, and the second clock information can be used to generate the transmit clock of the transmit circuit of the transmission circuit.

[0099] In some possible embodiments, when each transmission circuit also includes a data cache circuit, the method may further include: the data cache circuit of each transmission circuit stores a mark signal and channel data, such as storing a mark signal and parallel channel data output by a deserializer; the serializer of the transmission circuit obtains the mark signal and channel data from the data cache circuit, such as obtaining a mark signal and parallel channel data from the data cache circuit.

[0100] It can be understood that all relevant contents in the embodiments corresponding to the communication device provided above can be referred to the corresponding steps in the embodiment of the method, and will not be repeated here.

[0101] In an embodiment of the present application, when receiving channel data, the receiving circuit of each transmission circuit sends a mark signal to the delay processing circuit, and sends the mark signal and the data to the sending circuit of the transmission circuit. When receiving the mark signal and the channel data, the sending circuit of each transmission circuit also sends the mark signal to the delay processing circuit. In this way, the delay processing circuit can perform end-to-end measurement of the transmitted channel data according to the mark signal transmitted by the receiving circuit and the sending circuit of each transmission circuit to determine the delay deviation between different channel data, and adjust the delay of the path where the channel data of multiple channels are located according to the delay deviation, or adjust the delay of the channel data transmitted by at least one transmission circuit among the multiple transmission circuits, that is, the delay deviation between the transmission paths corresponding to the channel data of the multiple channels, so as to reduce the delay deviation between different paths and improve the accuracy of the deviation adjustment.

[0102] In another aspect of the present application, a chip is provided. The chip may include a packaging substrate, and a communication device disposed on the packaging substrate. The communication device is any one of the communication devices provided above.

[0103] In another aspect of the present application, a communication system is provided, which includes a sending device, a relay device and a receiving device. The sending device can send data to the receiving device through the relay device, and the relay device can include any one of the communication devices provided above.

[0104] In another aspect of the present application, a computer-readable storage medium is provided, in which instructions are stored. When the instructions are executed on a device, the device executes any one of the data transmission methods provided in the above method embodiments.

[0105] In yet another aspect of the present application, a computer program product is provided. When the computer program product is executed on a device, the device is enabled to execute any one of the data transmission methods provided in the above method embodiments.

[0106] It can be understood that all relevant contents in the embodiments corresponding to the communication device provided above can be referred to in the corresponding embodiments of the chip, the communication system, the computer-readable storage medium and the computer program product, and will not be repeated here.

[0107] Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A communication device, characterized in that: The communication device comprises: a delay processing circuit, and a plurality of transmission circuits coupled to the delay processing circuit, the plurality of transmission circuits corresponding to a plurality of channels one by one, and each of the plurality of transmission circuits comprising a receiving circuit and a transmitting circuit; The receiving circuit of each transmission circuit is used to receive the channel data of the corresponding channel, send a mark signal to the delay processing circuit, and send the mark signal and the channel data to the sending circuit in the transmission circuit; The sending circuit of each transmission circuit is used to receive the mark signal and the channel data, send the mark signal to the delay processing circuit, and send the channel data according to the sending clock; The delay processing circuit is used to determine the delay deviation between the channel data transmitted by the multiple transmission circuits according to the marking signals sent by the receiving circuits and the sending circuits of the multiple transmission circuits, and adjust the sending clock of at least one transmission circuit among the multiple transmission circuits according to the delay deviation.

2. The device according to claim 1, characterized in that The multiple channels are multiple channels bound in the same port.

3. The device according to claim 1 or 2, characterized in that: The marking signal is sent periodically.

4. The device according to claim 3, characterized in that The period of sending the marking signal is configurable.

5. The device according to any one of claims 1 to 4, characterized in that: The receiving circuit of each transmission circuit includes: a deserializer and a measurement trigger circuit; The deserializer is used to receive serial channel data and convert the serial channel data into parallel channel data; The measurement trigger circuit is used to generate the marking signal and send the marking signal to the deserializer and the delay processing circuit; The deserializer is further configured to receive the marking signal and send the marking signal and the channel data to the sending circuit.

6. The device according to any one of claims 1 to 5, characterized in that: The delay processing circuit includes: a delay measurement circuit and a delay adjustment circuit; The delay measurement circuit is used to determine the delay of the channel data transmitted by the transmission circuit according to the marking signal sent by the receiving circuit and the sending circuit of each transmission circuit; The delay adjustment circuit is used to determine the delay deviation between the channel data transmitted by the multiple transmission circuits according to the delay of the channel data transmitted by the multiple transmission circuits, and adjust the sending clock of at least one transmission circuit among the multiple transmission circuits according to the delay deviation.

7. The device according to claim 6, characterized in that The delay adjustment circuit is further used to determine the at least one transmission circuit and output delay adjustment information according to the delay deviation between the channel data transmitted by the multiple transmission circuits, and the delay adjustment information is used to adjust the transmission clock of the at least one transmission circuit.

8. The device according to claim 7, characterized in that Each transmission circuit also includes a clock tracking circuit; The clock tracking circuit is used to receive the delay adjustment information and output clock information according to the delay adjustment information, wherein the clock information is used to adjust the sending clock of the sending circuit.

9. A data transmission method, characterized in that: Applied to a communication device, the communication device comprising: a delay processing circuit, and a plurality of transmission circuits coupled to the delay processing circuit, the plurality of transmission circuits corresponding to a plurality of channels one by one, each of the plurality of transmission circuits comprising a receiving circuit and a transmitting circuit; the method comprising: The receiving circuit of each transmission circuit receives the channel data of the corresponding channel, sends a mark signal to the delay processing circuit, and sends the mark signal and the channel data to the sending circuit in the transmission circuit; The sending circuit of each transmission circuit receives the mark signal and the channel data, sends the mark signal to the delay processing circuit, and sends the channel data according to the sending clock; The delay processing circuit determines the delay deviation between the channel data transmitted by the multiple transmission circuits according to the mark signals sent by the receiving circuits and the sending circuits of the multiple transmission circuits, and adjusts the sending clock of at least one transmission circuit among the multiple transmission circuits according to the delay deviation.

10. The method according to claim 9, characterized in that The multiple channels are multiple channels bound in the same port.

11. The method according to claim 9 or 10, characterized in that: The marking signal is sent periodically.

12. The method according to claim 11, characterized in that The period of sending the marking signal is configurable.

13. The method according to any one of claims 9 to 12, characterized in that: The receiving circuit of each transmission circuit includes a deserializer and a measurement trigger circuit; the receiving circuit of each transmission circuit receives channel data of a corresponding channel, sends a mark signal to the delay processing circuit, and sends the mark signal and the channel data to the sending circuit in the transmission circuit, including: The deserializer receives serial channel data and converts the serial channel data into parallel channel data; The measurement trigger circuit generates the marker signal and sends the marker signal to the deserializer and the delay processing circuit; The deserializer receives the marker signal and sends the marker signal and the channel data to the transmitting circuit.

14. The method according to any one of claims 9 to 13, characterized in that: The delay processing circuit includes a delay measurement circuit and a delay adjustment circuit; the delay processing circuit determines the delay deviation between the channel data transmitted by the multiple transmission circuits according to the mark signals sent by the receiving circuits and the sending circuits of the multiple transmission circuits, and adjusts the sending clock of at least one transmission circuit among the multiple transmission circuits according to the delay deviation, including: The delay measurement circuit determines the delay of the channel data transmitted by the transmission circuit according to the marking signal sent by the receiving circuit and the sending circuit of each transmission circuit; The delay adjustment circuit determines the delay deviation between the channel data transmitted by the multiple transmission circuits according to the delay of the channel data transmitted by the multiple transmission circuits, and adjusts the sending clock of at least one transmission circuit among the multiple transmission circuits according to the delay deviation.

15. The method according to claim 14, characterized in that The delay adjustment circuit adjusts the transmission clock of at least one transmission circuit among the multiple transmission circuits according to the delay deviation, including: The delay adjustment circuit determines the at least one transmission circuit according to the delay deviation between the channel data transmitted by the multiple transmission circuits and outputs delay adjustment information, where the delay adjustment information is used to adjust the transmission clock of the at least one transmission circuit.

16. The method according to claim 15, characterized in that Each transmission circuit also includes a clock tracking circuit; the method also includes: The clock tracking circuit receives the delay adjustment information, and outputs clock information according to the delay adjustment information, where the clock information is used to adjust a sending clock of the sending circuit.

17. A chip, characterized in that: The chip includes a packaging substrate and a communication device arranged on the packaging substrate, and the communication device is the communication device according to any one of claims 1-8.

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