Selective silicon germanium process and structure

Abstract

The invention relates to selective silicon germanium processes and structures. Described examples include a semiconductor device having a first p-channel field effect transistor (p-FET) (146). The first p-FET (146) includes: a first gate dielectric layer (106) on a surface of a substrate; a first gate structure (108) on the first gate dielectric layer; and a first silicon germanium (SiGe) region (138) disposed in the substrate (102) on both sides of the first gate structure, the first SiGe region (138) extending from the surface of the substrate to a first depth. The semiconductor device also has a second p-FET (148). The second p-FET includes: a second gate dielectric layer (106) on the surface of the substrate; a second gate structure (108) on the second gate dielectric layer (106); and a second SiGe region (140) disposed in the substrate on both sides of the second gate structure, the second SiGe region (140) extending from the surface of the substrate (102) to a second depth, the second depth being different from the first depth.

Description

Technical Field

[0001] This relates generally to semiconductor structures and processing, and more particularly to silicon germanium (SiGe) structures and processing. Background Art

[0002] Silicon germanium (SiGe) structures have proven useful for improving the operating speed of devices in silicon semiconductor integrated circuits. This is especially true for p-type transistors because the lattice strain between silicon and germanium makes the carrier holes in the semiconductor more mobile. However, adding SiGe structures can add significant process complexity. It is desirable to provide SiGe processes and structures that reduce process complexity. Summary of the invention

[0003] According to an example, a semiconductor device includes a first p-channel field effect transistor (p-FET). The first p-FET includes: a first gate dielectric layer on a surface of a substrate; a first gate structure on the first gate dielectric layer; and a first silicon germanium (SiGe) region disposed in the substrate, on both sides of the first gate structure, the first SiGe region extending from the surface of the substrate to a first depth. The semiconductor device also includes a second p-FET. The second p-FET includes: a second gate dielectric layer on the surface of the substrate; a second gate structure on the second gate dielectric layer; and a second SiGe region disposed in the substrate, on both sides of the second gate structure, the second SiGe region extending from the surface of the substrate to a second depth, the second depth being different from the first depth. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a side view of an exemplary integrated circuit.

[0005] Figure 2A 2 through 2 (collectively referred to as “FIG. 2”) are side views illustrating an exemplary process.

[0006] Figure 3 is a side view of another exemplary integrated circuit.

[0007] Figure 4 is a side view of another exemplary integrated circuit.

[0008] Figure 5 is a side view of another exemplary integrated circuit. DETAILED DESCRIPTION

[0009] In the drawings, corresponding numerals and symbols generally refer to corresponding parts unless otherwise indicated. The drawings are not necessarily drawn to scale.

[0010] In this specification, the term "coupled" may include connections made with intervening elements, and additional elements and various connections may exist between any elements that are "coupled." Also, the terms "on" and "over" as used herein may include layers or other elements with intervening or additional elements between an element and the element "on" or "over" the element.

[0011] Figure 1 1 is a side view of an exemplary integrated circuit 100. In this illustration, an isolation region 104 divides a substrate 102 into four regions, but the disclosure is not limited thereto. For example, the substrate 102 may include less than four regions (e.g., two or three regions) or more than four regions (e.g., five, six, or even more regions). The substrate 102 has a surface 103. The four regions may have different exemplary device types. In most circuits, these four types are not necessarily adjacent to each other. However, most transistors will have isolation structures to isolate them from other devices in the integrated circuit.

[0012] The four types of devices shown are n-type field effect transistors (n-FETs) for logic operations (labeled "nFET logic"), n-FETs for static random access memory (SRAM) (labeled "nFET SRAM"), p-type field effect transistors (p-FETs) for logic operations (labeled "pFET logic"), and p-FETs for SRAM (labeled "pFET SRAM"). Logic and SRAM devices are indicated because of their different characteristics. For example, the speed of a logic device is more important than avoiding leakage problems. An SRAM device may stay in one state for a large amount of time, during which leakage problems can cause random data flips. Therefore, the requirement for an SRAM device is low leakage, with less emphasis on speed.

[0013] Figure 1 Each transistor in the n-FET structure 146 includes a gate 108, a gate silicide 109, and sidewall spacers 112. The n-FET includes a lightly doped drain (LDD) region 114 that is n-type and a source / drain region 115. Each transistor also includes a gate dielectric 106 at the surface 103 of the substrate 102. The p-FET structure 146 includes a silicon germanium (SiGe) region 138 and a lightly doped drain (LDD) region 128. The p-FET structure 146 also includes a source / drain region 129 (shown as a dashed line). The source / drain region 129 may be formed in the SiGe region 138, as shown. Figure 1, and the SiGe region 138 and the source / drain region 129 therein may be collectively referred to as the SiGe source / drain region. Similarly, the p-FET structure 148 includes the SiGe region 140 and the LDD region 132. The p-FET structure 148 also includes the source / drain region 133 (shown as a dotted line). The SiGe region 140 and the source / drain region 133 therein may be collectively referred to as the SiGe source / drain region.

[0014] Although source / drain regions 129, 133 are described as being present with SiGe regions 138, 140, respectively, the present disclosure is not limited thereto. For example, source / drain region 129 may extend further into substrate 102 than SiGe region 138—e.g., source / drain region 129 extends beyond a bottom interface between SiGe region 138 and substrate 102. Similarly, in some examples, source / drain region 133 may extend further into substrate 102 than SiGe region 140—e.g., source / drain region 133 extends beyond a bottom interface between SiGe region 140 and substrate 102.

[0015] The respective SiGe regions 138 and SiGe regions 140 increase the mobility of holes in the corresponding channel regions (between the LDD regions below the gate 108) of the P-FET structures 146 and 148, thereby increasing the velocity of the bulk carriers of the p-type device. It is noteworthy that in this example, the SiGe region 140 extends less into the substrate 102 than the SiGe region 138. Also, the SiGe region 140 protrudes above the surface 103 of the substrate 102, while the top surface of the SiGe region 138 is substantially flush with the surface 103. In addition, the source / drain region 133 extends less into the substrate 102 than the source / drain region 129. The relatively shallow source / drain region 133 can advantageously reduce the possibility of leakage in the p-FET structure 148 compared to the p-FET structure 146. Also, the relatively deep SiGe region 138 can increase the velocity of the p-FET structure 146 compared to the p-FET structure 148.

[0016] All transistors are protected by an interlayer dielectric 141. Source / drain contacts 144 extend through openings 142 in the interlayer dielectric 141 to provide electrical coupling to their respective source / drain regions at the silicide regions 143. Similar contacts (not shown) are provided to portions of the gate 108 that extend into or out of the page to provide contact to the gate 108 at the gate silicide 109.

[0017] Figures 2A to 2O (collectively referred to as “ FIG. 2 ”) is a side view illustrating an exemplary process for fabricating an integrated circuit 100 . Figure 2A A substrate 102 is shown having a surface 103 (eg, a top surface). Figure 2A Also shown are isolation regions 104 formed by etching trenches in substrate 102 and filling the trenches with a dielectric material or with polysilicon lined with a dielectric material.

[0018] A gate oxide layer 106 is then formed at the surface 103, such as Figure 2B . In an example, the gate oxide layer 106 can be formed using thermal oxidation. In another example, the gate oxide layer is a high-K dielectric material having a dielectric constant greater than that of silicon dioxide, such as hafnium silicate, zirconium silicate, hafnium dioxide, and zirconium dioxide. Such high-K dielectric materials can be deposited to a thickness of 3nm to 8nm using atomic layer deposition. A polysilicon layer is then deposited to a thickness of 100nm to 300nm, for example, by chemical vapor deposition (CVD) of silane. A cap layer is formed on the polysilicon layer. In some examples, the cap layer includes silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. These layers are etched (e.g., using a photoresist mask) to form the gate 108 and the gate cap 110, as shown. Figure 2B As shown in .

[0019] One or more dielectric layers 111 of dielectric material are then deposited (eg, using a conformal CVD process) to a thickness of 1 nm to 5 nm, such as Figure 2C . The dielectric layer 111 may include silicon nitride, silicon oxide, or a combination thereof. Subsequently, a silicon nitride / silicon oxynitride layer is deposited (e.g., using a CVD process) to a thickness of 10 nm to 50 nm. This silicon nitride / silicon oxynitride layer is then anisotropically etched to form spacers 120, such as Figure 2C As shown in .

[0020] The dielectric layer 111 is then etched to form sidewall spacers 112 on the sidewalls of the gates 108. In other words, portions of the dielectric layer 111 between the gates 108 (eg, portions of the dielectric layer 111 not covered by the spacers 120) are removed, such as Figure 2D In some examples, this etch will also remove the dielectric layer 111 on top of the gate cap 110, such as Figure 2D In some examples, this etching will thin the dielectric layer 111 on top of the gate cap 110, but may not completely remove the dielectric layer (although Figure 2D The thinned dielectric layer 111 on top of the gate cap 110 is not explicitly shown).

[0021] The photoresist mask 122 is then Figure 2E . Then an ion implantation process of n-type dopant atoms (e.g., phosphorus and arsenic) is performed. For example, the implantation of arsenic has an energy of 0.5 keV to 3 keV and a 1×10 14 Up to 1×1016 Atom / cm 2 The dose may include a dose having an energy of 2keV to 40keV and 1×10 13 Up to 1×10 14 Other halogen-based implants, such as boron or BF2, may be implanted at a dosage of 1000 Å. Annealing may then be performed to form the LDD region 114.

[0022] A hard mask 124 is then deposited (eg, using a CVD process) to a thickness of 10 nm to 50 nm, such as Figure 2F The hard mask 124 comprises silicon nitride in this example to allow for differential etching of silicon dioxide and silicon as explained further below.

[0023] Figure 2G The formation of a patterned photoresist mask 126 (e.g., using a photolithography process) is shown, which covers all areas except where the p-FET structure 146 will be formed. The photoresist mask 126 is subsequently used during an etching process to etch away the exposed portions of the hard mask 124, such as Figure 2H 148. An etchant such as sulfur hexafluoride is used for selectivity to silicon nitride of the hard mask 124 (e.g., preferentially removing silicon nitride over other materials). As further explained below, the hard mask 124 may be completely or partially removed depending on the desired depth of the resulting SiGe region in the p-FET structure 146. In this exemplary process flow for forming a relatively deep SiGe region in the p-FET structure 146 as compared to the p-FET structure 148, the hard mask 124 over the p-FET structure 146 may be completely removed or may be thinned to have a smaller remaining thickness than the p-FET structure 148 (as shown in reference to FIG. 149). Fig.2I In addition, a 1×10 14 Up to 1×10 16 Atom / cm 2 The LDD region 128 is formed by an ion implantation process of boron or BF2 with a dose of 1000 Å to form the LDD region 128. This ion implantation process may also include a halogen-based implant of phosphorus and / or arsenic with an energy of 5 keV to 30 keV and a concentration of 1×10 14 Up to 1×10 15 The ion implantation process may be performed before etching the hard mask 124 or after at least partially etching the hard mask 124, depending on the desired electrical properties of the p-FET structure 146. Subsequently, the photoresist mask 126 is removed.

[0024] Fig.2IThe formation of a patterned photoresist mask 130 is shown, which covers the integrated circuit 100 except where the p-FET structure 148 is to be formed. In this example, the photoresist mask 130 is then used to partially etch the exposed portions of the hard mask 124. An etchant such as sulfur hexafluoride is used for selectivity to silicon nitride. As further explained below, the hard mask 124 can be completely or partially removed depending on the desired depth of the resulting SiGe region in the p-FET structure 148. In this exemplary process flow, in which a relatively shallow SiGe region is formed in the p-FET structure 148 as compared to the p-FET structure 146, the hard mask 124 over the p-FET structure 148 can be thinned to have a greater remaining thickness than the p-FET structure 146, but is not completely removed. In addition, a 1×10 200 Å process with an energy of 2 keV to 10 keV and a 1×10 14 Up to 1×10 16 Atom / cm 2 The LDD region 132 is formed by an ion implantation process of boron or BF2 with a dose of 1000 Å. The ion implantation process may also include a halogen-based implant of phosphorus and / or arsenic with an energy of 5 keV to 30 keV and a concentration of 1×10 14 Up to 1×10 15 The ion implantation process may be performed before etching the hard mask 124 or after at least partially etching the hard mask 124, depending on the desired electrical properties of the p-FET structure 148. Subsequently, the photoresist mask 130 is removed.

[0025] In some examples, even when an ion implantation process with the same implantation conditions (e.g., energy and dose) is used to form the LDD regions 128 and 132, the resulting LDD regions 128 and 132 may be different from each other due to the different remaining thicknesses of the hard mask 124 (e.g., above the surface 103 of the substrate 102, above the spacers 120) through which the ion implantation process is performed—e.g., different dopant profiles in the substrate 102 with different implantation projections, at different spacings from the edge of the gate 108. In some examples, the hard mask 124 above the p-FET structure 148 may remain intact (e.g., not etched) so that the SiGe region is not present. Figure 5 In the p-FET structure 148 shown in FIG.

[0026] Figure 2JA recess etch process is shown for etching substrate 102 with an etchant that is more selective to silicon than to silicon nitride (and silicon oxide) (e.g., using a plasma enhanced etch) to form cavities 134 and 136, respectively, in substrate 102. Examples of such etches include H2 / CF4, SF6, and HBr / Cl2. Hard mask 124 protects most areas from this etching—e.g., areas containing n-FETs. In addition, spacers 120 and gate caps 110 protect gate structures and corresponding channel regions for p-FET structures 146, 148. In this exemplary embodiment, hard mask 124 is thinned over p-FET structure 148, but is not as thin as described above. Fig.2I Therefore, before starting to remove silicon to form cavity 136, a portion of the etching time when the etchant is removing silicon to form cavity 134 will be required to remove the remaining portion of hard mask 124. In this way, different cavities between two different p-FET structures can be provided without the need for additional masking and separate etching steps for forming different cavities.

[0027] For example, a difference in the depth of cavity 134 and cavity 136 may be created, such as Figure 2J , i.e., depth D1 is greater than depth D2 (e.g., relative to surface 103). Additionally, because portions of the remaining hard mask 124 will be on the spacers 120 of the p-FET structure 148 (or the remaining hard mask 124 on the spacers 120 of the p-FET structure 148 is thicker than the remaining hard mask 124 on the spacers 120 of the p-FET structure 146), the lateral distance (S2) between the cavity 136 and the gate 108 in the p-FET structure 148 is greater than the lateral distance (S1) between the cavity 134 and the gate 108 in the p-FET structure 146—e.g., the lateral distances S1, S2 measured at a plane corresponding to the surface 103 of the substrate 102.

[0028] Figure 2K The results of crystalline etching in cavity 134 and cavity 136 are shown - for example, different etching rates based on different crystalline surfaces exposed to the etchant. An exemplary crystalline oriented etchant is tetramethylammonium hydroxide (TMAH). When Figure 2L When epitaxially depositing (forming, growing) SiGe in the step of , this etching step can be used to prevent excessive stress during the epitaxial process. As a result of the crystallographic etching, although Figure 2K The depths D1a and D2a depicted in FIG. Figure 2J , but the depth D1a remains greater than D2a. Figure 2K The lateral distances S1a and S2a depicted in the figure may be different from Figure 2J, but the lateral distance S2a remains greater than the lateral distance S1a.

[0029] Figure 2L SiGe region 138 and SiGe region 140 are shown formed in cavities 134 and 136, respectively. SiGe region 138 and SiGe region 140 are formed simultaneously using epitaxial deposition, which allows for precise control of the deposited materials and their composition between p-FET structure 146 and p-FET structure 148. In the example, SiGe is deposited. 1-x Ge x 1, wherein x varies between 0.2 and 0.5. In addition to silicon and germanium, boron may be included during deposition to provide a SiGe region having the same conductivity as LDD region 128 and LDD region 132. Given the additional material required to fill cavity 134 (e.g., due to its deeper recess into substrate 102 than cavity 136), SiGe region 140 may extend above top surface 103 of substrate 102. That is, thickness T2 of SiGe region 140 may be substantially equal to thickness T1 of SiGe region 138. In other words, SiGe region 140 may have a greater extension above top surface 103 than SiGe region 138 due to having a shallower depth (e.g., D2a is less than D1a).

[0030] Subsequently, source / drain regions for n-FET and p-FET structures 146, 148 are formed. For example, Figure 2M The hard mask 124 and the spacer 120 are shown to have been removed using a wet etch with a chemistry that is selective to silicon nitride and silicon dioxide, respectively. Figure 2M As shown in , the gate cap 110 can be removed so that the gate 108 can be implanted with dopants that form source / drain regions for the n-FET structure and the p-FET structure 146, 148. In addition, Figure 2M Spacers 121 are shown formed prior to respective source / drain implant processes (e.g., depositing a dielectric layer and anisotropically etching the dielectric layer) for n-FET and p-FET structures 146, 148. Spacers 121 may have a larger base width than spacers 120 so that the source / drain implants are further from the edge of gate 108 than from the legs of sidewall spacers 112. One or more anneals may follow the source / drain implant processes. Figure 2M Also shown are the resulting source / drain regions 115 of the n-FET structure and the corresponding source / drain regions 129, 133 for the p-FET structures 146, 148 shown in dashed lines. Figure 2M As depicted in , source / drain regions 129, 133 may be contained in SiGe regions 138, 140, respectively.

[0031] Figure 2N It is shown that the spacer 121 can be thinned and the gate silicide 109 and the silicide region 143 are formed by a silicide process. In some examples, the silicide process includes depositing a silicide metal layer, such as titanium, cobalt, nickel, platinum, or molybdenum. Subsequently, an annealing process reacts the silicide metal with the exposed silicon (e.g., in the source / drain regions 114, SiGe regions 138, SiGe regions 140, and gate 108). The unreacted silicide metal (e.g., the silicide metal deposited on the spacer 121) is then removed. The silicide region 143 (and the gate silicide 109) provide better conductivity to the source / drain contacts 144 (and the gate contact not shown), which include the desired contact metal, such as titanium / tungsten.

[0032] Fig.2O The thinned spacers 121 are shown removed after the silicidation process. A thin silicon nitride liner layer (not shown) is formed and planarized, followed by the formation and planarization of a pre-metal dielectric (PMD) 141 (e.g., tetraethyl orthosilicate (TEOS) deposited by CVD). Fig.2O Also shown is an opening 142 etched through the interlayer dielectric 141. The opening 142 is formed by reactive ion etching (RIE). Subsequently, source / drain contacts 144 (and gate contacts not shown) are formed in the opening 142, which include the desired contact metal, such as titanium / tungsten.

[0033] Figure 3 3 is a side view of another exemplary integrated circuit 300. Integrated circuit 300 is similar to integrated circuit 100 ( Figure 1 ), in reference Figure 2L In contrast to the integrated circuit 100, the hard mask 124 ( Figure 2G ) is thinned over p-FET structure 346 and removed over p-FET structure 348 (or hard mask 124 over p-FET structure 348 may be thinned to have a smaller remaining thickness than p-FET structure 346). Thus, the cavity of SiGe region 338 extends less into substrate 102 than the cavity of SiGe region 340. Figures 2A to 2O The process of epitaxial deposition of SiGe region 338 and SiGe region 340 is performed in the same epitaxial deposition process. As a result, SiGe region 338 extends less into substrate 102 than SiGe region 340 - for example, depth D1a from surface 103 is less than depth D2a from surface 103. In addition, lateral distance S1a is greater than lateral distance S2a. Figures 2M to 2O The described process steps may be performed to complete the formation of the p-FET structures 346 , 348 .

[0034] Figure 44 is a side view of another exemplary integrated circuit 400. The integrated circuit 400 is similar to the integrated circuit 100 ( Figure 1 ), in reference Figure 2L As in the integrated circuit 100, the hard mask 124 ( Figure 2G ) is thinned over p-FET SRAM 448 and removed over p-FET logic 446 (or hard mask 124 over p-FET structure 446 can be thinned to have a smaller remaining thickness than p-FET structure 448). Thus, the cavity of SiGe region 440 extends less into substrate 102 than the cavity of SiGe region 438—e.g., depth D1a from surface 103 is greater than depth D2a from surface 103. Figure 2A 0, SiGe region 438 and SiGe region 440 are formed in the same epitaxial deposition process. However, the epitaxial deposition process for integrated circuit 400 is extended so that SiGe regions 438, 440 extend above surface 103 of substrate 102 - for example, at heights H1, H2 relative to surface 103, such as Figure 4 . In other words, SiGe region 440 may extend further above surface 103 of substrate 102 than SiGe region 438—for example, height H2 of SiGe region 440 is greater than corresponding height H1 of SiGe region 438 (which may be zero in some cases). In some examples, the SiGe region protruding above surface 103 may be beneficial in enabling subsequently formed source / drain regions of a p-FET structure to have a shallower junction depth relative to surface 103, thereby reducing leakage in the p-FET structure. Subsequently, reference is made to Figures 2M to 2O The described process steps may be performed to complete the formation of the p-FET structures 446 , 448 .

[0035] Therefore, as shown in FIGS. 2 to 4, by adjusting the hard mask 124 ( Figure 2G ) thickness, achieving control over the relative structural features of the resulting SiGe (e.g., depth extending into the substrate, lateral distance from the gate edge, protrusion above the substrate surface) without additional lithographic masking.

[0036] Figure 5 is a side view of another exemplary integrated circuit 500. Integrated circuit 500 is similar to integrated circuit 100 ( Figure 1 ), in reference Figure 2L In contrast to the integrated circuit 100, the hard mask 124 ( Figure 2G) is removed (or thinned) on the p-FET structure 546, but remains intact on the p-FET structure 548. Therefore, although the cavity and corresponding SiGe region 538 are formed for the p-FET structure 546, the hard mask 124 protects the p-FET structure 548. As a result, the p-FET structure 546 does not have a SiGe region. Figures 2M to 2O The described process steps may be performed to complete the formation of the p-FET structures 546 , 548 .

[0037] Modifications are possible in the examples described, and other examples are possible within the scope of the claims. For example, although the above examples are based on forming SiGe regions for p-FETs, the disclosure is not limited thereto. In some examples, the methods described herein can be used to form SiC regions with different structural features for different n-FET structures - for example, n-FETs for logic operations, n-FETs for SRAM.

Claims

1. A semiconductor device comprising: A first p-channel field effect transistor p-FET comprising: a first gate dielectric layer on a surface of the substrate; a first gate structure on the first gate dielectric layer; and a first silicon germanium (SiGe) region disposed in the substrate, on both sides of the first gate structure, the first SiGe region extending from the surface of the substrate to a first depth; and A second p-FET comprising: a second gate dielectric layer on the surface of the substrate; a second gate structure on the second gate dielectric layer; and A second SiGe region is disposed in the substrate on both sides of the second gate structure, the second SiGe region extending from the surface of the substrate to a second depth, the second depth being different from the first depth.

2. The semiconductor device according to claim 1, wherein: The first SiGe region is laterally spaced apart from respective sidewalls of the first gate structure by a first distance; and The second SiGe region is laterally spaced apart from respective sidewalls of the second gate structure by a second distance different than the first distance.

3. The semiconductor device according to claim 1, wherein: The first SiGe region includes a first portion extending from the surface of the substrate to a first height; and The second SiGe region includes a second portion extending from the surface of the substrate to a second height that is different from the first height.

4. The semiconductor device according to claim 1, wherein: The first p-FET includes a first lightly doped drain (LDD) region extending laterally between the first SiGe region and the first gate structure; and The second p-FET includes a second lightly doped drain (LDD) region extending laterally between the second SiGe region and the second gate structure, the second LDD region being different from the first LDD region. 5 . The semiconductor device according to claim 1 , wherein the first SiGe region and the second SiGe region are formed simultaneously.

6. The semiconductor device according to claim 1, further comprising: a source region and a drain region of the first p-FET disposed in a corresponding first SiGe region; as well as The source and drain regions of the second p-FET are disposed in respective second SiGe regions.

7. The semiconductor device according to claim 1, further comprising: a first silicide region disposed on the first SiGe region; as well as A second silicide region is disposed on the second SiGe region. 8 . The semiconductor device according to claim 1 , wherein the first gate dielectric layer and the second gate dielectric layer are formed simultaneously.

9. The semiconductor device according to claim 1, wherein the first SiGe region and the second SiGe region include Si 1-x Ge x A silicon-germanium alloy wherein x varies between 0.2 and 0.

5.

10. The semiconductor device of claim 1, wherein at least one of the first gate dielectric layer and the second gate dielectric layer comprises a high-k dielectric material having a dielectric constant greater than that of silicon dioxide SiO2.

11. The semiconductor device according to claim 1, further comprising: An n-channel field effect transistor n-FET is in the substrate, wherein the n-FET does not include a SiGe region.

12. A method comprising: A hard mask is deposited over a first p-channel field effect transistor (p-FET) structure in a first region of a substrate and a second p-FET structure in a second region of the substrate, wherein— The first p-FET structure comprises: a first gate dielectric layer on a surface of the substrate; a first gate structure on the first gate dielectric layer; A first spacer formed on a sidewall of the first gate structure; and a first source / drain region of the substrate on either side of the first gate structure; and The second p-FET structure comprises: a second gate dielectric layer on the surface of the substrate; a second gate structure on the second gate dielectric layer; a second spacer formed on a sidewall of the second gate structure; as well as a second source / drain region of the substrate on both sides of the second gate structure; forming a first patterned photoresist mask, wherein the first patterned photoresist mask covers the second region and uncovers the first region to expose the first p-FET structure; performing a first etching process after forming the first patterned photoresist mask, the first etching process being configured to remove at least a portion of the hard mask over the first p-FET structure; removing the first patterned photoresist mask; forming a second patterned photoresist mask, wherein the second patterned photoresist mask covers the first region and uncovers the second region to expose the second p-FET structure; as well as A second etching process is performed after forming the second patterned photoresist mask, the second etching process being configured to remove at least a portion of the hard mask over the second p-FET structure, the second etching process being different from the first etching process.

13. The method according to claim 12, further comprising: A first implantation process is performed after forming the first patterned photoresist mask and before performing the first etching process, the first implantation process being configured to form a first lightly doped drain (LDD) region in the first source / drain region.

14. The method according to claim 13, further comprising: A first implantation process is performed after forming the first patterned photoresist mask and after performing the first etching process, the first implantation process being configured to form a first lightly doped drain (LDD) region in the first source / drain region.

15. The method according to claim 12, further comprising: A second implantation process is performed after forming the second patterned photoresist mask and before performing the second etching process, the second implantation process being configured to form a second lightly doped drain (LDD) region in the second source / drain region.

16. The method of claim 12, further comprising: After forming the second patterned photoresist mask and after performing the second etching process, a second implantation process is performed, the second implantation process being configured to form a second lightly doped drain (LDD) region in the second source / drain region.

17. The method of claim 12, wherein: The first source / drain region has a first thickness of the hard mask remaining as a result of performing the first etching process; and The second source / drain region has a second thickness of the hard mask remaining due to performing the second etching process, the second thickness being different from the first thickness.

18. The method of claim 12, wherein: As a result of performing the first etching process, the first spacer has a first width close to the surface of the substrate; and As a result of performing the second etching process, the second spacer has a second width close to the surface of the substrate, the second width being different from the first width.

19. The method of claim 12, further comprising: removing the second patterned photoresist mask; as well as performing a recess etch process configured to produce: a first cavity in the first source / drain region, the first cavity having a first depth from the surface of the substrate, and A second cavity in the second source / drain region has a second depth from the surface of the substrate, the second depth being different from the first depth.

20. The method of claim 19, wherein the second depth differs from the first depth due at least in part to the second etching process being different from the first etching process.

21. The method of claim 19, further comprising: An epitaxial process is performed to selectively form a first silicon germanium SiGe region in the first cavity and a second SiGe region in the second cavity.

22. The method of claim 21, wherein: The first SiGe region is laterally spaced apart a first distance from respective sidewalls of the first gate structure; and The second SiGe region is laterally spaced apart from respective sidewalls of the second gate structure by a second distance different than the first distance.

23. The method of claim 21, wherein: The first SiGe region includes a first portion extending from the surface of the substrate to a first height; and The second SiGe region includes a second portion extending from the surface of the substrate to a second height that is different from the first height.

24. The method of claim 21, further comprising: removing the first spacer and the second spacer after performing the epitaxial process; forming a third spacer on sidewalls of the first gate structure and the second gate structure; as well as performing a third implantation process, the third implantation process being configured to form: source and drain regions of the first p-FET structure in respective first SiGe regions; as well as A source region and a drain region of the second p-FET structure are provided in respective second SiGe regions.

25. The method of claim 24, further comprising: performing a third etching process configured to reduce a width of the third spacer proximate the surface of the substrate; as well as A silicidation process is performed, the silicidation process configured to form a first silicide region on the first SiGe region and a second silicide region on the second SiGe region.

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