Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment, the semiconductor device comprises a plurality of layers of memory cells stacked along a direction vertical to a substrate and a first word line, and each layer of memory cell comprises a first transistor and a second transistor; the first transistor comprises a first semiconductor sub-layer; a second semiconductor sub-layer is arranged between every two adjacent first semiconductor sub-layers to form a first semiconductor layer, the first semiconductor layers and the control electrodes are arranged in the first holes, and the first word lines are arranged in the second holes, penetrate through the different layers and extend in the direction perpendicular to the substrate. The distance between the first word line and the first semiconductor sub-layer in the direction parallel to the substrate is smaller than the distance between the first word line and the second semiconductor sub-layer in the direction parallel to the substrate. According to the scheme provided by the embodiment, the parasitic semiconductor layer can be controlled through the control electrode, so that electric leakage of the parasitic transistor is avoided, a parasitic channel does not need to be etched, and an effective channel of the device is prevented from being influenced.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and an electronic device, which can avoid leakage caused by parasitic transistors and improve device performance.

[0006] The present disclosure provides a semiconductor device, comprising a plurality of memory cells stacked in a direction perpendicular to a substrate, and a first word line, wherein:

[0007] Each layer of the storage unit comprises: a first transistor and a second transistor; the second transistor and the first transistor are sequentially distributed along a first direction parallel to the substrate;

[0008] The first transistor includes a first semiconductor sublayer, a first electrode, and a second electrode; the first semiconductor sublayer is connected to the first electrode and the second electrode respectively;

[0009] The second transistor comprises a third gate electrode, wherein the third gate electrode is connected to the first electrode;

[0010] A second semiconductor sublayer is disposed between adjacent first semiconductor sublayers, and the first semiconductor sublayer and the second semiconductor sublayer are connected to form an integrated structure called a first semiconductor layer, and the first semiconductor layer extends in a direction perpendicular to the substrate;

[0011] A first hole and a second hole penetrating different layers, the second hole being connected to the first hole, the first semiconductor layer and a control electrode extending in a direction perpendicular to the substrate and penetrating different layers being arranged in the first hole, wherein the first semiconductor layer surrounds a side wall of the control electrode;

[0012] The first word line is arranged in the second hole and extends through the different layers along a direction perpendicular to the substrate, and the distance between the first word line and the first semiconductor sublayer along a direction parallel to the substrate is smaller than the distance between the first word line and the second semiconductor sublayer along a direction parallel to the substrate.

[0013] In some embodiments, the semiconductor device further comprises:

[0014] Insulating layers and conductive layers are alternately distributed from top to bottom in a direction perpendicular to the substrate; the first hole and the second hole penetrate the insulating layer and the conductive layer;

[0015] The first semiconductor layer, the second gate insulating layer surrounding the side wall of the control electrode, and the control electrode are sequentially distributed in the first hole from outside to inside;

[0016] A first gate insulating layer surrounding the side wall of the first word line and the first word line are sequentially distributed in the second hole from outside to inside.

[0017] In some embodiments, a first sub-hole of the first hole located in the insulating layer has a smaller aperture than a second sub-hole of the first hole located in the conductive layer.

[0018] In some embodiments, a third sub-hole of the second hole located in the insulating layer has a smaller aperture than a fourth sub-hole of the second hole located in the conductive layer.

[0019] In some embodiments, a sidewall of the first semiconductor sublayer is connected to a sidewall of the first gate insulating layer, and the insulating layer is disposed between a sidewall of the second semiconductor sublayer and a sidewall of the first gate insulating layer.

[0020] In some embodiments, the arrangement direction of the first holes and the second holes is perpendicular to the first direction.

[0021] In some embodiments, the first electrode and the second electrode are distributed on the outer wall of the first semiconductor sublayer and are spaced apart along the first direction, and the first word line is distributed in the area between the first electrode and the second electrode on the outer wall of the first semiconductor sublayer.

[0022] In some embodiments, a first groove with an opening facing away from the first word line, the control electrode and the second electrode is provided between adjacent insulating layers, the bottom wall of the first groove exposes the first gate insulating layer and the first semiconductor sublayer, the first electrode is distributed on the bottom wall of the first groove and the side wall perpendicular to the substrate, the second semiconductor layer is distributed on the bottom wall of the first groove and the side wall perpendicular to the substrate, and is also distributed on the adjacent insulating layer constituting the side wall of the first groove.

[0023] In some embodiments, the semiconductor device also includes a second groove arranged on the side of the first groove away from the first semiconductor layer and extending along the second direction, the second groove is connected to multiple first grooves in the same column, the opening of the second groove is away from the first electrode, the second semiconductor layers of the second transistors in the same column distributed along the second direction are connected to form an integrated structure, the integrated structure formed by the second semiconductor layer is also arranged on the side walls and bottom walls of the second groove, and the first direction and the second direction intersect.

[0024] In some embodiments, the semiconductor device further includes: a memory cell array distributed along a direction perpendicular to the substrate, each layer of the memory cell array including multiple rows and columns of memory cells respectively distributed along the first direction and the second direction, the multiple layers of memory cells stacked along a direction perpendicular to the substrate are multiple memory cells at the same position in different layers, and the second electrodes of the first transistors in the same column distributed along the second direction are connected to form a first bit line extending along the second direction.

[0025] In some embodiments, adjacent first transistors along the first direction are connected to different first bit lines.

[0026] In some embodiments, the semiconductor device further includes: a second bit line distributed on a bottom wall and a side wall of the second groove in which the second semiconductor layer is disposed and extending along a second direction.

[0027] In some embodiments, adjacent second transistors along the first direction are connected to different second bit lines.

[0028] In some embodiments, the second semiconductor layers of the second transistors of different layers are arranged alternately.

[0029] In some embodiments, the third gate electrode and the first electrode of the same memory cell are connected to form an integrated structure.

[0030] In some embodiments, the second transistor also includes a third electrode, and the third electrodes of the second transistors of the storage cells at the same position in multiple layers are connected to form an integrated structure extending in a direction perpendicular to the substrate, and the integrated structure formed by the third electrode connection includes a vertical portion extending in a direction perpendicular to the substrate and a horizontal portion extending from the vertical portion in a horizontal direction, and the horizontal portion is connected to the second semiconductor layer distributed on the bottom wall of the first groove, and is connected to the second semiconductor layer distributed in an area adjacent to the bottom wall of the first groove.

[0031] In some embodiments, the second transistor also includes a fourth gate electrode arranged on a side of the third electrode away from the first transistor, and the fourth gate electrodes of the second transistors of the storage cells at the same position in multiple layers are connected to form an integrated structure extending in a direction perpendicular to the substrate, and the orthographic projection of the fourth gate electrode on the substrate is located within the orthographic projection of the first groove on the substrate.

[0032] In some embodiments, the semiconductor device further comprises:

[0033] A third hole penetrating each of the insulating layers and each of the conductive layers; the third hole comprises a fourth hole and a fifth hole penetrating each of the insulating layers and each of the conductive layers, and the arrangement direction of the fourth hole and the fifth hole is the same as the arrangement direction of the first transistor and the second transistor;

[0034] The third hole is provided with a third gate insulating layer and a second semiconductor layer from outside to inside;

[0035] A plurality of third electrodes connected into an integrated structure are distributed in the fourth hole;

[0036] The fourth gate insulating layer and the fourth gate electrode are sequentially distributed in the fifth hole from outside to inside.

[0037] In some embodiments, a diameter of a fifth sub-hole of the third hole located in the insulating layer is smaller than a diameter of a sixth sub-hole of the third hole located in the conductive layer.

[0038] In some embodiments, the fourth hole includes a seventh sub-hole located in the insulating layer and an eighth sub-hole located in the conductive layer, and a boundary of the seventh sub-hole close to the fifth hole in the orthographic projection of the substrate overlaps with a boundary of the eighth sub-hole close to the fifth hole in the orthographic projection of the substrate, and other boundaries of the seventh sub-hole in the orthographic projection of the substrate fall within the orthographic projection of the eighth sub-hole on the substrate.

[0039] In some embodiments, the fifth hole includes a ninth sub-hole located in the insulating layer and a tenth sub-hole located in the conductive layer, and a boundary of the ninth sub-hole close to the fourth hole in the orthographic projection of the substrate overlaps with a boundary of the tenth sub-hole close to the fourth hole in the orthographic projection of the substrate, and other boundaries of the ninth sub-hole in the orthographic projection of the substrate fall within the orthographic projection of the tenth sub-hole on the substrate.

[0040] The present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0041] Providing a substrate, on which a first insulating film and a conductive layer film are alternately deposited in sequence to form a stacked structure including insulating layers and conductive layers alternately arranged;

[0042] The stacked structure is patterned to form first trenches penetrating each layer and extending in a first direction, wherein adjacent first trenches include first transistor regions and second transistor regions distributed along the first direction;

[0043] forming a second hole penetrating the stacked structure in a direction perpendicular to the substrate in the first transistor region, and laterally etching the conductive layer in each second hole so that the aperture of the second hole in the conductive layer is larger than the aperture of the second hole in the insulating layer; and sequentially forming a first gate insulating layer and a first word line of the first transistor on the sidewalls of the second hole;

[0044] Forming a first hole penetrating the stacked structure in the first transistor region in a direction perpendicular to the substrate, and laterally etching the conductive layer in each of the first holes so that the aperture of the first hole in the conductive layer is larger than the aperture of the insulating layer, and each first gate insulating layer between any conductive layers in the second hole is exposed;

[0045] A first semiconductor layer of a first transistor connected to each of the first gate insulating layers, a second gate insulating layer, and a control electrode of the first transistor corresponding to different layers are sequentially formed in the first hole, the first semiconductor layer comprises a plurality of first semiconductor sublayers arranged at intervals and a second semiconductor sublayer located between adjacent first semiconductor sublayers, the first semiconductor sublayer and the second semiconductor sublayer are connected to form an integrated structure, and a distance between the first word line and the first semiconductor sublayer along a direction parallel to the substrate is smaller than a distance between the first word line and the second semiconductor sublayer along a direction parallel to the substrate;

[0046] A second transistor is formed in the second transistor region, and the first transistor and the second transistor are connected via a conductive layer serving as a sidewall of the first hole and a sidewall of the second hole.

[0047] In some embodiments, it also includes:

[0048] A third trench penetrating the layers is formed between first transistor regions adjacent to each other along the first direction, and the third trench extends along the second direction; the conductive layer is laterally etched in the third trench to the adjacent first transistor region to form a first transverse trench, and a first bit line filling the first transverse trench is formed in the first transverse trench, and the first transverse trench is connected to the first hole and the second hole.

[0049] In some embodiments, forming a second transistor in the second transistor region includes:

[0050] Forming a second trench extending along the second direction and penetrating through each layer between the adjacent second transistor regions along the first direction; etching the conductive layer laterally in the second trench to the adjacent second transistor region, forming a second transverse trench in each conductive layer;

[0051] forming a third hole penetrating the stacked structure in a direction perpendicular to the substrate in the first transistor region, and laterally etching the conductive layer in each third hole to form a transverse groove, so that the aperture of the third hole in the conductive layer is larger than the aperture of the third hole in the insulating layer, and the third hole is connected to the second trench, and the bottom wall and the side wall of the transverse groove in a direction perpendicular to the substrate are the conductive layer;

[0052] forming a third gate insulating layer and a second semiconductor layer of a second transistor in the third hole and the second trench, and the second semiconductor layer is formed only on the inner walls of the second transverse trench and the transverse groove; forming a second bit line filling the second transverse trench in the second transverse trench formed with the second semiconductor layer;

[0053] A fourth hole is formed in the third hole and penetrates the stacked structure in a direction perpendicular to the substrate, and the conductive layer is laterally etched in each fourth hole to expose the second semiconductor layer arranged on the bottom wall of the lateral groove and the side wall close to the bottom wall of the groove, and to expose each third gate insulating layer between any conductive layers in the fourth hole; and a plurality of third electrodes of the second transistors are formed in the fourth hole.

[0054] In some embodiments, forming a second transistor in the second transistor region further comprises:

[0055] A fifth hole is formed in the third hole and penetrates the stacked structure in a direction perpendicular to the substrate. The conductive layer is laterally etched in each fifth hole to expose the second semiconductor layer that is arranged in the lateral groove and is not connected to the third electrode, and to expose each third gate insulating layer between any conductive layers in the fourth hole, and the third electrode; and a plurality of fourth gate insulating layers and fourth gate electrodes of the second transistors are formed in the fifth hole.

[0056] An embodiment of the present disclosure provides an electronic device, comprising the semiconductor device described in any of the above embodiments, or a semiconductor device manufactured according to the semiconductor device manufacturing method described in any of the above embodiments.

[0057] The embodiments of the present disclosure include a semiconductor device and a manufacturing method thereof, and an electronic device. The semiconductor device includes multiple layers of memory cells stacked in a direction perpendicular to a substrate, a first word line, and each layer of the memory cells includes: a first transistor and a second transistor; the second transistor and the first transistor are sequentially distributed along a first direction parallel to the substrate; the first transistor includes a first semiconductor sublayer, a first electrode, and a second electrode; the first semiconductor sublayer is connected to the first electrode and the second electrode respectively; the second transistor includes a third gate electrode, and the third gate electrode is connected to the first electrode; a second semiconductor sublayer is arranged between adjacent first semiconductor sublayers, and the first semiconductor sublayer and the second semiconductor sublayer are connected to form an integrated structure called a first semiconductor layer, and the first semiconductor layer extends in a direction perpendicular to the substrate; a first hole and a second hole are passed through different layers, and the first hole is provided with the first semiconductor layer and a control electrode extending in a direction perpendicular to the substrate and passing through different layers, wherein the first semiconductor layer surrounds the side wall of the control electrode; the first word line is arranged in the second hole and passes through the different layers and extends in a direction perpendicular to the substrate, and the distance between the first word line and the first semiconductor sublayer in a direction parallel to the substrate is less than the distance between the first word line and the second semiconductor sublayer in a direction parallel to the substrate. The semiconductor device provided in this embodiment controls the second semiconductor sublayer by setting a control electrode, and makes the control of the second semiconductor sublayer by the first word line weaker than that of the first semiconductor sublayer, so that the parasitic transistor can be turned off while the first transistor is turned on, thereby avoiding leakage caused by the parasitic transistor, and there is no need to etch and remove the parasitic semiconductor layer, so as to avoid affecting the channel area of ​​the first transistor, simplifying the process and improving device performance.

[0058] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by implementing the present disclosure. The objects and advantages of the present disclosure can be realized and obtained by the structures particularly pointed out in the description and the drawings.

[0059] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution and do not constitute a limitation on the technical solution.

[0061] Figure 1A A schematic circuit diagram of a memory cell array of a semiconductor device provided as an exemplary embodiment;

[0062] Figure 1B A schematic circuit diagram of a memory cell provided for an exemplary embodiment;

[0063] Figure 1C A circuit diagram of a memory cell array of a semiconductor device provided for another exemplary embodiment;

[0064] Figure 1D for Figure 1C A circuit diagram of a memory cell in the semiconductor device shown;

[0065] Figure 2A A top view of a semiconductor device provided for an exemplary embodiment;

[0066] Figure 2B For along Figure 2A Cross-section view along the AA direction;

[0067] Figure 2C For along Figure 2A Cross-section along the BB direction;

[0068] Figure 2D For along Figure 2A Cross-sectional view in the CC direction;

[0069] Figure 2E For along Figure 2A Cross-section along the mid-DD direction;

[0070] Figure 2F For along Figure 2A Cross-section along the EE direction;

[0071] Figure 3A A top view of a semiconductor device provided for another exemplary embodiment;

[0072] Figure 3B For along Figure 3A Cross-section view along the AA direction;

[0073] Figure 3C For along Figure 3A Cross-section along the BB direction;

[0074] Figure 3D For along Figure 3A Cross-sectional view in the CC direction;

[0075] Figure 3E For along Figure 3A Cross-sectional view along the DD direction,

[0076] Figure 3F For along Figure 3A Cross-section along the EE direction;

[0077] Figure 4A A top view of a plurality of stacked structures provided by an exemplary embodiment;

[0078] Figure 4B For along Figure 4A Cross-section view along the AA direction;

[0079] Figure 5A A top view after forming a first groove is provided for an exemplary embodiment;

[0080] Figure 5B For along Figure 5A Cross-section view along the AA direction;

[0081] Figure 5C For along Figure 5A Cross-section along the BB direction;

[0082] Fig. 6A A top view after forming a second groove and a third hole is provided for an exemplary embodiment;

[0083] Figure 6B For along Fig. 6A Cross-section view along the AA direction;

[0084] Figure 6C For along Fig. 6A Cross-section along the BB direction;

[0085] Fig. 7A A top view after forming a third gate insulating layer, a second semiconductor layer and a first protective layer provided for an exemplary embodiment;

[0086] Figure 7B For along Fig. 7A Cross-section view along the AA direction;

[0087] Figure 7C For along Fig. 7A Cross-section along the BB direction;

[0088] Fig. 8A A top view of a second semiconductor layer after different layers are disconnected provided for an exemplary embodiment;

[0089] Figure 8B For along Fig. 8A Cross-section view along the AA direction;

[0090] Figure 8C For along Fig. 8A Cross-section along the BB direction;

[0091] Fig. 9A A top view after forming a second bit line is provided for an exemplary embodiment;

[0092] Fig. 9B For along Fig. 9A Cross-section view along the AA direction;

[0093] Fig. 9C For along Fig. 9ACross-section along the BB direction;

[0094] Fig. 10A A top view after disconnecting second bit lines of different layers provided for an exemplary embodiment;

[0095] Fig. 10B For along Fig. 10A Cross-section view along the AA direction;

[0096] Fig. 10C For along Fig. 10A Cross-section along the BB direction;

[0097] Fig.11A A top view after forming a third electrode of a second transistor provided for an exemplary embodiment;

[0098] Fig. 11B For along Fig.11A Cross-section view along the AA direction;

[0099] Fig. 11C For along Fig.11A Cross-section along the BB direction;

[0100] Fig. 12A A top view after forming a fifth hole is provided for an exemplary embodiment;

[0101] Fig. 12B For along Fig. 12A Cross-section view along the AA direction;

[0102] Fig. 12C For along Fig. 12A Cross-section along the BB direction;

[0103] Fig.13A A top view after forming a fourth gate insulating layer and a second word line is provided for an exemplary embodiment;

[0104] Fig. 13B For along Fig.13A Cross-section view along the AA direction;

[0105] Fig. 13C For along Fig.13A Cross-section along the BB direction;

[0106] Fig.14A A top view after forming a third groove and a second hole is provided for an exemplary embodiment;

[0107] Fig. 14B For along Fig.14A Cross-section view along the AA direction;

[0108] Fig. 14C For along Fig.14A Cross-section along the BB direction;

[0109] Fig.14D For along Fig.14A Cross-sectional view in the CC direction;

[0110] Fig.15A A top view after forming a third protective layer provided for an exemplary embodiment;

[0111] Fig. 15B For along Fig.15A Cross-section view along the AA direction;

[0112] Fig. 15C For along Fig.15A Cross-section along the BB direction;

[0113] Fig.15D For along Fig.15A Cross-sectional view in the CC direction;

[0114] Fig.16A A top view after exposing the third groove is provided for an exemplary embodiment;

[0115] Fig. 16B For along Fig.16A Cross-section view along the AA direction;

[0116] Fig. 16C For along Fig.16A Cross-section along the BB direction;

[0117] Fig.16D For along Fig.16A Cross-sectional view in the CC direction;

[0118] Fig.17A A top view after forming a first bit line is provided for an exemplary embodiment;

[0119] Fig. 17B For along Fig.17A Cross-section view along the AA direction;

[0120] Fig. 17C For along Fig.17A Cross-section along the BB direction;

[0121] Fig.17D For along Fig.17A Cross-sectional view in the CC direction;

[0122] Fig.18A A top view after forming a first gate insulating layer and a first word line is provided for an exemplary embodiment;

[0123] Fig.18B For along Fig.18A Cross-section view along the AA direction;

[0124] Fig.18C For along Fig.18ACross-section along the BB direction;

[0125] Fig.18D For along Fig.18A Cross-sectional view in the CC direction;

[0126] Fig.19A A top view after forming a first hole is provided for an exemplary embodiment;

[0127] Fig.19B For along Fig.19A Cross-section view along the AA direction;

[0128] Fig.19C For along Fig.19A Cross-section along the BB direction;

[0129] Fig.19D For along Fig.19A Cross-sectional view in the CC direction;

[0130] Fig.19E For along Fig.19A Cross-section along the mid-DD direction;

[0131] Fig. 20A A top view after forming a first semiconductor layer, a second gate insulating layer and a control electrode provided for an exemplary embodiment;

[0132] Fig. 20B For along Fig. 20A Cross-section view along the AA direction;

[0133] Fig. 20C For along Fig. 20A Cross-section along the BB direction;

[0134] Fig.20D For along Fig. 20A Cross-sectional view in the CC direction;

[0135] Fig.20E For along Fig. 20A Cross-sectional view along the DD direction,

[0136] Fig.20F For along Fig. 20A Cross-sectional view along the EE direction. DETAILED DESCRIPTION

[0137] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0138] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0139] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0140] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0141] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0142] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0143] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0144] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0145] In the present disclosure, "connection" includes the case where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0146] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0147] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.

[0148] In the embodiments of the present disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0149] For metal oxide semiconductors as the channels of transistors, some semiconductor materials are very sensitive to the surrounding environment, especially hydrogen and oxygen. Therefore, when manufacturing semiconductor devices, the effects of dry and wet etching on semiconductor materials should be avoided as much as possible. In 3D stacked semiconductor devices, the semiconductor layer is located in the hole that runs through each layer of transistors, and the sidewalls of the hole are distributed with semiconductor layers. There are effective channels located in the transistor layer and parasitic channels located between adjacent transistor layers. The parasitic MOS corresponding to the parasitic channel affects the power consumption of the device. One way to remove the parasitic MOS is to remove the parasitic channel by etching, but the effective channel is easily affected during the etching process, affecting the device performance.

[0150] In the exemplary embodiment of the present disclosure, the parasitic semiconductor layer is retained, and after the semiconductor layer is deposited on the inner side wall of the hole, the process step of removing the parasitic channel is not performed, and the parasitic channel is not etched, but a control electrode for controlling the parasitic MOS is added, that is, two gate electrodes are set in the semiconductor device, the first gate electrode controls the opening and closing of the effective transistor, and the second gate electrode controls the closing of the parasitic transistor between the effective transistors. The off voltage of the transistor (for example, it can be a negative voltage for an n-type transistor) is applied to the second gate electrode to turn off the parasitic transistor. When data is accessed (written or read), the on voltage (for example, a positive voltage greater than the transistor on threshold for an n-type transistor) is applied to the first gate electrode to turn on the transistor, and the parasitic transistor is not turned on (the first gate electrode is far from the parasitic channel of the parasitic transistor and cannot control the parasitic transistor); in the non-working state (stand-by state) of the storage unit or the transistor, such as the off state, the off voltage (for example, it can be a negative voltage for an n-type transistor) is applied to both the first gate electrode and the second gate electrode, thereby turning off the transistor and the parasitic transistor. This solution does not remove the parasitic semiconductor layer, and there is no impact on the channel of the transistor due to the removal of the parasitic semiconductor layer. It can also avoid leakage caused by the parasitic transistor, thereby improving device performance.

[0151] Figure 1A A circuit diagram of a semiconductor device is provided for an exemplary embodiment. Figure 1B for Figure 1A Schematic diagram of the circuit of a memory cell in the semiconductor device shown. Figure 2A A schematic plan view of a semiconductor device provided by an exemplary embodiment. Figure 2B For along Figure 2A Cross-section view along the AA direction; Figure 2C For along Figure 2A Cross-section along the BB direction; Figure 2D For along Figure 2A Cross-section view in the CC direction; Figure 2E For along Figure 2A Cross-sectional view along the DD direction, Figure 2F For along Figure 2A Cross-sectional view along the EE direction.

[0152] like Figure 1A , Figure 1B , FIG. 2A to FIG. 2F As shown, an embodiment of the present disclosure provides a semiconductor device, including a plurality of memory cell arrays vertically stacked on a substrate 1 , and the plurality of memory cell arrays may be distributed along a third direction Z. The third direction Z may be perpendicular to the substrate 1 .

[0153] The memory cell array may include a plurality of first bit lines 30 (eg Figure 1AWBL00, WBL01, WBL02), a plurality of second bit lines 31 (such as Figure 1A RBL00, RBL01, RBL02), a plurality of first word lines 40 (such as Figure 1A WWL00, WWL01), a plurality of second word lines 46 (such as Figure 1A RWL00, RWL01) and multiple memory cells S1 in the memory cell array. The multiple memory cells S1 of the memory cell array may be arrayed along a first direction X and a second direction Y. The first direction X and the second direction Y may intersect. The first bit line 30 and the second bit line 31 may be conductive lines extending along a second direction Y parallel to the substrate 1, and multiple first bit lines 30 of the same memory cell array may be spaced apart from each other, and multiple second bit lines 31 of the same memory cell array may be spaced apart from each other. The multiple first bit lines 30 may be distributed along the first direction X. The multiple second bit lines 31 may be distributed along the first direction X. The first bit lines 30 and the second bit lines 31 may be spaced apart from each other along the first direction X. The first bit lines 30 of different memory cell arrays may be stacked and arranged on the substrate 1, and the first bit lines 30 at the same position of different layers may be spaced apart from each other, and the second bit lines 31 of different memory cell arrays may be stacked and arranged on the substrate 1, and the second bit lines 31 at the same position of different layers may be spaced apart from each other.

[0154] In some embodiments, the first bit line 30 is, for example, a write bit line (WBL), the second bit line 31 is, for example, a read bit line (RBL), the first word line 40 is, for example, a write word line (WWL), and the second word line 46 is, for example, a read word line (RWL).

[0155] The first word line 40 and the second word line 46 may extend along a third direction Z, and memory cells stacked at the same position in a direction perpendicular to the substrate 1 share the first word line 40 and the second word line 46 .

[0156] The memory cell may be a 2T0C memory cell, the memory cell may include a first transistor and a second transistor, the first transistor may include a first semiconductor sublayer 231, a first gate electrode 26, a first electrode 51, and a second electrode 52. The first gate electrode 26 may be a part of a first word line 40, and the first gate electrode 26 of a first transistor at a same position in a different layer may be a part of the same first word line 40. The first electrode 51 may be connected to a third gate electrode 21 of a second transistor, and the second electrode 52 may be connected to a first bit line 30. The second electrode 52 may be a part of the first bit line 30.

[0157] The second electrodes 52 of the first transistors of the same memory cell array in the same column may be connected to the same first bit line 30. That is, the second electrodes 52 of the first transistors in the same column distributed along the second direction Y are connected to form the first bit line 30 extending along the second direction Y.

[0158] The first transistor and the second transistor of the same memory cell may be distributed along a first direction X.

[0159] The first transistor may further include: a second gate electrode 28 , and the second gate electrodes 28 of the first transistors at the same position of the memory cell arrays at different layers are connected to form a control electrode 45 .

[0160] In some embodiments, the second transistor may be a dual-gate structure, and may include a third gate electrode 21, a fourth gate electrode 22, a second semiconductor layer 25, a third electrode 61, and a fourth electrode 62. The third gate electrode 21 is connected to the first electrode 51, and the second semiconductor layer 25 is connected to the third electrode 61 and the fourth electrode 62, respectively. The connection end of the first electrode 51 and the third gate electrode 21 serves as a storage node (SN), the fourth gate electrodes 22 of the memory cells at the same position in different layers are connected to form a second word line 46, the third electrode 61 may be connected to a ground terminal (GND), and the fourth electrode 62 may be connected to a second bit line 31. The fourth electrodes 62 of the second transistors of the memory cells in the same column of the same memory cell array may be connected to the same second bit line 31. That is, the fourth electrodes 62 of the second transistors in the same column distributed along the second direction Y are connected to form a second bit line 31 extending along the second direction Y.

[0161] In some embodiments, the second transistor can be a single-gate structure, including a third gate electrode 21, a second semiconductor layer 25, a third electrode 61 and a fourth electrode 62, the third gate electrode 21 is connected to the first electrode 51, the second semiconductor layer 25 is respectively connected to the third electrode 61 and the fourth electrode 62, and the third electrodes 61 of the storage cells at the same position in different layers are connected to form a second word line 46.

[0162] The connection end of the first electrode 51 and the third gate electrode 21 serves as a storage node (SN), the fourth gate electrode 22 is connected to form a second word line 46, the third electrode 61 can be connected to the ground terminal (GND), and the fourth electrode 62 can be connected to the second bit line 31. The fourth electrodes 62 of the second transistors of the memory cells in the same column of the same memory cell array can be connected to the same second bit line 31. That is, the fourth electrodes 62 of the second transistors in the same column distributed along the second direction Y are connected to form a second bit line 31 extending along the second direction Y.

[0163] In some embodiments, the first transistor may be a write transistor and the second transistor may be a read transistor.

[0164] The following description is made by taking a semiconductor device including a plurality of vertically stacked memory cells at the same position as an example.

[0165] like FIG. 2A to FIG. 2E As shown, an embodiment of the present disclosure provides a semiconductor device, which may include: a plurality of memory cells S1 stacked in a direction perpendicular to a substrate 1;

[0166] Each layer of the storage unit S1 includes: a first transistor and a second transistor; the first transistor and the second transistor are sequentially distributed along a first direction X parallel to the substrate 1;

[0167] A plurality of first transistors are distributed in different layers and stacked along a direction perpendicular to the substrate 1, wherein the first transistor may include a first electrode 51, a second electrode 52, a first semiconductor sublayer 231 and a first gate electrode 26, wherein the first semiconductor sublayer 231 is respectively connected to the first electrode 51 and the second electrode 52 of the first transistor;

[0168] The second transistor may include a third gate electrode 21, a fourth gate electrode 22, a second semiconductor layer 25, a third electrode 61 and a fourth electrode 62; the third gate electrode 21 is connected to the first electrode 51; the second semiconductor layer 25 is connected to the third electrode 61 and the fourth electrode 62 respectively;

[0169] A second semiconductor sublayer 232 is disposed between adjacent first semiconductor sublayers 231. The first semiconductor sublayer 231 and the second semiconductor sublayer 232 are connected to form an integrated structure called a first semiconductor layer 23. The first semiconductor layer 23 extends in a direction perpendicular to the substrate 1. The first semiconductor sublayer 231 is a channel region of the first transistor, and the second semiconductor sublayer 232 is a parasitic semiconductor layer between adjacent first transistors.

[0170] A first word line 40, which penetrates the different layers and extends in a direction perpendicular to the substrate 1, and the first gate electrode 26 of each of the first transistors is a part of the first word line 40;

[0171] A first hole K1 and a second hole K2 penetrating different layers, wherein the second hole K2 is connected to the first hole K1, and the first semiconductor layer 23 and the control electrode 45 extending in a direction perpendicular to the substrate 1 and penetrating different layers are arranged in the first hole K1, wherein the first semiconductor layer 23 surrounds the side wall of the control electrode 45;

[0172] The first word line 40 is arranged in the second hole and extends through the different layers in a direction perpendicular to the substrate 1 . The distance between the first word line 40 and the first semiconductor sublayer 231 in a direction parallel to the substrate 1 is smaller than the distance between the first word line 40 and the second semiconductor sublayer 232 in a direction parallel to the substrate 1 .

[0173] The semiconductor device provided in this embodiment sets a control electrode 45, and makes the first word line 40 control the second semiconductor sublayer 232 weaker than the first semiconductor sublayer 231, so that the parasitic transistor can be turned off by the control electrode 45 to avoid leakage caused by the parasitic transistor, and there is no need to etch and remove the parasitic semiconductor layer to avoid affecting the channel area of ​​the transistor, thereby simplifying the process and improving device performance.

[0174] Among them, the first gate electrode 26 of the first transistor of different layers can be a part of the first word line 40, that is, before and after the first word line 40 is formed, there is no need to separately make the first gate electrode 26. After the first word line 40 is made, a part of the first word line 40 plays the role of the first gate electrode 26.

[0175] The control electrode 45 can extend through the different layers in a direction perpendicular to the substrate 1 and be located in the area enclosed by the first semiconductor layer of each stacked first transistor. The control electrode 45 includes a plurality of second gate electrodes 28. That is, the second gate electrode 28 is a part of the control electrode 45. Before and after the control electrode 45 is formed, there is no need to separately make the second gate electrode 28. After the control electrode 45 is made, a part of the control electrode 45 plays the role of the second gate electrode 28. The second gate electrode 28, the second semiconductor sublayer 232, and the two adjacent first semiconductor sublayers 231 constitute a parasitic transistor. The second gate electrode 28 can control the closing of the second semiconductor sublayer 232 so that the two adjacent first semiconductor sublayers 231 are disconnected in terms of signal.

[0176] In some embodiments, the control electrode 45 is configured to apply a first turn-off voltage during the working phase of the transistor connected to the first word line 40 so that the parasitic transistor between adjacent first transistors is turned off; and to apply a second turn-off voltage during the non-working phase of the transistor connected to the first word line 40 so as to turn off the first transistor together with the first word line 40.

[0177] In some embodiments, the first semiconductor layer 23 may surround a sidewall of the control electrode 45 .

[0178] In some embodiments, the first semiconductor layer 23 may extend on the side wall of the control electrode 45 to form an annular semiconductor layer extending in a direction perpendicular to the substrate 1. The first semiconductor layer 23 may extend only in a direction perpendicular to the substrate 1 (there may be a region protruding in a horizontal direction during the extension process), or the main body of the first semiconductor layer 23 extends in a direction perpendicular to the substrate 1, and may extend in a horizontal direction (parallel to the substrate 1) at the end.

[0179] In the present disclosure, surrounding can be understood as partial or full surrounding. For example, the first semiconductor layer 23 surrounding the control electrode 45 can be partially or fully surrounding the control electrode 45. In some embodiments, the surrounding can be a full surrounding as a whole, and the cross-section of the first semiconductor layer 23 can be a closed ring. The interception direction of the cross-section is intercepted along a direction parallel to the substrate. In some embodiments, the surrounding can be a partial surrounding, and the cross-section after the surrounding is not closed, but presents a ring shape. For example, a ring with an opening can be understood as a U-shaped cross-section, etc., where the interception direction of the cross-section is parallel to the substrate.

[0180] The semiconductor device may further include a first gate insulating layer 24 surrounding the sidewall of the first word line 40 and extending in a direction perpendicular to the substrate 1 . The first word line 40 is insulated from the first semiconductor layer 23 by the first gate insulating layer 24 .

[0181] It can be understood that the first word line 40 and the control electrode 45 are respectively located on both sides of the first semiconductor layer 23, and are respectively connected to the first semiconductor layer 23 through the first gate insulating layer 24, so as to simultaneously control the channel region corresponding to the effective transistor of the first semiconductor layer 23, and also simultaneously control the parasitic semiconductor layer between the effective transistors.

[0182] The semiconductor device may further include a second gate insulating layer 27 surrounding the side wall of the control electrode 45 and extending in a direction perpendicular to the substrate 1 . The second gate insulating layer 27 is arranged between the side wall of the control electrode 45 and the side wall of the first semiconductor layer 23 . The control electrode 45 is insulated from the first semiconductor layer 23 by the second gate insulating layer 27 .

[0183] In some embodiments, the semiconductor device may further include:

[0184] Insulating layers and conductive layers are alternately distributed from top to bottom in a direction perpendicular to the substrate 1; the first hole K1 and the second hole K2 penetrate each of the insulating layers and each of the conductive layers;

[0185] The first gate insulating layer 24 surrounding the side wall of the first word line 40 and the first word line 40 are sequentially distributed in the second hole K2 from outside to inside;

[0186] The first semiconductor layer 23, the second gate insulating layer 27 surrounding the side wall of the control electrode 45, and the control electrode 45 are sequentially distributed in the first hole K1 from outside to inside;

[0187] The first electrode 51 and the second electrode 52 are disposed on the conductive layer.

[0188] The solution provided in this embodiment can form the word line 40, the first gate insulating layer 24, the control electrode 45, the second gate insulating layer 27, and the semiconductor layer 23 at one time, thereby simplifying the process.

[0189] In some embodiments, the orthographic projection of the first sub-hole of the first hole K1 located in the insulating layer on the substrate 1 may fall within the orthographic projection of the second sub-hole of the first hole K1 located in the conductive layer on the substrate 1, that is, the aperture of the first sub-hole of the first hole K1 located in the insulating layer is smaller than the aperture of the second sub-hole of the first hole K1 located in the conductive layer. The solution provided in this embodiment can make the distances between the first word line 40 and the first semiconductor sublayer 231 and the second semiconductor sublayer 232 different by setting the first sub-hole and the second sub-hole with different apertures (the first semiconductor sublayer 231 is located in the second sub-hole, the second semiconductor sublayer 232 is located in the first sub-hole, and the first semiconductor sublayer 231 is closer to the outside of the first hole K1 relative to the second semiconductor sublayer 232, so that the first semiconductor sublayer 231 is closer to the first word line 40 than the second semiconductor sublayer 232), so that the first word line 40 controls the second semiconductor sublayer 232 less than the first semiconductor sublayer 231, thereby preventing the first word line 40 from turning on the parasitic transistor when turning on the first transistor.

[0190] In some embodiments, the orthographic projection of the third sub-hole of the second hole K2 located in the insulating layer on the substrate 1 may fall within the orthographic projection of the fourth sub-hole of the second hole K2 located in the conductive layer on the substrate 1, that is, the aperture of the third sub-hole of the second hole K2 located in the insulating layer is smaller than the aperture of the fourth sub-hole of the second hole K2 located in the conductive layer. The solution provided in this embodiment can make the distances between the first word line 40 and the first semiconductor sublayer 231 and the second semiconductor sublayer 232 different by setting the third sub-hole and the fourth sub-hole of different apertures (the first semiconductor sublayer 231 is located in the area where the conductive layer is located, and the first word line 40 protrudes relative to the fourth sub-hole in the third sub-hole (located in the conductive layer), so that the first word line 40 is close to the first semiconductor sublayer 231 and far from the second semiconductor sublayer 232), so that the control of the first word line 40 on the second semiconductor sublayer 232 is weaker than that on the first semiconductor sublayer 231, so as to avoid the first word line 40 turning on the parasitic transistor when the first transistor is turned on.

[0191] In some embodiments, the orthographic projection of the third sub-hole of the second hole K2 located in the insulating layer on the substrate 1 may fall within the orthographic projection of the fourth sub-hole of the second hole K2 located in the conductive layer on the substrate 1, and the orthographic projection of the first sub-hole of the first hole K1 located in the insulating layer on the substrate 1 may fall within the orthographic projection of the second sub-hole of the first hole K1 located in the conductive layer on the substrate 1. Compared with the previous two solutions, the solution provided in this embodiment can further increase the distance between the first word line 40 and the second semiconductor layer 232, reduce the influence of the first word line 40 on the parasitic transistor, and is more conducive to shutting down the parasitic transistor.

[0192] In some embodiments, the fourth gate electrodes 22 of the second transistors of the memory cells at the same position in multiple layers are connected to form a second word line 46 extending in a direction perpendicular to the substrate 1 .

[0193] In some embodiments, the third gate electrode 21 and the first electrode 51 of the same memory cell are connected to form an integrated structure, that is, the third gate electrode 21 and the first electrode 51 share the same electrode.

[0194] In some embodiments, the first electrode 51 and the second electrode 52 are distributed on the outer wall of the first semiconductor sublayer 231 and are spaced apart along the first direction X, and the first word line 40 is distributed in the area between the first electrode 51 and the second electrode 52 on the outer wall of the first semiconductor sublayer 231 .

[0195] In some embodiments, a first groove with an opening away from the first word line 40, the control electrode 45 and the second electrode 52 is provided between adjacent insulating layers, that is, the first groove is a lateral groove, the bottom wall of the first groove exposes the first gate insulating layer 24 and the first semiconductor sublayer 231, the first electrode 51 is distributed on the bottom wall of the first groove and the side wall perpendicular to the substrate 1, that is, on a plane parallel to the substrate 1, the cross section of the first electrode 51 is U-shaped with an opening away from the first word line 40, the second semiconductor layer 25 is distributed on the bottom wall of the first groove and the side wall perpendicular to the substrate 1, and is also distributed on the adjacent insulating layer constituting the side wall of the first groove. That is, the second semiconductor layer 25 is provided on the inner wall of the first groove (including the bottom wall and each side wall). The second semiconductor layer 25 is insulated from the first electrode 51 by the third gate insulating layer 29.

[0196] In some embodiments, the semiconductor device further includes a second groove disposed on a side of the first groove away from the first semiconductor layer 23 and extending along the second direction Y, the second groove is connected to a plurality of first grooves in the same column, the opening of the second groove is away from the first electrode 51, the second semiconductor layers 25 of the second transistors in the same column distributed along the second direction Y are connected to form an integrated structure, and the integrated structure formed by the second semiconductor layer 25 is also disposed on the sidewalls and bottom wall of the second groove. The third gate insulating layer 29 is also distributed on the sidewalls and bottom wall of the second groove.

[0197] In some embodiments, the second bit line 31 is distributed on the bottom wall and side wall of the second groove provided with the second semiconductor layer 25. That is, the semiconductor device is provided with a second groove extending along the second direction, the second groove is connected to a plurality of first grooves, and the second semiconductor layer 25 and the second bit line 31 are sequentially provided on the inner wall of the second groove. The second semiconductor layer 25 is provided on the inner wall of the first groove.

[0198] In some embodiments, on a plane parallel to the substrate 1 , a cross section of the third electrode 61 is located within a U-shaped opening formed by the first electrode 51 .

[0199] In some embodiments, the third electrodes 61 of the second transistors of the memory cells at the same position in multiple layers are connected to form an integrated structure extending in a direction perpendicular to the substrate 1. The integrated structure formed by the connection of the third electrodes 61 includes a vertical portion extending in a direction perpendicular to the substrate 1 and a horizontal portion extending from the vertical portion in a horizontal direction, and the horizontal portion is connected to the second semiconductor layer 25 distributed on the bottom wall of the first groove, and is connected to the second semiconductor layer 25 distributed in a region adjacent to the bottom wall of the first groove.

[0200] In some embodiments, the fourth gate electrodes 22 of the second transistors of the storage cells at the same position in multiple layers are connected to form an integrated structure extending in a direction perpendicular to the substrate 1, and the orthographic projection of the fourth gate electrode 22 on the substrate 1 is located within the orthographic projection of the first groove on the substrate 1.

[0201] In some embodiments, the second semiconductor layers 25 of the second transistors of different layers are arranged at intervals.

[0202] In some embodiments, the semiconductor device may further include:

[0203] A third hole K3 penetrating each of the insulating layers and each of the conductive layers; the third hole is divided into a fourth hole K4 and a fifth hole K5 penetrating each of the insulating layers and each of the conductive layers, and the arrangement direction of the fourth hole K4 and the fifth hole K5 is the same as the arrangement direction of the first transistor and the second transistor;

[0204] The third hole K3 is provided with a third gate insulating layer 29 and a second semiconductor layer 25 from outside to inside;

[0205] A plurality of third electrodes 61 connected into an integrated structure are distributed in the fourth hole K4;

[0206] The fourth gate insulating layer 39 and the fourth gate electrode 22 are sequentially distributed in the fifth hole K5 from inside to outside.

[0207] In some embodiments, the orthographic projection of the fifth sub-hole of the third hole K3 located in the insulating layer on the substrate 1 falls within the orthographic projection of the sixth sub-hole of the third hole K3 located in the conductive layer on the substrate 1. That is, the aperture of the fifth sub-hole of the third hole K3 located in the insulating layer is smaller than the aperture of the sixth sub-hole of the third hole K3 located in the conductive layer.

[0208] In some embodiments, the fourth hole K4 includes a seventh sub-hole located in the insulating layer and an eighth sub-hole located in the conductive layer, and a boundary of the seventh sub-hole close to the fifth hole K5 in the orthographic projection of the substrate 1 overlaps with a boundary of the eighth sub-hole close to the fifth hole K5 in the orthographic projection of the substrate 1, and other boundaries of the seventh sub-hole in the orthographic projection of the substrate 1 fall within the orthographic projection of the eighth sub-hole in the substrate 1.

[0209] In some embodiments, the fifth hole K5 includes a ninth sub-hole located in the insulating layer and a tenth sub-hole located in the conductive layer, and a boundary of the ninth sub-hole close to the fourth hole K4 in the orthographic projection of the substrate 1 overlaps with a boundary of the tenth sub-hole close to the fourth hole K4 in the orthographic projection of the substrate, and other boundaries of the ninth sub-hole in the orthographic projection of the substrate 1 fall within the orthographic projection of the tenth sub-hole on the substrate.

[0210] In some embodiments, the arrangement direction of the first holes K1 and the second holes K2 may be perpendicular to the arrangement direction of the first electrodes 51 and the second electrodes 52. The arrangement direction of the first electrodes 51 and the second electrodes 52 is, for example, the first direction X, and the arrangement direction of the first holes K1 and the second holes K2 is, for example, the second direction Y. That is, on a plane parallel to the substrate 1, the first holes K1 and the second holes K2 may be arranged along the second direction Y, and the arrangement order of the first holes K1 and the second holes K2 along the second direction Y is not limited to Figure 2A As shown in FIG, the positions of the first hole K1 and the second hole K2 can be interchanged.

[0211] In some embodiments, the second hole K2 and the first hole K1 may be located between the first electrode 51 and the second electrode 52 .

[0212] In some embodiments, the size of the second sub-hole along the arrangement direction of the first electrode 51 and the second electrode 52 may be the same as the size of the fourth sub-hole along the arrangement direction of the first electrode 51 and the second electrode 52. That is, the size of the second sub-hole along the first direction X may be the same as the size of the fourth sub-hole in the first direction X.

[0213] In some embodiments, the sidewall of the first semiconductor sublayer 231 may be connected to the sidewall of the first gate insulating layer 24 , and the insulating layer may be disposed between the sidewall of the second semiconductor sublayer 232 and the sidewall of the first gate insulating layer 24 .

[0214] In some embodiments, the first electrode 51 and the second electrode 52 are distributed on the outer wall of the first semiconductor sublayer 231 and are spaced apart along a first direction X parallel to the substrate 1 , and the word line 40 is distributed in the area between the first electrode 51 and the second electrode 52 on the outer wall of the first semiconductor sublayer 231 .

[0215] In some embodiments, the second electrode 52 of the first transistor may be a portion of the first bit line 30 to which the second electrode 52 is connected. For example, the first bit line 30 is a straight line (eg Figure 2A As shown), the side wall of the straight line is connected to the first semiconductor layer 23, or the first bit line 30 has a branch of an integral design, and the branch is connected to the first semiconductor layer 23, wherein the extension direction of the branch intersects with the extension direction of the first bit line 30, such as approximately perpendicular.

[0216] The branches may be a plurality of branches on one sidewall of the first bit line 30 , or a plurality of branches on both sidewalls at the same time, and each branch may form a transistor or a memory cell accordingly. Figure 2A In the embodiment, the first bit line 30 is a straight line, and the side wall of the straight line is connected only to the first semiconductor layer 23 located on one side of the first bit line 30. In the present embodiment, transistors in two adjacent columns are connected to different first bit lines 30, and the first bit lines 30 connected to the two adjacent columns of transistors are separated by an insulating film layer. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the first bit line 30 may be connected to the first semiconductor layers 23 on both sides of the first bit line 30, that is, one first bit line 30 may connect the first semiconductor layers 23 of the first transistors in two adjacent columns.

[0217] FIG. 2A to FIG. 2FThe semiconductor device structure shown is only an example, and the embodiments of the present disclosure are not limited thereto. For structures in which there are semiconductor layers extending through multiple layers in a direction perpendicular to the substrate 1, resulting in the presence of parasitic transistors between adjacent first transistors, the parasitic transistors can be turned off by setting a corresponding second gate electrode for controlling the parasitic transistors. The embodiments of the present disclosure do not limit the position and shape of the second gate electrode, and the second gate electrodes of parasitic transistors in different layers can be manufactured separately.

[0218] Figure 1C A circuit diagram of a semiconductor device is provided for another exemplary embodiment. Figure 1D for Figure 1C Schematic diagram of the circuit of a memory cell in the semiconductor device shown. Figure 3A A schematic plan view of a semiconductor device provided for another exemplary embodiment, Figure 3B For along Figure 3A Cross-section view along the AA direction;

[0219] Figure 3C For along Figure 3A Cross-section along the BB direction; Figure 3D For along Figure 3A Cross-section view in the CC direction;

[0220] Figure 3E For along Figure 3A Cross-sectional view along the DD direction, Figure 3F For along Figure 3A Cross-sectional view along the EE direction. Figure 1C , Figure 1D , FIG. 3A to FIG. 3F As shown, in this embodiment, the second transistor is a single-gate structure, that is, the second transistor includes a third gate electrode 21, a third electrode 61, a fourth electrode 62, a third gate insulating layer 29, and a second semiconductor layer 25. The positions and shapes of the third gate electrode 21, the third electrode 61, the fourth electrode 62, the third gate insulating layer 29, and the second semiconductor layer 25 can refer to the previous embodiment and will not be repeated. The second transistor does not include the fourth gate electrode 22 and the fourth gate insulating layer 39, and the positions where the fourth gate electrode 22 and the fourth gate insulating layer 39 are located can be filled with an insulating film layer. The structure of the first transistor can refer to the previous embodiment and will not be repeated. In this embodiment, the third electrode 61 of the second transistor at the same position is connected to form a second word line 46.

[0221] The technical solution of this embodiment is further explained below through the manufacturing process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which are mature manufacturing processes in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0222] In some embodiments, when the second transistor has a dual-gate structure, the manufacturing process of the semiconductor device may include:

[0223] 101) providing a substrate 1, depositing a conductive layer film and a first insulating film alternately on the substrate 1 in sequence to form a stacked structure, and depositing a hard mask film on the stacked structure to form a hard mask layer 9, such as Figure 4A and Figure 4B As shown, Figure 4A A top view of a stacked structure is provided for an exemplary embodiment. Figure 4B For along Figure 4A The cross-sectional view along the AA direction. Figure 4B As shown, the stack structure may include a stack of conductive layers 11 and first insulating layers 10 that are alternately arranged.

[0224] In some embodiments, substrate 1 may be a semiconductor substrate having one or more layers, structures or regions formed thereon.Substrate 1 may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0225] In some embodiments, the first insulating film and the conductive layer film may be deposited by chemical vapor deposition.

[0226] In some embodiments, the first insulating film may be a low-K dielectric layer, that is, a dielectric layer with a dielectric constant K<3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ) and the like.

[0227] In some embodiments, the conductive layer film may be, for example, the following conductive materials:

[0228] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0229] Alternatively, it may be a conductive metal oxide, metal nitride, metal silicide, metal carbide, etc., such as conductive metal oxide materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, conductive metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0230] Alternatively, it may be polysilicon, silicon, germanium, silicon germanium, etc. which are conductive after being doped.

[0231] In some embodiments, the hard mask layer 9 includes but is not limited to at least one of the following: carbon, polysilicon, silicon oxide, etc.

[0232] Figure 4B The stacked structure shown in the figure includes three first insulating layers 10 and three conductive layers 11, which is only an example. In other embodiments, the stacked structure may include more or fewer first insulating layers 10 and conductive layers 11 that are alternately arranged.

[0233] 102) etching the stacked structure to form a first trench T1;

[0234] The etching the stack structure to form the first trench T1 may include:

[0235] The plurality of stacked structures are etched to form a plurality of first trenches T1 penetrating the plurality of stacked structures; the plurality of first trenches T1 extend along a first direction X, adjacent first trenches T1 include a first transistor region 100 and a second transistor region 200, and adjacent first transistor regions 100 along the first direction X include a first bit line region 300. The conductive layer 11 forms a preset pattern, and the preset pattern of the conductive layer 11 may include a plurality of first sub-portions and a second sub-portion connected to the first sub-portion, the first sub-portion may extend along the first direction X, and the second sub-portion may extend along the second direction Y, with reference to Figure 5A The preset pattern of the hard mask layer 9 shown in the figure, and the preset patterns of the other film layers are consistent with the preset pattern of the hard mask layer 9.

[0236] A second insulating film is deposited and polished to form a second insulating layer 13 filling the first trench T1; the second insulating layer 13 may be flush with the hard mask layer 9. Figure 5A , Figure 5B and Figure 5C As shown, Figure 5A This is a top view after the first trench T1 is formed. Figure 5B For along Figure 5A Cross-sectional view along the AA direction, Figure 5C For along Figure 5A The first direction X and the second direction Y may intersect. In some embodiments, the first direction X and the second direction Y may be perpendicular.

[0237] In some embodiments, the second insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ) and the like.

[0238] 103) forming a second trench T2 and a third hole K3;

[0239] The forming of the second trench T2 and the third hole K3 may include:

[0240] The stacked structure is dry-etched between the second transistor regions 200 adjacent to each other along the first direction X to form a second trench T2 penetrating the stacked structure, and a third hole K3 penetrating the stacked structure is formed in the second transistor region 200. The second trench T2 extends along the second direction Y. The third hole K3 includes a fifth sub-hole located in the first insulating layer 10 and a sixth sub-hole located in the conductive layer 11, and at this time, the apertures of the fifth sub-hole and the sixth sub-hole are consistent; the second trench T2 includes a first sub-trench located in the first insulating layer 10 and a second sub-trench located in the conductive layer 11, and at this time, the width of the first sub-trench along the first direction X is consistent with the width of the second sub-trench along the first direction X;

[0241] The conductive layer 11 is laterally etched in the third hole K3 along the first direction X and the second direction Y to expand the aperture of the sixth sub-hole of the third hole K3 located in the conductive layer 11, and the conductive layer 11 is laterally etched in the second trench T2 along the first direction X to expand the width of the second sub-groove of the second trench T2 located in the conductive layer 11 along the first direction X, so that the third hole K3 and the second trench T2 are connected, as shown in FIG. Fig. 6A , Figure 6B and Figure 6C As shown, Fig. 6A The top view after forming the second trench T2 and the third hole K3 is shown in FIG. Figure 6B For along Fig. 6A Cross-sectional view along the AA direction, Figure 6C For along Fig. 6A Cross-sectional view along the BB direction.

[0242] At this time, the third hole K3 forms a plurality of holes of two types with different sizes. Along the second direction Y, the aperture of the fifth sub-hole of the third hole K3 located in the first insulating layer 10 is smaller than the aperture of the sixth sub-hole of the third hole K3 located in the conductive layer 11, that is, the orthographic projection of the fifth sub-hole of the third hole K3 located in the first insulating layer 10 on the substrate 1 falls within the orthographic projection of the sixth sub-hole located in the conductive layer 11 on the substrate 1. Along the first direction X close to the second groove T2 side, the boundary of the orthographic projection of the fifth sub-hole on the substrate 1 overlaps with the boundary of the orthographic projection of the sixth sub-hole on the substrate 1 (the boundary of the fifth sub-hole is a part of the boundary of the sixth sub-hole), and along the first direction X away from the second groove T2 side, the orthographic projection of the fifth sub-hole on the substrate 1 falls within the orthographic projection of the sixth sub-hole located in the conductive layer 11 on the substrate 1. At this time, in addition to the first longitudinal hole K30 that penetrates the stacked structure along the direction perpendicular to the substrate 1, the third hole K3 also includes a first transverse groove K31 located in each conductive layer 11. The second trench T2 forms two types of grooves of different sizes. The width of the first sub-groove of the second trench T2 located in the first insulating layer 10 along the first direction X is smaller than the width of the second sub-groove located in the conductive layer 11 along the first direction X. The orthographic projection of the first sub-groove of the second trench T2 located in the first insulating layer 10 on the substrate 1 falls into the orthographic projection of the second sub-groove located in the conductive layer 11, and the third hole K3 is connected to the second trench T2. At this time, in addition to the first longitudinal trench T20 that penetrates the stacking structure in a direction perpendicular to the substrate 1, the second trench T2 also includes two transverse trenches located in each conductive layer 11: a first transverse trench T21 and a second transverse trench T22. Subsequently, a second bit line 31 is formed in the first transverse trench T21 and the second transverse trench T22, respectively, and the second transistors in the same layer and column are connected to the same second bit line 31. Therefore, the first transverse trench T21 and the second transverse trench T22 extend along the second direction Y to the area where the second transistors in the same layer and column are located. The conductive layer 11 is exposed on three sides of the sidewall of the sixth sub-hole, that is, when the conductive layer 11 is laterally etched, the conductive layer 11 is not completely etched through, and a portion of the conductive layer 11 is still retained. Fig. 6A In the area where the third hole K3 is located, the inner rectangle is the fifth sub-hole, and the outer rectangle is the sixth sub-hole. In the area where the second groove T2 is located, the inner strip running through the second direction Y is the first sub-groove, and the outer strip running through the second direction Y is the second sub-groove.

[0243] 104) forming a third gate insulating layer 29 and a second semiconductor layer 25 of the second transistor, and forming a first protective layer 8;

[0244] The forming of the third gate insulating layer 29 and the second semiconductor layer 25 of the second transistor, and the first protective layer 8 may include: depositing a third gate insulating film, a second semiconductor film and a first protective layer film in sequence on the substrate 1 forming the aforementioned structure to form the third gate insulating layer 29, the second semiconductor layer 25 and the first protective layer 8, wherein the first protective layer 8 fills the third hole K3 and the second trench T2, as shown in FIG. Fig. 7A , Figure 7B and Figure 7C As shown, Fig. 7A A top view after forming the third gate insulating layer 29, the second semiconductor layer 25 and the first protective layer 8, Figure 7B For along Fig. 7A Cross-sectional view along the AA direction, Figure 7C For along Fig. 7A The third gate insulating layer 29 covers the sidewalls and bottom wall of the third hole K3 and the sidewalls and bottom wall of the second trench T2.

[0245] In some embodiments, the third gate insulating film may include one or more layers of High-K dielectric material, such as a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. may be included. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials. The subsequent second gate insulating film and the first gate insulating film are similar to the third gate insulating film and will not be repeated.

[0246] In an exemplary embodiment of the present disclosure, the material of the second semiconductor layer 25 may be silicon or polysilicon with a band gap less than 1.65 eV, or may be a wide band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.

[0247] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may contain compounds of other elements, such as N, Si, etc., and may contain other small amounts of doping elements.

[0248] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific details can be adjusted according to the actual situation.

[0249] These materials have a wide band gap and a low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of dynamic memory.

[0250] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

[0251] The materials of the first semiconductor layer 23 and the second semiconductor layer 25 are similar and are not described in detail.

[0252] In some embodiments, the first protective layer film may be an insulating material, including but not limited to SiN and the like.

[0253] 105) disconnecting the second semiconductor layer 25 of different layers;

[0254] The disconnecting of the second semiconductor layer 25 of different layers may include: dry etching to remove the second semiconductor layer 25 and the first protective layer 8 located in the first longitudinal hole K30 and the first longitudinal groove T20 from the top layer to the bottom layer, so that the second semiconductor layer 25 is disconnected to form a plurality of parts, each part being a semiconductor layer of a second transistor, so that the parasitic semiconductor layer between the second transistors can be removed to reduce leakage;

[0255] Deposit a second protective layer film to form a second protective layer 7, such as Fig. 8A , Figure 8B and Figure 8CAs shown, Fig. 8A This is a top view after the second semiconductor layer 25 of different layers is disconnected. Figure 8B For along Fig. 8A Cross-sectional view along the AA direction, Figure 8C For along Fig. 8A The second protective layer 7 fills the first longitudinal hole K30 and the first longitudinal groove T20.

[0256] In some embodiments, the second protective layer film can be an insulating material, including but not limited to SiN and the like.

[0257] 106) forming a second bit line 31;

[0258] The forming of the second bit line 31 may include: dry etching to remove the second protection layer 7 in the first longitudinal groove T20 from the top layer to the bottom layer, and then passing an etching solution into the first longitudinal groove T20 to wetly etch and remove part of the first protection layer 8; that is, lateral etching to remove part of the first protection layer 8 in the first lateral groove T21 and the second lateral groove T22;

[0259] A first conductive film is deposited on the substrate 1 having the aforementioned structure to form a second bit line 31, wherein the second bit line 31 fills the first longitudinal trench T20, the first transverse trench T21 and the second transverse trench T22. Fig. 9A , Fig. 9B and Fig. 9C As shown, Fig. 9A is a top view after the second bit line 31 is formed. Fig. 9B For along Fig. 9A Cross-sectional view along the AA direction, Fig. 9C For along Fig. 9A Cross-sectional view along the BB direction.

[0260] In some embodiments, the first conductive film includes but is not limited to at least one of the following or a combination thereof:

[0261] Metals or alloys, for example, metals containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc., and metal alloys containing the aforementioned metals;

[0262] Alternatively, it can be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as tin-doped indium oxide (ITO), indium-doped zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), ruthenium oxide (RuOx) and other metal oxide conductive materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other metal nitride materials.

[0263] The materials of the subsequent second conductive film, the third conductive film, and the fourth conductive film are similar to those of the first conductive film, and are not described in detail.

[0264] 107) disconnecting the second bit line 31 of the different layer;

[0265] The disconnecting of different second bit lines 31 may include: dry etching the second bit lines 31 from the top layer to the bottom layer, removing the second bit lines 31 located in the first longitudinal trench T20, forming a plurality of second bit lines 31 distributed in different layers, so that the second bit lines 31 in different layers are disconnected, and the adjacent second bit lines 31 in the same layer are disconnected. Two adjacent second bit lines 31 are located in the first transverse trench T21 and the second transverse trench T22, respectively.

[0266] A third insulating film is deposited on the substrate 1 having the above structure to form a third insulating layer 14. Fig. 10A , Fig. 10B and Fig. 10C As shown, Fig. 10A FIG. 1 is a top view after disconnecting the second bit lines 31 of different layers. Fig. 10B For along Fig. 10A Cross-sectional view along the AA direction, Fig. 10C For along Fig. 10A The third insulating layer 14 fills the first longitudinal trench T20. The second bit lines 31 at the same position in different layers are separated by the first insulating layer 10, and the adjacent second bit lines 31 in the same layer are separated by the third insulating layer 14.

[0267] In some embodiments, the third insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ) and the like.

[0268] 108) forming a third electrode 61 of the second transistor;

[0269] The forming of the third electrode 61 of the second transistor may include: removing a portion of the second protection layer 7 from the top layer to the bottom layer in the third hole K3 by dry etching to form a fourth hole K4, wherein the fourth hole K4 is located at an end of the third hole K3 away from the second trench T2, and the fourth hole K4 is located in the seventh sub-hole of the first insulating layer 10, three side walls of which expose the third gate insulating layer 29, and one side wall of which exposes the second protection layer 7;

[0270] The portion of the first protection layer 8 located in the sixth sub-hole is removed by wet lateral etching through the fourth hole K4 to expose the portion of the second semiconductor layer 25 located in the sixth sub-hole, so that three side walls of the eighth sub-hole of the fourth hole K4 located in the conductive layer 11 expose the second semiconductor layer 25, and the other side wall exposes the first protection layer 8 and the second protection layer 7;

[0271] The second conductive film is deposited to fill the fourth hole K4 to form the third electrode 61. Fig.11A , Fig. 11B and Fig. 11C As shown, Fig.11A is a top view after forming the third electrode 61 of the second transistor, Fig. 11B For along Fig.11A Cross-sectional view along the AA direction, Fig. 11C For along Fig.11A The third electrodes 61 of the second transistors at the same position in different layers can be connected to form an integrated structure, and the third electrode 61 can be grounded later. In some embodiments, the third electrode 61 is, for example, a source electrode of the second transistor.

[0272] 109) forming a fifth hole K5;

[0273] The forming of the fifth hole K5 may include: removing the second protection layer 7 from the top layer to the bottom layer in the third hole K3 by dry etching to form the fifth hole K5, wherein the fifth hole K5 is located at one end of the third hole K3 close to the second trench T2, and the third gate insulating layer 29 is exposed on three side walls of the ninth sub-hole of the first insulating layer 10, and the third electrode 61 is exposed on one side wall;

[0274] The entire first protection layer 8 located in the sixth sub-hole is removed by wet lateral etching through the fifth hole K5, exposing a portion of the second semiconductor layer 25 located in the sixth sub-hole, so that the side wall of the tenth sub-hole of the fifth hole K5 located in the conductive layer 11 exposes the second semiconductor layer 25, the second bit line 31 and the third electrode 61, as shown in FIG. Fig. 12A , Fig. 12B and Fig. 12C As shown, Fig. 12A This is a top view after the fifth hole K5 is formed. Fig. 12B For along Fig. 12A Cross-sectional view along the AA direction, Fig. 12C For along Fig. 12A Cross-sectional view along the BB direction.

[0275] 110) forming a fourth gate insulating layer 39 and a second word line 46;

[0276] The forming of the fourth gate insulating layer 39 and the second word line 46 may include: depositing a fourth gate insulating film and a third conductive film filling the fifth hole K5 on the substrate 1 formed with the aforementioned structure in sequence, so as to form the fourth gate insulating layer 39 and the second word line 46. Fig.13A , Fig. 13B and Fig. 13C As shown, Fig.13A This is a top view after forming the fourth gate insulating layer 39 and the second word line 46. Fig. 13B For along Fig.13A Cross-sectional view along the AA direction, Fig. 13C For along Fig.13A The second word line 46 also serves as the gate electrodes of the plurality of second transistors, namely the fourth gate electrodes 22 . The fourth gate electrodes 22 of the plurality of second transistors are connected to form the second word line 46 .

[0277] 111) forming a third trench T3 and a second hole K2;

[0278] The forming of the third trench T3 and the second hole K2 may include: dry etching the stack structure, forming a third trench T3 penetrating the stack structure in the bit line region 300, and forming a second hole K2 penetrating the stack structure in the first transistor region 100, wherein the second hole K2 includes a third sub-hole located in the first insulating layer 10 and a fourth sub-hole located in the conductive layer 11, and at this time, the apertures of the third sub-hole and the fourth sub-hole are consistent; the third trench T3 includes a third sub-trench located in the first insulating layer 10 and a fourth sub-trench located in the conductive layer 11, and at this time, the width of the third sub-trench along the first direction X is consistent with the width of the fourth sub-trench along the first direction X;

[0279] The conductive layer 11 is laterally etched to enlarge the aperture of the fourth sub-hole of the second hole K2 located in the conductive layer 11, and to enlarge the width of the fourth sub-groove of the third trench T3 located in the conductive layer 11 along the first direction X, as shown in FIG. Fig.14A , Fig. 14B , Fig. 14C and Fig.14D As shown, Fig.14A This is a top view after the third trench T3 and the second hole K2 are formed. Fig. 14B For along Fig.14A Cross-sectional view along the AA direction, Fig. 14C For along Fig.14A Cross-sectional view along the BB direction, Fig.14D For along Fig.14ACross-sectional view along CC direction. At this time, the second hole K2 forms a plurality of holes of two types with different sizes, the aperture of the third sub-hole of the second hole K2 located in the first insulating layer 10 is smaller than the aperture of the fourth sub-hole located in the conductive layer 11, and the orthographic projection of the third sub-hole of the second hole K2 located in the first insulating layer 10 on the substrate 1 falls within the orthographic projection of the fourth sub-hole located in the conductive layer 11 on the substrate 1. The third trench T3 forms two types of grooves of different sizes, the width of the third sub-groove of the third trench T3 located in the first insulating layer 10 along the first direction X is smaller than the width of the fourth sub-groove located in the conductive layer 11 along the first direction X, the orthographic projection of the third sub-groove of the third trench T3 located in the first insulating layer 10 on the substrate 1 falls within the orthographic projection of the fourth sub-groove located in the conductive layer 11, and the second hole K2 and the third trench T3 are connected. At this time, in addition to the second longitudinal groove T30 that penetrates the stacking structure in a direction perpendicular to the substrate 1, the third groove T3 also includes two transverse grooves: a third transverse groove T31 and a fourth transverse groove T32. Subsequently, a first bit line 30 is formed in the third transverse groove T31 and the fourth transverse groove T32 respectively, and the first transistors in the same layer and column are connected to the same first bit line 30. Therefore, the third groove T3 extends along the second direction Y to the area where the first transistors in the same layer and column are located.

[0280] 112) forming a third protective layer 6;

[0281] The forming of the third protective layer 6 may include: depositing a third protective layer thin film on the substrate 1 forming the aforementioned structure to form the third protective layer 6, wherein the third protective layer 6 fills the second hole K2 and the third trench T3, as shown in FIG. Fig.15A , Fig. 15B , Fig. 15C and 15D As shown, Fig.15A This is a top view after the third protective layer 6 is formed. Fig. 15B For along Fig.15A Cross-sectional view along the AA direction, Fig. 15C For along Fig.15A Cross-sectional view along the BB direction, Fig.15D For along Fig.15A Cross-sectional view along CC direction.

[0282] In some embodiments, the third protection layer film is an insulating material having an etching selectivity ratio with the first insulating film, such as SiN.

[0283] 113) exposing the third trench T3;

[0284] Exposing the third trench T3 may include: etching away the third protection layer 6 of the third trench T3 to expose the third trench T3, that is, the third protection layer 6 in the third trench T3 is completely etched away, so as to subsequently form the first bit line 30 in the third trench T3. Fig.16A , Fig. 16B , Fig. 16C and Fig.16D As shown, Fig.16A is a top view after the third trench T3 is exposed, Fig. 16B For along Fig.16A Cross-sectional view along the AA direction, Fig. 16C For along Fig.16A Cross-sectional view along the BB direction, Fig.16D For along Fig.16A Cross-sectional view along CC direction.

[0285] In some embodiments, the third protection layer 6 in the second longitudinal trench T30 may be removed by dry etching first, and then the third protection layer 6 in the third transverse trench T31 ​​and the fourth transverse trench T32 may be removed by wet transverse etching.

[0286] 114) forming a first bit line 30;

[0287] The forming of the first bit line 30 may include: depositing a fourth conductive film on the substrate 1 forming the above structure; removing the fourth conductive film in the second longitudinal groove T30 from the top layer to the bottom layer by dry etching to form the first bit line 30; removing the fourth conductive film in the second longitudinal groove T30 may disconnect the first bit lines 30 in different layers, and may disconnect the first bit lines 30 adjacent to each other in the same layer. Two adjacent first bit lines 30 in the same layer are respectively located in the third transverse groove T31 and the fourth transverse groove T32.

[0288] A fourth insulating film is deposited on the substrate 1 having the above structure to form a fourth insulating layer 15, and the fourth insulating layer 15 fills the second longitudinal trench T30. Fig.17A , Fig. 17B , Fig. 17C and Fig.17D As shown, Fig.17A This is a top view after forming the first bit line 30. Fig. 17B For along Fig.17A Cross-sectional view along the AA direction, Fig. 17C For along Fig.17A Cross-section along the BB direction, Fig.17D For along Fig.17A Cross-sectional view along CC direction.

[0289] The first bit lines 30 at the same position in different layers are separated by the first insulating layer 10 , and the adjacent first bit lines 30 in the same layer are separated by the fourth insulating layer 15 .

[0290] In some embodiments, the fourth insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ) and the like.

[0291] 115) forming a first gate insulating layer 24 and a first word line 40;

[0292] The forming of the first gate insulating layer 24 and the first word line 40 may include: depositing a first gate insulating film and a first gate electrode film in the second hole K2 in sequence to form the first gate insulating layer 24 and the first word line 40; the first word line 40 fills the second hole K2, such as Fig.18A , Fig.18B , Fig.18C and 18D As shown, Fig.18A FIG. 4 is a top view after forming the first gate insulating layer 24 and the first word line 40. Fig.18B For along Fig.18A Cross-sectional view along the AA direction, Fig.18C For along Fig.18A Cross-sectional view along the BB direction, Fig.18D For along Fig.18A The first gate electrode 26 of the first transistor at the same position in different layers is a part of the first word line 40. The first gate insulating layer 24 covers the bottom wall and side walls of the second hole K2.

[0293] In some embodiments, the first gate electrode film may be one or more of the following different types of materials:

[0294] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0295] Alternatively, it may be a conductive metal oxide, metal nitride, metal silicide, metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum doped zinc oxide (AZO) and other conductive metal oxide materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other conductive metal nitride materials;

[0296] Alternatively, it may be polysilicon, silicon, germanium, silicon germanium, etc. which are conductive after being doped.

[0297] 116) forming a first hole K1;

[0298] The forming of the first hole K1 may include: dry etching the stacked structure to form a first hole K1 penetrating the plurality of stacked structures in the first transistor region 100, wherein the first hole K1 includes a first sub-hole located in the first insulating layer 10 and a second sub-hole located in the conductive layer 11, and at this time, the first sub-hole and the second sub-hole have the same aperture; the first hole K1 is connected to the second hole K2;

[0299] The conductive layer 11 is laterally etched to enlarge the aperture of the second sub-hole of the first hole K1 located in the conductive layer 11, such as Fig.19A , Fig.19B , Fig.19C , Fig.19D and Fig.19E As shown, Fig.19A This is a top view after the first hole K1 is formed. Fig.19B For along Fig.19A Cross-sectional view along the AA direction, Fig.19C For along Fig.19A Cross-sectional view along the BB direction, Fig.19D For along Fig.19A Cross-sectional view in CC direction, Fig.19E For along Fig.19A The cross-sectional view along the DD direction. The DD direction is parallel to the AA direction. At this time, the first hole K1 forms a plurality of holes of two types with different sizes, and the aperture of the first sub-hole of the first hole K1 located in the first insulating layer 10 is smaller than the aperture of the second sub-hole located in the conductive layer 11, that is, the orthographic projection of the first sub-hole of the first hole K1 located in the first insulating layer 10 on the substrate 1 falls within the orthographic projection of the second sub-hole located in the conductive layer 11 on the substrate 1. In this step, the remaining conductive layer 11 is the first electrode 51 of the first transistor. The first electrode 51 is provided on the outer side wall of the third gate insulating layer 29 (the side wall facing away from the third hole K3) as the side wall of the first lateral groove K31.

[0300] 117) forming a first semiconductor layer 23, a second gate insulating layer 27 and a control electrode 45;

[0301] The forming of the first semiconductor layer 23, the second gate insulating layer 27 and the control electrode 45 may include: depositing a semiconductor film, a second gate insulating film and a second gate electrode film in the first hole K1 in sequence to form the first semiconductor layer 23, the second gate insulating layer 27 and the control electrode 45, wherein the control electrode 45 fills the first hole K1. Fig. 20A , Fig. 20B , Fig. 20C , Fig.20D , Fig.20E and Fig.20F As shown, Fig. 20A FIG. 4 is a top view after forming the first semiconductor layer 23, the second gate insulating layer 27 and the control electrode 45. Fig. 20B For along Fig. 20A Cross-sectional view along the AA direction, Fig. 20C For along Fig. 20A Cross-sectional view along the BB direction, Fig.20D For along Fig. 20A Cross-sectional view in CC direction, Fig.20E For along Fig. 20A Cross-sectional view along the DD direction, Fig.20F For along Fig. 20A The cross-sectional view along the EE direction is perpendicular to the AA direction.

[0302] In some embodiments, the second gate electrode film may be one or more of the following different types of materials:

[0303] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0304] Alternatively, it may be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0305] Alternatively, it may be polysilicon, silicon, germanium, silicon germanium, etc. which are conductive after being doped.

[0306] In another exemplary embodiment, a process for manufacturing a semiconductor device may include:

[0307] 201)~208), same as steps 101)~108); forming FIG. 11A to FIG. 11C In the structure shown, the third electrode 61 formed in this step also serves as the second word line;

[0308] 209)~215), same as steps 111)~117), forming FIG. 3A to FIG. 3F In this embodiment, steps 109) to 110) are not performed, and the fourth gate insulating layer 39 and the fourth gate electrode 22 are not generated.

[0309] The present disclosure also provides an electronic device, including the semiconductor device of the aforementioned embodiment, or a semiconductor device manufactured according to the semiconductor device manufacturing method of any of the aforementioned embodiments. The electronic device may be: a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0310] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A semiconductor device, characterized in that: The invention comprises a plurality of memory cells stacked in a direction perpendicular to the substrate, a first word line, wherein: Each layer of the storage unit comprises: a first transistor and a second transistor; the second transistor and the first transistor are sequentially distributed along a first direction parallel to the substrate; The first transistor includes a first semiconductor sublayer, a first electrode, and a second electrode; the first semiconductor sublayer is connected to the first electrode and the second electrode respectively; The second transistor comprises a third gate electrode, wherein the third gate electrode is connected to the first electrode; A second semiconductor sublayer is disposed between adjacent first semiconductor sublayers, and the first semiconductor sublayer and the second semiconductor sublayer are connected to form an integrated structure called a first semiconductor layer, and the first semiconductor layer extends in a direction perpendicular to the substrate; A first hole and a second hole penetrating different layers, the second hole being connected to the first hole, the first semiconductor layer and a control electrode extending in a direction perpendicular to the substrate and penetrating different layers are arranged in the first hole, wherein the first semiconductor layer surrounds a side wall of the control electrode; The first word line is arranged in the second hole and extends through the different layers along a direction perpendicular to the substrate, and the distance between the first word line and the first semiconductor sublayer along a direction parallel to the substrate is smaller than the distance between the first word line and the second semiconductor sublayer along a direction parallel to the substrate.

2. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: Insulating layers and conductive layers are alternately distributed from top to bottom in a direction perpendicular to the substrate; the first hole and the second hole penetrate the insulating layer and the conductive layer; The first semiconductor layer, the second gate insulating layer surrounding the side wall of the control electrode, and the control electrode are sequentially distributed in the first hole from outside to inside; A first gate insulating layer surrounding the side wall of the first word line and the first word line are sequentially distributed in the second hole from outside to inside.

3. The semiconductor device according to claim 2, characterized in that The aperture of a first sub-hole of the first hole located in the insulating layer is smaller than the aperture of a second sub-hole of the first hole located in the conductive layer.

4. The semiconductor device according to claim 2, characterized in that The aperture of the third sub-aperture of the second hole located in the insulating layer is smaller than the aperture of the fourth sub-aperture of the second hole located in the conductive layer.

5. The semiconductor device according to claim 2, wherein: The sidewall of the first semiconductor sublayer is connected to the sidewall of the first gate insulating layer, and the insulating layer is disposed between the sidewall of the second semiconductor sublayer and the sidewall of the first gate insulating layer.

6. The semiconductor device according to claim 2, wherein: The arrangement direction of the first holes and the second holes is perpendicular to the first direction.

7. The semiconductor device according to claim 2, characterized in that The first electrode and the second electrode are distributed on the outer side wall of the first semiconductor sublayer and are spaced apart along the first direction. The first word line is distributed in a region between the first electrode and the second electrode on the outer side wall of the first semiconductor sublayer.

8. The semiconductor device according to claim 7, characterized in that A first groove with an opening facing away from the first word line, the control electrode and the second electrode is provided between adjacent insulating layers, the bottom wall of the first groove exposes the first gate insulating layer and the first semiconductor sublayer, the first electrode is distributed on the bottom wall of the first groove and the side wall perpendicular to the substrate, the second semiconductor layer is distributed on the bottom wall of the first groove and the side wall perpendicular to the substrate, and is also distributed on the adjacent insulating layer constituting the side wall of the first groove.

9. The semiconductor device according to claim 8, characterized in that The semiconductor device also includes a second groove arranged on a side of the first groove away from the first semiconductor layer and extending along a second direction, the second groove being connected to multiple first grooves in the same column, the opening of the second groove away from the first electrode, the second semiconductor layers of the second transistors in the same column distributed along the second direction are connected to form an integrated structure, the integrated structure formed by the second semiconductor layer is also arranged on the side wall and bottom wall of the second groove, and the first direction and the second direction intersect.

10. The semiconductor device according to claim 7, wherein: The semiconductor device also includes: a memory cell array distributed in a direction perpendicular to the substrate, each layer of the memory cell array includes a plurality of rows and columns of memory cells respectively distributed in the first direction and the second direction, the plurality of layers of memory cells stacked in a direction perpendicular to the substrate are a plurality of memory cells in the same position in different layers, and the second electrodes of the first transistors in the same column distributed in the second direction are connected to form a first bit line extending along the second direction.

11. The semiconductor device according to claim 10, characterized in that The first transistors adjacent to each other along the first direction are connected to different first bit lines.

12. The semiconductor device according to claim 9, characterized in that The semiconductor device further includes a second bit line distributed on a bottom wall and a side wall of the second groove where the second semiconductor layer is disposed and extending along a second direction.

13. The semiconductor device according to claim 12, characterized in that The second transistors adjacent in the first direction are connected to different second bit lines.

14. The semiconductor device according to claim 8, characterized in that The second semiconductor layers of the second transistors of different layers are arranged alternately.

15. The semiconductor device according to claim 8, characterized in that The third gate electrode and the first electrode of the same memory cell are connected to form an integrated structure.

16. The semiconductor device according to claim 8, characterized in that The second transistor also includes a third electrode, and the third electrodes of the second transistors of the storage cells at the same position in multiple layers are connected to form an integrated structure extending in a direction perpendicular to the substrate, and the integrated structure formed by the connection of the third electrodes includes a vertical part extending in a direction perpendicular to the substrate and a horizontal part extending from the vertical part in a horizontal direction, and the horizontal part is connected to the second semiconductor layer distributed on the bottom wall of the first groove, and is connected to the second semiconductor layer distributed in an area adjacent to the bottom wall of the first groove.

17. The semiconductor device according to claim 16, characterized in that The second transistor also includes a fourth gate electrode arranged on a side of the third electrode away from the first transistor, and the fourth gate electrodes of the second transistors of the storage cells at the same position in multiple layers are connected to form an integrated structure extending in a direction perpendicular to the substrate, and the orthographic projection of the fourth gate electrode on the substrate is located within the orthographic projection of the first groove on the substrate.

18. The semiconductor device according to claim 17, wherein: The semiconductor device further comprises: A third hole penetrating each of the insulating layers and each of the conductive layers; the third hole comprises a fourth hole and a fifth hole penetrating each of the insulating layers and each of the conductive layers, and the arrangement direction of the fourth hole and the fifth hole is the same as the arrangement direction of the first transistor and the second transistor; The third hole is provided with a third gate insulating layer and a second semiconductor layer from outside to inside; A plurality of third electrodes connected into an integrated structure are distributed in the fourth hole; The fourth gate insulating layer and the fourth gate electrode are sequentially distributed in the fifth hole from outside to inside.

19. The semiconductor device according to claim 18, characterized in that The aperture of the fifth sub-hole of the third hole located in the insulating layer is smaller than the aperture of the sixth sub-hole of the third hole located in the conductive layer.

20. The semiconductor device according to claim 18, wherein: The fourth hole includes a seventh sub-hole located in the insulating layer and an eighth sub-hole located in the conductive layer, and a boundary of the seventh sub-hole close to the fifth hole in the orthographic projection of the substrate overlaps with a boundary of the eighth sub-hole close to the fifth hole in the orthographic projection of the substrate, and other boundaries of the orthographic projection of the seventh sub-hole on the substrate fall within the orthographic projection of the eighth sub-hole on the substrate.

21. The semiconductor device according to claim 18, wherein: The fifth hole includes a ninth sub-hole located in the insulating layer and a tenth sub-hole located in the conductive layer, and a boundary of the ninth sub-hole close to the fourth hole in the orthographic projection of the substrate overlaps with a boundary of the tenth sub-hole close to the fourth hole in the orthographic projection of the substrate, and other boundaries of the ninth sub-hole in the orthographic projection of the substrate fall within the orthographic projection of the tenth sub-hole on the substrate.

22. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, on which a first insulating film and a conductive layer film are alternately deposited in sequence to form a stacked structure including insulating layers and conductive layers alternately arranged; The stacked structure is patterned to form first trenches penetrating each layer and extending in a first direction, wherein adjacent first trenches include first transistor regions and second transistor regions distributed along the first direction; forming a second hole penetrating the stacked structure in a direction perpendicular to the substrate in the first transistor region, and laterally etching the conductive layer in each second hole so that the aperture of the second hole in the conductive layer is larger than the aperture of the second hole in the insulating layer; and sequentially forming a first gate insulating layer and a first word line of the first transistor on the sidewalls of the second hole; Forming a first hole penetrating the stacked structure in the first transistor region in a direction perpendicular to the substrate, and laterally etching the conductive layer in each of the first holes so that the aperture of the first hole in the conductive layer is larger than the aperture of the insulating layer, and each first gate insulating layer between any conductive layers in the second hole is exposed; A first semiconductor layer of a first transistor connected to each of the first gate insulating layers, a second gate insulating layer, and a control electrode of the first transistor corresponding to different layers are sequentially formed in the first hole, the first semiconductor layer comprises a plurality of first semiconductor sublayers arranged at intervals and a second semiconductor sublayer located between adjacent first semiconductor sublayers, the first semiconductor sublayer and the second semiconductor sublayer are connected to form an integrated structure, and a distance between the first word line and the first semiconductor sublayer along a direction parallel to the substrate is smaller than a distance between the first word line and the second semiconductor sublayer along a direction parallel to the substrate; A second transistor is formed in the second transistor region, and the first transistor and the second transistor are connected via a conductive layer serving as a sidewall of the first hole and a sidewall of the second hole.

23. The method for manufacturing a semiconductor device according to claim 22, wherein: Also includes: forming a third trench penetrating through each layer between first transistor regions adjacent to each other in the first direction, wherein the third trench extends along the second direction; The conductive layer is laterally etched in the third trench to an adjacent first transistor region to form a first transverse trench, a first bit line filling the first transverse trench is formed in the first transverse trench, and the first transverse trench is connected to the first hole and the second hole.

24. The method for manufacturing a semiconductor device according to claim 22, wherein: Forming a second transistor in the second transistor region includes: Forming a second trench extending along the second direction and penetrating through each layer between the adjacent second transistor regions along the first direction; etching the conductive layer laterally in the second trench to the adjacent second transistor region, forming a second transverse trench in each conductive layer; forming a third hole penetrating the stacked structure in a direction perpendicular to the substrate in the first transistor region, and laterally etching the conductive layer in each third hole to form a transverse groove, so that the aperture of the third hole in the conductive layer is larger than the aperture of the third hole in the insulating layer, and the third hole is connected to the second trench, and the bottom wall and the side wall of the transverse groove in a direction perpendicular to the substrate are the conductive layer; forming a third gate insulating layer and a second semiconductor layer of a second transistor in the third hole and the second trench, and the second semiconductor layer is formed only on the inner walls of the second transverse trench and the transverse groove; forming a second bit line filling the second transverse trench in the second transverse trench formed with the second semiconductor layer; A fourth hole is formed in the third hole and penetrates the stacked structure in a direction perpendicular to the substrate, and the conductive layer is laterally etched in each fourth hole to expose the second semiconductor layer arranged on the bottom wall of the lateral groove and the side wall close to the bottom wall of the groove, and to expose each third gate insulating layer between any conductive layers in the fourth hole; and a plurality of third electrodes of the second transistors are formed in the fourth hole.

25. The method for manufacturing a semiconductor device according to claim 24, characterized in that: Forming a second transistor in the second transistor region further includes: A fifth hole is formed in the third hole and penetrates the stacked structure in a direction perpendicular to the substrate. The conductive layer is laterally etched in each fifth hole to expose the second semiconductor layer that is arranged in the lateral groove and is not connected to the third electrode, and to expose each third gate insulating layer between any conductive layers in the fourth hole, and the third electrode; and a plurality of fourth gate insulating layers and fourth gate electrodes of the second transistors are formed in the fifth hole.

26. An electronic device, characterized in that: A semiconductor device comprising the semiconductor device according to any one of claims 1 to 21, or a semiconductor device manufactured according to the semiconductor device manufacturing method according to any one of claims 22 to 25.

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