Three-dimensional memory device

Abstract

A three-dimensional memory device is provided. The three-dimensional memory device comprises: a memory cell array implemented in a first chip; and a peripheral circuit implemented in the second chip and a third chip overlapping the first chip in the vertical direction. The peripheral circuit includes: a first peripheral circuit implemented in the second chip and the third chip; a second peripheral circuit implemented in the second chip and including at least one high voltage transistor; and a third peripheral circuit implemented in the third chip and including at least one low voltage transistor. The first peripheral circuit includes: a first sub-peripheral circuit implemented in the second chip and including at least one high-voltage transistor; and a second sub-peripheral circuit implemented in the third chip and including at least one low voltage transistor.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0148250 filed on October 31, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor device, and more particularly to a three-dimensional memory device. Background Art

[0003] Storage devices are used to store data and can be divided into volatile storage devices and non-volatile storage devices. As an example of a non-volatile storage device, a flash memory device can be used in mobile phones, digital cameras, mobile computing devices, stationary computing devices, and other devices. As information communication devices develop to have more and more functions, large-capacity and highly integrated memories are required. Therefore, a three-dimensional (3D) non-volatile storage device is proposed, which includes a plurality of word lines stacked on a substrate in a vertical direction.

[0004] As the number of layers of word lines stacked on a substrate in a 3D nonvolatile memory device increases, the cell area required to provide the same capacity decreases rapidly. However, compared with the reduction in cell area, the area required to implement peripheral circuits decreases at a slower rate. This becomes a limiting factor in reducing the chip size of memory devices. Summary of the invention

[0005] Embodiments of the present disclosure provide a memory device capable of reducing the area occupied by peripheral circuits.

[0006] Embodiments of the present disclosure provide a memory device capable of ensuring performance of circuit elements of a peripheral circuit implemented by a high-voltage transistor.

[0007] According to one aspect of an example embodiment, a memory device includes: a memory cell array implemented in a first chip; and a peripheral circuit implemented in a second chip and a third chip vertically overlapping the first chip. The peripheral circuit includes: a first peripheral circuit implemented in the second chip and the third chip; a second peripheral circuit implemented in the second chip and including at least one high-voltage transistor; and a third peripheral circuit implemented in the third chip and including at least one low-voltage transistor. The first peripheral circuit includes: a first sub-peripheral circuit implemented in the second chip and including at least one high-voltage transistor; and a second sub-peripheral circuit implemented in the third chip and including at least one low-voltage transistor.

[0008] According to one aspect of an example embodiment, a memory device includes: a first chip including a memory cell array; a second chip bonded to the first chip and including at least one high voltage transistor; and a third chip bonded to the second chip and including at least one low voltage transistor. The at least one high voltage transistor provided in the second chip overlaps with the at least one low voltage transistor provided in the third chip in a vertical direction.

[0009] According to one aspect of an example embodiment, a memory device includes: a first chip including a memory cell array; a second chip including a plurality of high-voltage transistors and overlapping the first chip in a vertical direction; and a third chip including a plurality of low-voltage transistors and overlapping the second chip in a vertical direction. The second chip includes: a plurality of transmission transistors connected to word lines of the memory cell array; and a plurality of high-voltage page buffers connected to bit lines of the memory cell array. The third chip includes: a voltage generator configured to generate a voltage provided to the plurality of transmission transistors; and a plurality of low-voltage page buffers corresponding to the plurality of high-voltage page buffers, respectively, and including a plurality of latches.

[0010] The peripheral circuit can be implemented by at least two chips different from each other, and the at least two chips different from each other can be bonded to each other in a vertical direction. Therefore, the area occupied by the peripheral circuit when viewed on a plane can be reduced.

[0011] The high voltage transistor may be implemented to have a sufficient width or length. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects and features of the present disclosure will be more clearly understood from the following description of example embodiments in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a block diagram illustrating a storage device according to an example embodiment;

[0014] Figure 2 It is shown Figure 1 A diagram of a memory block among a plurality of memory blocks included in a memory cell array and a peripheral circuit corresponding to the memory block;

[0015] Figure 3A and Figure 3B is a block diagram illustrating circuit elements of a peripheral circuit of a memory device arranged in different chips according to example embodiments;

[0016] Figure 4 is a block diagram illustrating a storage device according to an example embodiment;

[0017] Figure 5 is a block diagram illustrating a voltage generator according to an example embodiment;

[0018] Figure 6 is a circuit diagram illustrating a pass transistor group according to an example embodiment;

[0019] Figure 7 is a circuit diagram illustrating a page buffer according to an example embodiment;

[0020] Figure 8 is a block diagram illustrating a memory device provided in first to third chips according to example embodiments;

[0021] Fig. 9A , Fig. 9B and Fig. 9C is a diagram showing circuit elements of a memory device according to example embodiments, the circuit elements being arranged in different chips from each other;

[0022] Fig.10 is along the lines of an exemplary embodiment 9A to 9C A cross-sectional view taken along line AA';

[0023] Fig.11A is a diagram showing a high voltage transistor according to an example embodiment;

[0024] Fig. 11B is a diagram showing a low voltage transistor according to an example embodiment;

[0025] Fig.12 is along the lines of an exemplary embodiment 9A to 9C A cross-sectional view taken along line BB';

[0026] Fig.13 is along the lines of an exemplary embodiment 9A to 9C A cross-sectional view taken along line AA';

[0027] Fig.14A is a more detailed illustration of the Fig.13 A graph of region A;

[0028] Fig. 14B is shown in more detail Fig.13 A graph of region B;

[0029] Fig.15 is along the lines of an exemplary embodiment 9A to 9C A cross-sectional view taken along line AA';

[0030] Fig.16 and Fig.17 is a diagram showing a configuration in first to third chips according to example embodiments. Figure 4 A block diagram of a storage device; and

[0031] Fig.18 is along the lines of an exemplary embodiment 9A to 9CA cross-sectional view taken along line AA'. DETAILED DESCRIPTION

[0032] Example embodiments will be described below with reference to the accompanying drawings. The embodiments described herein are example embodiments, and therefore, the present disclosure is not limited thereto and may be implemented in various other forms. Each example embodiment provided in the following description does not exclude association with one or more features of another example or another embodiment that is also provided herein or is not provided herein but is consistent with the present disclosure. Statements such as "at least one of..." modify the entire list of elements when preceding a list of elements, rather than modifying individual elements in the list. For example, the statement "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0033] Figure 1 is a block diagram illustrating a memory device 1000A according to example embodiments.

[0034] The memory device 1000A may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure formed by manufacturing at least one chip including a memory cell, manufacturing at least one chip including a peripheral circuit, and connecting the chips to each other in a bonding process. Specifically, the peripheral circuit of the memory device 1000A may be implemented by at least two chips, and the at least two chips may be vertically connected to each other through a bonding process. Therefore, when viewed in the vertical direction, the area occupied by the peripheral circuit may be reduced.

[0035] In addition, among the multiple circuit elements constituting the peripheral circuit of the memory device 1000A, the high-voltage transistors can be arranged in the same chip. Since the number of high-voltage transistors is relatively small compared to the number of other circuit elements, the high-voltage transistors can be arranged with sufficient width or length, thereby ensuring the performance of the high-voltage transistors.

[0036] refer to Figure 1 , the memory device 1000A may include a memory cell array 1100 and a peripheral circuit 1200 .

[0037] The memory cell array 1100 may include a plurality of memory cells. As an example, the memory cell array 1100 may include a plurality of flash memory cells, however, example embodiments are not limited thereto. According to example embodiments, the memory cell may be a resistive memory cell such as a resistive RAM (ReRAM), a phase change RAM (PRAM), or a magnetic RAM (MRAM).

[0038] The memory cell array 1100 may include a plurality of memory blocks. Each memory block may have a two-dimensional structure or a three-dimensional structure. In a memory block having a two-dimensional structure (or a horizontal structure), the memory cell may be formed in a horizontal direction relative to the substrate. In a memory block having a three-dimensional structure (or a vertical structure), the memory cell may be formed in a vertical direction relative to the substrate. Each memory cell may store multi-bit data therein.

[0039] The memory cell array 1100 may be disposed on a first wafer. The first wafer on which the memory cell array 1100 is disposed may be referred to as a first chip "CHIP 1".

[0040] The peripheral circuit 1200 may be disposed adjacent to the memory cell array 1100. As an example, the peripheral circuit 1200 may be disposed in a vertical direction relative to the memory cell array 1100 to overlap the memory cell array 1100 in the vertical direction. The peripheral circuit 1200 may include a plurality of peripheral circuit units, peripheral unit 1, peripheral unit 2, and peripheral unit 3.

[0041] The first peripheral circuit unit 11_1 may be a circuit element including at least one high voltage transistor and at least one low voltage transistor. As an example, the first peripheral circuit unit 11_1 may include a first sub-peripheral circuit unit 11_1a and a second sub-peripheral circuit unit 11_1b, the first sub-peripheral circuit unit 11_1a may include at least one high voltage transistor, and the second sub-peripheral circuit unit 11_1b may include at least one low voltage transistor.

[0042] The second peripheral circuit unit 11_2 may be a circuit element including at least one high-voltage transistor.

[0043] The third peripheral circuit unit 11_3 may be a circuit element including at least one low voltage transistor.

[0044] According to an example embodiment, the peripheral circuit 1200 may be implemented by a second wafer and a third wafer. The second wafer provided with a portion of the circuit elements of the peripheral circuit 1200 may be referred to as a second chip "CHIP 2", and the third wafer provided with other circuit elements of the peripheral circuit 1200 may be referred to as a third chip "CHIP 3". The second chip "CHIP 2" and the third chip "CHIP 3" may be connected to each other in a vertical direction by a bonding process. As described above, since the peripheral circuit 1200 is manufactured to have a C2C structure, the area occupied by the peripheral circuit 1200 when viewed in the vertical direction may be reduced.

[0045] In addition, according to example embodiments, high-voltage transistors in the circuit elements of the peripheral circuit 1200 may be centrally disposed in the same chip. As an example, the first sub-peripheral circuit unit 11_1a configured to include a high-voltage transistor in the first peripheral circuit unit 11_1, and the second peripheral circuit unit 11_2 configured to include a high-voltage transistor may be disposed in the second chip "CHIP 2". The third peripheral circuit unit 11_3 configured to include a low-voltage transistor may be disposed in the third chip "CHIP 3".

[0046] Among the circuit elements constituting the peripheral circuit 1200, the number of high-voltage transistors may be smaller than the number of other circuit elements. Therefore, when the high-voltage transistors among the circuit elements constituting the peripheral circuit 1200 are centrally arranged in the second chip "CHIP2", the high-voltage transistors may have a sufficient width or length. Therefore, the performance degradation that occurs when implementing a small high-voltage transistor and the cost increase due to an additional process may be prevented.

[0047] As described above, the peripheral circuit 1200 can be implemented by at least two chips, and therefore, the area occupied by the peripheral circuit 1200 can be reduced. In addition, since the high-voltage transistors in the circuit elements of the peripheral circuit 1200 can be centrally arranged in the same chip, the high-voltage transistors can be implemented with sufficient width or length, and as a result, the performance of the high-voltage transistors can be improved.

[0048] Figure 2 It is shown Figure 1 A diagram of a memory block BLKa among multiple memory blocks included in a memory cell array 1100 and a peripheral circuit corresponding to the memory block BLKa.

[0049] refer to Figure 2 , the memory block BLKa may include a plurality of strings STR arranged in rows and columns. The strings STR may be commonly connected to a common source line CSL. Figure 2 A structure in which the common source line CSL is connected to the lower end of the string STR is shown. However, as long as the common source line CSL is electrically connected to the lower end of the string STR, the common source line CSL is not limited to being physically located at the lower end of the string STR. As an example, Figure 2 A structure in which the strings STR are arranged in four rows and four columns (4×4) is shown, however, the memory block BLKa may include fewer or more strings.

[0050] The strings of each row may be connected in common to the ground selection line GSL1 or GSL2. As an example, the strings of the first and second rows may be connected in common to the first ground selection line GSL1, and the strings of the third and fourth rows may be connected in common to the second ground selection line GSL2, however, this is only an example. According to example embodiments, four different ground selection lines may be provided, and the strings of each row may be implemented to be connected to different ground selection lines from each other.

[0051] The string of each row may be connected to a corresponding string selection line among first to fourth string selection lines SSL1 to SSL4 , and the string of each column may be connected to a corresponding bit line among first to fourth bit lines BL1 to BL4 .

[0052] Each string may include at least one ground selection transistor GST connected to a ground selection line GSL1 or GSL2 , a plurality of memory cells MC1 to MC8 respectively connected to a plurality of word lines WL1 to WL8 , and string selection transistors SST respectively connected to string selection lines SSL1 , SSL2 , SSL3 , and SSL4 .

[0053] In each string, the ground selection transistor GST, the memory cells MC1 to MC8, and the string selection transistor SST may be connected in series with each other in a direction perpendicular to the peripheral circuit 1200, and may be sequentially stacked in a direction perpendicular to the peripheral circuit 1200. In each string STR, at least one of the memory cells MC1 to MC8 may be used as a dummy memory cell. The dummy memory cell may not be programmed (e.g., programming is prohibited) or may be programmed differently from the remaining memory cells in the memory cells MC1 to MC8.

[0054] The memory cell array 1100 may be provided in a first chip "CHIP 1", the peripheral circuit 1200 may be provided in a second chip "CHIP 2" and a third chip "CHIP 3", and the first chip "CHIP 1" to the third chip "CHIP 3" may be connected to each other through a bonding process. As an example, the bonding process may refer to a process of electrically or physically connecting a bonding metal pattern formed on a top metal layer of one chip to a bonding metal pattern formed on a top metal layer of another chip. As an example, when the bonding metal pattern includes copper (Cu), the bonding process may be a Cu-Cu bonding process. According to example embodiments, the bonding metal pattern may include aluminum (Al) or tungsten (W).

[0055] The second chip "CHIP 2" may be disposed below the first chip "CHIP 1", and the third chip "CHIP 3" may be disposed below the second chip "CHIP 2". That is, in the vertical direction, the first chip "CHIP 1", the second chip "CHIP 2", and the third chip "CHIP 3" may overlap each other. Therefore, when viewed in the vertical direction, the area occupied by the peripheral circuit 1200 may be reduced.

[0056] Figure 3A and Figure 3B is a block diagram illustrating circuit elements of a peripheral circuit of a memory device arranged in different chips according to example embodiments. Figure 3A and Figure 3B The storage device may correspond to Figure 1 Therefore, in Figure 3A and Figure 3B In the drawings, the same or similar reference numerals denote Figure 1 The same or similar elements are described herein, and therefore, repeated description of the same or similar elements will be omitted.

[0057] refer to Figure 3A , circuit elements of the peripheral circuit 1200 may be disposed in the second chip “CHIP 2 ” and the third chip “CHIP 3 ”, and the second chip “CHIP 2 ” and the third chip “CHIP 3 ” may be connected to each other through a bonding process.

[0058] Among the circuit elements of the peripheral circuit 1200, the high-voltage transistor may be provided in the second chip "CHIP 2". As an example, the second peripheral circuit unit 11_2 including the high-voltage transistor may be provided in the second chip "CHIP 2". In addition, the first sub-peripheral circuit unit 11_1a including the high-voltage transistor of the first peripheral circuit unit 11_1 may be provided in the second chip "CHIP 2".

[0059] Among the circuit elements of the peripheral circuit 1200, the circuit elements other than the high voltage transistors may be provided in the third chip "CHIP 3". As an example, the third peripheral circuit unit 11_3 including the low voltage transistor may be provided in the third chip "CHIP 3". In addition, the second sub-peripheral circuit unit 11_1b including the low voltage transistor of the first peripheral circuit unit 11_1 may be provided in the third chip "CHIP 3".

[0060] According to example embodiments, circuit elements of the peripheral circuit 1200 that are respectively provided in the second chip ' CHIP 2 ' and the third chip ' CHIP 3 ' may be distinguished from each other based on their operations.

[0061] As an example, a transistor such as a pass transistor may be provided in the second chip "CHIP 2", wherein the transistor selects a row line (e.g., a word line WL, a string selection line SSL, a ground selection line GSL, etc.) or provides a high voltage to the row line. According to example embodiments, a transistor that selects a column line such as a bit line BL (e.g., a bit line selection transistor of a page buffer) or a transistor that provides a high voltage to the column line may be provided in the second chip "CHIP 2".

[0062] As an example, a circuit element that receives data from the outside and provides the received data to the page buffer, for example, an input / output circuit, may be provided in the third chip "CHIP 3". According to an example embodiment, a circuit element that temporarily stores data corresponding to each bit line BL, for example, a latch of the page buffer may be provided in the third chip "CHIP3".

[0063] These will be referenced later Figures 4 to 8 Describe in detail.

[0064] According to example embodiments, circuit elements of the peripheral circuit 1200 that are respectively provided in the second chip ' CHIP 2 ' and the third chip ' CHIP 3 ' may be distinguished from each other based on their structures.

[0065] As an example, a transistor having a relatively thick gate insulating layer may be disposed in a second chip "CHIP 2", and a transistor having a relatively thin gate insulating layer may be disposed in a third chip "CHIP 3". Fig.10 , Fig.11A and Fig. 11B This is described in detail.

[0066] According to example embodiments, circuit elements of the peripheral circuit 1200 respectively provided in the second chip ' CHIP 2 ' and the third chip ' CHIP 3 ' may be based on a structure of an element isolation region.

[0067] As an example, the circuit elements disposed in the second chip "CHIP 2" may be defined by a relatively deep element isolation region, and the circuit elements disposed in the third chip "CHIP 3" may be defined by a relatively shallow element isolation region. Fig.13 , Fig.14A and Fig. 14B This is described in detail.

[0068] Figure 1 and Figure 3AA structure is shown in which the high-voltage transistor among the circuit elements of the peripheral circuit 1200 is disposed in the second chip “CHIP 2” and the circuit elements other than the high-voltage transistor among the circuit elements of the peripheral circuit 1200 are disposed in the third chip “CHIP 3.” However, these are examples, and example embodiments are not limited thereto.

[0069] As an example, refer to Figure 3B , the third peripheral circuit unit 11_3 and the second sub-peripheral circuit unit 11_1b including the low voltage transistor in the circuit elements of the peripheral circuit 1200 can be set in the second chip "CHIP 2", and the second peripheral circuit unit 11_2 and the first sub-peripheral circuit unit 11_1a including the high voltage transistor in the circuit elements of the peripheral circuit 1200 can be set in the third chip "CHIP 3".

[0070] According to example embodiments, high voltage transistors and some low voltage transistors among circuit elements of the peripheral circuit 1200 may be disposed in a second chip “CHIP 2 ”, and other low voltage transistors among circuit elements of the peripheral circuit 1200 may be disposed in a third chip “CHIP 3 ”.

[0071] According to example embodiments, some high voltage transistors among circuit elements of the peripheral circuit 1200 may be disposed in a second chip “CHIP 2 ”, and low voltage transistors and other high voltage transistors among circuit elements of the peripheral circuit 1200 may be disposed in a third chip “CHIP 3 ”.

[0072] As described above, the peripheral circuit of the memory device can be implemented by connecting at least two chips to each other through a bonding process. Therefore, when viewed in the vertical direction, the area occupied by the peripheral circuit can be reduced. In addition, according to example embodiments, a relatively small number of high-voltage transistors can be concentrated in the same chip. Therefore, the high-voltage transistor can have a sufficient width or length, and the performance of the high-voltage transistor can be ensured.

[0073] Hereinafter, the configuration and structure of the memory device according to the example embodiment will be described in more detail. In addition, for ease of explanation, it is assumed that the high-voltage transistor in the circuit element of the peripheral circuit is set in the second chip "CHIP 2", and the circuit elements other than the high-voltage transistor in the circuit element of the peripheral circuit are set in the third chip "CHIP 3".

[0074] In addition, for ease of explanation, it is assumed that the page buffer includes both high-voltage transistors and low-voltage transistors. It is assumed that the transfer transistor includes a high-voltage transistor. In addition, it is assumed that a circuit element (e.g., a voltage generator) that generates a voltage required by the storage device, a circuit element (e.g., an input / output circuit) that receives data from the outside and provides the received data to the page buffer, and a circuit element (e.g., a control logic) that controls the overall operation of the storage device are implemented by a low-voltage transistor, however, this is only an example. According to an example embodiment, similar to the page buffer, the voltage generator, the input / output circuit, and the control logic can be implemented to include both high-voltage transistors and low-voltage transistors.

[0075] Figure 4 is a block diagram illustrating a memory device 1000B according to example embodiments.

[0076] refer to Figure 4 , the memory device 1000B may include a memory cell array 1100 and a peripheral circuit 1200 .

[0077] The memory cell array 1100 may be connected to the page buffer circuit 1220 through the bit lines BL, and may be connected to the address decoder 1210 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL. The memory cell array 1100 may include a plurality of memory cells.

[0078] The peripheral circuit 1200 may be disposed adjacent to the memory cell array 1100. As an example, the peripheral circuit 1200 may be disposed in a vertical direction relative to the memory cell array 1100 to overlap the memory cell array 1100 when viewed in the vertical direction. The peripheral circuit 1200 may include an address decoder 1210, a page buffer circuit 1220, an input / output circuit 1230, a voltage generator 1240, and a control logic 1250.

[0079] The address decoder 1210 may be connected to the memory cell array 1100 through a row line. The row line may include a selection line, for example, a string selection line SSL and a ground selection line GSL, and a word line WL. In response to the control of the control logic 1250, the address decoder 1210 may select one of a plurality of memory blocks, may select one of the word lines WL of the selected memory block, and may select one of the string selection lines SSL.

[0080] The address decoder 1210 may include a plurality of pass transistors PT. One end of each of the pass transistors PT may be connected to a corresponding row line among the row lines. Each of the pass transistors PT may receive a voltage from the voltage generator 1240 and may provide the received voltage to the corresponding row line.

[0081] The pass transistor PT may be implemented by a high voltage transistor and may be provided in the second chip “CHIP 2.” The pass transistor PT may be referred to as a pass transistor group PTG.

[0082] The page buffer circuit 1220 may be connected to the memory cell array 1100 through a column line. The column line may include, for example, a bit line BL. The page buffer circuit 1220 may temporarily store data to be programmed in a selected page or data read out from a selected page.

[0083] The page buffer circuit 1220 may include a plurality of page buffers PB. Each page buffer PB may include a high voltage page buffer PB_HV and a low voltage page buffer PB_LV. The high voltage page buffer PB_HV may select a bit line BL, and the low voltage page buffer PB_LV may temporarily store data.

[0084] In the page buffer PB, the high voltage page buffer PB_HV may include a high voltage transistor and may be provided in the second chip "CHIP 2". In the page buffer PB, the low voltage page buffer PB_LV may include a plurality of low voltage transistors and latches and may be provided in the third chip "CHIP 3". The plurality of high voltage page buffers PB_HV may be referred to as a high voltage page buffer group PBG_HV, and the plurality of low voltage page buffers PB_LV may be referred to as a low voltage page buffer group PBG_LV.

[0085] The input / output circuit 1230 may be connected to the page buffer circuit 1220 through the data line DL, and may be connected to an external source through the input / output line. The input / output circuit 1230 may receive data from an external source during a programming operation to program it into a selected memory cell of the memory cell array 1100, and may transmit data read from a selected memory cell to the outside during a read operation.

[0086] The input / output circuit 1230 may include a low voltage transistor and may be provided in a third chip “CHIP 3”.

[0087] The voltage generator 1240 may receive an internal voltage from the control logic 1250 and may generate a row line voltage required to read or write data. The row line voltage may be applied to the string selection line SSL, the word line WL, and / or the ground selection line GSL through the address decoder 1210 .

[0088] The voltage generator 1240 may include a charge pump and / or a low voltage transistor, and may be provided in the third chip “CHIP 3”.

[0089] The control logic 1250 may control the overall operation of the memory device 1000B. The control logic 1250 may include a low voltage transistor and may be provided in a third chip "CHIP 3".

[0090] As described above, the circuit elements of the peripheral circuit 1200 may be arranged in the second chip "CHIP 2" or the third chip "CHIP 3" according to the operations they support. Specifically, among the circuit elements of the peripheral circuit 1200, high-voltage transistors may be concentrated in the second chip "CHIP 2".

[0091] Figure 5 It is shown Figure 4 1240 is a block diagram of a voltage generator 1240.

[0092] refer to Figure 5 , the voltage generator 1240 may include a high voltage generator 1241 and a low voltage generator 1242 .

[0093] The high voltage generator 1241 may generate a program voltage VPGM, a program pass voltage VPPASS, a verification pass voltage VVPASS, a read pass voltage VRPASS, and an erase voltage VERS according to an operation mode of the memory device 1000B in response to the control of the control logic 1250. In addition, according to example embodiments, when the memory device 1000B supports a GIDL erase operation, the high voltage generator 1241 may also generate a GIDL voltage VGIDL. In addition, according to example embodiments, in response to the control of the control logic 1250, the high voltage generator 1241 may generate a bit line selection signal BLSLT according to an operation mode of the memory device 1000B.

[0094] A program voltage VPGM may be applied to a selected word line, and a program pass voltage VPPASS, a verification pass voltage VVPASS, and a read pass voltage VRPASS may be applied to unselected word lines. In addition, when the memory device 1000B supports a GIDL erase operation, a GIDL voltage VGIDL may be applied to the GIDL line. In addition, a bit line selection signal BLSLT may be applied to the gate of a bit line selection transistor corresponding to the selected bit line BL.

[0095] The low voltage generator 1242 may generate a program verification voltage VPV, a read voltage VRD, an erase verification voltage VEV, a first on-voltage VON1, and a second on-voltage VON2 in response to the control of the control logic 1250 according to an operation mode of the memory device 1000B.

[0096] According to the operation mode, a program verification voltage VPV, a read voltage VRD, and an erase verification voltage VEV may be applied to a selected word line. According to the operation mode, a first turn-on voltage VON1 and a second turn-on voltage VON2 may be applied to a string selection transistor and a ground selection transistor.

[0097] However, this is just an example, and the high voltage generator 1241 may also generate various high voltages according to example embodiments.

[0098] Figure 6 It is shown Figure 4 For ease of explanation, it is assumed that the storage device 1000B supports Figure 6 Therefore, it is assumed that the string STR1 includes a first GIDL transistor GDT1 and a second GIDL transistor GDT2, and the first GIDL transistor GDT1 and the second GIDL transistor GDT2 are disposed at a lower portion and an upper portion of the string STR1, respectively.

[0099] refer to Figure 6 The pass transistor group PTG may include a plurality of pass transistors PT1 to PT10. The pass transistor group PTG may be disposed between the voltage generator 1240 and the string STR1, and may provide the voltage generated by the voltage generator 1240 to the row lines SSL, GSL, GIDL1, GIDL2, DWL, and WL1 to WL5 of the string STR1.

[0100] As an example, one end of the first pass transistor PT1 may be connected to the voltage generator 1240, and the other end of the first pass transistor PT1 may be connected to the first GIDL line GIDL1. During the GIDL erase operation, the first pass transistor PT1 may be turned on in response to the voltage level of the block word line BLKWL, and may provide the GIDL voltage generated by the voltage generator 1240 to the first GIDL line GIDL1.

[0101] Similarly, one end of each of the second to tenth pass transistors PT2 to PT10 may be connected to the voltage generator 1240, and the other end of each of the second to tenth pass transistors PT2 to PT10 may be connected to the row line of the string STR1. Each of the second to tenth pass transistors PT2 to PT10 may provide a voltage generated by the voltage generator 1240 according to an operation mode to a corresponding row line in response to a voltage level of the block word line BLKWL.

[0102] According to the operation mode, each of the pass transistors PT1 to PT10 can receive one of the program voltage VPGM, the program pass voltage VPPASS, the verification pass voltage VVPASS, the read pass voltage VRPASS, and the GIDL voltage VGIDL generated by the high voltage generator 1241, and can provide the received voltage to the corresponding row line. Therefore, all the pass transistors PT1 to PT10 can be implemented by high voltage transistors and can be set in the second chip "CHIP 2".

[0103] However, this is only an example, and according to an example embodiment, some of the pass transistors PT1 to PT10 may be implemented by low-voltage transistors. In this case, the pass transistors implemented by high-voltage transistors may be provided in the second chip "CHIP2", and the pass transistors implemented by low-voltage transistors may be provided in the third chip "CHIP 3". According to an example embodiment, both the pass transistors implemented by high-voltage transistors and the pass transistors implemented by low-voltage transistors may be provided in the second chip "CHIP 2".

[0104] Figure 7 It is shown Figure 4 Circuit diagram of page buffer PB.

[0105] refer to Figure 7 , the page buffer PB may include a high voltage page buffer PB_HV and a low voltage page buffer PB_LV.

[0106] The high voltage page buffer PB_HV may include a bit line selection transistor TR_BL. The bit line selection transistor TR_BL may be turned on in response to a bit line selection signal BLSLT, and may connect the bit line BL to the low voltage page buffer PB_LV. In this case, the voltage level of the bit line selection signal BLSLT may be a high voltage, and therefore, the bit line selection transistor TR_BL may be implemented by a high voltage transistor. The high voltage page buffer PB_HV may be provided in a second chip "CHIP 2".

[0107] The low voltage page buffer PB_LV may include a plurality of transistors TR_LV1 to TR_LVk and a plurality of latches LATCH 1 to LATCH n. As an example, the low voltage page buffer PB_LV may store a read result for data stored in a memory cell during a read operation, or may store data to be programmed during a program operation. In this case, the transistors TR_LV1 to TR_LVk may be turned on in response to control signals C1 to Ck at a low voltage level, respectively, and thus, the transistors TR_LV1 to TR_LVk may be implemented by low voltage transistors. The low voltage page buffer PB_LV may be provided in a third chip "CHIP 3".

[0108] The high voltage page buffer PB_HV and the low voltage page buffer LV may be respectively arranged in the second chip "CHIP 2" and the third chip "CHIP 3", and the high voltage page buffer PB_HV and the low voltage page buffer PB_LV may at least partially overlap each other in the vertical direction. Therefore, a metal line connecting the high voltage page buffer PB_HV and the low voltage page buffer PB_LV is not required, or if present, it does not need to be very long. For example, the metal line may extend in the vertical direction between the second chip "CHIP 2" and the third chip "CHIP 3". Therefore, degradation of the page buffer performance due to parasitic resistance caused by the long metal line can be prevented.

[0109] Figure 8 The first chip to the third chip are provided Figure 4 A block diagram of a storage device 1000B is shown.

[0110] refer to Figure 8 , the first chip 'CHIP 1' to the third chip 'CHIP 3' may be connected to each other through a bonding process.

[0111] The memory cell array may be provided in a first chip 'CHIP 1'.

[0112] The high-voltage transistors among the circuit elements of the peripheral circuit 1200 may be disposed in the second chip “CHIP 2.” As an example, the pass transistor PT and the high-voltage page buffer PB_HV may be disposed in the second chip “CHIP 2.”

[0113] Circuit elements other than the high voltage transistor among the circuit elements of the peripheral circuit 1200 may be provided in a third chip “CHIP 3.” As an example, a low voltage page buffer PB_LV, a voltage generator 1240 , a control logic 1250 , and an input / output circuit 1230 may be provided in the third chip “CHIP 3”.

[0114] However, this is only an example, and according to example embodiments, some circuit elements disposed in the third chip “CHIP 3” may be disposed in the second chip “CHIP 2”.

[0115] As reference Figures 4 to 8 As described above, the circuit elements constituting the peripheral circuit of the memory device according to the example embodiment may be arranged in the second chip "CHIP 2" or the third chip "CHIP 3" according to the operations supported by them. Specifically, among the circuit elements constituting the peripheral circuit 1200, the high-voltage transistors may be centrally arranged in the same chip, such as the second chip "CHIP2". Therefore, the area occupied by the peripheral circuit may be reduced when viewed in the vertical direction, and the performance of the high-voltage transistor may be ensured.

[0116] 9A to 9C is a diagram showing circuit elements of a memory device arranged in different chips according to an example embodiment. Specifically, Fig. 9A A structure in which a memory cell array and a word line bonding area WLBA are provided in a first chip “CHIP 1” is shown. Fig. 9B A structure in which a pass transistor region PTA and a high-voltage page buffer region PBA_HV are provided in the second chip “CHIP 2” is shown. Fig. 9C FIG. 2 shows a structure in which a low voltage page buffer area PBA_LV is provided in a third chip “CHIP 3”. Example embodiments are not limited to 9A to 9C The chip may include the elements shown and discussed in the figure, and other circuit elements may also be included in the chip.

[0117] refer to Fig. 9A , the memory cell array and the word line bonding area WLBA may be provided in the first chip "CHIP 1". As an example, the first memory cell array "memory cell array 1" to the fourth memory cell array "memory cell array 4" may be arranged along the X-axis direction and the Y-axis direction, and the word line bonding area WLBA may be provided near the side surface of the corresponding memory cell array in the first memory cell array "memory cell array 1" to the fourth memory cell array "memory cell array 4". In the word line bonding area WLBA, the word line may extend along the X-axis direction and may be connected to a plurality of cell contact plugs.

[0118] refer to Fig. 9B , pass transistor group PTG (reference Figure 4 ) and the high voltage page buffer group PBG_HV (reference Figure 4 ) may be disposed in the second chip “CHIP2. A region in which the pass transistor group PTG is disposed may be referred to as a pass transistor region PTA, and a region in which the high-voltage page buffer group PBG_HV is disposed may be referred to as a high-voltage page buffer region PBA_HV.

[0119] In the vertical (Z-axis) direction, the transfer transistor area PTA may completely or partially overlap the word line bonding area WLBA. That is, the transfer transistor PT may be disposed in the second chip "CHIP 2" to be adjacent to the cell contact plug formed in the first chip "CHIP 1". Therefore, a metal line for electrically connecting the transfer transistor PT and the corresponding cell contact plug may not be required, or the metal line may be minimized. Therefore, degradation of the performance of the memory device due to parasitic resistance caused by the long metal line may be prevented.

[0120] In addition, in the vertical direction, the high voltage page buffer area PBA_HV may completely or partially overlap the memory cell array. That is, the high voltage page buffer PB_HV may be disposed in the second chip "CHIP 2" to be adjacent to the bit line BL formed in the first chip "CHIP 1". Therefore, a metal line for electrically connecting the bit line BL and the corresponding high voltage page buffer PB_HV may not be required, or the metal line may be minimized. Therefore, degradation of the memory device performance due to parasitic resistance caused by the long metal line may be prevented.

[0121] refer to Fig. 9C , low voltage page buffer group PBG_LV (reference Figure 4 ) may be provided in the third chip “CHIP 3.” A region where the low voltage page buffer group PBG_LV is provided may be referred to as a low voltage page buffer region PBA_LV.

[0122] In the vertical direction, the low voltage page buffer area PBA_LV may completely or partially overlap the high voltage page buffer area PBA_HV. That is, the low voltage page buffer PB_LV may be disposed in the third chip "CHIP 3" to be adjacent to the high voltage page buffer PB_HV disposed in the second chip "CHIP 2". Therefore, a metal line for electrically connecting the high voltage page buffer PB_HV and the corresponding low voltage page buffer PB_LV may not be required, or the metal line may be minimized. Therefore, degradation of the performance of the storage device due to parasitic resistance caused by the long metal line may be prevented.

[0123] Other circuit elements, such as the input / output circuit 1230, the voltage generator 1240, the control logic 1250, etc., may also be provided in the third chip "CHIP 3". In this case, each circuit element may be provided adjacent to a circuit element that performs a related operation. As an example, a circuit element that controls the operation of the page buffer PB may be provided adjacent to the low voltage page buffer area PBA_LV, and thus, resistance may be minimized.

[0124] Fig.10 is along 9A to 9C A cross-sectional view taken along the line A-A'.

[0125] refer to Fig.10, the storage device 1000C may have a C2C structure. In this regard, the first chip "CHIP 1", the second chip "CHIP 2", and the third chip "CHIP 3" may be connected to each other through a bonding process in a vertical direction after being manufactured separately. As an example, the bonding process may refer to a process of electrically or physically connecting a bonding metal pattern formed on a top metal layer of an upper chip to a bonding metal pattern formed on a top metal layer of a lower chip. As an example, when the bonding metal pattern includes copper (Cu), the bonding process may be a Cu-Cu bonding process. As another example, the bonding metal pattern may be formed of aluminum (Al) or tungsten (W).

[0126] The memory device 1000C may include first to third chips “CHIP 1” to “CHIP 3”, a memory cell array may be formed in the first chip “CHIP 1”, and a peripheral circuit may be formed in the second and third chips “CHIP 2” and “CHIP 3”. In addition, when viewed in the vertical direction, the memory device 1000C may include a bit line bonding area BLBA, a word line bonding area WLBA, and an external pad bonding area PA.

[0127] The third chip “CHIP 3 ” may include a substrate 110 and a plurality of circuit elements 120 a , 120 b , and 120 c formed in the substrate 110 .

[0128] The substrate 110 may have a plate-like shape extending along a plane defined by the X-axis direction and the Y-axis direction. The substrate 110 may be a semiconductor substrate. As an example, the substrate 110 may be, but is not limited to, a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin layer formed by a selective epitaxial growth method.

[0129] An interlayer insulating layer 115 including one or more insulating layers may be disposed on the circuit elements 120a, 120b, and 120c, and a plurality of metal lines may be disposed in the interlayer insulating layer 115 to connect the circuit elements 120a, 120b, and 120c. As an example, the metal lines may include first metal lines 130a, 130b, and 130c connected to the circuit elements 120a, 120b, and 120c, respectively, and a second metal line 140c disposed on the first metal line 130c. The metal lines may include at least one of various conductive materials. As an example, the first metal lines 130a, 130b, and 130c may be formed of tungsten having a relatively high resistivity, and the second metal line 140c may be formed of copper having a relatively low resistivity.

[0130] The interlayer insulating layer 115 may be disposed on the first substrate 110 and may include an insulating material such as silicon oxide, silicon nitride, or the like.

[0131] The second chip “CHIP 2 ” may include a substrate 210 and a plurality of circuit elements 220 a , 220 b , and 220 c formed in the substrate 210 .

[0132] Similar to the third chip "CHIP 3", the substrate 210 of the second chip "CHIP 2" may have a plate-like shape extending along a plane defined by the X-axis direction and the Y-axis direction. The substrate 210 may be a semiconductor substrate. In addition, similar to the third chip "CHIP3", an interlayer insulating layer 215 including one or more insulating layers may be provided on the circuit elements 220a, 220b, and 220c, and a plurality of metal wires may be provided in the interlayer insulating layer 215 to connect the circuit elements 220a, 220b, and 220c.

[0133] The third chip "CHIP 3" and the second chip "CHIP 2" may be connected to each other through a bonding process. As an example, upper bonding metals 152, 172a, 170b, and 170c may be formed at the top metal layer of the third chip "CHIP 3", and lower bonding metals 252_1, 272_1a, 270_1b, and 270_1c having shapes corresponding to the upper bonding metals 152, 172a, 170b, and 170c may be formed at the bottom metal layer of the second chip "CHIP 2". The upper bonding metals 152, 172a, 170b, and 170c of the third chip "CHIP 3" may be electrically connected to the lower bonding metals 252_1, 272_1a, 270_1b, and 270_1c of the second chip "CHIP 2" through a bonding process.

[0134] Some circuit elements of the third chip "CHIP 3" may be electrically connected to some circuit elements of the second chip "CHIP 2". As an example, the circuit element 120c of the third chip "CHIP 3" may be connected to the circuit element 220c of the second chip "CHIP 2" through the through electrode 292. The through electrode 292 may penetrate the substrate 210. The upper surface of the through electrode 292 may be in contact with the first metal wire 230c of the second chip "CHIP 2". The lower surface of the through electrode 292 may be in contact with the bonding metal 270_1c. The circuit element 220c of the second chip "CHIP 2" may be electrically connected to the circuit element 120c of the third chip "CHIP 3" through the through electrode 292 and the bonding metals 270_1c and 170c. In addition, according to example embodiments, all or part of the side surface of the through electrode 292 may be surrounded by the through electrode insulating layer 291.

[0135] The circuit element 220c of the second chip "CHIP 2" disposed in the bit line bonding area BLBA and the circuit element 120c of the third chip "CHIP3" disposed in the bit line bonding area BLBA may constitute a page buffer PB. As an example, the circuit element 220c of the second chip "CHIP 2" may be a high-voltage transistor disposed in the high-voltage page buffer area PBA_HV (refer to Fig. 9B The circuit element 120c of the third chip "CHIP 3" may be a low voltage transistor disposed in the low voltage page buffer region PBA_LV (refer to Fig. 9C ).

[0136] In this case, the circuit element 220c constituting the high voltage page buffer PB_HV of the second chip "CHIP 2" and the circuit element 120c constituting the low voltage page buffer PB_LV of the third chip "CHIP 3" can partially overlap each other in the vertical direction. Therefore, the length of the metal wire connecting the circuit element 220c and the circuit element 120c can be minimized, thereby reducing the parasitic resistance caused by the long metal wire.

[0137] The circuit elements 220a and 220b of the second chip "CHIP 2" respectively disposed in the external pad bonding area PA and the word line bonding area WLBA may include high voltage transistors such as pass transistors. The circuit elements 120a and 120b of the third chip "CHIP 3" respectively disposed in the external pad bonding area PA and the word line bonding area WLBA may include low voltage transistors constituting peripheral circuits such as input / output circuits, voltage generators, etc.

[0138] refer to Fig.10 , the first chip "CHIP 1" may include a substrate 310 and a common source line 320. A plurality of word lines 331 to 338 (330) may be stacked on the substrate 310 in a direction perpendicular to the upper surface of the substrate 310 (e.g., a Z-axis direction). A string selection line and a ground selection line may be disposed on and below the word line 330, and the word line 330 may be disposed between the string selection line and the ground selection line. The substrate 310 may be a semiconductor substrate.

[0139] A plurality of channel structures CH may be formed in the first chip "CHIP 1". The channel structure CH may be disposed in the bit line bonding area BLBA, may extend in a direction perpendicular to the upper surface of the substrate 310, and may penetrate the word line 330, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer.

[0140] In the word line bonding area WLBA, the word line 330 of the first chip "CHIP 1" may extend in the X-axis direction substantially parallel to the upper surface of the substrate 310, and may be connected to a plurality of cell contact plugs 341 to 347 (340). The first metal line 350b and the second metal line 360b may be sequentially connected to the upper portion of the cell contact plug 340 connected to the word line 330. The cell contact plug 340 may be connected to the circuit element 220b of the second chip "CHIP 2" through the upper bonding metal 370b of the first chip "CHIP 1" and the upper bonding metal 270b of the second chip "CHIP 2". In this case, the circuit element 220b of the second chip "CHIP 2" may be used as a transfer transistor PT.

[0141] The common source line contact plug 380 may be arranged in the external pad bonding area PA. The common source line contact plug 380 may be formed of a conductive material, such as a metal, a metal compound, or doped polysilicon. The first metal line 350a and the second metal line 360a may be sequentially stacked on the upper portion of the common source line contact plug 380. The common source line contact plug 380 may be electrically connected to the circuit elements of the second chip "CHIP 2".

[0142] The input / output pad 306 may be disposed in the external pad bonding area PA. As an example, the upper insulating layer 301 may be disposed on the substrate 310 to cover the upper surface of the substrate 310. The input / output pad 306 may be disposed on the upper insulating layer 301. The input / output pad 306 may be electrically connected to one of the circuit elements of the second chip "CHIP 2" and / or the third chip "CHIP 3" through the input / output contact plug 304.

[0143] The first chip "CHIP 1" and the second chip "CHIP 2" may be connected to each other through a bonding process. As an example, upper bonding metals 352, 372a, 370b, and 370c may be formed at the top metal layer of the first chip "CHIP 1", and upper bonding metals 252, 272a, 270b, and 270c having shapes corresponding to the shapes of the upper bonding metals 352, 372a, 370b, and 370c may be formed at the top metal layer of the second chip "CHIP 2". The upper bonding metals 352, 372a, 370b, and 370c of the first chip "CHIP 1" may be electrically connected to the upper bonding metals 252, 272a, 270b, and 270c of the second chip "CHIP 2" through a bonding process.

[0144] Fig.11A is a diagram showing a high voltage transistor according to an example embodiment, and Fig. 11B is a diagram showing a low voltage transistor according to an example embodiment. As an example, Fig.11AThe high voltage transistor can be Fig.10 The circuit element 220c is formed in the second chip "CHIP 2", and Fig. 11B The low voltage transistor can be Fig.10 The circuit element 120c is formed in the third chip "CHIP 3".

[0145] refer to Fig.11A , the circuit element 220c of the second chip "CHIP 2" may be a high voltage transistor. The circuit element 220c may include a substrate 210, a second impurity region IR2, a second gate pattern GP2, a second gate insulating layer Gox2, a metal contact 230a1, and a metal line 230a. The second impurity region IR2 may be defined in the substrate 210. As an example, the second impurity region IR2 may be defined in a well region of the substrate 210.

[0146] refer to Fig. 11B , the circuit element 120c of the third chip "CHIP 3" may be a low voltage transistor. The circuit element 120c may include a substrate 110, a first impurity region IR1, a first gate pattern GP1, a first gate insulating layer Gox1, a metal contact 130a1, and a metal line 130a. The first impurity region IR1 may be defined in the substrate 110. As an example, the first impurity region IR1 may be defined in a well region "well" of the substrate 110.

[0147] refer to Fig.11A and Fig. 11B , the size of the circuit element 220c as a high voltage transistor can be formed to be larger than the size of the circuit element 120c as a low voltage transistor.

[0148] The thickness TH2 of the second gate insulating layer Gox2 of the circuit element 220c as a high voltage transistor may be greater than the thickness TH1 of the first gate insulating layer Gox1 of the circuit element 120c as a low voltage transistor. According to example embodiments, the distance S3 between the gate pattern GP2 and the metal contact 230a1 of the circuit element 220c as a high voltage transistor may be greater than the distance S1 between the gate pattern GP1 and the metal contact 130a1 of the circuit element 120c as a low voltage transistor. According to example embodiments, the distance S4 between the metal contacts 230a1 of the circuit element 220c as a high voltage transistor may be greater than the distance S2 between the metal contacts 130a1 of the circuit element 120c as a low voltage transistor.

[0149] According to the memory device 1000C, since the number of high-voltage transistors set in the second chip "CHIP 2" is relatively small and the high-voltage transistors are separated from circuit elements of other peripheral circuits, the high-voltage transistors can have sufficient width or length, thereby improving the performance of the high-voltage transistors.

[0150] Fig.12 is along 9A to 9C A cross-sectional view taken along line BB'. Fig.12 The connection relationship between the word line and the pass transistor is shown. Fig.12 The structure shown is Fig.10 , Fig.11A and Fig. 11B The structures of are similar, and therefore, repeated descriptions of similar structures will be omitted.

[0151] refer to Fig.12 In the word line bonding area WLBA, the word line 331 and the cell contact plug 341 may be formed in the first chip "CHIP 1", and the circuit element 220b as the pass transistor may be formed in the second chip "CHIP 2". The circuit element 120b constituting the voltage generator 1240 may be formed in the third chip "CHIP 3".

[0152] In the first chip “CHIP 1 ”, a lower portion of the cell contact plug 341 may be connected to the word line 331 . Metal lines 350 b and 360 b and a bonding metal 370 b may be sequentially connected to an upper portion of the cell contact plug 341 .

[0153] In the second chip "CHIP 2", metal lines 230b and 240b and bonding metal 270b may be sequentially connected to the upper portion of circuit element 220b. Circuit element 220b may be connected to corresponding word line 331 through metal lines, bonding metal and cell contact plug 341. Circuit element 220b may be a pass transistor.

[0154] In addition, the circuit element 220b of the second chip "CHIP 2" may be electrically connected to the circuit element 120b of the third chip "CHIP 3" through the through electrode 292_1. The through electrode 292_1 may penetrate the substrate 210. The upper surface of the through electrode 292_1 may contact the first metal wire 230b of the second chip "CHIP 2", and the lower surface of the through electrode 292_1 may contact the bonding metal 270_1b. All or part of the side surface of the through electrode 292_1 may be surrounded by the through electrode insulating layer 291_1.

[0155] In the third chip "CHIP 3", metal lines 130b, 140b and bonding metal 170b may be sequentially connected to the upper portion of the circuit element 120b. The circuit element 120b may be electrically connected to the circuit element 220b of the second chip "CHIP 2" through the metal line and the bonding metal. As an example, the circuit element 120b of the third chip "CHIP 3" may constitute a voltage generator 1240 that generates a high voltage. In this case, the voltage generated by the voltage generator 1240 of the third chip "CHIP 3" may be applied to the word line of the first chip "CHIP 1" according to whether the circuit element 220b of the second chip "CHIP 2" is turned on.

[0156] In this case, the circuit element 220b of the second chip "CHIP 2" can be implemented by a high-voltage transistor, and the circuit element 120b of the third chip "CHIP 3" can be implemented by a low-voltage transistor. In addition, the circuit element 220b of the second chip "CHIP 2" and the circuit element 120b of the third chip "CHIP 3" can be arranged to overlap each other in the vertical direction. Therefore, the length of the metal wire connecting the circuit element 220b and the circuit element 120b can be minimized, and therefore, the parasitic resistance caused by the metal wire can be reduced.

[0157] Fig.13 According to an exemplary embodiment, 9A to 9C A cross-sectional view taken along line AA'. Fig.14A is shown in more detail Fig.13 A graph of area A, and Fig. 14B is shown in more detail Fig.13 Figure 2. Region B of the graph.

[0158] Fig.13 The storage device 1000D is similar to Fig.10 Therefore, in the storage device 1000C Fig.13 In the drawings, the same or similar reference numerals denote Fig.10 The same or similar elements are described herein, and thus, repeated description of the same elements will be omitted.

[0159] refer to Fig.13 , the element isolation region 211 may be formed in the second chip “CHIP 2”, and the element isolation region 111 may also be formed in the third chip “CHIP 3”. The element isolation region 211 of the second chip “CHIP 2” may be formed in the substrate 210, and an active region may be defined in the substrate 210. The element isolation region 111 of the third chip “CHIP 3” may be formed in the substrate 110, and an active region may be defined in the substrate 110.

[0160] In this case, the element isolation region 211 defined between the high voltage transistors of the second chip “ CHIP 2 ” may be formed deeper than the element isolation region 111 defined between the low voltage transistors of the third chip “ CHIP 3 ”.

[0161] As an example, the element isolation region 211 of the second chip “CHIP 2” may include a deep element isolation region 211_1 and a shallow element isolation region 211_2. Fig.14A As shown. The deep element isolation region 211_1 may be formed by filling the deep trench with a trench insulating material. The shallow element isolation region 211_2 may be formed by filling the shallow trench with a trench insulating material. The trench insulating material may include, for example, silicon oxide, such as tonn silazane (TOSZ) or undoped silicate glass (USG).

[0162] As an example, the element isolation region 111 of the third chip “CHIP 3” may be as follows: Fig. 14B That is, the element isolation region 111 of the third chip “CHIP 3” can be formed by filling the shallow trench with a trench insulating material.

[0163] As described above, the element isolation region 211 formed in the second chip “CHIP 2 ” provided with the high voltage transistor may be formed deeper than the element isolation region 111 formed in the third chip “CHIP 3 ” provided with the low voltage transistor.

[0164] Fig.15 According to an exemplary embodiment, 9A to 9C A cross-sectional view taken along line AA'.

[0165] Fig.15 The storage device 1000E is similar to Fig.10 and Fig.13 Therefore, in Fig.15 In the drawings, the same or similar reference numerals denote Fig.10 and Fig.13 The same or similar elements are described herein, and thus, repeated description of the same elements will be omitted.

[0166] As mentioned above Fig.10 and Fig.13 As discussed, the input / output pads may be formed in the first chip 'CHIP 1', however, this is merely an example and the input / output pads may be formed in various locations according to example embodiments.

[0167] As an example, the lower insulating layer 101 may cover the lower surface of the substrate 110 of the third chip “CHIP 3”, and the input / output pads 105 may be formed on the lower insulating layer 101, as shown in FIG. Fig.15 As shown. The input / output pad 105 may be connected to at least one of a plurality of circuit elements 120a, 120b, and 120c provided in the third chip "CHIP 3" through the input / output contact plug 103, and may be spaced apart from the substrate 110 by the lower insulating layer 101. In addition, a side surface insulating layer may be provided between the input / output contact plug 103 and the substrate 110. For example, the side surface insulating layer may surround the input / output contact plug 103 between the input / output contact plug 103 and the substrate 110. Therefore, the input / output contact plug 103 may be electrically separated from the substrate 110.

[0168] Fig.16 and Fig.17 FIG. 2 is a diagram showing a first chip “CHIP 1 ” to a third chip “CHIP 3 ” arranged in accordance with example embodiments. Figure 4 A block diagram of a storage device. Fig.16 and Fig.17 Storage device and Figure 8 Therefore, in Fig.16 and Fig.17 In the drawings, the same or similar reference numerals denote Figure 8 The same or similar elements are described herein, and thus, repeated description of the same elements will be omitted.

[0169] As mentioned above Figures 4 to 15 As described above, in some example embodiments, only high voltage transistors are provided in the second chip “CHIP 2.” However, this is merely an example, and example embodiments are not limited thereto.

[0170] As an example, refer to Fig.16 , in addition to the pass transistor PT and the high-voltage page buffer PB_HV as high-voltage transistors, a low-voltage transistor may also be provided in the second chip "CHIP 2". A circuit element provided in the second chip "CHIP 2" and including a low-voltage transistor may be referred to as a fourth peripheral circuit unit. As an example, the voltage generator 1240 may be implemented to include a low-voltage transistor, and the voltage generator 1240 may be provided in the second chip "CHIP 2". In this case, the voltage generator 1240 may be provided in an area other than an area in which the pass transistor PT and the high-voltage page buffer PB_HV are provided. Therefore, the space within the second chip "CHIP 2" may be effectively utilized.

[0171] In addition, as mentioned above Figures 4 to 15As discussed, a first chip 'CHIP 1 ' provided with a memory cell array may be connected to a second chip 'CHIP 2 ' provided with a high voltage transistor through a bonding process, however, this is merely an example and example embodiments are not limited thereto.

[0172] As an example, refer to Fig.17 , the first chip “CHIP 1” can be connected to the third chip “CHIP 3” mainly provided with low voltage transistors through a bonding process, and the third chip “CHIP 3” can be connected to the second chip “CHIP 2” provided with high voltage transistors through a bonding process.

[0173] Fig.18 is along the lines of an exemplary embodiment 9A to 9C For ease of explanation, Fig.18 , various structures that are changeable and applicable to a storage device according to example embodiments are fully illustrated.

[0174] For the sake of explanation, assume that Fig.18 In the memory device 1000F, two chips "CHIP 1a" and "CHIP 1b" formed with a memory cell array are connected to two chips "CHIP 2" and "CHIP 3" formed with a peripheral circuit through a bonding process. In addition, in the following description, the first a chip "CHIP 1a" and the first b chip "CHIP 1b" may be referred to as a first cell region "CELL 1" and a second cell region "CELL 2", respectively, and the second chip "CHIP 2" and the third chip "CHIP 3" may be referred to as a first peripheral circuit region "PERI 1" and a second peripheral circuit region "PERI 2", respectively.

[0175] The two chips “CHIP 1 a ” and “CHIP 1 b ” where the memory cell array is formed may be referred to as a cell region, and the two chips “CHIP 2 ” and “CHIP 3 ” where the peripheral circuit is formed may be referred to as a peripheral circuit region.

[0176] refer to Fig.18, the memory device 1000F may have a chip-to-chip (C2C) structure. The C2C structure may be obtained by manufacturing at least one upper chip including a cell area "CELL" and at least one lower chip including a peripheral circuit area "PERI" and connecting the upper chip and the lower chip via a bonding process. As an example, the bonding process may refer to a process of electrically or physically connecting a bonding metal pattern formed on a top metal layer of the upper chip to a bonding metal pattern formed on a top metal layer of the lower chip. As an example, when the bonding metal pattern is formed of copper (Cu), the bonding process may be a Cu-Cu bonding process. According to example embodiments, the bonding metal pattern may be formed of aluminum (Al) or tungsten (W).

[0177] The memory device 1000F may include at least one upper chip, the at least one upper chip including a cell region. In addition, the memory device 1000F may include at least one lower chip, the at least one lower chip including a peripheral circuit region. As an example, the memory device 1000F may include two upper chips and two lower chips, such as Fig.18 However, this is just an example, and the number of upper chips and the number of lower chips should not be limited to or thereby.

[0178] When the memory device 1000F includes two upper chips and two lower chips, the memory device 1000F may be manufactured by manufacturing a first a chip "CHIP 1a" and a first b chip "CHIP 1b" including a cell region and a second chip "CHIP 2" and a third chip "CHIP 3" including a peripheral circuit region, and connecting the first chip to the third chip via a bonding process. The first a chip "CHIP 1a" may be connected to the first b chip "CHIP 1b" by a bonding process after flipping, and the first b chip "CHIP 1b" may be connected to the second chip "CHIP 2" by a bonding process after flipping.

[0179] In the following description, the upper and lower parts of the first a chip and the first b chip are defined based on the orientation of the first a chip and the first b chip before flipping. Fig.18 In the embodiment, the upper portions of the second chip "CHIP 2" and the third chip "CHIP3" are defined relative to the +Z axis direction, and the upper portions of the first a chip "CHIP 1a" and the first b chip "CHIP 1b" are defined relative to the -Z axis direction, however, this is only an example. According to example embodiments, only one of the first a chip and the first b chip may be inverted and may be connected by a bonding process.

[0180] In the memory device 1000F, each of the first and second peripheral circuit regions PERI 1 and PERI 2 and each of the first and second cell regions CELL 1 and CELL 2 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0181] The peripheral circuit may include a first peripheral circuit region “PERI 1” and a second peripheral circuit region “PERI 2” vertically stacked in the Z-axis direction. However, this is only an example, and the number of vertically stacked peripheral circuit regions should not be limited thereto.

[0182] The first peripheral circuit region “PERI 1 ” may include a first substrate 110 and a plurality of circuit elements 120 a , 120 b , and 120 c formed in the first substrate 110 .

[0183] The first substrate 110 may have a plate-like shape extending along a plane defined by a first horizontal direction and a second horizontal direction (X-axis direction and Y-axis direction). The first substrate 110 may be a semiconductor substrate. As an example, the substrate 110 may be, but is not limited to, a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin layer formed by a selective epitaxial growth method.

[0184] An interlayer insulating layer 115 including one or more insulating layers may be disposed on the circuit elements 120a, 120b, and 120c, and a plurality of metal lines may be disposed in the interlayer insulating layer 115 to connect the circuit elements 120a, 120b, and 120c. As an example, the metal lines may include first metal lines 130a, 130b, and 130c connected to the circuit elements 120a, 120b, and 120c, respectively, and second metal lines 140a, 140b, and 140c disposed on the first metal lines 130a, 130b, and 130c, respectively. The metal lines may include at least one of various conductive materials. As an example, the first metal lines 130a, 130b, and 130c may be formed of tungsten having a relatively high resistivity, and the second metal lines 140a, 140b, and 140c may be formed of copper having a relatively low resistivity.

[0185] Although only the first metal lines 130a, 130b, and 130c and the second metal lines 140a, 140b, and 140c are shown and described, example embodiments are not limited thereto or thereby. According to example embodiments, one or more additional metal lines may be further formed on the second metal lines 140a, 140b, and 140c. In this case, the second metal lines 140a, 140b, and 140c may be formed of aluminum. At least a portion of the one or more additional metal lines formed on the second metal lines 140a, 140b, and 140c may be formed of copper, wherein copper has a lower resistivity than the aluminum used in the second metal lines 140a, 140b, and 140c.

[0186] The interlayer insulating layer 115 may be disposed on the first substrate 110 and may include an insulating material such as silicon oxide, silicon nitride, or the like.

[0187] The second peripheral circuit region “PERI 2 ” may include a second substrate 210 and a plurality of circuit elements 220 a , 220 b , and 220 c formed on the second substrate 210 .

[0188] The second substrate 210 may have a plate shape extending along a plane defined by a first horizontal direction and a second horizontal direction (X-axis direction and Y-axis direction). The second substrate 210 may be a semiconductor substrate.

[0189] An interlayer insulating layer 215 including one or more insulating layers may be disposed on the circuit elements 220a, 220b, and 220c, and a plurality of metal lines may be disposed in the interlayer insulating layer 215 to connect the circuit elements 220a, 220b, and 220c. In addition, a portion of the circuit elements 220a, 220b, and 220c on the second substrate 210 may be electrically connected to a portion of the circuit elements 120a, 120b, and 120c on the first substrate 110.

[0190] Each of the first cell region "CELL 1" and the second cell region "CELL 2" may include at least one memory block. The first cell region "CELL 1" may include a third substrate 310 and a common source line 320. A plurality of word lines 331 to 338 (330) may be stacked on the third substrate 310 in a direction perpendicular to an upper surface of the third substrate 310 (e.g., a Z-axis direction). A string selection line and a ground selection line may be disposed on and below the word line 330, respectively, and the word line 330 may be disposed between the string selection line and the ground selection line.

[0191] Similarly, the second cell region "CELL 2" may include a fourth substrate 410 and a common source line 420, and a plurality of word lines 431 to 438 (430) may be stacked on the fourth substrate 410 in a direction perpendicular to the upper surface of the fourth substrate 410 (e.g., the Z-axis direction). The third substrate 310 and the fourth substrate 410 may include various materials and may be a silicon substrate, a silicon germanium substrate, a germanium substrate, or a substrate including a single crystal epitaxial layer grown on a single crystal silicon substrate. A plurality of channel structures CH may be formed in each of the first cell region "CELL 1" and the second cell region "CELL 2".

[0192] According to an example embodiment, as shown in region A1, the channel structure CH may be disposed in the bit line bonding region BLBA, and may extend in a direction perpendicular to the upper surface of the third substrate 310 to penetrate the word line 330, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer. The channel layer may be electrically connected to the first metal line 350c and the second metal line 360c in the bit line bonding region BLBA. As an example, the second metal line 360c may be a bit line and may be connected to the channel structure CH through the first metal line 350c. The bit line 360c may extend in a first horizontal direction (Y-axis direction) substantially parallel to the upper surface of the third substrate 310.

[0193] According to an example embodiment, as shown in area A2, the channel structure CH may include a lower channel LCH and an upper channel UCH connected to the lower channel LCH. As an example, the channel structure CH may be formed by a process for the lower channel LCH and a separate process for the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the upper surface of the third substrate 310, and may penetrate the common source line 320 and the lower word lines 331 and 332. The lower channel LCH may include a data storage layer, a channel layer, and a buried insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 333 to 338. The upper channel UCH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 350c and the second metal line 360c. As the channel length increases, it becomes more difficult to form a channel with a uniform width due to process-related reasons. The memory device 1000F may have a uniform channel through a lower channel LCH and an upper channel UCH formed through sequential processes.

[0194] As shown in area A2, when the channel structure CH includes a lower channel LCH and an upper channel UCH, a word line located near the boundary between the lower channel LCH and the upper channel UCH may be a dummy word line. As an example, word lines 432 and 433 forming the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. In this case, data may not be stored in a memory cell connected to the dummy word line. The number of pages corresponding to the memory cell connected to the dummy word line may be less than the number of pages corresponding to the memory cell connected to the normal word line. The voltage level applied to the dummy word line may be different from the voltage level applied to the normal word line, and therefore, the influence of the uneven channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device may be reduced.

[0195] In region A2, the number of lower word lines 331 and 332 penetrated by the lower channel LCH is less than the number of upper word lines 333 to 338 penetrated by the upper channel UCH. However, this is merely an example, and example embodiments are not limited thereto. According to example embodiments, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated by the upper channel UCH. In addition, the structure and connection relationship of the channel structure CH set in the first cell region "CELL 1" described above may be applicable to the channel structure CH set in the second cell region "CELL2".

[0196] In the bit line bonding area BLBA, a first through electrode THV1 may be disposed in the first cell area “CELL 1”, and a second through electrode THV2 may be disposed in the second cell area “CELL 2”. Fig.18 As shown, the first through electrode THV1 may penetrate the common source line 320 and the word line 330, however, this is only an example, and the first through electrode THV1 may also penetrate the third substrate 310. The first through electrode THV1 may include a conductive material. According to example embodiments, the first through electrode THV1 may include a conductive material surrounded by an insulating material. The second through electrode THV2 may have substantially the same shape and structure as the first through electrode THV1.

[0197] The first through-electrode THV1 and the second through-electrode THV2 may be electrically connected to each other through the first through-metal pattern 372d and the second through-metal pattern 472d. The first through-metal pattern 372d may be formed at the lower end of the first b-chip "CHIP 1b" including the first cell region "CELL 1", and the second through-metal pattern 472d may be formed at the upper end of the first a-chip "CHIP 1a" including the second cell region "CELL 2". The first through-electrode THV1 may be electrically connected to the first metal wire 350c and the second metal wire 360c. The lower through-hole 371d may be formed between the first through-electrode THV1 and the first through-metal pattern 372d, and the upper through-hole 471d may be formed between the second through-electrode THV2 and the second through-metal pattern 472d. The first through-metal pattern 372d may be connected to the second through-metal pattern 472d by a bonding process.

[0198] In addition, in the bit line bonding area BLBA, an upper metal pattern 252 may be formed at the top metal layer of the second peripheral circuit area "PERI 2", and an upper metal pattern 392 having the same shape as the upper metal pattern 252 may be formed at the top metal layer of the first cell area "CELL 1". The upper metal pattern 392 of the first cell area "CELL 1" may be electrically connected to the upper metal pattern 252 of the second peripheral circuit area "PERI 2" through a bonding process.

[0199] Similarly, in the bit line bonding area BLBA, an upper metal pattern may be formed at the top metal layer of the second peripheral circuit area "PERI 2", and an upper metal pattern having the same shape as the upper metal pattern may be formed at the top metal layer of the first peripheral circuit area "PERI 1". The upper metal pattern of the second peripheral circuit area "PERI 2" may be electrically connected to the upper metal pattern of the first peripheral circuit area "PERI 1" through a bonding process.

[0200] In the bit line bonding area BLBA, the bit line 360c may be electrically connected to the page buffer included in the first peripheral circuit area "PERI 1" and / or the second peripheral circuit area "PERI 2". As an example, some circuit elements 220c of the second peripheral circuit area "PERI 2" may provide a high voltage page buffer PB_HV, and some circuit elements 120c of the first peripheral circuit area "PERI 1" may provide a low voltage page buffer PB_LV. The bit line 360c may be electrically connected to the circuit elements 220c and 120c providing the page buffer through the upper bonding metal 370c of the first cell area "CELL 1" and the upper bonding metal 270c of the second peripheral circuit area "PERI 2".

[0201] refer to Fig.18, in the word line bonding area WLBA, the word line 330 of the first cell region “CELL 1” may extend in a second horizontal direction (X-axis direction) substantially parallel to the upper surface of the third substrate 310, and may be connected to a plurality of cell contact plugs 341 to 347 (340). The first metal line 350b and the second metal line 360b may be sequentially connected to the upper portion of the cell contact plug 340 connected to the word line 330. In the word line bonding area WLBA, the cell contact plug 340 may be connected to the second peripheral circuit region “PERI 2” through the upper bonding metal 370b of the first cell region “CELL 1” and the upper bonding metal 270b of the second peripheral circuit region “PERI 2”.

[0202] The cell contact plug 340 may be electrically connected to a row decoder included in the first peripheral circuit region "PERI 1" and / or the second peripheral circuit region "PERI 2". As an example, some circuit elements 220b of the second peripheral circuit region "PERI 2" may provide a transfer transistor PT, and the cell contact plug 340 may be electrically connected to the circuit element 220b providing the transfer transistor PT through the upper bonding metal 370b of the first cell region "CELL 1" and the upper bonding metal 270b of the second peripheral circuit region "PERI 2".

[0203] Similarly, in the word line bonding area WLBA, the word line 430 of the second cell region “CELL 2” may extend in a second horizontal direction (X-axis direction) substantially parallel to the upper surface of the fourth substrate 410, and may be connected to a plurality of cell contact plugs 441 to 447 (440). The cell contact plug 440 may be connected to the second peripheral circuit region “PERI 2” through the upper metal pattern of the second cell region “CELL 2”, the lower metal pattern and the upper metal pattern of the first cell region “CELL 1”, and the cell contact plug 348.

[0204] In the word line bonding area WLBA, the upper bonding metal 370b may be formed in the first cell area "CELL 1", and the upper bonding metal 270b may be formed in the second peripheral circuit area "PERI 2". The upper bonding metal 370b of the first cell area "CELL 1" may be electrically connected to the upper bonding metal 270b of the second peripheral circuit area "PERI 2" through a bonding process. The upper bonding metal 370b and the upper bonding metal 270b may include aluminum, copper, or tungsten.

[0205] In the external pad bonding area PA, a lower metal pattern 371e may be formed at a lower portion of the first cell area "CELL 1", and an upper metal pattern 472a may be formed at an upper portion of the second cell area "CELL 2". In the external pad bonding area PA, the lower metal pattern 371e of the first cell area "CELL 1" and the upper metal pattern 472a of the second cell area "CELL 2" may be connected to each other through a bonding process. Similarly, an upper metal pattern 372a may be formed at an upper portion of the first cell area "CELL 1", and an upper metal pattern 272a may be formed at an upper portion of the second peripheral circuit area "PERI 2". The upper metal pattern 372a of the first cell area "CELL 1" and the upper metal pattern 272a of the second peripheral circuit area "PERI 2" may be connected to each other through a bonding process.

[0206] Common source line contact plugs 380 and 480 may be disposed in the external pad bonding area PA. Common source line contact plugs 380 and 480 may be formed of a conductive material, such as a metal, a metal compound, or doped polysilicon. The common source line contact plug 380 of the first cell area "CELL 1" may be electrically connected to the common source line 320, and the common source line contact plug 480 of the second cell area "CELL 2" may be electrically connected to the common source line 420. The first metal line 350a and the second metal line 360a may be sequentially stacked on the common source line contact plug 380 of the first cell area "CELL 1", and the first metal line 450a and the second metal line 460a may be sequentially stacked on the common source line contact plug 480 of the second cell area "CELL 2".

[0207] The input / output pads 105, 405, and 406 may be disposed in the external pad landing area PA. Fig.18 , the lower insulating layer 101 may cover the lower surface of the first substrate 110, and the first input / output pad 105 may be formed on the lower insulating layer 101. The first input / output pad 105 may be connected to at least one of the circuit elements 120a disposed in the first peripheral circuit region "PERI 1" through the first input / output contact plug 103, and may be spaced apart from the first substrate 110 by the lower insulating layer 101. In addition, a side surface insulating layer may be disposed between the first input / output contact plug 103 and the first substrate 110. For example, the side surface insulating layer may surround the input / output contact plug 103 between the input / output contact plug 103 and the substrate 110. Therefore, the first input / output contact plug 103 and the first substrate 110 may be electrically separated from each other.

[0208] An upper insulating layer 401 may be formed on the fourth substrate 410 to cover the upper surface of the fourth substrate 410. Second input / output pads 405 and / or third input / output pads 406 may be disposed on the upper insulating layer 401. The second input / output pads 405 may be connected to at least one of the circuit elements 220a disposed in the second peripheral circuit region "PERI 2" through second input / output contact plugs 403 and 303, and the third input / output pads 406 may be connected to at least one of the circuit elements 220a disposed in the second peripheral circuit region "PERI 2" through third input / output contact plugs 404 and 304.

[0209] According to example embodiments, the fourth substrate 410 may not be disposed in a region where the input / output contact plug is disposed. As shown in region B, the third input / output contact plug 404 may be separated from the fourth substrate 410 in a direction substantially parallel to the upper surface of the fourth substrate 410, and may be connected to the third input / output pad 406 after penetrating the interlayer insulating layer 415 of the second cell region "CELL 2". In this case, the third input / output contact plug 404 may be formed by various processes.

[0210] According to example embodiments, as shown in region B1, the third input / output contact plug 404 may extend in the vertical direction (Z-axis direction), and may have a diameter that increases as the distance from the upper insulating layer 401 decreases. That is, unlike the diameter of the channel structure CH of region A1 that decreases as the distance from the upper insulating layer 401 decreases, the diameter of the third input / output contact plug 404 may increase as the distance from the upper insulating layer 401 decreases. As an example, the third input / output contact plug 404 may be formed after the second cell region "CELL 2" is bonded to the first cell region "CELL 1" through a bonding process.

[0211] According to example embodiments, as shown in region B2, the third input / output contact plug 404 may extend in the vertical direction (Z-axis direction), and may have a diameter that decreases as the distance from the upper insulating layer 401 decreases. That is, similar to the channel structure CH, the diameter of the third input / output contact plug 404 may decrease as the distance from the upper insulating layer 401 decreases. As an example, the third input / output contact plug 404 may be formed together with the cell contact plug 440 before the second cell region "CELL 2" is bonded to the first cell region "CELL 1".

[0212] According to example embodiments, the input / output contact plug may be disposed to overlap with the fourth substrate 410. For example, as shown in region C, the second input / output contact plug 403 may be formed to penetrate the interlayer insulating layer 415 of the second cell region "CELL 2" in the vertical direction (Z-axis direction), and may be electrically connected to the second input / output pad 405 through the fourth substrate 410. In this case, the second input / output contact plug 403 and the second input / output pad 405 may be connected to each other in various ways.

[0213] According to example embodiments, as shown in region C1, an opening 408 may be defined through the fourth substrate 410, and the second input / output contact plug 403 may be directly connected to the second input / output pad 405 via the opening 408 defined through the fourth substrate 410. In this case, as shown in region C1, a diameter of the second input / output contact plug 403 may increase as a distance from the second input / output pad 405 decreases. However, this is merely an example, and a diameter of the second input / output contact plug 403 may decrease as a distance from the second input / output pad 405 decreases.

[0214] According to example embodiments, as shown in region C2, an opening 408 may be defined through the fourth substrate 410, and a contact 407 may be formed in the opening 408. One end of the contact 407 may be connected to the second input / output pad 405, and the other end of the contact 407 may be connected to the second input / output contact plug 403. Therefore, the second input / output contact plug 403 may be electrically connected to the second input / output pad 405 through the contact 407 in the opening 408. In this case, the diameter of the contact 407 may increase as the distance from the second input / output pad 405 decreases, and the diameter of the second input / output contact plug 403 may decrease as the distance from the second input / output pad 405 decreases, as shown in region C2. As an example, the third input / output contact plug 403 may be formed together with the cell contact plug 440 before the second cell region “CELL 2” is bonded to the first cell region “CELL 1”, and the contact 407 may be formed after the second cell region “CELL 2” is bonded to the first cell region “CELL 1”.

[0215] In addition, according to example embodiments, as shown in region C3, a blocking member 409 may be further formed at the upper surface of the opening 408 of the fourth substrate 410 compared to region C2. The blocking member 409 may be a metal line disposed on the same layer as the common source line 420, however, this is only an example. According to example embodiments, the blocking member 409 may be a metal line disposed on the same layer as at least one word line 430. The second input / output contact plug 403 may be electrically connected to the second input / output pad 405 through the contact 407 and the blocking member 409.

[0216] Similar to the second input / output contact plug 403 and the third input / output contact plug 404 of the second cell area "CELL 2", the diameters of the second input / output contact plug 303 and the third input / output contact plug 304 of the first cell area "CELL 1" may decrease as the distance from the lower metal pattern 371e decreases, or may increase as the distance from the lower metal pattern 371e decreases.

[0217] According to example embodiments, a slit 411 may be formed in the fourth substrate 410. As an example, the slit 411 may be formed at any position in the external pad bonding area PA. As an example, as shown in area D, when viewed in a plan view, the slit 411 may be disposed between the second input / output pad 405 and the cell contact plug 440. However, this is only an example, and when viewed in a plan view, the slit 411 may be formed to allow the second input / output pad 405 to be located between the slit 411 and the cell contact plug 440.

[0218] According to example embodiments, as shown in region D1, slits 411 may be formed through fourth substrate 410. Slits 411 may prevent fourth substrate 410 from being slightly cracked when opening 408 is formed. However, this is only an example, and slits 411 may be formed at a depth of about 60% to 70% of the thickness of fourth substrate 410.

[0219] According to example embodiments, as shown in region D2, a conductive material 412 may be formed in the slit 411. The conductive material 412 may be used, for example, to discharge leakage current generated when driving circuit elements of the external pad bonding region PA to the outside. In this case, the conductive material 412 may be connected to an external ground line.

[0220] According to example embodiments, as shown in region D3, an insulating material 413 may be formed in the slit 411. The insulating material 413 may be formed, for example, to electrically separate the second input / output pad 405 and the second input / output contact plug 403 disposed in the external pad bonding region PA from the word line bonding region WLBA. Since the insulating material 413 is formed in the slit 411, a voltage provided via the second input / output pad 405 may be prevented from affecting a metal layer disposed on the fourth substrate 410 in the word line bonding region WLBA.

[0221] The first input / output pad 105, the second input / output pad 405, and the third input / output pad 406 may be selectively formed according to example embodiments. As an example, the memory device 1000F may include only the first input / output pad 105 disposed over the first substrate 201, may include only the second input / output pad 405 disposed over the fourth substrate 410, or may include only the third input / output pad 406 disposed on the upper insulating layer 401.

[0222] According to example embodiments, at least one of the third substrate 310 of the first cell region "CELL 1" and the fourth substrate 410 of the second cell region "CELL 2" may be used as a sacrificial substrate and may be completely or partially removed before or after the bonding process. After removing the substrate, an additional layer may be provided. For example, the third substrate 310 of the first cell region "CELL 1" may be removed before or after the second peripheral circuit region "PERI 2" is bonded to the first cell region "CELL 1", and an insulating layer covering the upper surface of the common source line 320 or a conductive layer connecting the common source line 320 may be formed. Similarly, the fourth substrate 410 of the second cell region "CELL 2" may be removed before or after the first cell region "CELL 1" is bonded to the second cell region "CELL 2", and an upper insulating layer 401 covering the upper surface of the common source line 420 or a conductive layer connecting the common source line 420 may be formed.

[0223] As described above, the memory device 1000F may have a C2C structure, and specifically, a lower chip constituting a peripheral circuit may include a first peripheral circuit region “PERI 1” and a second peripheral circuit region “PERI 2” which are sequentially stacked in a vertical direction (Z-axis direction).

[0224] In this case, the first peripheral circuit region "PERI 1" may include circuit elements 120a, 120b, and 120c disposed on the substrate 110, the second peripheral circuit region "PERI 2" may include circuit elements 220a, 220b, and 220c disposed on the substrate 210, and a portion of the circuit elements 120a, 120b, and 120c may be electrically connected to a portion of the circuit elements 220a, 220b, and 220c. The circuit elements 120a, 120b, and 120c disposed on the first peripheral circuit region "PERI 1" may be implemented by low voltage transistors, and the circuit elements 220a, 220b, and 220c disposed on the second peripheral circuit region "PERI 2" may be implemented by high voltage transistors.

[0225] As described above, since the first peripheral circuit region “PERI 1” and the second peripheral circuit region “PERI 2” are formed by stacking two chips in the vertical direction (Z-axis direction), the area required to form the peripheral circuits when viewed in a plan view can be reduced.

[0226] Furthermore, since circuit elements implemented by the high-voltage transistor are densely arranged in the second peripheral circuit region “PERI 2 ”, the high-voltage transistor may have a sufficient width and length.

[0227] For ease of explanation, the page buffer is described as including both a high-voltage transistor and a low-voltage transistor, the transfer transistor is described as including a high-voltage transistor, and the voltage generator, the input / output circuit, and the control logic are described as including a low-voltage transistor. However, this is only an example, and the example embodiments are not limited thereto. As an example, at least one of the voltage generator, the input / output circuit, and the control logic may be implemented to include a high-voltage transistor and a low-voltage transistor. That is, at least one of the voltage generator, the input / output circuit, and the control logic may be implemented by Figure 1 In this case, the first peripheral circuit unit can be implemented as in the reference Figures 4 to 18 As an example, when the voltage generator is implemented by the first peripheral circuit unit, the high voltage transistor of the voltage generator may be arranged in the second chip, and the low voltage transistor of the voltage generator may be provided in the third chip.

[0228] While various aspects of the example embodiments have been particularly shown and described above, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the claims.

Claims

1. A storage device, comprising: A memory cell array implemented in a first chip; as well as The peripheral circuit is implemented in the second chip and a third chip vertically overlapping the first chip, Wherein, the peripheral circuit includes: A first peripheral circuit is implemented in the second chip and the third chip; a second peripheral circuit implemented in the second chip and comprising at least one high-voltage transistor; and a third peripheral circuit implemented in the third chip and comprising at least one low voltage transistor, and Wherein, the first peripheral circuit includes: a first sub-peripheral circuit implemented in the second chip and comprising at least one high-voltage transistor; and The second sub-peripheral circuit is implemented in the third chip and includes at least one low-voltage transistor.

2. The storage device according to claim 1, wherein: The first sub-peripheral circuit overlaps the second sub-peripheral circuit along the vertical direction.

3. The storage device according to claim 2, wherein: The first sub-peripheral circuit includes a first transistor, the second sub-peripheral circuit includes a second transistor, and a gate insulating layer of the first transistor has a length in the vertical direction greater than a length of a gate insulating layer of the second transistor in the vertical direction.

4. The storage device according to claim 3, wherein: The first transistor is a high voltage page buffer transistor, and the second transistor is a low voltage page buffer transistor.

5. The storage device according to claim 1, wherein: The second chip comprises: a first substrate in which the second peripheral circuit is disposed; and a first element isolation region extending into the first substrate, Wherein, the third chip includes: a second substrate in which the third peripheral circuit is disposed; and a second element isolation region extending into the second substrate, and Wherein, the length of the first component isolation region in the vertical direction is greater than the length of the second component isolation region in the vertical direction.

6. The storage device according to claim 1, wherein: The first chip includes a plurality of cell contact plugs respectively connected to a plurality of word lines of the memory cell array, The second peripheral circuit of the second chip includes a plurality of transmission transistors respectively connected to the plurality of cell contact plugs, and The word line bonding region of the first chip where the plurality of cell contact plugs are arranged overlaps with the transfer transistor region of the second chip where the plurality of transfer transistors are arranged along the vertical direction.

7. The storage device according to claim 6, wherein: The third peripheral circuit includes a voltage generator, and the transfer transistor region overlaps a region where the voltage generator is disposed in the vertical direction.

8. The storage device according to claim 1, wherein: The third peripheral circuit of the third chip further includes an input / output circuit, and the input / output circuit includes the at least one low voltage transistor of the third peripheral circuit.

9. The storage device according to claim 1, wherein: The first chip and the second chip are bonded to each other, and The second chip and the third chip are bonded to each other.

10. The storage device according to claim 9, wherein: An upper bonding metal disposed on the second chip is bonded to a bonding metal of the first chip, and The lower bonding metal disposed under the second chip is bonded to the bonding metal of the third chip.

11. The storage device according to claim 10, wherein: The second chip comprises: a substrate in which the second peripheral circuit is disposed; and A through electrode extends into the substrate and electrically connects the second peripheral circuit and the lower bonding metal.

12. The storage device according to claim 1, wherein: The first chip and the third chip are bonded to each other, and the third chip and the second chip are bonded to each other.

13. The storage device according to claim 1, wherein: The peripheral circuit further includes: a fourth peripheral circuit implemented in the second chip and including at least one low-voltage transistor.

14. A storage device, comprising: A first chip includes a memory cell array; a second chip, bonded to the first chip and comprising at least one high-voltage transistor; as well as a third chip, bonded to the second chip and comprising at least one low voltage transistor, The at least one high-voltage transistor provided in the second chip overlaps with the at least one low-voltage transistor provided in the third chip along a vertical direction.

15. The storage device according to claim 14, wherein: The second chip comprises: a first substrate in which the at least one high-voltage transistor is disposed; and a first element isolation region extending into the first substrate, Wherein, the third chip includes: a second substrate in which the at least one low voltage transistor is disposed; and a second element isolation region extending into the second substrate, and Wherein, the length of the first component isolation region in the vertical direction is greater than the length of the second component isolation region in the vertical direction.

16. The storage device according to claim 15, wherein: The second chip further includes: a through-electrode extending into the first substrate and electrically connecting the at least one high-voltage transistor of the second chip and the at least one low-voltage transistor of the third chip.

17. The storage device according to claim 14, wherein: A length of the gate insulating layer of the at least one high voltage transistor in the vertical direction is greater than a length of the gate insulating layer of the at least one low voltage transistor in the vertical direction.

18. The storage device according to claim 14, wherein: The second chip further includes: a plurality of pass transistors connected to a plurality of word lines of the memory cell array, and The third chip further includes: a voltage generator configured to generate voltages provided to the plurality of word lines.

19. The storage device according to claim 18, wherein: A pass transistor region of the second chip in which the plurality of pass transistors are arranged overlaps with a region of the third chip in which the voltage generator is provided in the vertical direction.

20. A storage device, comprising: A first chip includes a memory cell array; a second chip, comprising a plurality of high-voltage transistors and overlapping the first chip in a vertical direction; as well as a third chip, comprising a plurality of low voltage transistors, and overlapping the second chip along the vertical direction, Wherein, the second chip comprises: a plurality of pass transistors connected to word lines of the memory cell array; and A plurality of high-voltage page buffers connected to the bit lines of the memory cell array, and Wherein, the third chip includes: a voltage generator configured to generate a voltage provided to the plurality of pass transistors; and A plurality of low voltage page buffers respectively correspond to the plurality of high voltage page buffers and include a plurality of latches.

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